Pixel array and autofocus image sensor comprising the same

Abstract

A pixel array and an autofocus image sensor including the same are provided. The pixel array includes a substrate, a plurality of pixels, a deep device isolation region, and a plurality of first landing regions. The substrate includes a first surface having a gate electrode disposed thereon and a second surface opposite the first surface. The plurality of pixels is disposed in the substrate and includes a plurality of first pixels configured to detect a phase difference and a plurality of second pixels configured to detect an image. The deep device isolation region is disposed in the substrate and extends substantially vertically from the second surface of the substrate to isolate the plurality of pixels from one another. The plurality of first landing regions is disposed in the substrate adjacent to the first surface and adjacent to only at least some of the plurality of first pixels.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0090165, filed on July 25, 2019, in the Korean Intellectual Property Office (KIPO), the contents of which are hereby incorporated by reference in its entirety. TECHNICAL FIELD

[0003] Example embodiments relate generally to image sensors, and more particularly, to a pixel array included in an autofocus image sensor and an autofocus image sensor including the pixel array. BACKGROUND

[0004] A complementary metal-oxide-semiconductor (CMOS) image sensor is an image capturing device manufactured using a CMOS process. Compared to a conventional charge-coupled device (CCD) image sensor, which generally uses a relatively high-voltage analog circuit, a CMOS image sensor generally has a lower manufacturing cost and a smaller pixel size. Accordingly, a CMOS-type image sensor can have a lower power consumption requirement relative to a CCD-type image sensor. In addition, as the performance of CMOS image sensors continues to improve, CMOS image sensors are being increasingly widely used in mobile electronic devices, such as smart phones, tablet personal computers (PCs), and digital cameras.

[0005] In a digital image processing device such as a camera, it can be helpful to detect a focus control state of a photographing lens to automatically control focusing of the lens. To achieve this, a conventional digital image processing device includes an additional focus detection device separate and / or different from an image sensor. In this case, the cost of the focus detection device and / or an additional optical lens can be increased, and / or the overall size of the digital image processing device can be increased by the focus detection device. To address these problems, an autofocus image sensor using a method of detecting a phase difference has been developed. SUMMARY

[0006] At least one example embodiment of the disclosure provides a pixel array included in an autofocus image sensor capable of having improved or enhanced full-well capacity (FWC) characteristics.

[0007] At least one example embodiment of the disclosure provides an autofocus image sensor including a pixel array and capable of having improved or enhanced FWC characteristics.

[0008] According to an example embodiment, a pixel array included in an autofocus image sensor includes a substrate, a plurality of pixels, a deep device isolation region, and a plurality of first landing regions. The substrate includes a first surface and a second surface opposite the first surface, a gate electrode disposed on the first surface. The plurality of pixels is disposed in the substrate and includes a plurality of first pixels configured to detect a phase difference and a plurality of second pixels configured to detect an image. The deep device isolation region is disposed in the substrate and extends substantially vertically from the second surface of the substrate to isolate the plurality of pixels from each other. The plurality of first landing regions is disposed in the substrate adjacent to the first surface and adjacent to at least some of the plurality of first pixels only.

[0009] According to an example embodiment, an autofocus image sensor includes a pixel array and a plurality of column drive circuits. The pixel array generates a plurality of analog pixel signals based on incident light, the plurality of analog pixel signals representing phase difference information and image information. The plurality of column drive circuits is connected to a plurality of columns in the pixel array and converts the plurality of analog pixel signals to a plurality of digital signals. The pixel array includes a substrate, a plurality of pixels, a deep device isolation region, and a plurality of first landing regions. The substrate includes a first surface and a second surface opposite the first surface, a gate electrode disposed on the first surface. The plurality of pixels is disposed in the substrate and includes a plurality of first pixels configured to detect a phase difference and a plurality of second pixels configured to detect an image. The deep device isolation region is disposed in the substrate and extends substantially vertically from the second surface of the substrate to isolate the plurality of pixels from each other. The plurality of first landing regions is disposed in the substrate adjacent to the first surface and adjacent to at least some of the plurality of first pixels only.

[0010] According to an example embodiment, a pixel array included in an autofocus image sensor includes a substrate, a plurality of pixels, a deep device isolation region, and a plurality of landing regions. The substrate includes a first surface and a second surface opposite the first surface, a gate electrode disposed on the first surface. The plurality of pixels is disposed in the substrate and detects a phase difference and detects an image. The deep device isolation region is disposed in the substrate and extends substantially vertically from the second surface of the substrate to isolate the plurality of pixels from each other. The plurality of landing regions is disposed in the substrate adjacent to the first surface and adjacent to at least some of the plurality of pixels only. BRIEF DESCRIPTION OF DRAWINGS

[0011] The above and other aspects and features of the present disclosure will become more apparent by describing in detail example embodiments thereof with reference to the attached drawings.

[0012] Figure 1 is a plan view of a pixel array included in an autofocus image sensor according to an example embodiment.

[0013] Figure 2 is Figure 1A plan view of the layout of a portion of the pixel array in an autofocus image sensor.

[0014] Figure 3 , Figure 4A and Figure 4B This is a diagram illustrating an example of performing autofocus using an autofocus image sensor according to an example embodiment.

[0015] Figure 5 This is a circuit diagram illustrating an example of pixels included in a pixel array in an autofocus image sensor according to an example embodiment.

[0016] Figure 6 yes Figure 1 A plan view of the lower layout of a portion of the pixel array in an autofocus image sensor.

[0017] Figure 7 It is an example of a pixel array included in an autofocus image sensor. Figure 6 A cross-sectional view taken from line A-A'.

[0018] Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 8E and Figure 8F It is used to describe manufacturing Figure 6 and Figure 7 A cross-sectional view of a method that includes a pixel array in an autofocus image sensor.

[0019] Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 and Figure 15 Other examples of pixel arrays included in autofocus image sensors are along... Figure 6 A cross-sectional view taken from line A-A'.

[0020] Figure 16 It is a plan view of a pixel array included in an autofocus image sensor according to an example embodiment.

[0021] Figure 17 yes Figure 16 A plan view of the layout of a portion of the pixel array in an autofocus image sensor.

[0022] Figure 18 It is a plan view of a pixel array included in an autofocus image sensor according to an example embodiment.

[0023] Figure 19yes Figure 18 A cross-sectional view of an example of a pixel array included in an autofocus image sensor.

[0024] Figure 20 It is a plan view of a pixel array included in an autofocus image sensor according to an example embodiment.

[0025] Figure 21 and Figure 22 yes Figure 20 A cross-sectional view of an example of a pixel array included in an autofocus image sensor.

[0026] Figure 23 It is a plan view of a pixel array included in an autofocus image sensor according to an example embodiment.

[0027] Figure 24 yes Figure 23 A cross-sectional view of an example of a pixel array included in an autofocus image sensor.

[0028] Figure 25 It is a plan view of a pixel array included in an autofocus image sensor according to an example embodiment.

[0029] Figure 26 This is a circuit diagram illustrating another example of pixels included in a pixel array in an autofocus image sensor according to an example embodiment.

[0030] Figure 27 yes Figure 25 A cross-sectional view of an example of a pixel array included in an autofocus image sensor.

[0031] Figure 28 It is a plan view of a pixel array included in an autofocus image sensor according to an example embodiment.

[0032] Figure 29 yes Figure 28 A plan view of the layout of a portion of the pixel array in an autofocus image sensor.

[0033] Figure 30 yes Figure 28 A cross-sectional view of an example of a pixel array included in an autofocus image sensor.

[0034] Figure 31 This is a cross-sectional view of an example of a pixel array included in an autofocus image sensor according to an exemplary embodiment.

[0035] Figure 32 This is a block diagram illustrating an autofocus image sensor according to an example embodiment.

[0036] Figure 33is a block diagram illustrating an electronic system including an autofocus image sensor according to an example embodiment. DETAILED DESCRIPTION

[0037] Various example embodiments will be more fully described with reference to the accompanying drawings. However, the present disclosure can be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Like reference numerals refer to like elements throughout the present disclosure.

[0038] According to an example embodiment, at least one of the components, elements, modules or units described herein can be implemented as various numbers of hardware, software and / or firmware structures.

[0039] Figure 1 is a plan view of a pixel array included in an autofocus image sensor according to an example embodiment.

[0040] Referring to Figure 1 , a pixel array 100 included in an autofocus image sensor includes a plurality of pixels and a plurality of first ground regions GR1.

[0041] The plurality of pixels includes a plurality of first pixels AFP and a plurality of second pixels NP. The plurality of first pixels AFP is configured to detect a phase difference and obtain autofocus (AF) information. The plurality of first pixels AFP can be referred to as autofocus (AF) pixels. The plurality of second pixels NP is configured to detect an image. The plurality of second pixels NP can be referred to as normal pixels. The AF pixels AFP and the normal pixels NP can be disposed in one pixel array 100.

[0042] As will be described later with reference to Figure 7 , the plurality of pixels is formed or disposed in a substrate, and the pixel array 100 includes a deep device isolation region to isolate or space the plurality of pixels from each other.

[0043] The plurality of first ground regions GR1 is disposed adjacent to or only adjacent to at least some of the plurality of first pixels AFP. In Figure 1 an example, a number of the plurality of first ground regions GR1 can be substantially equal to a number of the plurality of first pixels AFP, and the plurality of first ground regions GR1 can be disposed adjacent to all of the first pixels AFP of the plurality of first pixels AFP. In other words, each of the plurality of first pixels AFP can include a respective one of the plurality of first ground regions GR1. To reduce a dark current, a reference voltage (e.g., a ground voltage) can be applied to the plurality of first ground regions GR1.

[0044] In some example embodiments, the plurality of first ground regions GR1 can be arranged uniformly and regularly throughout the pixel array 100.

[0045] The plurality of pixels can be divided into a plurality of pixel groups PG, each of the plurality of pixel groups PG including at least one of the plurality of first pixels AFP and at least one of the plurality of second pixels NP. The plurality of pixel groups PG can be repeatedly arranged along a first direction DR1 and a second direction DR2 intersecting (e.g., substantially perpendicular to) the first direction DR1. The plurality of pixel groups PG can include the same number of first pixels AFP.

[0046] Although Figure 1 An example in which one pixel group PG includes 4 x 4 pixels (specifically, two first pixels AFP and fourteen second pixels NP) is illustrated, but example embodiments are not limited thereto, and the configuration of the pixel group PG can be variously changed or modified according to example embodiments.

[0047] The pixel array 100 included in the auto focus image sensor according to example embodiments can be implemented such that the first pixels AFP for obtaining AF information and the second pixels NP for obtaining image information are disposed in one pixel array 100. In addition, in order to reduce dark current, the first ground region GR1 can be disposed only in the first pixels AFP, not in the second pixels NP. Accordingly, even if the size of the pixel is reduced, the photoelectric conversion region included in the second pixels NP can be expanded or enlarged, and thus full well capacity (FWC) characteristics can be improved or enhanced.

[0048] Figure 2 is Figure 1 a plan view of a layout of a portion of a pixel array included in an auto focus image sensor. For ease of explanation, Figure 2 a layout of one pixel group PG included in the pixel array 100 of Figure 1 is illustrated.

[0049] Referring to Figure 1 and Figure 2 The pixel array 100 included in the auto focus image sensor can include a focus detection region 11 and an image detection region 13. The focus detection region 11 can include first and second AF pixels 21R and 21L adjacent to each other and configured to detect a phase difference. The image detection region 13 can include normal pixels 23 for detecting an image.

[0050] A color filter array including a plurality of color filters can be disposed on the focus detection area 11 and the image detection area 13. For example, the color filter array can be a Bayer pattern array composed of red (R), green (G), and blue (B). However, example embodiments are not limited thereto, and the color filter array can employ a complementary color system (e.g., a system using magenta, cyan, and yellow), or can further include a white (W) color filter or a transparent color filter. The color filters disposed on the AF pixels 21R and 21L can not be used for color compensation, and the color filters can also be formed on the AF pixels 21R and 21L for a process of facilitating formation of the color filter array. A microlens array including a plurality of microlenses 35 can be disposed on the color filter array.

[0051] Although Figure 2 not shown in FIGS. 1 and 2, the color filters disposed on the AF pixels 21R and 21L of the focus detection area 11 can be omitted according to example embodiments.

[0052] A light-shielding pattern at least controlling the amount of light reception of the AF pixels 21R and 21L can be disposed below the color filter array. Accordingly, the light-shielding pattern can include a plurality of first openings 31 formed on the AF pixels 21R and 21L. In addition, the light-shielding pattern can further include a plurality of second openings 33 formed on the normal pixels 23. The area of each of the first openings 31 can be smaller than the area of each of the second openings 33. For example, the area of each of the first openings 31 can be about 50% of the area of each of the second openings 33. Each of the first openings 31 can be disposed on one side with respect to an optical axis along which light is received. The first openings 31 of the first AF pixel 21R and the second AF pixel 21L adjacent to each other can be disposed horizontally symmetrically. The first openings 31 of the light-shielding pattern can reduce the amount of light incident on each of the AF pixels 21R and 21L compared to the amount of light incident on each of the normal pixels 23. In other words, the amount of light incident on each of the AF pixels 21R and 21L can be smaller than the amount of light incident on each of the normal pixels 23 due to the light-shielding pattern.

[0053] Figure 3 、 Figure 4A and Figure 4B are diagrams for describing examples of performing auto-focusing using an auto-focusing image sensor according to example embodiments.

[0054] Referring to Figure 3 、 Figure 4A and Figure 4B , light (or incident light) of an object that has passed through a lens 51 of an image capturing device (or an image processing device) passes through a plurality of microlenses (e.g., microlenses 35) included in the image capturing device (or the image processing device). Figure 2the microlens array 54 of the microlens 35 in FIG. 1A) to be introduced to the first AF pixel R and the second AF pixel L. The masks or openings 57 and 58 (e.g., diaphragms) that limit light input from the pupils 52 and 53 of the lens 51 can be provided adjacent to some portions of the first AF pixel R and the second AF pixel L. Light input from the pupil 52 provided above the optical axis 50 of the lens 51 is introduced to the second AF pixel L, and light input from the pupil 53 provided below the optical axis 50 of the lens 51 is introduced to the first AF pixel R. The term "pupil segmentation" means that the first AF pixel R and the second AF pixel L receive light projected from the positions of the pupils 53 and 52 through the microlens array 54 by the masks or openings 57 and 58, respectively. Figure 2 The first opening 31 in FIG. 1A can be provided adjacent to some portions of the first AF pixel R and the second AF pixel L. Light input from the pupil 52 provided above the optical axis 50 of the lens 51 is introduced to the second AF pixel L, and light input from the pupil 53 provided below the optical axis 50 of the lens 51 is introduced to the first AF pixel R. The term "pupil segmentation" means that the first AF pixel R and the second AF pixel L receive light projected from the positions of the pupils 53 and 52 through the microlens array 54 by the masks or openings 57 and 58, respectively.

[0055] Figure 4A and Figure 4B The pixel outputs of the continuous pupil segmentation of the first AF pixel R and the second AF pixel L according to the positions of the first AF pixel R and the second AF pixel L are shown in FIGS. 1B and 1C. In FIGS. 1B and 1C, Figure 4A and Figure 4B In each of FIGS. 1B and 1C, the horizontal axis represents the position of each of the first AF pixel R and the second AF pixel L, and the vertical axis represents the output value of each of the first AF pixel R and the second AF pixel L. Referring to FIGS. 1B and 1C, Figure 4A and Figure 4B The shape of the continuous output value of the first AF pixel R is substantially the same as the shape of the continuous output value of the second AF pixel L. However, as shown in FIGS. 1B and 1C, the positions (e.g., phases) of the output values of the first AF pixel R and the second AF pixel L can be different from each other. This is because the positions of the images formed based on the light provided from the pupils 52 and 53 of the lens 51 are different from each other. Therefore, if the lens 51 is out of focus, as shown in FIG. 1B, Figure 4A the phases of the output values of the first AF pixel R and the second AF pixel L are different. If the lens 51 is in focus, as shown in FIG. 1C, the images are formed at the same position. Figure 4A Figure 4B

[0056] ​​In addition, the direction of focus difference can be determined based on a difference between the phases of the output values of the first AF pixel R and the second AF pixel L. The front focus state means that the lens 51 is focused in front of the object. In the front focus state, the phase of the output value of the first AF pixel R is shifted left from the phase of the focus state, and the phase of the output value of the second AF pixel L is shifted right from the phase of the focus state. On the other hand, the rear focus state means that the lens 51 is focused behind the object. In the rear focus state, the phase of the output value of the first AF pixel R is shifted right from the phase of the focus state, and the phase of the output value of the second AF pixel L is shifted left from the phase of the focus state. The amount of shift between the phases of the output values of the first AF pixel R and the second AF pixel L can be used to obtain the amount of shift between the focus points.

[0057] Figure 5 is a circuit diagram illustrating an example of a pixel included in a pixel array included in an autofocus image sensor according to an example embodiment.

[0058] Referring to Figure 5 , the pixel or unit pixel 600 can include a photoelectric conversion section 610 and a signal generation section 612. Except that the openings having different sizes are respectively formed on the first pixel AFP and the second pixel NP as described with reference to Figure 2 , the first pixel AFP and the second pixel NP in Figure 1 may have the same pixel structure and circuit structure.

[0059] The photoelectric conversion section 610 can perform a photoelectric conversion operation. For example, the photoelectric conversion section 610 can convert incident light into photocharge during an integration mode. If the image sensor including the unit pixel 600 is a complementary metal-oxide semiconductor (CMOS) image sensor, image information of an object to be captured can be obtained by collecting charge carriers (e.g., electron-hole pairs) in the photoelectric conversion section 610 in proportion to the intensity of incident light passing through an opened shutter of the CMOS image sensor during the integration mode.

[0060] The signal generation section 612 can generate an electrical signal (e.g., an analog pixel signal VP) based on the photocharge generated by the photoelectric conversion operation during a readout mode. If the image sensor including the unit pixel 600 is a CMOS image sensor, the shutter can be closed during the readout mode after the integration mode, and the analog pixel signal VP can be generated based on the image information in the form of the charge carriers. For example, as illustrated in Figure 5 , the unit pixel 600 can have a four-transistor structure including four transistors.

[0061] For example, the signal generation section 612 can include a transfer transistor 620, a reset transistor 640, a drive transistor 650, a selection transistor 660, and a floating diffusion node 630. The transfer transistor 620 can be connected between the photoelectric conversion section 610 and the floating diffusion node 630, and can include a gate electrode configured to receive a transfer signal TX. The reset transistor 640 can be connected between a power supply voltage VDD and the floating diffusion node 630, and can include a gate electrode configured to receive a reset signal RX. The drive transistor 650 can be connected between the power supply voltage VDD and the selection transistor 660, and can include a gate electrode connected to the floating diffusion node 630. The selection transistor 660 can be connected between the drive transistor 650 and an output terminal configured to output an analog pixel signal VP, and can include a gate electrode configured to receive a selection signal SEL.

[0062] In some example embodiments, as will be described later with reference to Figure 26 one signal generation section can be shared by a plurality of photoelectric conversion units.

[0063] Figure 6 is a plan view of a lower layout of a portion of a pixel array included in an autofocus image sensor. Figure 1 is a cross-sectional view taken along line A-A' of the example of the pixel array included in the autofocus image sensor. For ease of illustration, Figure 7 shows a layout of an upper half of a pixel group PG included in the pixel array 100 of Figure 6 Figure 6 For ease of illustration, Figure 1

[0064] With reference to Figure 1 , Figure 6 and Figure 7 , the pixel array 100 included in the autofocus image sensor includes a substrate 101, a plurality of pixels AFP and NP, a deep device isolation region 110, and a plurality of first ground regions GR1 115. The pixel array 100 can further include a photoelectric conversion region PD, a floating diffusion region FD, a transfer gate TG, contacts C1 and C2, signal lines L1 and L2, a gate insulating layer 121, a first interlayer insulating layer 123, a second interlayer insulating layer 125, and a third interlayer insulating layer 127, a first passivation layer 129, a fixed charge layer 131, a first insulating layer 133, a second insulating layer 135, a light-shielding pattern 140, a second passivation layer 141, a planarization layer 143, a color filter 145, and a microlens 35.

[0065] ​​The substrate 101 includes a first surface 101a and a second surface 101b opposite to each other. A gate electrode (e.g., a transfer gate TG) and a wiring (e.g., signal lines L1 and L2) are provided on the first surface 101a. A light-blocking pattern 140, a color filter 145, a microlens 35, and the like are provided on the second surface 101b, and light is incident through the second surface 101b. For example, the first surface 101a can be a front surface, the second surface 101b can be a rear surface, and an autofocus image sensor including the pixel array 100 can be a backside illuminated image sensor (BIS) that operates in response to incident light that passes through the rear surface of the substrate 101.

[0066] In the BIS, since the gate electrode and the metal line connected to the gate electrode are not provided between the microlens 35 and the photoelectric conversion region PD, diffuse reflection and / or scattering due to the gate electrode and the metal line do not occur, and the distance from the microlens 35 to the photoelectric conversion region PD can be shorter. Therefore, light guiding efficiency and light sensitivity can be improved in the BIS. In addition, the positions of the signal lines L1 and L2 adjacent to the first surface 101a can not be limited. For example, the signal lines L1 and L2 can overlap the photoelectric conversion region PD.

[0067] A plurality of pixels AFP and NP are formed or provided in the substrate 101. The plurality of pixels AFP and NP include a plurality of first pixels AFP configured to detect a phase difference and a plurality of second pixels NP configured to detect an image. Referring to Figure 2 The AF pixels 21R and 21L in the focus detection region 11 and the normal pixels 23 in the image detection region 13 described can correspond to the plurality of first pixels AFP and the plurality of second pixels NP, respectively. Each of the plurality of pixels AFP and NP can include a photoelectric conversion region PD, a floating diffusion region FD, a transfer gate TG, and the like.

[0068] The photoelectric conversion region PD can correspond to the photoelectric conversion section 610 in Figure 5 The photoelectric conversion region PD can be provided adjacent to both the first surface 101a and the second surface 101b in the substrate 101, and can perform photoelectric conversion based on incident light to generate photocharge. For example, the photoelectric conversion region PD can generate an electron-hole pair in response to incident light, and can collect an electron and / or a hole of the electron-hole pair. The photoelectric conversion region PD can include a photodiode, a phototransistor, a photogate, a pinned photodiode (PPD), and / or a combination thereof.

[0069] The transfer gate TG can correspond to the transfer gate 620 in Figure 5The transfer transistor 620 in FIG. 6 corresponds to the transfer transistor 620 in FIG. 1. The transfer gate TG can be disposed on the first surface 101a of the substrate 101 with the gate insulating layer 121 interposed between the transfer gate TG and the first surface 101a, and the transfer gate TG can transfer photocharges collected by the photoelectric conversion region PD to the floating diffusion region FD. The floating diffusion region FD can be disposed adjacent to the first surface 101a of the substrate 101, and can accumulate photocharges collected by photoelectric conversion in the photoelectric conversion region PD. The AF information and / or the image information can be generated based on a charge amount of the photocharges received at the floating diffusion region FD. Figure 5 The floating diffusion node 630 in FIG. 6 corresponds to the floating diffusion node 630 in FIG. 1. The floating diffusion region FD can be disposed adjacent to the first surface 101a of the substrate 101, and can accumulate photocharges collected by photoelectric conversion in the photoelectric conversion region PD. The AF information and / or the image information can be generated based on a charge amount of the photocharges received at the floating diffusion region FD.

[0070] The deep device isolation region 110 is formed or disposed in the substrate 101, and extends substantially vertically from the second surface 101b of the substrate 101 to penetrate the substrate 101, thereby isolating or spacing the plurality of pixels AFP and NP from each other. The deep device isolation region 110 can not be in direct contact with the first surface 101a of the substrate 101. For example, in a cross-sectional view, the deep device isolation region 110 can have a first end and a second end that extend in a direction substantially perpendicular to the first surface 101a and the second surface 101b of the substrate 101. The first end can be in direct contact with the second surface 101b to be coplanar with the second surface 101b, and the second end can not be in direct contact with the first surface 101a and can not be coplanar with the first surface 101a. Accordingly, the depth of the deep device isolation region 110 can be less than the thickness of the substrate 101. The deep device isolation region 110 can have a grid structure in a plan view.

[0071] The deep device isolation region 110 can have a deep trench isolation (DTI) structure in which the deep device isolation region 110 has a relatively large depth and is relatively deeply formed in the substrate 101. For example, if the autofocus image sensor including the pixel array 100 is a BIS, the deep device isolation region 110 can have a backside DTI (BDTI) structure in which the deep device isolation region 110 extends from a back surface (e.g., the second surface 101b) of the substrate 101.

[0072] A plurality of first ground regions 115 are formed or configured to be adjacent to a first surface 101a in the substrate 101, and are configured to be adjacent to at least some of the plurality of first pixel AFPs or only to at least some of the plurality of first pixel AFPs. For example, the plurality of first ground regions 115 may be configured to be included in all of the plurality of first pixel AFPs. All of the plurality of second pixel NPs may not include ground regions 115. Since the deep device isolation region 110 does not directly contact the first surface 101a, the ground voltage applied to the plurality of first ground regions 115 in the plurality of first pixel AFPs can be provided to the plurality of adjacent second pixel NPs through the space or gap between the deep device isolation region 110 and the first surface 101a. Therefore, the plurality of second pixel NPs can operate stably even if the plurality of second pixel NPs do not include ground regions.

[0073] The first surface 101a of substrate 101 can be covered by a first interlayer insulating layer 123. Contact C1 can penetrate the first interlayer insulating layer 123. Contact C1 can contact the floating diffusion region FD. Signal line L1 can be disposed on the first interlayer insulating layer 123. Signal line L1 can contact contact C1. A second interlayer insulating layer 125 can cover the first interlayer insulating layer 123 and signal line L1. Contact C2 can penetrate the first interlayer insulating layer 123 and the second interlayer insulating layer 125. Contact C2 can contact the first ground region 115. Signal line L2 can be disposed on the second interlayer insulating layer 125. Signal line L2 can contact contact C2. A third interlayer insulating layer 127 can cover the second interlayer insulating layer 125 and signal line L2. The third interlayer insulating layer 127 can be covered by a first passivation layer 129. Signal lines L1 and L2 can correspond to interconnects.

[0074] although Figure 7 Not shown in the diagram, but used to form Figure 5 The reset transistor 640, drive transistor 650 and select transistor 660 can also be disposed on the first surface 101a of the substrate 101, and / or adjacent to the first surface 101a in the substrate 101. Contacts and signal lines connected to these components can also be disposed between the interlayer insulating layers 123, 125 and 127.

[0075] A fixed charge layer 131 may be disposed on a second surface 101b of the substrate 101. For example, the fixed charge layer 131 may have a negative fixed charge. Holes may accumulate around the second surface 101b due to the fixed charge layer 131, thereby effectively reducing the occurrence of dark current and white spots. A first insulating layer 133 and a second insulating layer 135 may be sequentially stacked on the fixed charge layer 131.

[0076] The light-blocking pattern 140 can be provided on the second insulating layer 135 (e.g., on the second surface 101b of the substrate 101). Through the light-blocking pattern 140, the amount of light incident on each of the plurality of first pixels AFP can be less than the amount of light incident on each of the plurality of second pixels NP. For example, the light-blocking pattern 140 can be provided only on the focus detection region 11. The light-blocking pattern 140 can have a grid structure overlapping the deep device isolation region 110 in a plan view. The area of the light-blocking pattern 140 on each of the plurality of first pixels AFP can be greater than the area of the light-blocking pattern 140 on each of the plurality of second pixels NP. The light-blocking pattern 140 can include a plurality of first openings 31 at least partially exposing the plurality of first pixels AFP.

[0077] Although Figure 6 and Figure 7 not illustrated in FIG. 1, according to example embodiments, the light-blocking pattern 140 can be provided on at least a portion of the image detection region 13 to form a plurality of second openings 33.

[0078] The second passivation layer 141 can be conformally stacked on the light-blocking pattern 140. A planarization layer 143 can be provided on the second passivation layer 141. A color filter array including color filters 145 can be provided on the planarization layer 143, and a microlens array including microlenses 35 can be provided on the color filter array. The microlenses 35 can adjust the optical path of light entering the microlenses 35 so that the light is focused on corresponding photoelectric conversion regions PD.

[0079] In some example embodiments, the color filter array can include a Bayer color filter including a red color filter, a green color filter, and / or a blue color filter, in other words, the color filter 145 can be one of a red color filter, a green color filter, and a blue color filter. In other example embodiments, the color filter array can include a yellow color filter, a magenta color filter, and / or a cyan color filter, in other words, the color filter 145 can be one of a yellow color filter, a magenta color filter, and a cyan color filter. The color filter array can further include a white color filter.

[0080] Although Figure 7 not illustrated in FIG. 1, an anti-reflection layer can be formed between the planarization layer 143 and the color filters 145. The anti-reflection layer can reduce and / or prevent incident light from being reflected by the second surface 101b of the substrate 101. In some example embodiments, the anti-reflection layer can be formed by alternately stacking materials having different refractive indices. A higher light transmittance of the anti-reflection layer can be achieved with increasing the stacking of such materials.

[0081] Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 8E andFigure 8F is for describing manufacturing Figure 6 and Figure 7 a cross-sectional view of a method of a pixel array included in an autofocus image sensor.

[0082] Referring to Figure 8A , a substrate 101 having a first surface 101a and a second surface 101b opposite to each other can be provided. The substrate 101 can be a semiconductor substrate. For example, the substrate 101 can be a p-type silicon substrate.

[0083] Referring to Figure 8B , a photoelectric conversion region PD, a floating diffusion region FD, and a first gate region GR1 can be formed in the substrate 101. For example, the photoelectric conversion region PD, the floating diffusion region FD, and the first gate region GR1 can be formed by using, for example, an ion implantation process. For example, the photoelectric conversion region PD and the floating diffusion region FD can be doped with an n-type impurity of a type opposite to that of the substrate 101, and the first gate region GR1 can be doped with a p-type impurity of the same type as that of the substrate 101 at a higher concentration (or at a higher density) than the substrate 101.

[0084] The floating diffusion region FD and the first gate region GR1 can be formed adjacent to the first surface 101a. The photoelectric conversion region PD can be formed adjacent to both the first surface 101a and the second surface 101b. Since the floating diffusion region FD and the first gate region 115 are disposed adjacent to the first surface 101a, a width (or an area) of a portion of the photoelectric conversion region PD adjacent to the first surface 101a can be smaller than a width (or an area) of a portion of the photoelectric conversion region PD adjacent to the second surface 101b. Since the FWC is the largest in the portion adjacent to the first surface 101a, it can be advantageous to improve the FWC characteristics by increasing the size, width, or area of the portion of the photoelectric conversion region PD adjacent to the first surface 101a.

[0085] In some example embodiments, the photoelectric conversion region PD can be formed by laminating two or more doped regions. In some example embodiments, the floating diffusion region FD can be doped at a higher concentration than the photoelectric conversion region PD.

[0086] Referring to Figure 8C , a gate insulating layer 121 and a transfer gate TG can be formed on the first surface 101a, and a first interlayer insulating layer 123 can be formed to cover the first surface 101a. Referring to Figure 8DFor example, the contact C1 can be formed to penetrate the first interlayer insulating layer 123, the signal line L1 can be formed on the first interlayer insulating layer 123, and the second interlayer insulating layer 125 can be formed on the first interlayer insulating layer 123. Also, the contact C2 can be formed to penetrate the first interlayer insulating layer 123 and the second interlayer insulating layer 125, the signal line L2 can be formed on the second interlayer insulating layer 125, and the third interlayer insulating layer 127 and the first passivation layer 129 can be sequentially formed on the second interlayer insulating layer 125.

[0087] For example, the transmission gate TG can be formed by forming a gate conductive layer from polysilicon, a metal, and / or a metal compound and by patterning the gate conductive layer. For example, the contacts C1 and C2 and the signal lines L1 and L2 can be formed by forming a conductive layer from copper, tungsten, titanium, and / or aluminum and by patterning the conductive layer. For example, the interlayer insulating layers 123, 125, and 127 can be formed from, for example, silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), silicon nitride (SiN x ), germanium oxynitride (GeO x N y ), germanium silicon oxide (GeSi x O y ), and / or a material having a high dielectric constant (e.g., hafnium oxide (HfO x ), zirconium oxide (ZrO x ), aluminum oxide (AlO x ), tantalum oxide (TaO x ), hafnium silicide (HfSi x ), and / or zirconium silicide (ZrSi x ).

[0088] Referring to Figure 8E The substrate 101 can be flipped so that the second surface 101b faces upward, and a backgrinding process can be performed on the second surface 101b so that portions adjacent to the second surface 101b of the substrate 101 are removed. For example, the grinding process can be performed by a mechanical process and / or a chemical process. For example, the mechanical process can be performed by rubbing a polishing pad on the second surface 101b. Also, the chemical process can be performed by injecting a chemical material (e.g., a "slurry") between the polishing pad and the second surface 101b.

[0089] Also, as described above, the substrate 101 can be flipped so that the second surface 101b faces upward, and a backgrinding process can be performed on the second surface 101b so that portions adjacent to the second surface 101b of the substrate 101 are removed. For example, the grinding process can be performed by a mechanical process and / or a chemical process. For example, the mechanical process can be performed by rubbing a polishing pad on the second surface 101b. Also, the chemical process can be performed by injecting a chemical material (e.g., a "slurry") between the polishing pad and the second surface 101b. Figure 8EAfter flipping the substrate 101 and removing the portion of the substrate 101 as shown, a deep device isolation region 110 can be formed in the substrate 101. For example, the deep device isolation region 110 can be formed of an insulating material such as silicon oxide. For example, the deep device isolation region 110 can be formed such that the insulating material is vertically formed from the second surface 101b in the substrate 101. Therefore, one end of the deep device isolation region 110 can be in direct contact with the second surface 101b, and the other end of the deep device isolation region 110 may not be in direct contact with the first surface 101a.

[0090] In some example embodiments, the deep device isolation region 110 can be filled with a dielectric material whose refractive index is lower than that of the substrate 101. In this example, although some incident light is refracted by the microlens 35, the leakage component of the incident light can be totally reflected at the sidewall surface of the deep device isolation region 110. The reflected component can reach the photoelectric conversion region PD, and thus can shield adjacent pixels from the leakage component. In addition, since the deep device isolation region 110 can be filled with a dielectric material, it can effectively prevent diffuse carriers generated by the incident light from being transported from the photoelectric conversion region PD to adjacent pixels.

[0091] In some example embodiments, deep device isolation regions 110 can be formed by repeatedly implanting dielectric material into substrate 101 at different energies. Although Figure 8E Not shown, but due to the repeated injection of dielectric material with different energies, the deep device isolation region 110 can have an embossed shape.

[0092] Reference Figure 8F A fixed charge layer 131, a first insulating layer 133, a second insulating layer 135, and a light-shielding pattern 140 can be sequentially formed on the second surface 101b. For example, the fixed charge layer 131 can be formed of a metal oxide including metallic elements (e.g., zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), yttrium (Y), and / or lanthanides). The fixed charge layer 131 can have at least one crystalline region. For example, the fixed charge layer 131 can be a hafnium oxide layer or an aluminum fluoride layer. For example, the first insulating layer 133 can be a silicon oxide layer, and the second insulating layer 135 can be a silicon nitride layer. For example, the light-shielding pattern 140 can be formed of an opaque metal.

[0093] In a BIS (Bipolar Integrated System), noise can arise due to surface defects (e.g., surface defects caused by the manufacturing process) present in the region adjacent to the second surface 101b of the substrate 101. If a fixed charge layer 131 is formed on the second surface 101b, holes can accumulate in the region adjacent to the second surface 101b of the substrate 101. The charges generated by the surface defects can combine with the holes accumulated in the region adjacent to the second surface 101b of the substrate 101 in the absence of any incident light. Therefore, dark current can be reduced, and light guiding efficiency and photosensitivity can be improved.

[0094] Next, as shown in the reference Figure 7 As described, a second passivation layer 141, a planarization layer 143, a color filter 145, and a microlens 35 can be sequentially formed on the light-shielding pattern 140. For example, the color filter 145 can be formed by using a dyeing process, a pigment dispersion process, and / or a printing process. For example, the microlens 35 can be formed by using a photoresist with light transmittance to form a pattern corresponding to the photoelectric conversion region PD and by reflowing these patterns to have a convex shape.

[0095] Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 and Figure 15 Other examples of pixel arrays included in autofocus image sensors are along... Figure 6 A cross-sectional view taken from line A-A'. (The text ends abruptly here, likely due to an incomplete sentence or a formatting error.) Figure 6 and Figure 7 Repeated description.

[0096] Reference Figure 9 In addition to Figure 9 The intermediate-depth device isolation region 110a includes, outside of the insulating layer 111 and the polysilicon pattern 113, Figure 9 Examples can be compared with Figure 7 The examples are basically the same.

[0097] An insulating layer 111 may surround a polysilicon pattern 113. The polysilicon pattern 113 may be formed or disposed within a deep device isolation region 110a (e.g., inside the insulating layer 111). For example, the polysilicon pattern 113 may be formed of polysilicon, metal, and / or metal compounds. Because the polysilicon pattern 113 has substantially the same coefficient of thermal expansion as the substrate 101 formed of silicon, it may be possible to reduce physical stress caused by the difference in the coefficients of thermal expansion between the materials. In some example embodiments, the polysilicon pattern 113 may be formed before or after the formation of the insulating layer 111.

[0098] Reference Figure 10 In addition toFigure 10 The middle deep device isolation region 110b includes a fixed charge layer 131 and a first insulating layer 133 in addition to the Figure 10 Examples can be substantially the same as those of Figure 7 For example, the fixed charge layer 131 can include a hafnium oxide layer. For example, the first insulating layer 133 can include a silicon oxide layer or a silicon nitride layer. The fixed charge layer 131 can be disposed on the second surface 101b, and can surround the sidewalls of the photoelectric conversion region PD, thereby further reducing the dark current.

[0099] Referring to Figure 11 Examples can be substantially the same as those of Figure 11 except that a portion of the deep device isolation region is changed in Figure 11 Examples can be substantially the same as those of Figure 7 except that a portion of the deep device isolation region 110g can extend from the second surface 101b of the substrate 101 and can be in direct contact with the first surface 101a of the substrate 101.

[0100] In some example embodiments, as described with reference to Figure 1 , the plurality of pixels can be divided into a plurality of pixel groups PG, each of the plurality of pixel groups PG includes at least one of the plurality of first pixels AFP and at least one of the plurality of second pixels NP, and a portion of the deep device isolation region 110g can extend from the second surface 101b of the substrate 101 and can be in direct contact with the first surface 101a of the substrate 101 such that the plurality of pixel groups PG are isolated from each other. In this example, a plurality of first grounding regions GR1 can be disposed in the substrate 101 such that each of the plurality of pixel groups PG includes at least one of the plurality of first grounding regions GR1. When the portion of the deep device isolation region 110g is in direct contact with the first surface 101a of the substrate 101, a ground voltage applied to the plurality of first grounding regions 115 can not provide to an adjacent pixel in some cases. Accordingly, when the plurality of pixel groups PG are isolated or spaced apart from each other by the portion of the deep device isolation region 110g, each of the plurality of pixel groups PG can include at least one of the plurality of first grounding regions GR1 for stable operation.

[0101] Referring to Figure 12 Examples can be substantially the same as those of Figure 12 except that the deep device isolation region includes a first sub deep device isolation region 110g1 and a second sub deep device isolation region 110g2 in Figure 12 Examples can be substantially the same as those of Figure 7 except that the first sub deep device isolation region 110g1 can be substantially the same as the deep device isolation region 110 in Figure 7 Examples can be substantially the same as those of Figure 11The portion of the deep device isolation region 110g that directly contacts the first surface 101a of the substrate 101 is substantially the same. For example, a first sub-deep device isolation region 110g1 can be formed such that an insulating material is vertically formed from the second surface 101b in the substrate 101, and a second sub-deep device isolation region 110g2 can be formed such that an insulating material is vertically formed from the first surface 101a in the substrate 101.

[0102] Reference Figure 13 ,Apart from Figure 13 Examples also include areas outside the shallow device isolation region 150, Figure 13 Examples can be compared with Figure 7 The examples are essentially the same. The shallow device isolation region 150 can have a shallow trench isolation (STI) structure, in which the shallow device isolation region 150 has a relatively small depth and is formed relatively shallowly in the substrate 101. The shallow device isolation region 150 can isolate the photoelectric conversion region PD, the floating diffusion region FD, and the first ground region GR1 from each other. For example, the shallow trench can be formed by etching the substrate 101 and can be filled with a filling insulating layer to form the shallow device isolation region 150.

[0103] Reference Figure 14 In addition to Figure 14 In addition to changing the structure of the photoelectric conversion region PD, Figure 14 Examples can be compared with Figure 7 The examples are essentially the same. The side surface of the photoelectric conversion region PD is spaced apart from the deep device isolation region 110. Figure 7 The examples are different, in Figure 14 In the example, at least a portion or all of the side surface of the photoelectric conversion region PD can be formed to contact the deep device isolation region 110, thereby increasing the size of the photoelectric conversion region PD.

[0104] Reference Figure 15 In addition to Figure 15 Besides partially altering the structure of the photoelectric conversion region PD, Figure 15 Examples can be compared with Figure 7 The examples are basically the same. Figure 15 In the example, the size of the photoelectric conversion region PD included in a plurality of second pixels NPs (e.g., normal pixel 23) can be larger than the size of the photoelectric conversion region PD included in a plurality of first pixels AFPs (e.g., AF pixels 21R and 21L). As described above, the plurality of second pixels NPs may not include ground regions, and thus the size of the photoelectric conversion region PD included in the plurality of second pixels NPs can be increased by means of portions in which no ground regions are formed.

[0105] In some example embodiments, references can be used.Figure 7 、 Figure 9 、 Figure 10 、 Figure 11 、 Figure 12 、 Figure 13 、 Figure 14 and Figure 15 describes two or more of the examples to implement a pixel array included in an autofocus image sensor according to example embodiments.

[0106] Figure 16 is a plan view of a pixel array included in an autofocus image sensor according to example embodiments. Figure 17 is Figure 16 a plan view of a layout of a portion of the pixel array included in the autofocus image sensor of Figure 1 and Figure 2 repeated descriptions will be omitted.

[0107] Referring to Figure 16 and Figure 17 , examples of Figure 16 and Figure 17 may be substantially the same as examples of Figure 16 and Figure 17 except for changes in the arrangement and structure of the plurality of first pixels AFP. Figure 1 Figure 2

[0108] A pixel array 100a included in an autofocus image sensor can include a focus detection region 11a and an image detection region 13a. The focus detection region 11a can include a third AF pixel 21U and a fourth AF pixel 21D adjacent to each other and for detecting a phase difference. The image detection region 13a can include normal pixels 23 for detecting an image.

[0109] A light-shielding pattern that controls at least an amount of light reception of the AF pixels 21U and 21D can be provided. The light-shielding pattern can include a plurality of first openings 31 formed on the AF pixels 21U and 21D. The first openings 31 of the third AF pixel 21U and the fourth AF pixel 21D adjacent to each other can be disposed vertically symmetrically. The first openings 31 of the light-shielding pattern can reduce an amount of light incident on each of the AF pixels 21U and 21D compared to an amount of light incident on each of the normal pixels 23.

[0110] In some example embodiments, a pixel array included in an autofocus image sensor according to example embodiments can be implemented to include both the AF pixels 21R and 21L described with reference to Figure 2 and the AF pixels 21U and 21D described with reference to Figure 17 .

[0111] ​​Figure 18 is a plan view of a pixel array included in an autofocus image sensor according to an example embodiment. Figure 19 is Figure 18 is a cross-sectional view of an example of a pixel array included in an autofocus image sensor according to Figure 1 , Figure 6 and Figure 7 repeated descriptions will be omitted.

[0112] Referring to Figure 18 and Figure 19 , except that a first pixel AFP' among the plurality of first pixels AFP and AFP' in Figure 18 and Figure 19 , Figure 18 and Figure 19 can be substantially the same as examples of Figure 1 , Figure 6 and Figure 7 .

[0113] In the pixel array 100b included in the autofocus image sensor, the number of the plurality of first ground regions GR1 can be less than the number of the plurality of first pixels AFP and AFP', and the plurality of first ground regions GR1 can be disposed adjacent to some of the first pixels AFP among the plurality of first pixels AFP and AFP'. In other words, some of the first pixels AFP among the plurality of first pixels AFP can include a respective first ground region GR1 of the plurality of first ground regions GR1, and the remaining first pixels AFP' among the plurality of first pixels AFP and AFP' can not include the plurality of first ground regions GR1. The first pixels not including the first ground region GR1 are designated as AFP'. Similar to that described with reference to Figure 1 , the plurality of first ground regions GR1 can be uniformly and regularly arranged throughout the pixel array 100b.

[0114] Figure 20 is a plan view of a pixel array included in an autofocus image sensor according to an example embodiment. Figure 21 and Figure 22 are Figure 20 cross-sectional views of examples of a pixel array included in an autofocus image sensor according to Figure 1 , Figure 6 and Figure 7 repeated descriptions will be omitted.

[0115] Referring to Figure 20 , Figure 21 and Figure 22 , except that the configuration of at least some of the plurality of second pixels is changed in Figure 20 , Figure 21 and Figure 22 ,Examples of Figure 20 , Figure 21 and Figure 22 may be substantially the same as examples of Figure 1 , Figure 6 and Figure 7 .

[0116] The pixel array 100c included in the autofocus image sensor can further include a plurality of second ground regions GR2. The plurality of second ground regions GR2 can be formed or disposed adjacent to the first surface 101a in the substrate 101, and can be disposed adjacent to only some of the plurality of second pixels NP and NP'. In other words, some of the plurality of second pixels NP and NP' can include a corresponding one of the plurality of second ground regions GR2. The second pixels including the second ground regions GR2 are designated as NP'. As with the plurality of first ground regions GR1, a ground voltage can be applied to the plurality of second ground regions GR2 to reduce dark current. The plurality of first ground regions GR1 and the plurality of second ground regions GR2 can be arranged uniformly and regularly throughout the pixel array 100c.

[0117] In some example embodiments, as shown in Figure 21 , the size (or area) of the second ground region 165 can be substantially the same as the size (or area) of the first ground region 115. In other example embodiments, as shown in Figure 22 , the size (or area) of the second ground region 165a can be smaller than the size (or area) of the first ground region 115. As described with reference to Figure 7 , a ground voltage can be provided to an adjacent pixel via a space between the deep device isolation region 110 and the first surface 101a, and thereby the plurality of second pixels NP and NP' can operate stably even if the second ground region 165a has a relatively small size.

[0118] Figure 23 is a plan view of a pixel array included in an autofocus image sensor according to an example embodiment. Figure 24 is a cross-sectional view of an example of the pixel array included in the autofocus image sensor of Figure 23 . Repetitive description with regard to Figure 1 , Figure 6 and Figure 7 will be omitted.

[0119] With reference to Figure 23 and Figure 24 , except for the first pixel AFP' among the plurality of first pixels AFP and AFP' and the second pixel NP' among the plurality of second pixels NP and NP' in Figure 23 and Figure 24 ,Figure 23 and Figure 24 Examples of Figure 1 , Figure 6 and Figure 7 may be substantially the same as examples of Figure 18 and Figure 19 described with reference to Figure 20 , Figure 21 and Figure 22 .

[0120] In some example embodiments, Figure 19 , Figure 21 , Figure 22 and Figure 24 the pixel array shown in Figure 7 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 and Figure 15 may be altered or modified based on examples as described with reference to

[0121] Figure 25 is a plan view of a pixel array included in an autofocus image sensor according to an example embodiment. Figure 26 is a circuit diagram showing another example of a pixel included in a pixel array included in an autofocus image sensor according to an example embodiment. Figure 27 is a cross-sectional view of an example of a pixel array included in an autofocus image sensor of Figure 25 . Repetitive description of Figure 1 , Figure 5 , Figure 6 and Figure 7 will be omitted.

[0122] Examples of Figure 25 , Figure 26 and Figure 27 may be substantially the same as examples of Figure 25 , Figure 26 and Figure 27 except that some of the pixels AFP and NP among the plurality of pixels AFP and NP adjacent to each other in Figure 25 , Figure 26 and Figure 27 , Figure 1 , Figure 5 , Figure 6 and Figure 7 .

[0123] In the pixel array 100e included in the autofocus image sensor, the floating diffusion region FD can be shared by four pixels that are adjacent to each other. For example, as Figure 26 As shown, the first pixel, second pixel, third pixel, and fourth pixel 600a include a first photoelectric conversion unit 610a, a second photoelectric conversion unit 610b, a third photoelectric conversion unit 610c, and a fourth photoelectric conversion unit 610d, as well as a signal generation unit 612a shared by the first photoelectric conversion unit 610a, the second photoelectric conversion unit 610b, the third photoelectric conversion unit 610c, and the fourth photoelectric conversion unit 610d.

[0124] The signal generation unit 612a may include a first transmission transistor 620a, a second transmission transistor 620b, a third transmission transistor 620c, and a fourth transmission transistor 620d, a floating diffusion node 630, a reset transistor 640, a drive transistor 650, and a selection transistor 660. The first transmission transistor 620a, second transmission transistor 620b, third transmission transistor 620c, and fourth transmission transistor 620d may be connected to the first photoelectric conversion unit 610a, second photoelectric conversion unit 610b, third photoelectric conversion unit 610c, and fourth photoelectric conversion unit 610d, respectively, and receive the first transmission signal TX1, the second transmission signal TX2, the third transmission signal TX3, and the fourth transmission signal TX4, respectively. The floating diffusion node 630 may be connected to the first transmission transistor 620a, second transmission transistor 620b, third transmission transistor 620c, and fourth transmission transistor 620d. The reset transistor 640 and the drive transistor 650 may be connected to the floating diffusion node 630, and the selection transistor 660 may be connected to the drive transistor 650.

[0125] although Figure 26 An example is shown in which the signal generation unit 612a is shared by four adjacent pixels, but the example embodiment is not limited to this, and the number of pixels sharing the signal generation unit can be changed according to the example embodiment.

[0126] like Figure 27 As shown, when adjacent pixels share the signal generation unit 612a, a floating diffusion region FD can be set between adjacent AF pixels 21R and 21L, and a floating diffusion region FD can be set between adjacent normal pixels 23.

[0127] In some example embodiments, it can be based on, as referenced Figures 18 to 24 The described examples are used to change or modify Figure 25 and Figure 27 The arrangement of the grounding areas is shown in the diagram. In some example embodiments, Figure 27 The pixel array shown can be based on, as referenced Figure 7 ,Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 and Figure 15 The examples described can be changed or modified, or can be implemented by combining two or more of the examples above.

[0128] Figure 28 It is a plan view of a pixel array included in an autofocus image sensor according to an example embodiment. Figure 29 yes Figure 28 A plan view of the layout of a portion of the pixel array in an autofocus image sensor. Figure 30 yes Figure 28 A cross-sectional view of an example pixel array included in an autofocus image sensor. (The text will be omitted.) Figure 1 , Figure 2 , Figure 6 and Figure 7 Repeated description.

[0129] Reference Figure 28 , Figure 29 and Figure 30 The pixel array 100f included in the autofocus image sensor includes a substrate 101, multiple pixels DP, a deep device isolation region 110, and multiple ground regions GR. The substrate 101, the deep device isolation region 110, and other components can be referenced. Figure 6 and Figure 7 The descriptions are basically the same.

[0130] Although multiple first pixels (AFPs) configured to detect phase differences and multiple second pixels (NPs) configured to detect images are referenced Figures 1 to 27 The examples described are spaced apart and distinguished from each other, but in Figure 28 , Figure 29 and Figure 30 In the example, each of the multiple pixel DPs can perform both the function of detecting phase difference and the function of detecting image. Multiple pixel DPs can be referred to as dual pixels.

[0131] like Figure 29 As shown, the focus detection region 11b and image detection region 13b of the pixel array 100f included in the autofocus image sensor can be the same region. The third opening 37 and the fourth opening 39 can be formed on each of the dual pixels 25 by a light-shielding pattern. Except that the third opening 37 and the fourth opening 39 are formed below the single microlens 35, the third opening 37 and the fourth opening 39 can be connected to… Figure 2It is similar to the first opening 31. Light corresponding to the left side can be received through the third opening 37, and light corresponding to the right side can be received through the fourth opening 39.

[0132] like Figure 30 As shown, each of the dual pixels 25 may include two photoelectric conversion regions PD. The photoelectric conversion region PD located on the left can be configured to correspond to the third opening 37, and can be... Figure 2 and Figure 7 The second AF pixel 21L operates similarly. The photoelectric conversion area PD located on the right can be set to correspond to the fourth opening 39, and can be... Figure 2 and Figure 7 The first AF pixel 21R operates similarly. Additionally, an image signal can be generated by summing the signals from the two photoelectric conversion regions PD. It can also be described that a photoelectric conversion region PD is defined as a sub-pixel, such that a microlens 35 is shared by the two sub-pixels.

[0133] Multiple ground regions GR can be configured to be adjacent to at least some of the multiple pixel DPs. The number of multiple ground regions GR can be less than the number of multiple pixel DPs, and each of the multiple pixel DPs may include one of the multiple ground regions GR.

[0134] Figure 31 This is a cross-sectional view of an example of a pixel array included in an autofocus image sensor according to an exemplary embodiment.

[0135] Reference Figure 31 Adjacent first AFP pixels (e.g., AF pixels 21R and 21L) can share a microlens 35, and each of the second NP pixels (e.g., normal pixel 23) can include a microlens 35 for each pixel. In other words, Figure 31 Examples can have references Figures 1 to 27 Examples and references described Figures 28 to 30 The structure of the example described.

[0136] In some example embodiments, it can be based on, as referenced Figures 18 to 24 The described examples are used to change or modify Figures 28 to 31 The arrangement of the grounding areas is shown in the diagram. In some example embodiments, Figures 28 to 31 The pixel array shown can be based on, as referenced Figure 7 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 and Figure 15The described examples are modified or changed, or can be implemented in combination with two or more of the above-described examples.

[0137] Figure 32 is a block diagram illustrating an autofocus image sensor according to an example embodiment.

[0138] Referring to Figure 32 , the autofocus image sensor 500 includes a pixel array 510, a correlated double sampling (CDS) block 530, and an analog-digital conversion (ADC) block 540. The autofocus image sensor 500 can further include a row driver 520, an image processing unit 550, a ramp signal generator 560, and a timing controller 580.

[0139] The pixel array 510 includes a plurality of pixels or a plurality of unit pixels PX arranged in a matrix form. Each of the plurality of unit pixels PX can be connected to a respective one of a plurality of rows RW1, RW2, …, RWX and a respective one of a plurality of columns CL1, CL2, …, CLY, where each of X and Y is a natural number greater than or equal to two. The pixel array 510 generates a plurality of analog pixel signals VP1, VP2, …, VPY based on incident light. The pixel array 510 can be a pixel array according to the example embodiments described with reference to Figures 1 to 31 The pixel array of the described example embodiments.

[0140] The row driver 520 can be connected to the plurality of rows RW1 ~ RWX in the pixel array 510. The row driver 520 can generate a driving signal to drive the plurality of rows RW1 ~ RWX. For example, the row driver 520 can drive the plurality of unit pixels PX included in the pixel array 510 row by row.

[0141] The correlated double sampling block 530 can include a plurality of correlated double sampling circuits (CDS) 530a, 530b, …, 530c. The plurality of correlated double sampling circuits 530a ~ 530c can be connected to the plurality of columns CL1 ~ CLY in the pixel array 510. The plurality of correlated double sampling circuits 530a ~ 530c can perform a correlated double sampling operation on the plurality of analog pixel signals VP1 ~ VPY output from the pixel array 510.

[0142] The analog-to-digital conversion block 540 includes a plurality of analog-to-digital converters 540a, 540b,..., 540c. The plurality of analog-to-digital converters 540a-540c are connected to the plurality of columns CL1-CLY in the pixel array 510 via the plurality of correlated double sampling circuits 530a-530c. The plurality of analog-to-digital converters 540a-540c perform a column analog-to-digital conversion operation that converts the plurality of analog pixel signals VP1-VPY (e.g., the plurality of correlated double sampled analog pixel signals output from the plurality of correlated double sampling circuits 530a-530c) in parallel (e.g., simultaneously or concurrently) to the plurality of digital signals CNT1, CNT2,..., CNTY.

[0143] Each of the plurality of analog-to-digital converters 540a-540c can include a respective one of a plurality of comparators 542a, 542b,..., 542c and a respective one of a plurality of counters (CNT) 544a, 544b,..., 544c. For example, the first analog-to-digital converter 540a can include the first comparator 542a and the first counter 544a. The first comparator 542a can compare the first analog pixel signal VP1 (e.g., the correlated double sampled first analog pixel signal output from the first correlated double sampling circuit 530a) to the ramp signal VRAMP to generate the first comparison signal CS1. The first counter 544a can count the level transition timing of the first comparison signal CS1 to generate the first digital signal CNT1.

[0144] The operations of the correlated double sampling block 530 and the analog-to-digital conversion block 540 can be performed on the plurality of unit pixels PX included in the pixel array 510 on a column-by-column basis.

[0145] The plurality of correlated double sampling circuits 530a-530c and the plurality of analog-to-digital converters 540a-540c can form a plurality of column drive circuits. For example, the first correlated double sampling circuit 530a and the first analog-to-digital converter 540a can form a first column drive circuit.

[0146] The image processing unit 550 can perform an image processing operation based on the plurality of digital signals CNT1-CNTY. For example, an operation to obtain AF information using AF pixels and an operation to obtain an image using normal pixels can be performed by the image processing unit 550.

[0147] In some example embodiments, the image processing unit 550 can be omitted, and the above-described image processing operations can be performed by an external processor (e.g., the application processor 1110 in FIG. 11). Figure 33

[0148] ​The ramp signal generator 560 can generate a ramp signal VRAMP. The timing controller 580 can control overall operation timing of the auto-focus image sensor 500, and can generate a control signal including a count enable signal CNT_EN, a clock signal (not shown), etc.

[0149] Figure 33 is a block diagram illustrating an electronic system including an auto-focus image sensor according to an example embodiment.

[0150] Referring to Figure 33 , the electronic system 1000 can be implemented as a data processing apparatus implemented as a data processing apparatus using or supporting a Mobile Industry Processor Interface (MIPI). The electronic system 1000 can include an application processor 1110, an auto-focus image sensor 1140, a display apparatus 1150, etc. The electronic system 1000 can further include a radio frequency (RF) chip 1160, a global positioning system (GPS) 1120, a memory 1170, a microphone (MIC) 1180, a dynamic random access memory (DRAM) 1185, and a speaker 1190. In addition, the electronic system 1000 can perform communication using an ultra-wideband (UWB) 1210, a wireless local area network (WLAN) 1220, a worldwide interoperability for microwave access (WIMAX) 1230, etc.

[0151] The application processor 1110 can be a controller or a processor that controls the operation of the auto-focus image sensor 1140. The auto-focus image sensor 1140 can be an auto-focus image sensor according to an example embodiment.

[0152] The application processor 1110 can include a display serial interface (DSI) host 1111 that performs serial communication with a DSI device 1151 of the display apparatus 1150, a camera serial interface (CSI) host 1112 that performs serial communication with a CSI device 1141 of the auto-focus image sensor 1140, a physical layer (PHY) 1113 that performs data communication with a PHY 1161 of the RF chip 1160 based on MIPI DigRF, and a DigRF master device 1114 that controls data communication of the physical layer 1161. A DigRF slave device 1162 of the RF chip 1160 can be controlled through the DigRF master device 1114.

[0153] In some example embodiments, the DSI host 1111 can include a serializer (SER), and the DSI device 1151 can include a deserializer (DES). In some example embodiments, the CSI host 1112 can include a deserializer (DES), and the CSI device 1141 can include a serializer (SER).

[0154] The inventive concept can be applied to various electronic devices and / or systems including an auto-focusing image sensor. For example, the inventive concept can be applied to systems such as a mobile phone, a smart phone, a tablet, a notebook, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a portable game console, a music player, a camcorder, a video player, a navigation device, a wearable device, an Internet of Things (IoT) device, an Internet of Everything (IoE) device, an electronic book reader, a virtual reality (VR) device, an augmented reality (AR) device, a robot device, etc.

[0155] A pixel array and an auto-focusing image sensor according to example embodiments can be implemented such that first pixels for obtaining auto-focusing (AF) information and second pixels for obtaining image information are disposed in one pixel array. In addition, a first contact region for reducing dark current can be disposed only in the first pixels, not in the second pixels. Accordingly, even if the size of the pixels is reduced, the photoelectric conversion region included in the second pixels can be expanded or enlarged, and thus FWC characteristics can be improved or enhanced.

[0156] In addition, example embodiments can be applied to a case in which the first contact regions are disposed only in some of the first pixels, a case in which the second contact regions are additionally arranged in some of the second pixels, and a case in which one pixel obtains AF information and image information together.

[0157] The foregoing is illustrative of example embodiments, and is not to be construed as limiting. Although a few example embodiments have been described in detail above, those skilled in the art will be able to make modifications and variations without departing from the scope of the inventive concept as set forth in the claims. Accordingly, all such modifications and variations are intended to be included within the scope of the disclosure as defined by the appended claims. Thus, it will be understood that the foregoing is illustrative of various example embodiments, and is not to be construed as limited. Modifications and other example embodiments are intended to fall within the scope of the disclosure as defined by the claims.

[0158] FIGURE TRANSLATION:

[0159] Figure 4A , Figure 4B :

[0160] OUTPUT VALUE OF AF PIXEL: Output value of an AF pixel

[0161] POSITION OF AF PIXEL: Position of an AF pixel

[0162] Figure 7 , Figures 9 to 15 , Figure 19 , Figure 21、 Figure 22 、 Figure 24 、 Figure 27 、 Figure 30 、 Figure 31 :

[0163] INCIDENT LIGHT: incident light

[0164] Figure 32 :

[0165] 520: row driver

[0166] 550: image processing unit

[0167] 560: ramp signal generator

[0168] 580: timing controller

[0169] Figure 33 :

[0170] 1110: application processor

[0171] 1111: DSI host

[0172] 1112: CSI host

[0173] DISPLAY SERIAL INTERFACE: display serial interface

[0174] CAMERA SERIAL INTERFACE: camera serial interface

[0175] 1150: display

[0176] 1151: DSI device

[0177] 1140: image sensor

[0178] 1141: CSI device

[0179] 1190: speaker

[0180] 1170: memory

[0181] 1160: RF chip

[0182] 1114: DigRF master device

[0183] 1162: DigRF slave device

Claims

1. A pixel array included in an autofocus image sensor, the pixel array comprising: a substrate including a first surface and a second surface opposite the first surface, a gate electrode disposed on the first surface; a plurality of pixels located in the substrate, the plurality of pixels including a plurality of first pixels configured to detect a phase difference and a plurality of second pixels configured to detect an image; a deep device isolation region located in the substrate, the deep device isolation region extending substantially vertically from the second surface of the substrate to isolate the plurality of pixels from each other; and a plurality of first contact regions adjacent to the first surface in the substrate and adjacent to at least some of the plurality of first pixels only, a ground voltage applied to each of the plurality of first contact regions being transmitted to at least some of the plurality of second pixels via a space between the deep device isolation region and the first surface of the substrate.

2. The pixel array of claim 1, wherein: a number of the plurality of first contact regions is equal to a number of the plurality of first pixels, and the plurality of first contact regions is adjacent to all of the plurality of first pixels.

3. The pixel array of claim 1, wherein: a number of the plurality of first contact regions is less than a number of the plurality of first pixels, and the plurality of first contact regions is adjacent to some of the plurality of first pixels.

4. The pixel array of claim 1, wherein: the substrate contains an impurity of a first conductivity type, and the plurality of first contact regions contains the same type of impurity as the substrate at a higher density than a density of the substrate.

5. The pixel array of claim 1, further comprising: a plurality of second contact regions adjacent to the first surface in the substrate and adjacent to some of the plurality of second pixels only. a size of each of the plurality of second contact regions is smaller than a size of each of the plurality of first contact regions.

6. The pixel array of claim 5, wherein, 7. The pixel array of claim 1, further comprising: a light-shielding pattern located on the substrate, the light-shielding pattern being configured such that an amount of first light incident on each of the plurality of first pixels is less than an amount of second light incident on each of the plurality of second pixels.

8. The pixel array of claim 7, wherein: the first light and the second light are incident through the second surface, and the light-shielding pattern is located on the second surface.

9. The pixel array of claim 7, wherein: the deep device isolation region has a grid structure, in a plan view, the light-shielding pattern has the grid structure overlapping the deep device isolation region, and an area of the light-shielding pattern on each of the plurality of first pixels is greater than an area of the light-shielding pattern on each of the plurality of second pixels. the light-shielding pattern includes:

10. The pixel array of claim 9, wherein, a plurality of first openings at least partially exposing the plurality of first pixels.

11. The pixel array of claim 7, further comprising: a plurality of color filters located on the light-shielding pattern; ​ and a plurality of microlenses positioned on the plurality of color filters.

12. The pixel array of claim 1, wherein: the deep device isolation region has a mesh structure, and a portion of the deep device isolation region extends from the second surface of the substrate and is in direct contact with the first surface of the substrate.

13. The pixel array of claim 12, wherein: the plurality of pixels are divided into a plurality of pixel groups, each of the plurality of pixel groups includes at least one of the plurality of first pixels and at least one of the plurality of second pixels, and the portion of the deep device isolation region extends from the second surface of the substrate and is in direct contact with the first surface of the substrate to isolate the plurality of pixel groups from each other.

14. The pixel array of claim 13, wherein, the plurality of first contact regions are positioned in the substrate such that each of the plurality of pixel groups includes at least one of the plurality of first contact regions.

15. The pixel array of claim 1, wherein, a depth of the deep device isolation region is less than a thickness of the substrate.

16. The pixel array of claim 1, further comprising: a polysilicon pattern positioned in the deep device isolation region.

17. The pixel array of claim 1, wherein, each of the plurality of pixels includes: a photoelectric conversion region in which photoelectric conversion is performed based on incident light; and a floating diffusion region configured to accumulate photocharge collected in the photoelectric conversion region.

18. The pixel array of claim 17, wherein, the floating diffusion region is shared by at least two adjacent pixels among the plurality of pixels.

19. The pixel array of claim 17, wherein, a photoelectric conversion region included in the plurality of second pixels is larger than a photoelectric conversion region included in the plurality of first pixels.

20. An autofocus image sensor, comprising: a pixel array configured to generate a plurality of analog pixel signals based on incident light, the plurality of analog pixel signals representing phase difference information and image information; and a plurality of column driver circuits connected to a plurality of columns in the pixel array, the plurality of column driver circuits configured to convert the plurality of analog pixel signals to a plurality of digital signals, wherein the pixel array includes: a substrate including a first surface and a second surface opposite to the first surface, a gate electrode disposed on the first surface; a plurality of pixels positioned in the substrate, the plurality of pixels including a plurality of first pixels configured to detect a phase difference and a plurality of second pixels configured to detect an image; a deep device isolation region positioned in the substrate, the deep device isolation region extending substantially vertically from the second surface of the substrate to isolate the plurality of pixels from each other; and a plurality of first contact regions adjacent to the first surface in the substrate and adjacent to only at least some of the plurality of first pixels, a ground voltage applied to each of the plurality of first contact regions is transmitted to at least some of the plurality of second pixels via a space between the deep device isolation region and the first surface of the substrate.

Images