Display device

Abstract

The present disclosure relates to a display device, comprising: a substrate including a display area and a peripheral area outside the display area; a thin film transistor arranged in the display area; a display element arranged in the display area; an interlayer insulating layer covering the thin film transistor; a first conductive layer arranged above the interlayer insulating layer; a first insulating layer covering the first conductive layer; a pad arranged in the peripheral area; and a second conductive layer covering a central portion of the pad. The pad is connected to a connection line through a contact hole, and the connection line is arranged on the same first layer as the gate electrode of the thin film transistor. The side surface of the pad is covered by the first insulating layer or the second conductive layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0089201 filed on July 23, 2019, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Example embodiments relate to a display device, and more particularly, to a display device having improved reliability. Background Art

[0004] A display device typically includes a substrate having a display area and a peripheral area. In the display area, scan lines and data lines are insulated from each other and include a plurality of pixels. Each pixel includes a thin film transistor and a pixel electrode electrically connected to the thin film transistor. In addition, the display area includes a counter electrode commonly provided to the pixel. The peripheral area may include various lines that transmit electrical signals to the display area, a scan driver, a data driver, a controller, and a pad unit. Summary of the Invention

[0005] Exemplary embodiments include a display device capable of preventing defects of a pad unit disposed in a peripheral region while also achieving a high-quality image in a display region. However, the present disclosure is not limited thereto.

[0006] According to an exemplary embodiment, a display device includes: a substrate including a display area and a peripheral area outside the display area; a thin film transistor arranged in the display area; a display element arranged in the display area; an interlayer insulating layer covering the thin film transistor; a first conductive layer arranged above the interlayer insulating layer; a first insulating layer covering the first conductive layer; a pad arranged in the peripheral area; and a second conductive layer covering a central portion of the pad. The pad is connected to a connection line through a contact hole, and the connection line is arranged on the same first layer as the gate electrode of the thin film transistor. The side surface of the pad is covered by the first insulating layer or the second conductive layer.

[0007] In one exemplary embodiment, the pad includes a first pad layer on the same second layer as the source electrode of the thin film transistor, and a second pad layer on the same third layer as the first conductive layer. The first insulating layer has an opening that exposes a central portion of the second pad layer. The second conductive layer contacts the second pad layer through the opening in the first insulating layer.

[0008] In one exemplary embodiment, the second conductive layer includes titanium (Ti).

[0009] In an exemplary embodiment, the pad includes a metal having higher electrical conductivity than that of the second conductive layer.

[0010] In an exemplary embodiment, the display device further comprises: a connecting electrode connecting the drain electrode of the thin film transistor to the pixel electrode of the display element, wherein the connecting electrode comprises the same material as that of the second conductive layer.

[0011] In one exemplary embodiment, the pad includes a first pad layer on the same second layer as the source electrode of the thin film transistor. The first insulating layer and the interlayer insulating layer include an opening corresponding to a center portion of the first pad layer. The second conductive layer contacts the first pad layer through the opening in the first insulating layer and the interlayer insulating layer.

[0012] In one exemplary embodiment, the pad includes a first pad layer on the same second layer as the source electrode of the thin film transistor, the second conductive layer is disposed on the first pad layer, and the first insulating layer and the interlayer insulating layer cover side surfaces of the second conductive layer and the first pad layer.

[0013] According to an exemplary embodiment, a display device includes: a substrate including a display area and a peripheral area outside the display area; a thin film transistor arranged in the display area; a display element arranged in the display area; a pad arranged in the peripheral area; and a second conductive layer covering the side surface and top surface of the pad. The pad is connected to a connection line through a contact hole, and the connection line is arranged on the same first layer as the gate electrode of the thin film transistor.

[0014] In one exemplary embodiment, the second conductive layer includes titanium (Ti).

[0015] In one exemplary embodiment, the display device further includes a storage capacitor disposed in the display area, wherein a first electrode of the storage capacitor is disposed on the same first layer as the gate electrode of the thin film transistor, and a second electrode of the storage capacitor is disposed on the same second layer as the source electrode of the thin film transistor.

[0016] In one exemplary embodiment, the display device further includes: a first conductive layer disposed above the thin film transistor; a first pad layer on a second layer same as a source electrode of the thin film transistor; and a second pad layer on a third layer same as the first conductive layer, stacked in the pad.

[0017] According to an exemplary embodiment, a display device includes: a lower substrate including a display area and a peripheral area outside the display area; and a plurality of pixels arranged in the display area. Each pixel includes a thin film transistor and an organic light-emitting diode. The display device also includes: a thin film encapsulation layer covering the organic light-emitting diode and including at least one inorganic encapsulation layer and at least one organic encapsulation layer. The display device also includes: an upper substrate arranged above the thin film encapsulation layer and facing the lower substrate; a pad arranged in the peripheral area; and a second conductive layer covering a central portion of the pad. The side surface of the pad is covered by the second conductive layer or the first insulating layer.

[0018] In an exemplary embodiment, the pad is connected to a connection line through a contact hole, and the connection line is arranged on the same layer as a gate electrode of the thin film transistor.

[0019] In one exemplary embodiment, the second conductive layer includes titanium (Ti).

[0020] In one exemplary embodiment, the display device further includes a connecting electrode connecting the thin film transistor and the pixel electrode of the organic light emitting diode in each pixel, wherein the connecting electrode comprises the same material as that of the second conductive layer.

[0021] In an exemplary embodiment, the display device further includes: a conductive layer disposed on the thin film transistor and connected to the thin film transistor through a contact hole.

[0022] In an exemplary embodiment, the display device further includes: a plurality of color conversion layers disposed on the upper substrate and corresponding to at least a portion of the plurality of pixels, and including a plurality of quantum dots.

[0023] In an exemplary embodiment, the plurality of pixels include a first pixel, a second pixel, and a third pixel. One of the plurality of color conversion layers corresponding to the first pixel emits red light, one of the plurality of color conversion layers corresponding to the second pixel emits green light, and none of the plurality of color conversion layers is arranged corresponding to the third pixel.

[0024] In one exemplary embodiment, the display device further includes a plurality of color filters arranged on the upper substrate and corresponding to the plurality of pixels.

[0025] In one exemplary embodiment, the organic light emitting diodes included in the plurality of pixels emit blue light. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other features of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0027] Figure 1A is a schematic plan view of a display device according to an exemplary embodiment;

[0028] Figure 1B is a schematic plan view of a display device according to an exemplary embodiment;

[0029] Figure 1C According to an exemplary embodiment Figure 1A or Figure 1B A schematic plan view of an enlarged portion of a pad unit;

[0030] Figure 2A According to an exemplary embodiment, Figure 1A and Figure 1B An equivalent circuit diagram of a pixel in a display device;

[0031] Figure 2B According to an exemplary embodiment, Figure 1A and Figure 1B An equivalent circuit diagram of a pixel in a display device;

[0032] Figure 3 is a schematic cross-sectional view of a display device according to an exemplary embodiment;

[0033] Figure 4A is a schematic plan view of a pad of a display device according to an exemplary embodiment;

[0034] Figure 4B According to an exemplary embodiment, Figure 4A A schematic cross-sectional view taken along line II-II';

[0035] Figure 5A is a schematic cross-sectional view of a pad of a display device according to an exemplary embodiment;

[0036] Figure 5B According to an exemplary embodiment, Figure 5A A schematic cross-sectional view taken along line II-II';

[0037] Figure 6 is a schematic cross-sectional view of a display device according to an exemplary embodiment;

[0038] Figure 7 is a schematic cross-sectional view of a display device according to an exemplary embodiment;

[0039] Figure 8is a schematic cross-sectional view of a display device according to an exemplary embodiment;

[0040] Figure 9 is a schematic cross-sectional view of a display device according to an exemplary embodiment;

[0041] Figure 10 is a schematic cross-sectional view of a display device according to an exemplary embodiment;

[0042] Figure 11 is a schematic cross-sectional view of a display device according to an exemplary embodiment; and

[0043] Figure 12A and Figure 12B Experimental examples in which indium tin oxide (ITO) and titanium (Ti) were respectively formed on upper portions of pads are respectively shown. DETAILED DESCRIPTION

[0044] Exemplary embodiments will be described more fully hereinafter with reference to the accompanying drawings. Like reference numerals may refer to like elements throughout the drawings. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one of...", when following a list of elements, modify the entire list of elements and do not modify the individual elements in the list.

[0045] It will be understood that the terms "first," "second," "third," etc., are used herein to distinguish one element from another, and that the elements are not limited by these terms. Thus, a "first" element in one exemplary embodiment may be described as a "second" element in another exemplary embodiment.

[0046] As used herein, the singular forms "a," "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0047] In this disclosure, it should be understood that terms such as “comprising,” “having,” and “including” are intended to indicate the presence of features or components, and are not intended to exclude the possibility that one or more other features or components may be present or may be added.

[0048] It will be understood that when a component such as a film, region, layer, or element is referred to as being "on," "connected to," "coupled to," or "adjacent to" another component, it can be directly or indirectly on, connected to, coupled to, or adjacent to the other component (e.g., intervening components may or may not be present). For example, it will be understood that when a layer, region, or component is referred to as being "connected to" another layer, region, or component, it can not only be directly electrically connected to the other layer, region, or component, but can also be indirectly electrically connected to the other layer, region, or component, with other layers, regions, or components interposed between the layer, region, or component and the other layer, region, or component. It will also be understood that when a component is referred to as being between two components, it can be the only component between the two components, or one or more intervening components may also be present. It will also be understood that when a component is referred to as "overlying" another component, it can be the only component overlying the other component, or one or more intervening components may also overly the other component. Other words used to describe relationships between elements should be interpreted in a similar manner.

[0049] Display devices according to exemplary embodiments may include, for example, organic light emitting display devices, inorganic light emitting display devices (inorganic EL display devices), quantum dot light emitting display devices, field emission display devices, surface conduction electron emitter display devices, or plasma display devices.

[0050] When two or more elements are described herein as being formed of the same material, in exemplary embodiments, the material(s) of the two or more elements may be the same, without different material(s) being present in any of the two or more elements. Additionally, when two or more elements are described herein as being disposed on the same layer, in exemplary embodiments, the two or more elements may be disposed directly on and in direct contact with the same layer without intervening elements or layers being disposed therebetween.

[0051] It should be understood that descriptions of features or aspects within each exemplary embodiment should typically be considered as available for other similar features or aspects in other exemplary embodiments, unless the context clearly dictates otherwise.

[0052] Hereinafter, although an organic light emitting display device is described as an example of a display device according to an exemplary embodiment, the display device of the present disclosure is not limited thereto and may be various types of display devices.

[0053] Figure 1A and Figure 1B is a schematic plan view of a display device according to an exemplary embodiment.

[0054] refer to Figure 1A, a display device may be formed by joining the lower substrate 100 to the upper substrate 200 using a sealing member 600. The sealing member 600 may be formed to surround outer surfaces of the lower substrate 100 and the upper substrate 200 to couple the lower substrate 100 to the upper substrate 200.

[0055] The display device includes a display area DA and a peripheral area PA arranged around the display area DA. The display device may provide an image by using light emitted from a plurality of pixels P arranged in the display area DA.

[0056] The display area DA includes a plurality of pixels P connected to a plurality of data lines DL extending in a first direction and to a plurality of scan lines SL extending in a second direction intersecting the first direction. Each pixel P is also connected to a driving voltage line PL extending in the first direction.

[0057] Each pixel P may include a display element such as an organic light emitting diode (OLED). Each pixel P may emit, for example, red, green, blue, or white light from the organic light emitting diode OLED. The pixel P of the present disclosure may be a sub-pixel that emits any one of red, green, blue, and white light. In an exemplary embodiment, all the organic light emitting diodes OLED included in the pixel P may emit light of the same color, and the color of each pixel P may be achieved by, for example, a color filter arranged on the upper portion of the organic light emitting diode OLED.

[0058] Each pixel P may be electrically connected to a built-in circuit disposed in the peripheral area PA. A first power line 10, a second power line 20, and a pad unit 30 may be disposed in the peripheral area PA.

[0059] The first power line 10 may be arranged to correspond to one side of the display area DA. The first power line 10 may be connected to a drive voltage ELVDD (see the following description). Figure 2A and Figure 2B ) are transmitted to a plurality of driving voltage lines PL of the pixels P.

[0060] The second power line 20 may partially surround the display area DA in a loop shape with one side open. For example, the second power line 20 may be provided on three of the four sides surrounding the display area DA. The second power line 20 may provide a common voltage to the counter electrode of the pixel P. The second power line 20 may be referred to as a common voltage supply line.

[0061] The pad unit 30 may include a plurality of pads 31 and may be arranged on one side of the lower substrate 100. For example, the pad unit 30 including a plurality of pads 31 may be provided on the lower side of the lower substrate 100, as shown in FIG. Figure 1AAs shown in . However, the present disclosure is not limited thereto. Each pad 31 can be connected to the first connection line 11 connected to the first power line 10, or can be connected to the connection line CW extending to the display area DA. The pads 31 of the pad unit 30 can be exposed by not being covered by the insulating layer and can be electrically connected to the printed circuit board PCB. The PCB terminal unit PCB-P of the printed circuit board PCB can be electrically connected to the pad unit 30.

[0062] The printed circuit board PCB transmits a signal or power of the controller to the pad unit 30. The controller can transmit the driving voltage ELVDD and the common voltage ELVSS (see the following description) through the first connection line 11 and the second connection line 21. Figure 2A and Figure 2B ) are provided to the first power line 10 and the second power line 20 respectively.

[0063] The data driver circuit 60 is electrically connected to a plurality of data lines DL. Data signals from the data driver circuit 60 can be provided to each pixel P via connection lines CW connected to the pad unit 30 and data lines DL connected to the connection lines CW. Although FIG. 1 illustrates the data driver circuit 60 as being disposed on a printed circuit board PCB, the present disclosure is not limited thereto. For example, in one exemplary embodiment, the data driver circuit 60 can be disposed above the lower substrate 100. For example, the data driver circuit 60 can be disposed between the pad unit 30 and the first power line 10.

[0064] The dam unit 120 may be arranged in the peripheral area PA. When the organic encapsulation layer 420 (see FIG. 4 ) of the thin film encapsulation layer 400 is formed Figure 10 ), the dam unit 120 can prevent the formation of an edge tail of the organic encapsulation layer 420 by preventing the organic material from flowing in the edge direction of the lower substrate 100. The dam unit 120 can be arranged in the peripheral area PA to surround at least a portion of the display area DA. The dam unit 120 may include a plurality of dams, and when a plurality of dams are arranged, each dam may be spaced apart from each other. The dam unit 120 may be arranged closer to the display area DA than the sealing member 600 in the peripheral area PA. A built-in driving circuit unit that provides a scan signal for each pixel P may be further included in the peripheral area PA. In an exemplary embodiment, the built-in driving circuit unit and the dam unit 120 may overlap each other.

[0065] Although Figure 1A It is shown that one printed circuit board PCB is attached to the pad unit 30, but the present disclosure is not limited thereto. For example, in an exemplary embodiment, a plurality of printed circuit boards PCB may be attached to the pad unit 30, as in Figure 1B As shown in .

[0066] In addition, in an exemplary embodiment, the pad unit 30 may be arranged along two sides of the lower substrate 100, as shown in FIG. Figure 1B The pad unit 30 may include a plurality of sub-pad units 30S, and one printed circuit board PCB may be attached to each sub-pad unit 30S.

[0067] Figure 1C According to an exemplary embodiment Figure 1A or Figure 1B FIG. 1 is a schematic plan view of an enlarged portion of the pad unit 30 .

[0068] refer to Figure 1C The pad 31 may be connected to the connection line CW extending to the display area DA through the first contact hole CNT1, and the upper portion of the pad 31 may be covered by the second conductive layer C-PVX. The pad 31 may be formed of a metal having higher electrical conductivity than the second conductive layer C-PVX.

[0069] Figure 2A and Figure 2B is an equivalent circuit diagram of a pixel P of a display device according to an exemplary embodiment.

[0070] refer to Figure 2A , each pixel P includes a pixel circuit PC connected to a scan line SL and a data line DL, and an organic light emitting diode OLED connected to the pixel circuit PC.

[0071] The pixel circuit PC includes a driving thin film transistor T1, a switching thin film transistor T2, and a storage capacitor Cst. The switching thin film transistor T2 is connected to a scan line SL and a data line DL, and transmits a data signal Dm input through the data line DL to the driving thin film transistor T1 according to a scan signal Sn input through the scan line SL.

[0072] The storage capacitor Cst is connected to the switching thin film transistor T2 and the driving voltage line PL and stores a voltage corresponding to a difference between a voltage received from the switching thin film transistor T2 and a driving voltage ELVDD (or power supply voltage) supplied to the driving voltage line PL.

[0073] The driving thin film transistor T1 can be connected to the driving voltage line PL and the storage capacitor Cst, and can control the driving current flowing from the driving voltage line PL to the organic light emitting diode OLED according to the voltage value stored in the storage capacitor Cst. The organic light emitting diode OLED can emit light with a certain brightness according to the driving current.

[0074] although Figure 2A It is shown that the pixel circuit PC includes two thin film transistors T1 , T2 and one storage capacitor Cst, but the present disclosure is not limited thereto.

[0075] refer to Figure 2BEach pixel P may include an organic light emitting diode (OLED) and a pixel circuit PC including a plurality of thin film transistors for driving the organic light emitting diode (OLED). The pixel circuit PC may include a driving thin film transistor T1, a switching thin film transistor T2, a sensing thin film transistor T3, and a storage capacitor Cst.

[0076] The scan line SL may be connected to the gate electrode G2 of the switching thin film transistor T2 , the data line DL may be connected to the source electrode S2 of the switching thin film transistor T2 , and the first electrode CE1 of the storage capacitor Cst may be connected to the drain electrode D2 of the switching thin film transistor T2 .

[0077] Therefore, in response to the scan signal Sn from the scan line SL of each pixel P, the switching thin film transistor T2 supplies the voltage of the data signal Dm input through the data line DL to the first node N.

[0078] The gate electrode G1 of the driving thin film transistor T1 can be connected to the first node N, the source electrode S1 of the driving thin film transistor T1 can be connected to the driving voltage line PL transmitting the driving voltage ELVDD, and the drain electrode D1 of the driving thin film transistor T1 can be connected to the anode electrode of the organic light emitting diode OLED.

[0079] Therefore, the driving thin film transistor T1 may adjust the amount of current flowing to the organic light emitting diode OLED according to the voltage (Vgs) between the source and gate electrodes of the driving thin film transistor T1 , ie, the voltage between the driving voltage ELVDD and the first node N.

[0080] The sensing control line SSL is connected to the gate electrode G3 of the sensing thin film transistor T3, the source electrode S3 of the sensing thin film transistor T3 is connected to the second node S, and the drain electrode D3 of the sensing thin film transistor T3 is connected to the reference voltage line RL. In other exemplary embodiments, the sensing thin film transistor T3 may be controlled by the scan line SL instead of the sensing control line SSL.

[0081] The sensing thin film transistor T3 can sense the potential of the pixel electrode (e.g., the anode electrode) of the organic light emitting diode OLED. The sensing thin film transistor T3 can supply a precharge voltage from the reference voltage line RL to the second node S in response to a sensing signal SSn from the sensing control line SSL, or can supply the voltage of the pixel electrode (e.g., the anode electrode) of the organic light emitting diode OLED to the reference voltage line RL during a sensing period.

[0082] A first electrode CE1 of the storage capacitor Cst is connected to a first node N, and a second electrode CE2 of the storage capacitor Cst is connected to a second node S. The storage capacitor Cst charges a voltage difference between voltages supplied to the first node N and the second node S, respectively, and supplies the charged voltage difference as a driving voltage of the driving thin film transistor T1. For example, the storage capacitor Cst may charge a voltage difference between a voltage of the data signal Dm supplied to the first node N and the second node S, respectively, and a precharge voltage (Vpre).

[0083] The bias electrode BSM may be formed to correspond to the driving thin film transistor T1 and may be connected to the source electrode S3 of the sensing thin film transistor T3. The bias electrode BSM may receive a voltage related to the potential of the source electrode S3 of the sensing thin film transistor T3, and thus the driving thin film transistor T1 may be stabilized. In other exemplary embodiments, the bias electrode BSM is not connected to the source electrode S3 of the sensing thin film transistor T3 and may be connected to a separate bias line.

[0084] The counter electrode (eg, cathode electrode) of the organic light emitting diode OLED receives a common voltage ELVSS. The organic light emitting diode OLED receives a driving current from the driving thin film transistor T1 to emit light.

[0085] although Figure 2B Each pixel P is shown to include signal lines SL, SSL, and DL, a reference voltage line RL, and a drive voltage line PL, but the present disclosure is not limited thereto. For example, in an exemplary embodiment, at least one of the signal lines SL, SSL, and DL and / or the reference voltage line RL and the drive voltage line PL may be shared by adjacent pixels.

[0086] The pixel circuit PC is not limited to the reference Figure 2A and Figure 2B The number of thin film transistors and storage capacitors and the circuit design are described, and the number of thin film transistors and storage capacitors and the circuit design may be variously changed.

[0087] Figure 3 It is along Figure 1A Line I-I' and Figure 1C 1 is a cross-sectional view of a portion of a display device according to an exemplary embodiment taken along line II-II′.

[0088] refer to Figure 3 According to an exemplary embodiment, the display device includes a pad 31 in the peripheral area PA. The edge (or side surface) of the pad 31 may be covered by the first insulating layer PVX, and the center portion of the pad 31 may be covered by the second conductive layer C-PVX.

[0089] The second conductive layer C-PVX may include a metal having a lower degree of oxidation than the material forming the pad 31 or a metal having higher corrosion resistance than the material forming the pad 31. The pad 31 may include a multilayer structure. In this case, the second conductive layer C-PVX may include a metal having a lower degree of oxidation than the uppermost layer of the pad 31 or a metal having higher corrosion resistance than the uppermost layer of the pad 31. In an exemplary embodiment, the pad 31 or the uppermost layer of the pad 31 may include copper (Cu), and the second conductive layer C-PVX may include titanium (Ti). In an exemplary embodiment, the pad 31 may include a first pad layer 31a and a second pad layer 31b, and each of the first pad layer 31a and the second pad layer 31b may include a multilayer structure.

[0090] Figure 3 Shown is a reference Figure 2A and Figure 2B The driving thin film transistor T1 and the storage capacitor Cst of the pixel circuit PC of each pixel P are included in the display area DA. For the convenience of description, the arrangement of the thin film transistors T1 and the storage capacitor Cst will now be described in terms of stacking order. Figure 3 The structure in .

[0091] The lower substrate 100 may include, for example, glass, ceramic, metal, or polymer resin such as polyimide. The lower substrate 100 may have a single-layer structure or a multi-layer structure, and may further include an inorganic layer in the case of the multi-layer structure.

[0092] The first buffer layer 111 may be disposed on the lower substrate 100. The first buffer layer 111 may prevent or reduce impurities from penetrating from the lower substrate 100 into the semiconductor layer A1. The first buffer layer 111 may include, for example, silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or zinc oxide (ZnO).

[0093] The bias electrode BSM may be arranged on the first buffer layer 111 to correspond to the driving thin film transistor T1. For example, the bias electrode BSM may overlap the semiconductor layer A1 of the driving thin film transistor T1. A voltage may be applied to the bias electrode BSM. For example, the bias electrode BSM may be connected to the sensing thin film transistor T3 (see FIG. Figure 2B ) of the source electrode S3 (see Figure 2B ) to be applied with the voltage of the source electrode S3. In addition, the bias electrode BSM can prevent external light from reaching the semiconductor layer A1. Therefore, the characteristics of the driving thin film transistor T1 can be stabilized. In an exemplary embodiment, the bias electrode BSM can be omitted.

[0094] The second buffer layer 112 may cover the bias electrode BSM and may be formed on the entire top surface of the lower substrate 100. The second buffer layer 112 may include, for example, silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or zinc oxide (ZnO).

[0095] The semiconductor layer A1 may be disposed on the second buffer layer 112. The semiconductor layer A1 may include, for example, amorphous silicon or polycrystalline silicon. In an exemplary embodiment, the semiconductor layer A1 may include an oxide of at least one or more materials selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). In an exemplary embodiment, the semiconductor layer A1 may include a zinc oxide-based material and may include, for example, Zn oxide, In-Zn oxide, or Ga-In-Zn oxide. In an exemplary embodiment, the semiconductor layer A1 may include, for example, In-Ga-Zn-O (IGZO), In-Sn-Zn-O (ITZO), or In-Ga-Sn-Zn-O (IGTZO) semiconductors, which include metals such as In, Ga, and tin (Sn) in ZnO. The semiconductor layer A1 may include a channel region and a source region and a drain region disposed on both sides of the channel region. The semiconductor layer A1 may include a single layer or multiple layers.

[0096] The gate electrode G1 is arranged above the semiconductor layer A1 to at least partially overlap with the semiconductor layer A1, with a gate insulating layer 113 located between the semiconductor layer A1 and the gate electrode G1. The gate electrode G1 may include, for example, molybdenum (Mo), Al, Cu, or Ti, and may include a single layer or multiple layers. The first electrode CE1 of the storage capacitor Cst may be arranged on the same layer as the gate electrode G1. The first electrode CE1 may include the same material as the gate electrode G1.

[0097] The connection line CW may be arranged on the gate insulating layer 113 located in the peripheral area PA. The connection line CW may extend to the display area DA and may be connected to a line arranged on a different layer through a contact hole. In the peripheral area PA, the connection line CW may be connected to the pad 31 through a first contact hole CNT1 defined in the first interlayer insulating layer 115. The connection line CW may be arranged on the same layer as the gate electrode G1 of the driving thin film transistor T1. For example, in one exemplary embodiment, both the connection line CW and the gate electrode G1 are directly disposed on and directly contact the gate insulating layer 113.

[0098] The gate insulating layer 113 may include an inorganic insulating material. The gate insulating layer 113 may include, for example, silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or zinc oxide (ZnO).

[0099] The first interlayer insulating layer 115 may cover the gate electrode G1 and the first electrode CE1 of the storage capacitor Cst. The first interlayer insulating layer 115 may include, for example, silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or zinc oxide (ZnO).

[0100] The second electrode CE2 of the storage capacitor Cst, the source electrode S1, the drain electrode D1, and the driving voltage line PL may be disposed on the first interlayer insulating layer 115. In the peripheral area PA, the first pad layer 31a may be disposed on the first interlayer insulating layer 115. The first pad layer 31a may be disposed on the same layer as the second electrode CE2 of the storage capacitor Cst, the source electrode S1, the drain electrode D1, and the driving voltage line PL. For example, in one exemplary embodiment, each of the first pad layer 31a, the second electrode CE2 of the storage capacitor Cst, the source electrode S1, the drain electrode D1, and the driving voltage line PL is directly disposed on and directly contacts the first interlayer insulating layer 115. The first pad layer 31a may contact the connection line CW through the first contact hole CNT1.

[0101] The second electrode CE2 of the storage capacitor Cst, the source electrode S1, the drain electrode D1, the driving voltage line PL, and the first pad layer 31a may include a conductive material including, for example, Mo, Al, Cu, or Ti, and may include a single layer or multiple layers including the above materials. In one exemplary embodiment, the second electrode CE2 of the storage capacitor Cst, the source electrode S1, the drain electrode D1, the driving voltage line PL, and the first pad layer 31a may include a Ti / Cu multilayer structure including a first layer including Ti and a second layer including Cu. The source electrode S1 and the drain electrode D1 may be connected to the source region or the drain region of the semiconductor layer A1 through contact holes.

[0102] The second electrode CE2 of the storage capacitor Cst overlaps the first electrode CE1, with the first interlayer insulating layer 115 located therebetween to form a capacitor. In this case, the first interlayer insulating layer 115 may function as a dielectric layer of the storage capacitor Cst. The thickness of the first interlayer insulating layer 115 may be designed according to the capacitance value of the storage capacitor Cst.

[0103] The second interlayer insulating layer 117 may be disposed on the second electrode CE2 of the storage capacitor Cst, the source electrode S1 of the driving thin film transistor T1, the drain electrode D1 of the driving thin film transistor T1, and the driving voltage line PL. Figure 3 As shown in , the second interlayer insulating layer 117 can contact and cover at least a portion of the drain electrode D1 of the driving thin film transistor T1, can cover at least a portion of the gate electrode G1 of the driving thin film transistor T1 (with the first interlayer insulating layer 115 interposed therebetween), can cover at least a portion of the semiconductor layer A1 of the driving thin film transistor T1 (with the first interlayer insulating layer 115, the gate electrode G1 and the gate insulating layer 113 interposed therebetween), and can contact and cover at least a portion of the source electrode S1 of the driving thin film transistor T1. Therefore, the second interlayer insulating layer 117 can be said to cover the driving thin film transistor T1. The second interlayer insulating layer 117 may include an inorganic insulating layer, and the inorganic insulating layer includes, for example, silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or zinc oxide (ZnO).

[0104] A conductive layer PL', also referred to herein as the first conductive layer PL', may be disposed on the second interlayer insulating layer 117. The first conductive layer PL' may contact the driving voltage line PL or the source electrode S1 of the driving thin film transistor T1 below the first conductive layer PL' via a contact hole penetrating the second interlayer insulating layer 117. The first conductive layer PL' may be connected to the driving voltage line PL to function as a line for transmitting a driving voltage. The inclusion of the first conductive layer PL' prevents a voltage drop in the driving voltage, and provides a uniform driving voltage across the display device.

[0105] In the peripheral area PA, the second interlayer insulating layer 117 may include an opening hole 117h that covers the edge (or side surface) of the first pad layer 31a and exposes the central portion of the first pad layer 31a. A second pad layer 31b may be provided to correspond to the opening hole 117h of the second interlayer insulating layer 117. The second pad layer 31b may be formed on the second interlayer insulating layer 117 and may contact the first pad layer 31a through the opening hole 117h of the second interlayer insulating layer 117. The second pad layer 31b may be provided on the same layer as the first conductive layer PL'. For example, in one exemplary embodiment, the second pad layer 31b and the first conductive layer PL' are directly provided on the second interlayer insulating layer 117 and directly contact the second interlayer insulating layer 117. The second pad layer 31b may be formed of the same material as the first conductive layer PL' at the same time as the first conductive layer PL' is formed. The formation of the second pad layer 31b may reduce the resistance of the pad 31.

[0106] An upper conductive layer spaced apart from the first conductive layer PL' may be further disposed over the second interlayer insulating layer 117. The upper conductive layer may be connected to the conductive layer disposed over the first interlayer insulating layer 115. The first conductive layer PL' and the second pad layer 31b may include a conductive material including, for example, Mo, Al, Cu, or Ti, and may include a single layer or multiple layers including the above materials. In one exemplary embodiment, the first conductive layer PL' and the second pad layer 31b may have a Ti / Cu multilayer structure including a first layer including Ti and a second layer including Cu.

[0107] The first conductive layer PL′ and the upper conductive layer disposed on the second interlayer insulating layer 117 may be covered by the first insulating layer PVX.

[0108] The first insulating layer PVX may include an inorganic material. The first insulating layer PVX may include, for example, SiN x and silicon oxide (SiO x ) is a single film or a multilayer film. The first insulating layer PVX can cover and protect a portion of the conductive layer or line arranged above the second interlayer insulating layer 117. A portion of the conductive layer and / or line formed together in the same process as the first conductive layer PL' may be exposed in a portion of the area of the lower substrate 100 (for example, a portion of the peripheral area PA). The exposed portion of the conductive layer and / or line may be damaged by an etchant during the patterning of the pixel electrode 310 to be described below, and since the first insulating layer PVX covers at least a portion of the conductive layer and / or line, it is possible to prevent the line from being damaged during the patterning process of the pixel electrode 310.

[0109] In addition, a planarization layer 118 including an organic material may be disposed on the first insulating layer PVX. Referring to the comparative example, when the first insulating layer PVX is not included, the first conductive layer PL' may be oxidized or corroded by reacting with oxygen penetrating into the planarization layer 118. However, in an exemplary embodiment, including the first insulating layer PVX can prevent the first conductive layer PL' from directly contacting the planarization layer 118, thereby preventing oxidation of the first conductive layer PL' and preventing changes in characteristics caused by oxidation.

[0110] The first insulating layer PVX may include an opening hole PVXh corresponding to the pad 31 of the peripheral area PA. For example, the first insulating layer PVX may include an opening hole PVXh that covers the edge (or side surface) of the pad 31 and exposes the central portion of the pad 31. The second conductive layer C-PVX may be arranged to correspond to the opening hole PVXh of the first insulating layer PVX. For example, in an exemplary embodiment, the side surface of the pad 31 may be covered by the first insulating layer PVX, and the central portion of the pad 31 may be covered by the second conductive layer C-PVX.

[0111] Because the pads 31 are subsequently electrically connected to an external device or a printed circuit board PCB (see FIG. 1 ), a portion of the first insulating layer PVX may be removed to expose the pads 31. In this case, the pads 31 may be damaged by an etchant used in a subsequent process.

[0112] The second conductive layer C-PVX may be a layer provided to protect the pad 31 from damage. In addition, the second conductive layer C-PVX may be a conductive medium to allow the pad 31 to be electrically connected to an external terminal. The second conductive layer C-PVX may be in direct contact with the second pad layer 31b through the opening hole PVXh of the first insulating layer PVX.

[0113] In an exemplary embodiment, the second conductive layer C-PVX may include a metal having a lower oxidation degree than that of the material forming the pad 31 or a metal having higher corrosion resistance than that of the material forming the pad 31. In an exemplary embodiment, the second conductive layer C-PVX may include Ti.

[0114] When the second conductive layer C-PVX includes a conductive oxide such as, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO) or aluminum zinc oxide (AZO), because the material has pinholes formed therein, the etchant may flow through the pinholes into the pad 31 below the pinholes.

[0115] In one exemplary embodiment, the second conductive layer C-PVX may include a metal instead of a conductive oxide to reduce the effect of pinholes. In addition, in one exemplary embodiment, the second conductive layer C-PVX includes a material having a lower degree of oxidation than the material included in the pad 31, for example, a material whose characteristics do not change even when exposed to the outside.

[0116] In the display area DA, a planarization layer 118 may be disposed on the first insulating layer PVX, and an organic light emitting diode OLED may be disposed on the planarization layer 118 .

[0117] The planarization layer 118 may include a single layer or multiple layers of a film including an organic material and provide a flat upper surface. The planarization layer 118 may include, for example, benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HDMSO), conventional commercial polymers such as poly(methyl methacrylate) (PMMA) or polystyrene (PS), polymer derivatives having phenol groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluoropolymers, p-xylene polymers, vinyl alcohol polymers, and mixtures thereof.

[0118] In the lower substrate 100 located in the display area DA, the organic light emitting diode OLED may be disposed on the planarization layer 118. The organic light emitting diode OLED includes a pixel electrode 310, an intermediate layer 320 including an organic emission layer, and an opposing electrode 330.

[0119] The pixel electrode 310 may include a (semi) transparent electrode or a reflective electrode. In an exemplary embodiment, the pixel electrode 310 may include a reflective layer and a transparent or semi-transparent electrode layer formed on the reflective layer, the reflective layer including, for example, silver (Ag), magnesium (Mg), Al, platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) or a compound thereof. The transparent or semi-transparent electrode layer may include at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO) and aluminum zinc oxide (AZO). In an exemplary embodiment, the pixel electrode 310 may include ITO / Ag / ITO.

[0120] A pixel-defining film 119 may be disposed on the planarization layer 118. The pixel-defining film 119 may define the emission region of the pixel P by having an opening corresponding to each sub-pixel in the display area DA, for example, an opening OP that exposes at least the central portion of the pixel electrode 310. Furthermore, the pixel-defining film 119 may prevent arcing at the edge (or side surface) of the pixel electrode 310 by increasing the distance between the edge (or side surface) of the pixel electrode 310 and the counter electrode 330 above the pixel electrode 310.

[0121] The pixel defining film 119 may be formed of one or more organic insulating materials selected from the group including, for example, polyimide, polyamide, acrylic resin, BCB, and phenolic resin, by, for example, a spin coating method.

[0122] The intermediate layer 320 of the organic light emitting diode OLED may include an organic emission layer. The organic emission layer may include an organic material including a fluorescent or phosphorescent material that emits red, green, blue or white light. The organic emission layer may include a low molecular weight material or a polymer material, and functional layers such as, for example, a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL) or an electron injection layer (EIL), which may be selectively arranged below or above the organic emission layer. The intermediate layer 320 may be arranged to correspond to each of the plurality of pixel electrodes 310. However, the intermediate layer 320 is not limited thereto. For example, various modifications may be made, such as including an intermediate layer 320 of a monomer layer above the plurality of pixel electrodes 310.

[0123] The counter electrode 330 may include a transparent electrode or a reflective electrode. In an exemplary embodiment, the counter electrode 330 may include a transparent or translucent electrode and may include a metal film having a small work function and including, for example, lithium (Li), calcium (Ca), lithium fluoride (LiF) / Ca, LiF / Al, Al, Ag, Mg or a compound thereof. In addition, a transparent conductive oxide (TCO) film such as ITO, IZO, ZnO or In2O3 may be further arranged on the metal film. The counter electrode 330 may be arranged above the display area DA and the peripheral area PA, and may be arranged on the intermediate layer 320 and the pixel defining film 119. The counter electrode 330 may be formed as a monomer in a plurality of organic light emitting diodes OLED to correspond to a plurality of pixel electrodes 310.

[0124] A spacer 119S may be further included on the pixel defining film 119. The spacer 119S may prevent damage caused by the mask. The spacer 119S and the pixel defining film 119 may be formed as a single body. For example, the spacer 119S and the pixel defining film 119 may be formed simultaneously in the same process using a half-tone mask process.

[0125] The pixel electrode 310 can be connected to the drain electrode D1 of the driving thin film transistor T1 via the connection electrode CM. The connection electrode CM can be connected to the drain electrode D1 of the driving thin film transistor T1 via a contact hole that penetrates the second interlayer insulating layer 117 and the first insulating layer PVX. The pixel electrode 310 can also be connected to the connection electrode CM via a contact hole that penetrates the planarization layer 118. The connection electrode CM can prevent damage to the drain electrode D1 of the driving thin film transistor T1. The connection electrode CM can be formed of the same material as the second conductive layer C-PVX at the same time as the second conductive layer C-PVX is formed.

[0126] Figure 4A is a schematic plan view of a pad 32 of a display device according to an exemplary embodiment. Figure 4B According to an exemplary embodiment Figure 4A The cross-sectional view of the pad 32 is taken along the line II-II'. Figure 4A and Figure 4B In, and Figure 3 The same reference numerals as those in the drawings denote the same components. Therefore, for convenience of explanation, redundant descriptions thereof will be omitted.

[0127] refer to Figure 4A and Figure 4B According to an exemplary embodiment, a display device may include a pad 32 in the peripheral area PA. The edge (or side surface) of the pad 32 may be covered by the second interlayer insulating layer 117 and / or the first insulating layer PVX, and the center portion of the pad 32 may be covered by the second conductive layer C-PVX.

[0128] In an exemplary embodiment, the pad 32 may include only a first pad layer 31a. The first pad layer 31a may be connected to the connection line CW through a first contact hole CNT1 penetrating the first interlayer insulating layer 115. The edge (or side surface) of the first pad layer 31a may be covered by the second interlayer insulating layer 117 and / or the first insulating layer PVX, and the central portion of the first pad layer 31a may be covered by the second conductive layer C-PVX. The second conductive layer C-PVX may be arranged inside the opening hole PVXh of the first insulating layer PVX and the opening hole 117h of the second interlayer insulating layer 117, and may be in direct contact with the upper surface of the first pad layer 31a. In addition, a portion of the second conductive layer C-PVX may extend to the upper surface of the first insulating layer PVX.

[0129] The first pad layer 31a may include a metal having excellent electrical conductivity. For example, the first pad layer 31a may include Cu. In an exemplary embodiment, the first pad layer 31a may include a Ti / Cu multilayer including a first layer including Ti and a second layer on the first layer including Cu. The second layer of the first pad layer 31a may include a material having a high degree of oxidation and may be easily damaged by an etchant during certain processes.

[0130] The second conductive layer C-PVX may include a metal having a lower degree of oxidation than the material of the pad 32 (e.g., the first pad layer 31a) or a metal having higher corrosion resistance than the material of the pad 32 (e.g., the first pad layer 31a). In an exemplary embodiment, the second conductive layer C-PVX may include Ti.

[0131] In an exemplary embodiment, since the edge (or side surface) of the pad 32 is covered by the first insulating layer PVX and / or the second interlayer insulating layer 117, and the central portion of the pad 32 is covered by the second conductive layer C-PVX, damage to the pad 32 by the etchant used during certain processes can be reduced and oxidation of the pad 32 can be prevented.

[0132] Figure 5A is a schematic plan view of a pad 32 of a display device according to an exemplary embodiment. Figure 5B According to an exemplary embodiment Figure 5A The cross-sectional view of the pad 32 is taken along the line II-II'. Figure 5A and Figure 5B In, and Figure 3 The same reference numerals as those in the drawings denote the same components. Therefore, for convenience of explanation, redundant descriptions thereof will be omitted.

[0133] refer to Figure 5A and Figure 5B According to an exemplary embodiment, a display device may include a pad 32 in the peripheral area PA. The edge (or side surface) of the pad 32 may be covered by the second interlayer insulating layer 117 and / or the first insulating layer PVX, and the center portion of the pad 32 may be covered by the second conductive layer C-PVX.

[0134] In an exemplary embodiment, the pad 32 may include only the first pad layer 31a. The first pad layer 31a may be connected to the connection line CW through the first contact hole CNT1 penetrating the first interlayer insulating layer 115. The edge (or side surface) of the first pad layer 31a may be covered by the second interlayer insulating layer 117 and / or the first insulating layer PVX, and the center portion of the first pad layer 31a may be covered by the second conductive layer C-PVX.

[0135] In one exemplary embodiment, the second conductive layer C-PVX may be formed before forming the second interlayer insulating layer 117. For example, after the conductive layer forming the first pad layer 31a is deposited, the conductive layer forming the second conductive layer C-PVX is deposited on the conductive layer forming the first pad layer 31a. Then, the conductive layer forming the first pad layer 31a and the conductive layer forming the second conductive layer C-PVX are simultaneously etched to form the first pad layer 31a and the second conductive layer C-PVX.

[0136] Next, the second interlayer insulating layer 117 and the first insulating layer PVX may be formed, and an opening hole 117h and PVXh exposing a central portion of the second conductive layer C-PVX may be formed.

[0137] Therefore, the second conductive layer C-PVX can be arranged inside the opening hole PVXh of the first insulating layer PVX and the opening hole 117h of the second interlayer insulating layer 117, and can directly contact the upper surface of the first pad layer 31a. In addition, the side surface of the second conductive layer C-PVX can be covered by the second interlayer insulating layer 117 and / or the first insulating layer PVX. The side surface of the pad 32 can also be covered by the second interlayer insulating layer 117 and / or the first insulating layer PVX.

[0138] The first pad layer 31a may include a metal having excellent electrical conductivity. For example, the first pad layer 31a may include Cu. In an exemplary embodiment, the first pad layer 31a may include a Ti / Cu multilayer including a first layer including Ti and a second layer on the first layer including Cu. The second layer of the first pad layer 31a may include a material having a high degree of oxidation and may be easily damaged by an etchant during certain processes.

[0139] The second conductive layer C-PVX may include a metal having a lower degree of oxidation than the material of the pad 32 (e.g., the first pad layer 31a) or a metal having higher corrosion resistance than the material of the pad 32 (e.g., the first pad layer 31a). In an exemplary embodiment, the second conductive layer C-PVX may include Ti.

[0140] In an exemplary embodiment, since the side surfaces of the pad 32 are covered by the first insulating layer PVX and / or the second interlayer insulating layer 117, and the central portion of the pad 32 is covered by the second conductive layer C-PVX, damage to the pad 32 by the etchant during certain processes can be reduced and oxidation of the pad 32 can be prevented.

[0141] Figure 6 is a cross-sectional view of a portion of a display device according to an exemplary embodiment, specifically illustrating the periphery of the pad 31. Figure 6 In, and Figure 3The same reference numerals as those in the drawings denote the same components. Therefore, for convenience of explanation, redundant descriptions thereof will be omitted.

[0142] refer to Figure 6 , a display device according to an exemplary embodiment may include a pad 31 in the peripheral area PA, and an edge (or side surface) of the pad 31 and a central portion of the pad 31 may be covered by the second conductive layer C-PVX.

[0143] In an exemplary embodiment, the second conductive layer C-PVX may cover the upper surface and the side surface of the pad 31. The width Wc of the second conductive layer C-PVX may be greater than the width Wp of the pad 31 to cover the side surface of the pad 31. Figure 6 In an exemplary embodiment shown in , since the second conductive layer C-PVX covers and protects the side surface of the pad 31, the first insulating layer PVX is not included.

[0144] The pad 31 may include a first pad layer 31a and a second pad layer 31b, and the second conductive layer C-PVX may cover the side surface of the second pad layer 31b. The side surface of the second pad layer 31b may be covered by the second interlayer insulating layer 117.

[0145] In the display area DA, the additional second conductive layer C-PVX' may be disposed on the first conductive layer PL' located on the second interlayer insulating layer 117. The width of the additional second conductive layer C-PVX' may be greater than the width of the first conductive layer PL'. The additional second conductive layer C-PVX' may cover the upper surface and side surfaces of the first conductive layer PL' so that the first conductive layer PL' does not directly contact the planarization layer 118. Therefore, damage and oxidation of the first conductive layer PL' can be prevented during the process.

[0146] The first conductive layer PL', the first pad layer 31a, and the second pad layer 31b may include a metal having excellent electrical conductivity. For example, the first conductive layer PL', the first pad layer 31a, and the second pad layer 31b may include Cu. In an exemplary embodiment, the first conductive layer PL', the first pad layer 31a, and the second pad layer 31b may include a Ti / Cu multilayer including a first layer including Ti and a second layer on the first layer including Cu.

[0147] The second conductive layer C-PVX may include a metal having a lower oxidation degree than that of the material included in the upper portion of the pad 31 or a metal having higher corrosion resistance than that of the material included in the upper portion of the pad 31. In an exemplary embodiment, the second conductive layer C-PVX may include Ti.

[0148] In exemplary embodiments, since the side surface and the center portion of the pad 31 are covered by the second conductive layer C-PVX, damage to the pad 31 by an etchant during certain processes may be reduced, and oxidation of the pad 31 may be prevented.

[0149] Figure 7 is a cross-sectional view of a portion of a display device according to an exemplary embodiment, which specifically illustrates the periphery of the pad 32. Figure 7 In, and Figure 3 The same reference numerals as those in the drawings denote the same components. Therefore, for convenience of explanation, redundant descriptions thereof will be omitted.

[0150] In accordance with Figure 7 In an exemplary embodiment, the first conductive layer PL' (see Figure 3 ) is not arranged in the display area DA. Therefore, the second interlayer insulating layer 117 (see FIG. 1 ) between the first conductive layer PL′ and the driving voltage line PL may be omitted. Figure 3 ).

[0151] refer to Figure 7 According to an exemplary embodiment, a display device may include a pad 32 in the peripheral area PA, an edge (or side surface) of the pad 32 may be covered by the first insulating layer PVX, and a central portion of the pad 32 may be covered by the second conductive layer C-PVX.

[0152] In accordance with Figure 7 In an exemplary embodiment, the pad 32 may include only the first pad layer 31a. The first pad layer 31a may be connected to the connection line CW through the first contact hole CNT1 penetrating the first interlayer insulating layer 115. The edge (or side surface) of the first pad layer 31a may be covered by the first insulating layer PVX, and the central portion of the first pad layer 31a may be covered by the second conductive layer C-PVX. The second conductive layer C-PVX may be arranged inside the opening hole PVXh of the first insulating layer PVX to directly contact the upper surface of the first pad layer 31a, and a portion of the second conductive layer C-PVX may extend to the upper surface of the first insulating layer PVX.

[0153] The first pad layer 31a may include a metal having excellent electrical conductivity. For example, the first pad layer 31a may include Cu. In an exemplary embodiment, the first pad layer 31a may include a Ti / Cu multilayer including a first layer including Ti and a second layer on the first layer including Cu. The second layer of the first pad layer 31a may include a material having a high degree of oxidation and may be easily damaged by an etchant during certain processes.

[0154] The second conductive layer C-PVX may include a metal having a lower degree of oxidation than the material of the pad 32 (e.g., the first pad layer 31a) or a metal having higher corrosion resistance than the material of the pad 32 (e.g., the first pad layer 31a). In an exemplary embodiment, the second conductive layer C-PVX may include Ti.

[0155] In accordance with Figure 7 In an exemplary embodiment, since the edge (or side surface) of the pad 32 is covered by the first insulating layer PVX and / or the second interlayer insulating layer 117, and the central portion of the pad 32 is covered by the second conductive layer C-PVX, damage to the pad 32 by the etchant during certain processes can be reduced and oxidation of the pad 32 can be prevented.

[0156] Figure 8 is a cross-sectional view of a portion of a display device according to an exemplary embodiment, specifically illustrating the periphery of the pad 32. Figure 8 In, and Figure 7 The same reference numerals as those in the drawings denote the same components. Therefore, for convenience of explanation, redundant descriptions thereof will be omitted.

[0157] refer to Figure 8 , the second conductive layer C-PVX may be arranged on the upper surface of the pad 32, and the first insulating layer PVX may be arranged to cover the second conductive layer C-PVX and the side surfaces of the pad 32. For example, the first insulating layer PVX may be arranged on the second conductive layer C-PVX and may include an opening hole PVXh exposing the upper surface of the second conductive layer C-PVX.

[0158] In accordance with Figure 8 In an exemplary embodiment, since the upper surface of the pad 32 is covered by the second conductive layer C-PVX and the side surface of the pad 32 is covered by the first insulating layer PVX, the pad 32 can be prevented from being damaged in certain processes and can be prevented from being oxidized.

[0159] Figure 9 is a cross-sectional view of a portion of a display device according to an exemplary embodiment. Figure 9 In, and Figure 7 The same reference numerals as those in the drawings denote the same components. Therefore, for convenience of explanation, redundant descriptions thereof will be omitted.

[0160] refer to Figure 9 , the second conductive layer C-PVX may be arranged to cover the upper surface and the side surface of the pad 32. For example, the width Wc of the second conductive layer C-PVX may be greater than the width Wp of the pad 32.

[0161] In addition, the drain electrode D1 arranged in the display area DA can be covered by the connection electrode CM, and the upper surface and side surfaces of the source electrode S1, the driving voltage line PL, and the second electrode CE2 can be covered by the additional second conductive layer C-PVX'. Therefore, since the drain electrode D1, the source electrode S1, the driving voltage line PL, and the second electrode CE2 do not directly contact the planarization layer 118, oxidation can be prevented.

[0162] In accordance with Figure 9 In an exemplary embodiment, since the upper surface and the side surface of the pad 32 are covered by the second conductive layer C-PVX, the pad 32 can be prevented from being damaged in certain processes and can be prevented from being oxidized.

[0163] Figure 10 is a schematic cross-sectional view of a display device according to an exemplary embodiment. Figure 10 In, and Figure 3 The same reference numerals as those in the drawings denote the same components. Therefore, for convenience of explanation, redundant descriptions thereof will be omitted.

[0164] According to an exemplary embodiment, a display device includes: a plurality of pixels P1, P2, and P3 arranged in a display area DA; a thin film encapsulation layer 400 covering the plurality of pixels P1, P2, and P3; and an upper substrate 200 arranged on the thin film encapsulation layer 400 and including a first color conversion layer QD1 and a second color conversion layer QD2 and a light-blocking pattern 210.

[0165] The intermediate layer 320 of the organic light-emitting diode OLED arranged in each pixel P1, P2, and P3 can be provided in common. Therefore, the organic light-emitting diode OLED included in each pixel P1, P2, and P3 can emit light of the same color. For example, the intermediate layer 320 can include an organic emission layer including a fluorescent or phosphorescent material that emits blue light. Functional layers such as HTL, HIL, ETL, or EIL can be selectively arranged below or above the organic emission layer.

[0166] Since the organic light-emitting diode OLED is easily damaged by external moisture or oxygen, the organic light-emitting diode OLED can be covered and protected by a thin film encapsulation layer 400. The thin film encapsulation layer 400 can cover the display area DA and can extend outside the display area DA. The thin film encapsulation layer 400 includes at least one organic encapsulation layer and at least one inorganic encapsulation layer. For example, the thin film encapsulation layer 400 may include a first inorganic encapsulation layer 410, an organic encapsulation layer 420, and a second inorganic encapsulation layer 430.

[0167] The first inorganic encapsulation layer 410 may cover the counter electrode 330 and may include, for example, silicon oxide, silicon nitride and / or silicon oxynitride. According to exemplary embodiments, other layers such as a capping layer may be provided between the first inorganic encapsulation layer 410 and the counter electrode 330. In an exemplary embodiment, since the first inorganic encapsulation layer 410 is formed along the underlying structure, the upper surface of the first inorganic encapsulation layer 410 is not substantially flat. The organic encapsulation layer 420 may cover the first inorganic encapsulation layer 410, and unlike the first inorganic encapsulation layer 410, the upper surface of the organic encapsulation layer 420 may be formed to be substantially flat. For example, the organic encapsulation layer 420 may have a substantially flat upper surface in a portion thereof corresponding to the display area DA. The organic encapsulation layer 420 may include one or more materials selected from a group including, for example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, and HMDSO. The second inorganic encapsulating layer 430 may cover the organic encapsulating layer 420 and may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0168] According to the multi-layer structure, even when cracks occur in the thin film encapsulation layer 400, the thin film encapsulation layer 400 can prevent the cracks from being connected between the first inorganic encapsulation layer 410 and the organic encapsulation layer 420, or between the organic encapsulation layer 420 and the second inorganic encapsulation layer 430. Therefore, the formation of a path through which external moisture or oxygen penetrates into the display area DA can be prevented or reduced.

[0169] Upper substrate 200 disposed to face lower substrate 100 may be disposed over thin film encapsulation layer 400 . First and second color conversion layers QD1 and QD2 , transmissive windows TW, and light-blocking patterns 210 may be disposed on upper substrate 200 .

[0170] The first color conversion layer QD1 and the second color conversion layer QD2 can be layers that sharpen the color of light emitted from the organic light emitting diode (OLED) or convert the color into another color. The first color conversion layer QD1 and the second color conversion layer QD2 can include quantum dots and can include quantum conversion layers. Quantum dots can be semiconductor particles with a diameter of only about 2 nm to about 10 nm and particles with unusual electrical and optical properties. When the quantum dots are exposed to light, the quantum dots can emit light at a specific frequency depending on the size of the particles and the type of material. For example, depending on the size of the particles and / or the type of material, the quantum dots can emit red, green, and blue light when receiving light.

[0171] The core of the quantum dot can be selected from, for example, Group II-VI compounds, Group III-V compounds, Group IV-VI compounds, Group IV elements, Group IV compounds, and combinations thereof.

[0172] The II-VI compounds can be selected from the group including, for example, binary compounds, ternary compounds and quaternary compounds, the binary compounds being selected from the group including CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, MgS and mixtures thereof, the ternary compounds being selected from the group including AgInS, CuInS, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe , CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, MgZnSe, MgZnS and mixtures thereof, and the quaternary compound is selected from the group including HgZnTeS, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, HgZnSTe and mixtures thereof.

[0173] The III-V compounds can be selected from the group including, for example, binary compounds, ternary compounds and quaternary compounds, the binary compounds being selected from the group including GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb and mixtures thereof, the ternary compounds being selected from the group including GaNPs, GaNAs, GaNSb, GaPAs, GaPSb, AlNPs, AlNAs, AlNSb, AlPAs, AlPSb, InGaP, InNP, InNAs, InNSb, InPAs, InPSb and mixtures thereof, and the quaternary compounds being selected from the group including GaAlNPs, GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNPs, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNPs, InAlNAs, InAlNSb, InAlPAs, InAlPSb and mixtures thereof.

[0174] The IV-VI compound can be selected from the group including, for example, binary compounds, ternary compounds, and quaternary compounds. The binary compound is selected from the group including SnS, SnSe, SnTe, PbS, PbSe, PbTe, and mixtures thereof. The ternary compound is selected from the group including SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, SnPbTe, and mixtures thereof. The quaternary compound is selected from the group including SnPbSSe, SnPbSeTe, SnPbSTe, and mixtures thereof. The IV group element can be selected from the group including, for example, Si, Ge, and mixtures thereof. The IV group compound can be a binary compound selected from the group including, for example, SiC, SiGe, and mixtures thereof.

[0175] Binary, ternary, and quaternary compounds can be present in a particle at a uniform concentration, or can be present in the same particle by being partially separated into different concentrations. In addition, one quantum dot can have a core / shell structure surrounding another quantum dot. The interface between the core and the shell can have a concentration gradient, where the concentration of the element in the shell decreases toward the center of the interface.

[0176] In an exemplary embodiment, a quantum dot may have a core-shell structure comprising a core comprising nanocrystals and a shell surrounding the core. The shell of the quantum dot may serve as a protective layer to prevent chemical modification of the core to maintain semiconductor properties and / or may serve as a charging layer for imparting electrophoretic properties to the quantum dot. The shell may comprise a single layer or multiple layers. The interface between the core and the shell may have a concentration gradient, wherein the concentration of the element in the shell decreases toward the center of the interface. Examples of the shell of the quantum dot may include metal or non-metal oxides, semiconductor compounds, or combinations thereof.

[0177] For example, the metal or non-metal oxide may include a binary compound such as SiO2, Al2O3, TiO2, ZnO, MnO, Mn2O3, Mn3O4, CuO, FeO, Fe2O3, Fe3O4, CoO, Co3O4, or NiO; or a ternary compound such as MgAl2O4, CoFe2O4, NiFe2O4, or CoMn2O4. However, the present disclosure is not limited thereto.

[0178] In addition, the semiconductor compound may include, for example, CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnSeS, ZnTeS, GaAs, GaP, GaSb, HgS, HgSe, HgTe, InAs, InP, InGaP, InSb, AlAs, AlP, or AlSb. However, the present disclosure is not limited thereto.

[0179] In one exemplary embodiment, the quantum dots may have a full width at half maximum (FWHM) of an emission wavelength spectrum of approximately 45 nm or less. In one exemplary embodiment, the quantum dots may have a FWHM of an emission wavelength spectrum of approximately 40 nm or less. In one exemplary embodiment, the quantum dots may have a FWHM of an emission wavelength spectrum of approximately 30 nm or less. Within the above ranges, color purity and color reproducibility can be improved. In addition, since light emitted by the quantum dots is emitted in all directions, the viewing angle of the light can be improved.

[0180] In addition, the form of quantum dots can be a commonly used form without particular limitation. More specifically, in exemplary embodiments, the form of quantum dots can include, for example, spherical, pyramidal, multi-armed or cubic nanoparticles, nanotubes, nanowires, nanofibers or nanosheets.

[0181] The first color conversion layer QD1 and the second color conversion layer QD2 may be arranged to correspond to at least a portion of the emission area defined by the opening OP of the pixel defining film 119. For example, the first color conversion layer QD1 may be arranged to correspond to the emission area of the first pixel P1, and the second color conversion layer QD2 may be arranged to correspond to the emission area of the second pixel P2. In an exemplary embodiment, the first color conversion layer QD1 and the second color conversion layer QD2 do not correspond to the emission area of the third pixel P3, and the transmission window TW may be arranged in the emission area of the third pixel P3. The transmission window TW may include an organic material that can emit light without converting the wavelength of light emitted from the organic light emitting diode OLED of the third pixel P3. However, the present disclosure is not limited thereto. The color conversion layer may be arranged in the emission area of the third pixel P3.

[0182] The scattering particles may be distributed in the first and second color conversion layers QD1 and QD2 and the transmission window TW, and thus, the color extension may be uniform.

[0183] A light-blocking pattern 210 may be disposed between the first and second color conversion layers QD1 and QD2 and the transmissive window TW. The light-blocking pattern 210 may be, for example, a black matrix and a component that improves color clarity and contrast. The light-blocking pattern 210 may be disposed between the emission regions of each pixel P1, P2, and P3. Since the light-blocking pattern 210 may be provided as a black matrix that absorbs visible light, color mixing of light emitted from the emission regions of adjacent pixels may be prevented, thereby improving visibility and contrast.

[0184] In an exemplary embodiment, all of the multiple organic light-emitting diodes (OLEDs) may emit blue light. In this case, the first color conversion layer (QD1) may include quantum dots that emit red light, and the second color conversion layer (QD2) may include quantum dots that emit green light. Thus, the light emitted from the display device may be red, green, and blue, and the combination of these colors can achieve various color representations.

[0185] A filler 610 may be further disposed between the lower substrate 100 and the upper substrate 200. The filler 610 may serve as a buffer against external pressure. The filler 610 may include an organic material such as, for example, methyl silicone, phenyl silicone, and polyimide. However, the filler 610 is not limited thereto. For example, according to an exemplary embodiment, the filler 610 may include a polyurethane resin, epoxy resin, or acrylic resin as an organic sealant, or silicone as an inorganic sealant.

[0186] According to an exemplary embodiment, as in Figure 10 The pad 31 and related layers shown in the peripheral area PA in the cross-sectional view of FIG. 3 can be arranged as shown in FIG. Figure 3 、 Figure 4B 、 Figure 5B and Figures 6 to 9 The configuration is shown in the cross-sectional view.

[0187] Figure 11 is a schematic cross-sectional view of a display device according to an exemplary embodiment. Figure 11 In, and Figure 10 The same reference numerals as those in the drawings denote the same components. Therefore, for convenience of explanation, redundant descriptions thereof will be omitted.

[0188] In accordance with Figure 11 In an exemplary embodiment, in the organic light emitting diode OLED included in the plurality of pixels P1, P2, and P3, a plurality of intermediate layers 320a and 320b and a plurality of counter electrodes 330a and 330b may be stacked.

[0189] For example, the organic light emitting diode OLED may include a first intermediate layer 320a, a first counter electrode 330a, a second intermediate layer 320b, and a second counter electrode 330b sequentially stacked on the pixel electrode 310. The first intermediate layer 320a and the second intermediate layer 320b may include an organic emission layer including a fluorescent or phosphorescent material that emits red, green, blue, or white light. The organic emission layer may include a low molecular weight material or a polymer material, and a functional layer such as, for example, an HTL, a HIL, an ETL, or an EIL may be selectively arranged below or above the organic emission layer. In an exemplary embodiment, the first intermediate layer 320a and the second intermediate layer 320b may include an organic emission layer that emits blue light.

[0190] The first counter electrode 330a and the second counter electrode 330b may include a transmissive electrode or a reflective electrode. In an exemplary embodiment, the counter electrode 330 may include a transparent or semi-transparent electrode and may include a metal film having a small work function and including, for example, Li, Ca, LiF / Ca, LiF / Al, Al, Ag, Mg, or a compound thereof. In addition, a TCO film such as, for example, ITO, IZO, ZnO, or In2O3 may be further disposed on the metal film. The first counter electrode 330a may be a floating electrode.

[0191] The first intermediate layer 320 a , the second intermediate layer 320 b , the first counter electrode 330 a , and the second counter electrode 330 b may be formed as a single body with respect to the plurality of pixels P1 , P2 , and P3 .

[0192] In an exemplary embodiment, first, second, and third color filters CF1, CF2, and CF3 may be included on the upper substrate 200. The first, second, and third color filters CF1, CF2, and CF3 may realize a full-color image, improve color purity, and improve outdoor visibility.

[0193] First, second, and third color filters CF1, CF2, and CF3 may be disposed on upper substrate 200 to correspond to emission regions of pixels P1, P2, and P3, respectively. Light blocking pattern 210 may be disposed between first, second, and third color filters CF1, CF2, and CF3.

[0194] The protective layer 220 may cover the light blocking pattern 210 and the first, second, and third color filters CF1, CF2, and CF3. The protective layer 220 may include an inorganic material such as, for example, silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO). The protective layer 220 may include an organic material such as, for example, polyimide or epoxy resin.

[0195] The first color conversion layer QD1, the second color conversion layer QD2, and the transmissive window TW may overlap with the first color filter CF1, the second color filter CF2, and the third color filter CF3, respectively. A protective layer 220 is located between the first color conversion layer QD1 and the first color filter CF1, between the second color conversion layer QD2 and the second color filter CF2, and between the transmissive window TW and the third color filter CF3. An additional protective layer 230 may be further included over the upper substrate 200 to cover the first color conversion layer QD1, the second color conversion layer QD2, and the transmissive window TW. Additional protective layer 230 may include an organic material or an inorganic material.

[0196] The first color conversion layer QD1 and the second color conversion layer QD2 may include quantum dots that emit different colors from each other. For example, the first color conversion layer QD1 may emit red light, and the second color conversion layer QD2 may emit green light. In addition, the transmission window TW may transmit blue light emitted from the organic light emitting diode OLED of the third pixel P3.

[0197] In this case, the first color filter CF1 may be a red color filter, the second color filter CF2 may be a green color filter, and the third color filter CF3 may be a blue color filter.

[0198] According to an exemplary embodiment, as in Figure 11 The pad 31 and related layers shown in the peripheral area PA in the cross-sectional view of FIG. 3 can be arranged as shown in FIG. Figure 3 、 Figure 4B 、 Figure 5B and Figures 6 to 9 The configuration is shown in the cross-sectional view.

[0199] The display device according to the exemplary embodiments can be applied to a display device having a large area. Therefore, the wires and pads included in the display device may include a metal with high electrical conductivity. Since metal with high electrical conductivity is likely to be damaged and oxidized during certain processes, according to the exemplary embodiments described herein, a highly reliable display device can be provided by introducing a first insulating layer and a second conductive layer to protect the wires and pads.

[0200] Figure 12A and Figure 12B Comparison is made when ITO is formed on the pad 31 ( Figure 12A ) and the case where Ti is formed on the pad 31 ( Figure 12B ) images.

[0201] refer to Figure 12A , when ITO is formed on the pad 31 and subsequent processes are performed, it can be seen that the pad 31 is damaged due to the etchant injected through the pinhole formed in the ITO.

[0202] Figure 12B An image is shown in which Ti is formed on the pad 31. When Ti is formed on the pad 31 and subsequent processes are performed, it can be seen that the pad 31 is not damaged.

[0203] As described above, the display device according to one or more exemplary embodiments includes the second conductive layer, and thus may implement a high-quality image.

[0204] While the present disclosure has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the present disclosure as defined by the following claims.

Claims

1. A display device, wherein: The display device includes: a substrate comprising a display area and a peripheral area outside the display area; a thin film transistor, arranged in the display area; a display element arranged in the display area; an interlayer insulating layer, covering the thin film transistor; a first conductive layer, arranged above the interlayer insulating layer; a first insulating layer, covering the first conductive layer; a pad arranged in the peripheral area; and a second conductive layer, covering the central portion of the pad, The pad is connected to a connection line through a contact hole, and the connection line is arranged on the same first layer as the gate electrode of the thin film transistor, and the side surface of the pad is covered by the first insulating layer or the second conductive layer. The pad includes a first pad layer on the same second layer as the source electrode of the thin film transistor, and a second pad layer on the same third layer as the first conductive layer. The first insulating layer includes an inorganic material, the first insulating layer has an opening hole exposing a central portion of the second pad layer, and The second conductive layer contacts the second pad layer through the opening hole of the first insulating layer.

2. The display device according to claim 1, wherein The second conductive layer includes titanium.

3. The display device according to claim 1, wherein The pad includes a metal having higher electrical conductivity than that of the second conductive layer.

4. The display device according to claim 1, wherein The display device further includes: connecting the drain electrode of the thin film transistor to the pixel electrode of the display element; The connecting electrode comprises the same material as that of the second conductive layer.

5. A display device, wherein: The display device includes: a substrate comprising a display area and a peripheral area outside the display area; a thin film transistor, arranged in the display area; a display element arranged in the display area; an interlayer insulating layer, covering the thin film transistor; a first conductive layer, arranged above the interlayer insulating layer; a first insulating layer, covering the first conductive layer; a pad arranged in the peripheral area; and a second conductive layer, covering the central portion of the pad, wherein the pad is connected to a connection line through a contact hole, and the connection line is arranged on the same first layer as the gate electrode of the thin film transistor, The side surface of the pad is covered by the first insulating layer or the second conductive layer, The pad includes a first pad layer on the same second layer as the source electrode of the thin film transistor, The first insulating layer and the interlayer insulating layer include an opening hole corresponding to a central portion of the first pad layer, and The second conductive layer contacts the first pad layer through the opening holes of the first insulating layer and the interlayer insulating layer.

6. A display device, wherein: The display device includes: a substrate comprising a display area and a peripheral area outside the display area; a thin film transistor, arranged in the display area; a display element arranged in the display area; an interlayer insulating layer, covering the thin film transistor; a first insulating layer, arranged above the interlayer insulating layer; a pad arranged in the peripheral area; and a second conductive layer covering the side surface and the upper surface of the pad, wherein the pad is connected to a connection line through a contact hole, and the connection line is arranged on the same first layer as the gate electrode of the thin film transistor, The first insulating layer and the interlayer insulating layer include an opening hole corresponding to a central portion of the pad, The second conductive layer contacts the pad through the opening holes of the first insulating layer and the interlayer insulating layer.

7. The display device according to claim 6, wherein The second conductive layer includes titanium.

8. The display device according to claim 6, wherein: The display device further includes: a storage capacitor disposed in the display area, The first electrode of the storage capacitor is arranged on the same first layer as the gate electrode of the thin film transistor, and the second electrode of the storage capacitor is arranged on the same second layer as the source electrode of the thin film transistor.

9. The display device according to claim 6, wherein: The display device further includes: a first conductive layer, arranged above the thin film transistor; A first pad layer on the same second layer as the source electrode of the thin film transistor and a second pad layer on the same third layer as the first conductive layer are stacked in the pad.

10. A display device, wherein: The display device includes: a lower substrate comprising a display area and a peripheral area outside the display area; a plurality of pixels arranged in the display area, each of the pixels comprising a thin film transistor and an organic light emitting diode; a thin film encapsulation layer, covering the organic light emitting diode and comprising at least one inorganic encapsulation layer and at least one organic encapsulation layer; an upper substrate, arranged above the thin film encapsulation layer and facing the lower substrate; a pad arranged in the peripheral area; and a second conductive layer, covering the central portion of the pad, The side surface of the pad is covered by the second conductive layer or the first insulating layer. The pad includes a first pad layer on the same second layer as the source electrode of the thin film transistor, and a second pad layer on the same third layer as the first conductive layer. The first insulating layer includes an inorganic material, the first insulating layer has an opening hole exposing a central portion of the second pad layer, and The second conductive layer contacts the second pad layer through the opening hole of the first insulating layer. The display device according to claim 10 , wherein The pad is connected to a connection line through a contact hole, and the connection line is arranged on the same layer as a gate electrode of the thin film transistor.

12. The display device according to claim 10, wherein The second conductive layer includes titanium.

13. The display device according to claim 10, wherein: The display device further includes: a connecting electrode, a pixel electrode connecting the thin film transistor and the organic light emitting diode in each pixel, The connecting electrode comprises the same material as that of the second conductive layer.

14. The display device according to claim 10, wherein: The display device further includes: A first conductive layer is disposed on the thin film transistor and connected to the thin film transistor through a contact hole.

15. The display device according to claim 10, wherein The display device further includes: A plurality of color conversion layers are arranged on the upper substrate and correspond to at least a portion of the plurality of pixels, and include a plurality of quantum dots.

16. The display device according to claim 15, wherein The plurality of pixels include a first pixel, a second pixel, and a third pixel, One color conversion layer corresponding to the first pixel among the plurality of color conversion layers emits red light, One color conversion layer corresponding to the second pixel among the plurality of color conversion layers emits green light, and Any one of the plurality of color conversion layers is not arranged corresponding to the third pixel.

17. The display device according to claim 10, wherein: The display device further includes: A plurality of color filters are arranged on the upper substrate and correspond to the plurality of pixels.

18. The display device according to claim 10, wherein The organic light emitting diodes included in the plurality of pixels emit blue light.

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