Method, device and system for operating multiple memory chips

Abstract

The present application relates to multi-memory die technology. A memory device may include multiple memory dies and may be configured to communicate with a host device. For example, each memory die may be coupled to a set of data pins including a corresponding subset of data pins (e.g., a set of 8 data pins with two subsets of 4 data pins). In addition, each memory die may have one or more auxiliary pins for channel coding information of data transmitted through one or more of the data pin subsets. In some cases, each memory die may include one or more additional auxiliary pins that can be used for channel coding information of a corresponding data pin subset or multiple data pin subsets. The channel coding information associated with the auxiliary pins may include error detection code information, data coding information, or any combination thereof.

Description

[0001] Cross Reference

[0002] This patent application claims priority to U.S. patent application No. 16 / 530,469, filed by Spirkl et al. on August 2, 2019, entitled “MULTIPLE MEMORY DIE TECHNIQUES,” which is assigned to its assignee and is expressly incorporated herein by reference in its entirety.

[0003] The technical field relates to multiple memory die technology. Background Art

[0004] The following relates generally to systems including at least one memory device, and more particularly to multiple memory die technology.

[0005] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of the memory device. For example, binary devices mostly store one of two states, usually represented by a logical 1 or a logical 0. In other devices, more than two states may be stored. To access the stored information, a component of the device may read or sense at least one stored state in the memory device. To store information, a component of the device may write or program a state in the memory device.

[0006] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), and others. Memory devices can be volatile or non-volatile. Non-volatile memory (such as FeRAM) can retain its stored logic state for a long time, even in the absence of external power. Volatile memory devices (such as DRAM) lose their stored state when disconnected from external power.

[0007] As memory devices enhance performance improvements, such as faster access operations and increased storage capacity, various problems associated with the memory devices and host devices may arise. Summary of the invention

[0008] An apparatus is described. In some examples, the apparatus may include a memory device, the memory device comprising a group of memory dies, each memory die in the group operable to communicate with a host device via: a group of 8 data pins, comprising a first subset of 4 data pins and a second subset of 4 data pins, the first subset of 4 data pins and the second subset of 4 data pins being operable to be independently addressed; and an auxiliary pin operable to carry channel encoding information of the first subset of 4 data pins.

[0009] An apparatus is described. In some examples, the apparatus may include a host device operable to communicate with a group of memory dies, wherein the host device is operable to communicate with respective memory dies in the group via: a group of 8 data pins including a first subset of 4 data pins and a second subset of 4 data pins, the first subset of 4 data pins and the second subset of 4 data pins being operable to be independently addressable; and an auxiliary pin operable to carry channel encoding information of the first subset of 4 data pins.

[0010] A method is described. In some examples, the method may include: communicating first data between a first memory die and a host device via a first set of four data pins and communicating channel encoding information for the first data via a first auxiliary pin corresponding to the first set of four data pins; and communicating second data between a second memory die and the host device via a second set of four data pins and communicating channel encoding information for the second data via a second auxiliary pin corresponding to the second set of four data pins.

[0011] A system is described. In some examples, the system may include: a memory device including a group of memory dies; and a host device coupled to the memory device, the system operable to: communicate data between the host device and a respective memory die in the group via a group of 8 data pins, the group of 8 data pins including a first subset of 4 data pins and a second subset of 4 data pins, the first subset of 4 data pins and the second subset of 4 data pins being operable to be independently addressable; and communicate channel encoding information of the first subset of 4 data pins with the respective memory die via an auxiliary pin. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 An example of a system supporting multiple memory die technology according to examples disclosed herein is illustrated.

[0013] Figure 2 An example of a memory device supporting multiple memory die technology according to the examples disclosed herein is illustrated.

[0014] Figure 3 An example of a device configuration supporting multiple memory die technology according to the examples disclosed herein is illustrated.

[0015] Figure 4 An example of a device configuration supporting multiple memory die technology according to the examples disclosed herein is illustrated.

[0016] Figure 5 An example of a device configuration supporting multiple memory die technology according to the examples disclosed herein is illustrated.

[0017] Figure 6 An example of a communication configuration supporting multiple memory die technology according to examples disclosed herein is illustrated.

[0018] Figure 7 An example of a communication configuration supporting multiple memory die technology according to examples disclosed herein is illustrated.

[0019] Figure 8 A block diagram of a memory device supporting multiple memory die technology according to aspects of the present invention is shown.

[0020] Figures 9 to 11 A flow chart is shown illustrating one or more methods of supporting multiple memory die technology according to examples disclosed herein. DETAILED DESCRIPTION

[0021] The architecture of a memory system, such as a memory system including dynamic random access memory (DRAM) devices, may be configured to support different operating modes. For example, the memory system may include a host device and one or more memory devices, and communication between the host device and the one or more memory devices may occur over multiple channels. In some cases, a channel may refer to a set of one or more lines through which data may be exchanged between the host device and the memory device. In some cases, a channel may refer to a logical entity for exchanging data between the host device and the memory device over one or more lines.

[0022] Based on the system configuration and operating mode, the memory device may simultaneously transfer different numbers of bits through each channel. As an example, a single memory device may communicate with a host device through two 16-bit wide channels (which may be referred to as x16 (by 16) mode, full input / output (I / O) mode, or other similar terms). As used herein, a channel or other width expressed in units of bits may refer to the number of lines included in a channel or other entity, and therefore the number of bits that can be simultaneously transferred through a channel or other entity, assuming a binary modulation scheme (although other modulation schemes may be used). In this example, communication may occur simultaneously through 32 data lines, 16 of which per channel.

[0023] Additionally or alternatively, two memory devices may communicate with the host device over two x16 channels, but where each x16 channel is split such that one x8 subset of the channels is coupled with one memory device and another x8 subset of the channels is coupled with another memory device (which may be referred to as x8 (by 8) mode, half I / O mode, or other similar terminology). That is, two 16-bit wide channels may be used by the host device, but where each 16-bit wide channel is split between the two memory devices (e.g., a first x8 subset of the channels is coupled with a first memory device, and a second x8 subset of the channels is coupled with a second memory device, where one x8 subset of each channel is used by the host device to communicate with each memory device). In such a case, the host device may communicate over 16 lines per channel, but where each channel is split between the two memory devices such that each memory device communicates over 8 lines per channel.

[0024] In either case, each x8 line group over which communication occurs may be associated with respective auxiliary lines for conveying error detection encodings, such as error detection code (EDC) lines, and respective auxiliary lines for data encodings, such as data bus inversion (DBI) lines or other types of data encoding lines. Furthermore, for memory devices having multiple memory dies, these configurations may be implemented using one channel per memory die or multiple channels per memory die, and each channel (and in some cases each x8 subset of channels) may be operated independently of one another (e.g., independently addressable by a host device).

[0025] As the demand for increased memory performance continues to increase, there may be many factors that contribute to the design and configuration of memory devices. For example, increasing the number of data pins (e.g., DQ pins) of a memory device may be undesirable due to physical constraints and other considerations (e.g., more data pins increase the area of ​​the memory device, while fewer data pins limit bandwidth). In addition, while the operational performance (e.g., the number of bits exchanged per pin or line as part of an access (e.g., read or write) operation) and capacity of memory devices are improved or otherwise evolved, it is desirable to ensure that the memory device is compatible with a range of host devices to enable broad application and implementation without also requiring enhancements to the host device design (e.g., requiring the host device to be able to match the highest performance level supported by the memory device). Therefore, various factors are considered when improving or otherwise altering the performance of a memory device (e.g., doubling the number of bits exchanged per pin or line as part of an access (e.g., read or write) operation).

[0026] As described herein, various configurations of memory devices can achieve increased data access rates while ensuring broad compatibility with other devices and other benefits that will be apparent to one of ordinary skill in the art. As an example, a memory device can be configured to transfer information using an increased amount of data per access per pin and / or using an increased number of channels (e.g., compared to a system using two channels), including channels that can be divided at a sub-x8 (e.g., sub-byte) granularity (e.g., to support splitting across multiple memory devices from the perspective of a host device).

[0027] As an example, as part of a memory system, a memory device may communicate with a host device over multiple (e.g., four) 8-bit wide channels, where each channel may correspond to a respective memory die at the memory device. Additionally or alternatively, multiple memory devices may communicate with a host device as part of a memory system. In such a case, each memory device may communicate via a 4-bit wide branch (which may also be referred to as a nibble) of a channel within a respective channel in a set of channels (e.g., 4 channels), where each channel may correspond to a respective memory die at the memory device. That is, for example, four 8-bit wide channels may be used by a host device, but where each 8-bit wide channel is split between two memory devices (e.g., a nibble wide portion of the channel is coupled with a first memory device, and a second nibble wide portion of the channel is coupled with a second memory device, where one nibble wide portion per channel is used by the host device to communicate with each memory device).

[0028] In such cases, various auxiliary pin and line configurations may be used for each 8-bit wide channel and nibbles therein (e.g., where auxiliary pins may be dedicated to some subset of data pins at the memory device). For example, a set of auxiliary pins at a memory device (e.g., EDC pins and DBI pins) may be dedicated to a subset of 4 data pins of the memory device. In other examples, a single auxiliary pin at the memory device may be dedicated to a subset of 4 data pins (e.g., where both EDC and DBI information may be carried together on a bidirectional auxiliary line). Additionally or alternatively, a set of one or more auxiliary pins may be configured to be dedicated to a set of data pins or to a subset thereof at a memory device (e.g., an EDC pin and a DBI pin (or a single auxiliary pin) may be configured to be dedicated to a set of 8 data pins (two subsets of 4 data pins) or to one of two subsets of 4 data pins). Through the various configurations of memory devices described herein, a memory system can support an increased number of bits per data line transferred to / from a host device during an access operation (e.g., in conjunction with an access operation) without increasing the area of ​​the memory device while maintaining compatibility with a variety of host devices and other benefits.

[0029] First, in reference Figure 1 and 2Features of the present invention are described in the context of the described memory system and memory die. Figures 3 to 7 Features of the present invention are described in the context of the described memory device configuration. Figures 8 to 11 These and other features of the present invention are further illustrated and described with reference to the described device diagrams and flow diagrams related to multiple memory die technology.

[0030] Figure 1 An example of a system 100 utilizing one or more memory devices according to examples disclosed herein is illustrated. The system 100 may include an external memory controller 105, a memory device 110, and a plurality of lines 115 (e.g., data and / or auxiliary lines) coupling the external memory controller 105 and the memory device 110. The system 100 may include one or more memory devices, but for ease of description, the one or more memory devices may be described as a single memory device 110.

[0031] System 100 may include part of an electronic device, such as a computing device, a mobile computing device, a wireless device, or a graphics processing device. System 100 may be an example of a portable electronic device. System 100 may be an example of a computer, a laptop, a tablet computer, a smartphone, a mobile phone, a wearable device, an Internet-connected device, or the like. Memory device 110 may be a component of the system configured to store data of one or more other components of system 100.

[0032] At least a portion of the system 100 may be an example of a host device. This host device may be an example of a device that uses memory to perform a process, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop computer, a tablet computer, a smart phone, a mobile phone, a wearable device, an Internet connection device, some other fixed or portable electronic device, or the like. In some cases, the host device may refer to hardware, firmware, software, or a combination thereof that implements the functions of the external memory controller 105. In some cases, the external memory controller 105 may be referred to as a host device. In some examples, the system 100 is a graphics card. The host device may communicate with the memory device 110 to request or transfer data or perform other functions. The host device and the memory device 110 may be coupled to each other via one or more wires, pins, or other connections to transfer data and control information.

[0033] In some cases, memory device 110 may be a standalone device or component configured to communicate with other components of system 100 and provide a physical memory address / space that may be used or referenced by system 100. In some examples, memory device 110 may be configured to work with at least one or more different types of systems 100. Signaling between components of system 100 and memory device 110 may operate to support modulation schemes for modulating signals, different pin designs for communicating signals, different packaging of system 100 and memory device 110, clock signaling and synchronization between system 100 and memory device 110, timing conventions, and / or other factors.

[0034] The memory device 110 may be configured to store data for components of the system 100. In some cases, the memory device 110 may be used as a slave device of the system 100 (e.g., responding to and executing commands provided by the system 100 through the external memory controller 105). Such commands may include access commands for access operations, such as write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands. The memory device 110 may include two or more memory dies 160 (e.g., memory chips) that support a desired or specified capacity of data storage. A memory device 110 that includes two or more memory dies may be referred to as a multi-memory die memory or package (also referred to as a multi-chip memory or package).

[0035] System 100 may further include a processor 120, a basic input / output system (BIOS) component 125, one or more peripheral components 130, and an input / output (I / O) controller 135. The components of system 100 may use a bus 140 to electronically communicate with each other.

[0036] Processor 120 may be configured to control at least a portion of system 100. Processor 120 may be a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or it may be a combination of these types of components. In such cases, processor 120 may be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general purpose graphics processing unit (GPGPU), or a single chip system (SoC), among other examples.

[0037] BIOS component 125 may be a software component including a BIOS operating as firmware that may initialize and run the various hardware components of system 100. BIOS component 125 may also manage the flow of data between processor 120 and various components of system 100, such as peripheral components 130, I / O controller 135, etc. BIOS component 125 may include a program or software stored in read-only memory (ROM), flash memory, or any other non-volatile memory.

[0038] Peripheral component 130 may be any input device or output device, or interface to such a device, that may be integrated into or with system 100. Examples may include a disk controller, a sound controller, a graphics controller, an Ethernet controller, a modem, a Universal Serial Bus (USB) controller, a serial or parallel port, or a peripheral card slot such as a Peripheral Component Interconnect (PCI) or a dedicated graphics port. Peripheral component 130 may be other components understood by those skilled in the art to be peripherals.

[0039] I / O controller 135 may manage data communications between processor 120 and peripheral components 130, input device 145, or output device 150. I / O controller 135 may manage peripheral devices that are not integrated into or with system 100. In some cases, I / O controller 135 may represent a physical connection or port to an external peripheral component.

[0040] Input device 145 may represent a device or signal external to system 100 that provides information, signals, or data to system 100 or its components. This may include a user interface or interfacing with or between other devices. In some cases, input device 145 may be a peripheral device that interfaces with system 100 via one or more peripheral components 130 or may be managed by I / O controller 135.

[0041] Output device 150 may represent a device or signal external to system 100 that is configured to receive output from system 100 or any of its components. Examples of output device 150 may include a display, an audio speaker, a printing device, or another processor on a printed circuit board, etc. In some cases, output device 150 may be a peripheral device that interfaces with system 100 via one or more peripheral components 130 or may be managed by I / O controller 135.

[0042] The components of system 100 may be composed of general or special purpose circuitry designed to perform its functions. This may include various circuit elements such as conductive lines, transistors, capacitors, inductors, resistors, amplifiers, or other active or passive elements configured to perform the functions described herein.

[0043] The memory device 110 may include a device memory controller 155 and one or more memory dies 160. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, and / or local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, and / or memory array 170-N). The memory array 170 may be a collection of memory cells (e.g., a grid) where each memory cell is configured to store at least one bit of digital data. Features of the memory array 170 and / or memory cells are described in detail below. Figure 2 Describe in more detail.

[0044] The memory device 110 may be an example of a two-dimensional (2D) memory cell array or may be an example of a three-dimensional (3D) memory cell array. For example, a 2D memory device may include a single memory die 160. A 3D memory device may include two or more memory dies 160 (e.g., memory die 160-a, memory die 160-b, and / or any number of memory dies 160-N). In a 3D memory device, multiple memory dies 160-N may be stacked on top of each other or next to each other. In some cases, the memory dies 160-N in a 3D memory device may be referred to as a deck / level / layer or a memory die. A 3D memory device may include any number of stacked memory dies 160-N (e.g., more than two, more than three, more than four, more than five, more than six, more than seven, more than eight). This may increase the number of memory cells that may be positioned on a substrate compared to a single 2D memory device, which in turn may reduce production costs or improve the performance of the memory array, or both. In some 3D memory devices, different layers may share at least one common access line, such that some layers may share at least one of a word line, a digit line, and / or a plate line.

[0045] The device memory controller 155 may include circuits or components configured to control the operation of the memory device 110. Thus, the device memory controller 155 may include hardware, firmware, and software that enable the memory device 110 to execute commands, and may be configured to receive, transmit, or execute commands, data, or control information related to the memory device 110. The device memory controller 155 may be configured to communicate with an external memory controller 105, one or more memory dies 160, or a processor 120. In some cases, the memory device 110 may receive data and / or commands from a host device or an external memory controller 105. For example, the memory device 110 may receive a write command indicating that the memory device 110 will store certain data on behalf of a component of the system 100 (e.g., the processor 120) or a read command indicating that the memory device 110 will provide certain data stored in the memory die 160 to a component of the system 100 (e.g., the processor 120). In some cases, the device memory controller 155 may control the operation of the memory device 110 described herein in conjunction with the local memory controller 165 of the memory die 160. Examples of components included in the device memory controller 155 and / or the local memory controller 165 may include a receiver for demodulating signals received from the external memory controller 105, a decoder for modulating and transmitting signals to the external memory controller 105, logic, decoders, amplifiers, filters, or the like.

[0046] A local memory controller 165 (e.g., local to the memory die 160) may be configured to control the operation of the memory die 160. Moreover, the local memory controller 165 may be configured to communicate (e.g., receive and transmit data and / or commands) with the device memory controller 155. The local memory controller 165 may support the device memory controller 155 in controlling the operation of the memory device 110 described herein. In some cases, the memory device 110 does not include a device memory controller 155, and the local memory controller 165 or the external memory controller 105 may perform the various functions described herein. Thus, the local memory controller 165 may be configured to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 105 or the processor 120 of the host device.

[0047] The external memory controller 105 may be configured to enable information, data, and / or commands to be communicated between components of the system 100 (e.g., the processor 120 of the host device) and the memory device 110. The external memory controller 105 may serve as a liaison between the components of the system 100 and the memory device 110, so that the components of the system 100 may not need to know the details of the operation of the memory device. The components of the system 100 may make requests (e.g., read commands or write commands) to the external memory controller 105, which the external memory controller 105 satisfies. The external memory controller 105 may convert or translate communications exchanged between the components of the system 100 and the memory device 110. In some cases, the external memory controller 105 may include a system clock that generates a common (source) system clock signal. In some cases, the external memory controller 105 may include a common data clock that generates a common (source) data clock signal.

[0048] In some cases, the external memory controller 105 or other components of the system 100 or its functions described herein may be implemented by the processor 120. For example, the external memory controller 105 may be hardware, firmware, or software, or some combination thereof, implemented by the processor 120 or other components of the system 100. Although the external memory controller 105 is depicted as being external to the memory device 110, in some cases, the external memory controller 105 or its functions described herein may be implemented by the memory device 110. For example, the external memory controller 105 may be hardware, firmware, or software, or some combination thereof, implemented by the device memory controller 155 or one or more local memory controllers 165. In some cases, the external memory controller 105 may be distributed across the processor 120 and the memory device 110, such that portions of the external memory controller 105 are implemented by the processor 120 and other portions are implemented by the device memory controller 155 or the local memory controller 165. Likewise, in some cases, one or more functions attributed herein to device memory controller 155 or local memory controller 165 may in some cases be performed by external memory controller 105 (separate from or included in processor 120).

[0049] Components of system 100 may exchange information with memory device 110 using a plurality of wires 115, which may be grouped into channels and their branches (e.g., half-byte wide branches) described herein, and may also include one or more auxiliary wires described herein. In some examples, wires 115 may enable communication between external memory controller 105 and memory device 110. Each wire 115 may include a signal path, which may include one or more transmission media (e.g., conductors) between terminals associated with components of system 100. For example, wire 115 may include a first terminal at external memory controller 105 including a pin or pad (which may be generally referred to as a pin, regardless of the physical shape) and a pin at memory device 110. A pin may be an example of a conductive input or output point of a device of system 100, and a pin may be configured to be used as part of wire 115.

[0050] In some cases, the pins of the terminals may be part of a signal path of line 115. Additional signal paths may be coupled with the terminals of the lines to route signals within components of system 100. For example, memory device 110 may include signal paths (e.g., signal paths internal to memory device 110 or its components, such as internal to memory die 160) that route signals from the terminals of line 115 to various components of memory device 110 (e.g., device memory controller 155, memory die 160, local memory controller 165, memory array 170).

[0051] The lines 115 (and associated signal paths and terminals) may be dedicated to conveying a particular type of information. In some cases, the lines 115 may be aggregated into a channel or a branch thereof. For example, a data channel may include any number of data lines (DQ lines 190) and thus may be x4 (e.g., including 4 DQ lines 190), x8 (e.g., including 8 DQ lines 190), x16 (including 16 DQ lines 190), etc. The signals conveyed through at least some of the lines 115 may use a double data rate (DDR) timing scheme. For example, some symbols of the signal may be recorded on the rising edge of the clock signal, and other symbols of the signal may be recorded on the falling edge of the clock signal. The signals conveyed through the channel may also use single data rate (SDR) signaling. For example, one symbol of the signal may be recorded for each clock cycle.

[0052] In some cases, the lines 115 may include one or more command and address (CA) lines 186. The CA lines 186 may be configured to communicate commands including control information associated with the commands (e.g., address information) between the external memory controller 105 and the memory device 110. For example, one or more CA lines 186 may be used to communicate a read command with an address of desired data. In some cases, the symbols carried by the CA lines 186 may be recorded (e.g., gated) on a rising clock signal edge and / or a falling clock signal edge. In some cases, the CA lines 186 may be grouped into CA channels, which may include any number of signal paths (e.g., 8 or 9 signal paths) for decoding address and command data. In some cases, a CA channel may correspond to (e.g., be dedicated to) a data channel. In other cases, the data channel associated with the information carried via the CA channel may be indicated using a channel select (CS) line (e.g., based on the state of the CS line).

[0053] In some cases, line 115 may include one or more clock signal (CK) lines 188. CK lines 188 may be configured to pass one or more common clock signals between external memory controller 105 and memory device 110. Each clock signal may be configured to oscillate between a high state and a low state and coordinate the actions of external memory controller 105 and memory device 110. In some cases, the clock signal may be a differential output (e.g., a CK_t signal and a CK_c signal), and the signal path of CK line 188 may be configured accordingly. In some cases, the clock signal may be single-ended. CK line 188 may include any number of signal paths. In some cases, clock signal CK (e.g., CK_t signal and CK_c signal) may provide a timing reference for command and addressing operations of memory device 110 or other full system operations of memory device 110. Therefore, clock signal CK may be variously referred to as control clock signal CK, command clock signal CK, or system clock signal CK. The system clock signal CK may be generated by a system clock, which may include one or more hardware components (eg, oscillators, crystals, logic gates, transistors, or the like).

[0054] In some cases, the lines 115 may include one or more data (DQ) lines 190, which may be grouped into channels (data channels) and their branches described herein. The data lines 190 may be configured to pass data and / or control information between the external memory controller 105 and the memory device 110. For example, the data lines 190 may pass information written to the memory device 110 (e.g., bidirectional) or information read from the memory device 110.

[0055] In some cases, line 115 may include one or more other lines 192 that may be dedicated to other purposes. These other lines 192 may include any number of signal paths. In some cases, other lines 192 may include one or more write clock signal (WCK) lines, which may be grouped into one or more WCK channels. Although the 'W' in WCK may nominally stand for "write", the write clock signal WCK (e.g., WCK_t signal and WCK_c signal) may provide a timing reference commonly used for access operations of the memory device 110 (e.g., a timing reference for both read and write operations). Therefore, the write clock signal WCK may also be referred to as a data clock signal WCK. The WCK channel may be configured to pass a common data clock signal between the external memory controller 105 and the memory device 110. The data clock signal may be configured to coordinate access operations (e.g., write operations or read operations) of the external memory controller 105 and the memory device 110. In some cases, the write clock signal may be a differential output (e.g., a WCK_t signal and a WCK_c signal), and the signal path of the WCK channel may be configured accordingly. The WCK channel may include any number of signal paths. The data clock signal WCK may be generated by a data clock, which may include one or more hardware components (e.g., an oscillator, a crystal, a logic gate, a transistor, or the like).

[0056] Lines 115 may couple external memory controller 105 and memory device 110 using a variety of different architectures. Examples of various architectures may include a bus, a point-to-point connection (e.g., a P2P connection), a crossbar switch, a high-density interposer (e.g., a silicon interposer), or a signal path formed in an organic substrate, or some combination thereof. For example, in some cases, the signal path may at least partially include a high-density interposer, such as a silicon interposer or a glass interposer.

[0057] In some cases, other lines 192 may include one or more auxiliary lines. Auxiliary lines may include EDC lines associated with one or more EDC pins on memory device 110. EDC lines may be configured to pass error detection signals (e.g., checksums) to improve system reliability. EDC lines may also pass tracking information, clock information, cyclic redundancy check (CRC) codes, and the like. EDC lines may include any number of signal paths, and in some cases, may be unidirectional (e.g., from memory device 110 to external memory controller 105). In some cases, other lines 192 may include one or more DBI lines associated with one or more DBI pins of memory device 110. DBI lines may be configured to carry information related to data encoding, which may facilitate efficient data transfer, reduce power consumption, and the like. Auxiliary channels (e.g., channels including DBI lines) may include any number of signal paths. In some cases, DBI channels may be unidirectional (e.g., from external memory controller 105 to memory device 110), or in some cases, may be bidirectional. In some cases, a single auxiliary line may convey information associated with (eg, that may otherwise be carried by) both the EDC line and the DBI line (eg, a single auxiliary line may combine the functionality of the EDC line and the DBI line).

[0058] In some examples, the external memory controller 105 may communicate with multiple (e.g., 2) memory devices 110, each having multiple memory dies 160. As an example, at least two memory devices 110 may be positioned on different (opposite) sides of the PCB, which may be referred to as a clamshell configuration or clamshell layout. In some cases, the use of multiple memory devices 110 may increase the memory storage capacity associated with the memory system, so that the external memory controller 105 may have a larger number of memory devices 110 available for information storage. In some memory systems with two memory devices 110, the host device may communicate with the two memory devices 110 as if communicating with a single memory device 110 (e.g., a single package) with twice the storage capacity, while the communication bandwidth (e.g., data rate counted from the host device perspective, data lines 190) may remain the same. In such cases, the communication between the external memory controller 105 and the memory devices 110 may be performed in an operating mode referred to as a half-I / O communication mode, x8 mode, or other similar terms.

[0059] The signals communicated over line 115 may be modulated using a variety of different modulation schemes. In some cases, a binary symbol (or binary level) modulation scheme may be used to modulate the signals communicated between the external memory controller 105 and the memory device 110. The binary symbol modulation scheme may be an example of an M-ary modulation scheme, where M is equal to 2. Each symbol of the binary symbol modulation scheme may be configured to represent one digital data bit (e.g., a symbol may represent a logical 1 or a logical 0). Examples of binary symbol modulation schemes include, but are not limited to, non-return to zero (NRZ), unipolar encoding, bipolar encoding, Manchester encoding, pulse amplitude modulation (PAM) with two symbols (e.g., PAM2), and / or others.

[0060] In some cases, a multi-symbol (or multi-level) modulation scheme may be used to modulate signals communicated between the external memory controller 105 and the memory device 110. The multi-symbol modulation scheme may be an example of an M-ary modulation scheme, where M is greater than or equal to 3. Each symbol of the multi-symbol modulation scheme may be configured to represent more than one digital data bit (e.g., a symbol may represent a logical 00, a logical 01, a logical 10, or a logical 11). Examples of multi-symbol modulation schemes include, but are not limited to, PAM3, PAM4, PAM8, etc., quadrature amplitude modulation (QAM), quadrature phase shift keying (QPSK), and / or others. A multi-symbol signal (e.g., a PAM3 signal or a PAM4 signal) may be a signal modulated using a modulation scheme including at least three levels encoding more than one information bit per symbol. The multi-symbol modulation scheme and symbols may alternatively be referred to as non-binary, multi-bit, or higher order modulation schemes and symbols. In some cases, the multi-symbol modulation scheme may increase the data rate at which data may be communicated via the one or more lines 115. Additionally or alternatively, the data rate at which data can be communicated via one or more lines 115 can be increased by increasing the baud rate and / or increasing the number of lines 115. A higher data rate per line 115 can result in a higher data rate for access commands (eg, read or write commands).

[0061] In some cases, it is desirable to increase the number of data bits transferred per data line 190 per access operation, but it is not desirable to increase the total amount of data received from or provided to a host device (e.g., an external memory controller 105) per access operation. The total amount of data received from or provided to a host device per access operation may be referred to as a data package size, packet size, or codeword size. In some cases, the packet size of a channel may be the product of the number of data bits transferred per data line 190 per access operation, the channel width (e.g., the number of data lines 190 included in the data channel), and the burst length (e.g., the number of symbols or unit intervals) per access operation.

[0062] For example, due to constraints on other devices (such as external memory controller 105) that communicate with memory device 110, it is not desirable to increase the packet size. For example, external memory controller 105 may be a traditional device, a low-power device, a low-throughput device, or otherwise configured to process a smaller amount of data per read or write operation. Additionally or alternatively, external memory controller 105 may process data at a lower data rate for efficiency, power saving, or accuracy. Therefore, as described herein, memory device 110 and external memory controller 105 may be configured with a greater number of independently addressable channels but with a reduced channel width and with one or more branches thereof to further enhance flexibility. For example, memory device 110 may also support transmitting data between memory device 110 and a host device through a data channel using a full I / O mode or a half I / O mode.

[0063] In one example, any number of x8 data lanes may be used to communicate between one or more memory devices 110 and a host device (e.g., as opposed to two data lanes). In full I / O mode, data pins associated with one or more x8 data lanes supported by memory device 110 may each be fully utilized, i.e., for a given x8 data lane operating in full I / O mode, data may be exchanged with memory device 110 via each of the 8 data pins associated with the x8 lane. For example, memory device 110 may support 4 x8 data lanes, each of which may operate in full I / O mode. In partial (e.g., half) I / O mode, data pins of one or more x8 data lanes supported by memory device 110 may each be partially utilized (e.g., a subset of the data pins of the x8 data lanes may be utilized). For example, for a given x8 data lane operating in half I / O mode, data may be exchanged with a memory device 110 via 4 of the 8 data pins associated with the x8 lane, and the other 4 of the 8 data pins associated with the x8 lane may not be utilized. In half I / O mode, each x8 lane may be associated with two memory dies 160, with each memory die 160 at a different memory device 110. For example, 4 data lines of the x8 lane may couple a host device with a first memory die 160 at a first memory device 110, and the remaining 4 data lines of the x8 lane may couple a host device with a second memory die 160 at a second memory device 110.

[0064] In one example, each memory die 160 of the memory device 110 can be coupled with a set of 8 data pins of the memory device 110, the set of 8 data pins comprising two subsets of 4 pins, where each data pin corresponds to a data line 190. In addition, each memory die 160 of the respective memory device 110 can also be coupled with auxiliary pins comprising one or more EDC pins, DBI pins, or pins combining the functionality of EDC pins and DBI pins. In such cases and as described in further detail herein, these auxiliary pins can be dedicated to different subsets of data pins.

[0065] Figure 2 An example of a memory device 200 according to examples disclosed herein is illustrated. The memory device 200 may be a reference Figure 1 1. An example of a memory die 160 is described. In some cases, the memory device 200 may be referred to as a memory chip, a memory device, or an electronic memory device. The memory device 200 may include one or more memory cells 205 that are programmable to store different logical states. Each memory cell 205 is programmable to store two or more states. For example, the memory cell 205 may be configured to store one bit of information at a time (e.g., a logical 0 or a logical 1). In some cases, a single memory cell 205 (e.g., a multi-level memory cell) may be configured to store more than one bit of information at a time (e.g., a logical 00, a logical 01, a logical 10, or a logical 11).

[0066] The memory cell 205 may store a charge representing a programmable state in a capacitor. A DRAM architecture may include a capacitor including a memory dielectric material for storing a charge representing a programmable state. In other memory architectures, other storage devices and components are possible. For example, a nonlinear (e.g., ferroelectric) memory dielectric material may be employed.

[0067] Operations such as reading and writing can be performed on memory cell 205 by activating or selecting access lines such as word line 210 and / or digit line 215. In some cases, digit line 215 may also be referred to as a bit line. References to access line, word line, and digit line or the like may be interchanged without loss of understanding or operation. Activating or selecting word line 210 or digit line 215 may include applying a voltage to the corresponding line.

[0068] The memory device 200 may include access lines, such as word lines 210 and digit lines 215, arranged in a grid-like pattern. Memory cells 205 may be positioned at the intersections of the word lines 210 and digit lines 215. A single memory cell 205 at the intersection thereof may be accessed by biasing the word lines 210 and digit lines 215 (e.g., applying a voltage to the word lines 210 or the digit lines 215).

[0069] Access to the memory cell 205 may be controlled by a row decoder 220 or a column decoder 225. For example, the row decoder 220 may receive a row address from a local memory controller 260 and activate a word line 210 based on the received row address. The column decoder 225 may receive a column address from a local memory controller 260 and may activate a digit line 215 based on the received column address. For example, the memory device 200 may include a plurality of word lines 210 labeled WL_1 to WL_M and a plurality of digit lines 215 labeled DL_1 to DL_N, where M and N depend on the size of the memory array. Thus, a memory cell 205 at its intersection may be accessed by activating a word line 210 and a digit line 215 (e.g., WL_1 and DL_3). In a two-dimensional or three-dimensional configuration, the intersection of a word line 210 and a digit line 215 may be referred to as the address of the memory cell 205.

[0070] Memory cell 205 may include a logic storage component, such as capacitor 230 and switching component 235. Capacitor 230 may be an example of a memory dielectric capacitor or a ferroelectric capacitor. A first node of capacitor 230 may be coupled to switching component 235, and a second node of capacitor 230 may be coupled to voltage source 240. In some cases, voltage source 240 may be a cell plate reference voltage (e.g., Vpl), or may be ground (e.g., Vss). In some cases, voltage source 240 may be an example of a plate line coupled to a plate line driver. Switching component 235 may be an example of a transistor or any other type of switching device that selectively establishes or releases electronic communication between two components.

[0071] Selecting or deselecting memory cell 205 can be accomplished by activating or deactivating switching component 235. Capacitor 230 can be in electronic communication with digit line 215 using switching component 235. For example, capacitor 230 can be isolated from digit line 215 when switching component 235 is deactivated, and capacitor 230 can be coupled to digit line 215 when switching component 235 is activated. In some cases, switching component 235 is a transistor, and its operation can be controlled by applying a voltage to the transistor gate, wherein the voltage difference between the transistor gate and the transistor source can be greater than or less than the threshold voltage of the transistor. In some cases, switching component 235 can be a p-type transistor or an n-type transistor. Word line 210 can be in electronic communication with the gate of switching component 235 and can activate / deactivate switching component 235 based on the voltage applied to word line 210.

[0072] The word line 210 can be a conductive line in electronic communication with the memory cell 205 for performing access operations on the memory cell 205. In some architectures, the word line 210 can be in electronic communication with a gate of a switching element 235 of the memory cell 205 and can be configured to control the switching element 235 of the memory cell. In some architectures, the word line 210 can be in electronic communication with a node of a capacitor of the memory cell 205, and the memory cell 205 may not include a switching element.

[0073] The digit line 215 can be a conductive line connecting the memory cell 205 and the sensing element 245. In some architectures, the memory cell 205 can be selectively coupled to the digit line 215 during portions of an access operation. For example, the word line 210 and the switching element 235 of the memory cell 205 can be configured to couple and / or isolate the capacitor 230 of the memory cell 205 and the digit line 215. In some architectures, the memory cell 205 can be in electronic communication (e.g., continuously) with the digit line 215.

[0074] The sensing component 245 may be configured to detect a state (e.g., charge) stored on the capacitor 230 of the memory cell 205 and determine the logic state of the memory cell 205 based on the stored state. In some cases, the charge stored by the memory cell 205 may be very small. Thus, the sensing component 245 may include one or more sense amplifiers for amplifying the signal output by the memory cell 205. The sense amplifier may detect small changes in the charge of the digit line 215 during a read operation and may generate a signal corresponding to a logic state 0 or a logic state 1 based on the detected charge. During a read operation, the capacitor 230 of the memory cell 205 may output a signal (e.g., discharge the charge) to its corresponding digit line 215. The signal may cause a voltage change of the digit line 215. The sensing component 245 may be configured to compare the signal received across the digit line 215 from the memory cell 205 with a reference signal 250 (e.g., a reference voltage). The sensing component 245 may determine the storage state of the memory cell 205 based on the comparison. For example, in binary signaling, if the digit line 215 has a higher voltage than the reference signal 250, the sensing component 245 can determine that the storage state of the memory cell 205 is a logic 1, and if the digit line 215 has a lower voltage than the reference signal 250, the sensing component 245 can determine that the storage state of the memory cell 205 is a logic 0. The sensing component 245 can include various transistors or amplifiers for detecting and amplifying the signal difference. The detected logic state of the memory cell 205 can be provided as an output of the sensing component 245 (e.g., to the input / output 255), and the detected logic state can be indicated to another component of the memory device 110 (e.g., device memory controller 155) that includes the memory device 200 (e.g., directly or using a local memory controller 260).

[0075] The local memory controller 260 may control the operation of the memory cell 205 through various components such as the row decoder 220, the column decoder 225, and the sensing component 245. The local memory controller 260 may be a reference Figure 1 1. In some cases, one or more of the row decoder 220, the column decoder 225, and the sensing component 245 may be co-located with the local memory controller 260. The local memory controller 260 may be configured to: Figure 1 The local memory controller 260 may receive commands and / or data, translate the commands and / or data into information that can be used by the memory device 200, perform one or more operations on the memory device 200, and transfer data from the memory device 200 to the external memory controller 105 (or device memory controller 155) of the host device in response to performing one or more operations. The local memory controller 260 may generate row and column address signals to activate the target word lines 210 and the target digit lines 215. The local memory controller 260 may also generate and control various voltages or currents used during the operation of the memory device 200. In general, the amplitude, shape, or duration of the applied voltages or currents discussed herein may be adjusted or changed and may be different due to the various operations discussed in operating the memory device 200.

[0076] In some cases, the local memory controller 260 may be configured to perform a write operation (e.g., a programming operation) on one or more memory cells 205 of the memory device 200. During a write operation, a memory cell 205 of the memory device 200 may be programmed to store a desired logic state. In some cases, multiple memory cells 205 may be programmed during a single write operation. The local memory controller 260 may identify a target memory cell 205 on which a write operation is performed. The local memory controller 260 may identify a target word line 210 and a target digit line 215 that are in electronic communication with the target memory cell 205 (e.g., an address of the target memory cell 205). The local memory controller 260 may activate the target word line 210 and the target digit line 215 (e.g., apply a voltage to the word line 210 or the digit line 215) to access the target memory cell 205. The local memory controller 260 may apply a specific signal (e.g., voltage) to the digital line 215 during a write operation to store a specific state (e.g., charge) in the capacitor 230 of the memory cell 205, which may indicate a desired logic state. In one example, the host device may send a write command to the local memory controller 260, where the command may be associated with a specific data rate.

[0077] In some cases, the local memory controller 260 may be configured to perform a read operation (e.g., a sensing operation) on one or more memory cells 205 of the memory device 200. During the read operation, the logic state stored in the memory cell 205 of the memory device 200 may be determined. In some cases, multiple memory cells 205 may be sensed during a single read operation. The local memory controller 260 may identify the target memory cell 205 on which the read operation is performed. The local memory controller 260 may identify the target word line 210 and the target digit line 215 in electronic communication with the target memory cell 205 (e.g., the address of the target memory cell 205). The local memory controller 260 may activate the target word line 210 and the target digit line 215 (e.g., apply a voltage to the word line 210 or the digit line 215) to access the target memory cell 205. The target memory cell 205 may transmit a signal to the sensing component 245 in response to biasing the access line. The sensing component 245 may amplify the signal. The local memory controller 260 may trigger the sensing component 245 (e.g., latch the sensing component) and thereby compare the signal received from the memory cell 205 to the reference signal 250. Based on the comparison, the sensing component 245 may determine the logic state stored on the memory cell 205. As part of a read operation, the local memory controller 260 may communicate the logic state stored on the memory cell 205 to the external memory controller 105 (or device memory controller 155). In one example, the host device may send a read command to the local memory controller 260, where the command may be associated with a particular data rate.

[0078] In some memory architectures, accessing the memory cell 205 may degrade or destroy the logic state stored in the memory cell 205. For example, a read operation performed in a DRAM architecture may partially or completely discharge the capacitor of the target memory cell. The local memory controller 260 may perform a rewrite operation or a refresh operation to return the memory cell to its original logic state. The local memory controller 260 may rewrite the logic state to the target memory cell after the read operation. In some cases, the rewrite operation may be considered as part of the read operation. In addition, activating a single access line (such as word line 210) may disturb the state stored in some memory cells that are in electronic communication with the access line. Therefore, a rewrite operation or a refresh operation may be performed on one or more memory cells that may not have been accessed. In one example, the host device may send a rewrite command to the local memory controller 260, where the command may be associated with a specific data rate.

[0079] In some cases, it may be desirable to increase the number of data bits transferred per data line per access operation, but it may not be desirable to increase the total amount of data received from or provided to the host device per access operation (e.g., data packet size). In some cases, the packet size of a channel may be the product of the number of data bits transferred per data line per access operation, the channel width (e.g., the number of data lines included in the data channel), and the burst length per access operation (e.g., the number of symbols or unit intervals).

[0080] For example, due to constraints on other devices (such as a host device) communicating with the memory device 200, it is not desirable to increase the packet size. For example, the host device may be a traditional device, a low-power device, a low-throughput device, or otherwise configured to process a smaller amount of data per read or write operation. Additionally or alternatively, the host device may process data at a lower data rate for efficiency, power saving, or accuracy. Therefore, as described herein, the memory device 200 and the host device may be configured with a greater number of independently addressable channels but with a reduced channel width. The memory device 200 may also support the use of full I / O mode or half I / O mode to transmit data between the memory device 200 and the host device through the data channel.

[0081] Thus, memory device 200 may be configured to support data channels that include a reduced number of data lines, and in some cases may support an increased number of such data channels or may be included in a device that supports an increased number of such data channels. In one example, memory device 200 may be coupled to a set of 8 data pins of memory device 110 that includes memory device 200 (e.g., input / output 255 may be coupled to the set of 8 data pins). The set of 8 data pins may include two subsets of 4 pins. In full I / O mode, the two subsets of 4 data pins coupled to memory device 200 may in turn be coupled to a host device, and the set of 8 data pins may correspond to channels (e.g., be included in a channel). In other examples (e.g., examples using half I / O mode), one of the subsets of 4 data pins coupled to memory device 200 may in turn be coupled to a host device, with one set not being connected (e.g., floating). Here, the host device can communicate with the memory device 200 via a first set of 4 data lines coupled to a subset of 4 data pins, and can communicate with the second memory device 200 via a second subset of 4 data lines, wherein the first subset of 4 data lines and the second subset of 4 data lines can collectively correspond to (e.g., be included in) a channel. The memory device 200 can also be coupled to one or more EDC pins, DBI pins, or pins that combine the functionality of an EDC pin and a DBI pin.

[0082] Figure 3An example of a device configuration 300 supporting multiple memory die technology according to examples disclosed herein is illustrated. Device configuration 300 may be an example of a communication configuration of a memory device 305 that includes a point-to-point connection to a host device 310. In some cases, memory device 305 may be an example of memory device 110 or 200, include the example, or be included in the example, as described with reference to FIG. Figure 1 and 2 In some cases, host device 310 and memory device 305 may together implement aspects of memory device 110 or 200, as described in reference Figure 1 and 2 Description. In some cases, memory device 305 may be an example of a DRAM memory device. In some examples, memory device 305 and host device 310 may employ device configuration 300 to transfer data corresponding to memory commands (eg, read, write, overwrite, etc.).

[0083] The memory device 305 can include one or more memory dies 340 (eg, the memory device 305 can contain any number of memory dies 340), which can be referenced. Figure 1 Memory device 305 may also be configured with one or more data pins 320 operable to transmit data and one or more auxiliary pins 330 operable to transmit control and other information (e.g., EDC or DBI information). In some cases, an auxiliary pin 330 (or multiple auxiliary pins 330) may be dedicated to one or more data pins 320. Data pins 320 or auxiliary pins 330 may be examples of pins, balls, connectors, or the like.

[0084] Memory die 340 may store data in one or more memory cells and may include an I / O interface 345 that may be used to transmit and receive data from host device 310. For example, I / O interface 345 may be coupled with one or more electrical connections 335 that may couple I / O interface 345 to one or more data pins 320 and / or one or more auxiliary pins 330.

[0085] The data pins 320 may be coupled to the host device 310 via data lines 315, which may represent an electrical connection (e.g., a solder connection, a printed circuit board (PCB) connection, etc.) between the memory device 305 and the host device 310 (e.g., DQ line 190). Similarly, the auxiliary pins 330 may be coupled to the host device 310 via auxiliary lines 325, which may represent an electrical connection (e.g., line 115) between the memory device 305 and the host device 310. For example, a data pin 320-a at the memory device 305 may be coupled to a data pin 320-b at the host device 310 via data lines 315, and an auxiliary pin 330-a at the memory device 305 may be coupled to an auxiliary pin 330-b at the host device 310 via auxiliary lines 325. The data pins 320 and auxiliary pins 330 at the host device 310 may interface with an I / O component of the host device, where the host device 310 may transmit and / or receive data via the I / O component. Each data line 315 and auxiliary line 325 may connect the memory device 305 and the host device 310 via a P2P connection such that each data pin 320 or auxiliary pin 330 at the memory device 305 may be coupled with one data pin 320 or auxiliary pin 330 at the host device 310. In some cases, a memory die 340 may be associated with one auxiliary pin 330, or in other cases, a memory die 340 may be associated with two auxiliary pins 330, four auxiliary pins 330, or another number of auxiliary pins 330.

[0086] The memory die 340 may operate in a full I / O mode, where all data pins 320-a associated with the memory die 340 may be coupled with the host device 310 (e.g., via data lines 315). Additionally or alternatively, the memory die 340 may operate in a half I / O mode or clamshell mode, where half of the data pins 320-a associated with the memory die 340 may be coupled with the host device 310 (e.g., via data lines 315). In one example, the memory die 340 may be associated with eight data pins 320-a and up to four auxiliary pins 330-a to communicate with the host device 310.

[0087] In some examples, the memory device 305 may be configured such that the 8 data pins 320 are independently addressable entities for data transfer. An independently addressable entity may be associated with a data channel (e.g., 8 data pins 320 may be associated with a channel). A channel may represent a group of independently addressable data lines 315 (e.g., 8 data pins 320) or may represent a logical entity for data transfer. A channel may be associated with one or more auxiliary pins 330 and corresponding auxiliary lines 325. In some cases, the 8 data pins 320 associated with one channel may correspond to one memory die 340 (e.g., in full I / O mode), or in other cases, a group of 4 data pins 320 may correspond to a first memory die 340, and a group of 4 data pins 320 may correspond to a second memory die 340 (not shown) (e.g., in half I / O mode). Thus, each memory die 340 of the memory device 305 can be associated with two segments of data pins 320 (e.g., two segments of 4 data pins 320) such that in half I / O mode, one of the two segments (e.g., 4 data pins 320) can be coupled with the host device 310, and in full I / O mode, both segments (e.g., 8 data pins 320) can be coupled with the host device 310.

[0088] An access operation (e.g., a read or write operation) may include transmitting data through the data lines 315 of a channel. For each access operation, the host device 310 or the memory device 305 may transmit a number of data bits through each data line 315 associated with the channel. Thus, for each access operation, the data lines of one channel may carry a number of bits, which may be referred to as a data packet size, equal to a multiple of the number of data lines 315 associated with the channel and the number of bits transmitted through each data line 315. For example, in conjunction with one read or write operation, one channel including 8 data lines 315, each of which carries 32 bits per read or write operation, may carry a data packet including 256 bits or 32 bytes. As described herein, channels may be independent, and access operations may be performed independently through different channels (and thus exchange independent data packets).

[0089] In some cases, the memory device 305 and / or the host device 310 may be configured to transfer a relatively large amount of data per data line 315 per access command (e.g., 32 bits per data line 315 per access command, as opposed to, for example, 16 bits). For example, the associated baud rate may be increased or the level of the modulation scheme may be increased, or both, to transfer a relatively large amount of data per data line per access command. However, in some cases, a constant data package size may be desired. For example, the host device 310 may be a conventional device, a low-power device, a low-throughput device, or may otherwise be configured to process a fixed amount of data per read or write operation. Additionally or alternatively, the host device 310 may process data at a lower data rate for efficiency, power conservation, or accuracy. Therefore, in some cases, the memory device 305 and the host device 310 may be configured to communicate over a channel with a relatively low number of data lines 315 per channel (e.g., 8 data lines 315 per channel, as opposed to, for example, 16).

[0090] Figure 4 An example of a device configuration 400 supporting multiple memory die technology according to examples disclosed herein is illustrated. Device configuration 400 can be an example of a communication configuration of a memory device 405 that includes a P2P connection to a host device 410. In some cases, memory device 405 can be an example of memory device 110, 200, or 305, include the examples, or be included in the examples, as described with reference to Figures 1 to 3 In some cases, host device 410 and memory device 405 may together implement aspects of memory device 110 or 200, as described in reference Figure 1 and 2 Description. In some cases, memory device 405 may be an example of a DRAM memory device. Memory device 405 and host device 410 may employ device configuration 400 to transfer data in full I / O mode or half I / O mode (eg, clamshell mode), or any combination thereof.

[0091] As reference Figure 34. As shown in FIG. 4, a channel for data transfer between a memory device 405 and a host device 410 may be associated with a number of data lines 415 and with one or more auxiliary lines, such as a DBI line 420 and / or an EDC line 425. A channel may be a logical or physical entity for transferring data between a memory device 405 and a host device 410 using a full I / O mode or a half I / O mode. In one example of a full I / O mode, a channel may include eight data lines 415, wherein the eight data lines 415 may be coupled with one memory die 430 of the memory device 405 (e.g., via data pins and device connections to the memory die 430). In one example of a half I / O mode, a channel may include eight data lines 415, wherein four of the data lines 415 may be coupled with a first memory die 430 and four of the data lines 415 may be coupled with a second memory die 430. In some modes, the host device 410 may also be coupled with a second memory device (not shown). For example, host device 410 may be coupled to memory die 430 of memory device 405 via four data lines 415, DBI line 420, EDC line 425, and may be coupled to memory die 430 on a second memory device in a similar manner.

[0092] The memory die 430 on the memory device 405 may include one or more independent I / O segments 435 (e.g., including segments 435-a and 435-b) that can independently transmit, receive, or operate in a silent mode. Each segment 435 of the memory die 430 may be coupled to a number of data pins associated with a channel (e.g., coupled to 4 pins, which in some cases may each be a subset of a set of 8 pins associated with a channel). Each segment 435 of the memory die 430 may also be coupled to a corresponding DBI line 420 and a corresponding EDC line 425 (e.g., via an auxiliary pin and device connection to the memory die 430). For example, segment 435-a may be coupled to one auxiliary pin corresponding to DBI line 420-a, one auxiliary pin corresponding to EDC line 425-a, and 4 data pins corresponding to 4 data lines 415-a (e.g., pins for half of the data lines 415-a corresponding to a channel). Similarly, segment 435-b may be coupled with one auxiliary pin corresponding to DBI line 420-b, one auxiliary pin corresponding to EDC line 425-b, and four data pins corresponding to four data lines 415-b. In such a case, each DBI line 420 and each EDC line 425 may be dedicated to conveying auxiliary information associated with respective data conveyed via data line 415 of the same segment 435.

[0093] Additionally or alternatively, one section 435 of memory die 430 (e.g., section 435-b) may not be coupled to any auxiliary pins, but may be coupled to four data pins corresponding to four data lines 415-b. In such cases, DBI line 420-a and EDC line 425-a may be dedicated to transmitting auxiliary information associated with data transmitted via both data line 415-a and data line 415-b. In some cases, when one section 435 is not coupled to any auxiliary pins, memory device 405 may be configured with a set of auxiliary pins associated with each memory die 430, which may simplify manufacturing and setup.

[0094] In some cases, memory device 405 may benefit from being configured with two sets of auxiliary pins per channel that may each be coupled to memory die 430. For example, in full I / O mode or half I / O mode, host device 410 may be coupled to one or both of DBI lines 420-a and 420-b and one or both of EDC lines 425-a and 425-b. In cases where host device 410 is coupled to both DBI lines 420-a and 420-b and / or both EDC lines 425-a and 425-b, two DBI lines 420 and EDC lines 425 may be utilized to simplify control transmissions, increase encoding space, and transmit additional information associated with access commands (e.g., increase functionality of DBI lines 420 and / or EDC lines 425 due to additional bandwidth). In some cases, an access command may cause memory device 405 to read or write 32 bits of information per data line 415, such that data lines 415-a and 415-b may each transfer 128 bits per access command (e.g., 32 bits transferred over 4 data lines 415). The total number of available bits on the I / O of each sector 435 (e.g., via EDC lines 425 or DBI lines 420) may be 160 bits, resulting in a 128:160 bit encoding scheme.

[0095] Figure 5 An example of a device configuration 500 supporting multiple memory die technology according to examples disclosed herein is illustrated. Device configuration 500 may be an example of a communication configuration of a memory device 505 that includes a P2P connection to a host device 510. In some cases, memory device 505 may be, include, or be included in an example of memory device 110, 200, 305, or 405, as described with reference to FIG. Figures 1 to 4 In some cases, host device 510 and memory device 505 may together implement aspects of memory device 110 or 200, as described in reference Figure 1 and 2Description. In some cases, memory device 505 may be an example of a DRAM memory device. Memory device 505 and host device 510 may employ device configuration 500 to transfer data in full I / O mode or half I / O mode (eg, clamshell mode), or any combination thereof.

[0096] As reference Figure 3 5. In the embodiment of the present invention, a channel for data transfer between a memory device 505 and a host device 510 may be associated with a number of data lines 515 and with one or more auxiliary lines, such as auxiliary lines 520. A channel may be a logical or physical entity for transferring data between a memory device 505 and a host device 510 using a full I / O mode or a half I / O mode. In one example of a full I / O mode, a channel may include 8 data lines 515, wherein the 8 data lines 515 may be coupled with one memory die 530 of the memory device 505 (e.g., via data pins and device connections to the memory die 530). In one example of a half I / O mode, a channel may include 8 data lines 515, wherein four of the data lines 515 may be coupled with a first memory die 530 and four of the data lines 515 may be coupled with a second memory die 530. In some modes, the host device 510 may also be coupled with a second memory device (not shown). For example, host device 510 may be coupled to memory die 530 on memory device 505 via four data lines 415 and auxiliary lines 520, and may be coupled to memory die 530 on a second memory device in a similar manner.

[0097] As described herein, auxiliary lines 520 may be configured to convey tracking information (e.g., EDC retention model), encoding (e.g., DBI encoding), error detection information (e.g., using CRC codes), timing information, and other information that may be transmitted over EDC lines or DBI lines. Auxiliary lines 520 may further be configured to transmit a number of signals equal to the number of signal combinations transmitted over EDC lines and DBI lines for one access command.

[0098] The memory die 530 on the memory device 505 may include one or more independent I / O segments 535 (e.g., including 535-a and 535-b) that can independently transmit, receive, or operate in silent mode. Each segment 535 of the memory die 530 may be coupled to half of the data pins associated with a channel (e.g., coupled to 4 pins, which in some cases may each be a subset of a set of 8 pins associated with a channel). Each segment 535 of the memory die 530 may also be coupled to a corresponding auxiliary line 520 (e.g., via an auxiliary pin and device connection to the memory die 530). For example, segment 535-a may be coupled to one auxiliary pin corresponding to the auxiliary line 520-a and 4 data pins corresponding to 4 data lines 515-a (e.g., pins for half of the data lines 515-a corresponding to the channel). Similarly, segment 535-b can be coupled to one auxiliary pin corresponding to auxiliary line 520-b and four data pins corresponding to four data lines 515-b. In such a case, each auxiliary line 520 can be dedicated to transmitting auxiliary information associated with corresponding data transmitted via data line 515 of the same segment 535.

[0099] Additionally or alternatively, one section 535 of memory die 530 (e.g., section 535-b) may not be coupled to any auxiliary pins, but may be coupled to four data pins corresponding to four data lines 515-b. In such cases, auxiliary lines 520-a may be dedicated to transmitting auxiliary information associated with data transmitted via both data lines 515-a and data lines 515-b. In some cases, when one section 535 is not coupled to any auxiliary pins, memory device 505 may be configured with a set of auxiliary pins associated with each memory die 530, which may simplify manufacturing and setup.

[0100] In some cases, a memory device 505 may benefit from being configured with two sets of auxiliary pins per channel that may each be coupled to a memory die 530. For example, in full I / O mode or half I / O mode, a host device 510 may be coupled to one or both of auxiliary lines 520-a and 520-b. In cases where the host device 510 is coupled to both auxiliary lines 520-a and 520-b, two auxiliary lines 520 may be utilized to simplify control transmissions, increase encoding space, and transmit additional information associated with access commands (e.g., increase the functionality of auxiliary lines 520 due to additional bandwidth). In some cases, an access command may cause the memory device 505 to read or write 32 bits of information per data line 515, such that data lines 515-a and 515-b may each transfer 128 bits per access command (e.g., 32 bits transferred over 4 data lines 515). The total number of available bits on the I / O of each segment 535 (eg, via auxiliary lines 520) may be 160 bits, resulting in a 128:160 bit encoding scheme.

[0101] Figure 6 An example of a communication configuration 600 supporting multiple memory die technology according to examples disclosed herein is illustrated. The communication configuration 600 can be implemented by a memory device 605 and a host device 610 (e.g., an external memory controller of the device), where data or information can be transferred between the host device 610 and the memory device 605 through one or more channels. In some cases, the memory device 605 can be a memory device such as the one described in reference to FIG. Figures 1 to 5 10, 110, 120, 130, 140, 150, 160, 170, 180, 190, 200, 210, 220, 230, 240, 250, 260, 270, 280, 290, 300, 310, 320, 330, 340, 350, 360, 370, 380, 390, 400, 410, 420, 430, 440, 450, 460, 470, 480, 490, 500, 600, 610, 620, 630, 640, 650, 660, 670, 680, 690, 700, 710, 720, 730, 740, 750, 760, 770, 780, 790, 800, 810, 820, 830, 840, 850, 860, 870, 880, 890, 900, 910, 920, 930, 940, 950, 960, 970, 980, 990, 1000, 1010, 1020, 1030, 1040, 1050, 1060, 1070, 1080, 1090, 1110, 1120, 1130, 1140, 1150, 1160, 1170, 1180

[0102] As reference Figure 3As described, the memory device 605 may be configured with a number of data pins (e.g., as fixed by physical constraints). The host device 610 or the memory device 605 may transfer data in full I / O mode using channels (e.g., independently configured data transfer entities), wherein each channel may include or be associated with a certain number of data lines 615 (e.g., 8 data lines 615). In one example, the memory device 605 may be configured with 32 data pins, which may be grouped into four groups of 8 data pins. Additionally or alternatively, the memory device 605 may be configured with any number of data pins, such as multiple groups of 4 data pins or multiple groups of 8 data pins. In some cases, each group of 8 data pins may be coupled to a corresponding group of 8 data lines 615 that may be included in the same channel. According to the full I / O mode, all data pins in each group of 8 data pins at the memory device 605 may be associated with a channel and used for data transfer. As described in reference to Figure 3 In the description, according to the full I / O mode, the data line 615 can also be coupled to each data pin associated with the memory die 625, where each group of 8 data pins can represent data pins associated with the memory die 625. Thus, each memory die 625 can be coupled to a number of data lines 615 (e.g., 8 data lines 615) corresponding to a channel.

[0103] The host device 610 may also be configured with data pins (e.g., as part of an I / O interface 620) that may be coupled to a data line 615 (e.g., a data line 615 associated with a channel). Thus, the I / O interface 620 of the host device 610 may be coupled to one or more memory dies 625 of the memory device 605. In some examples, each I / O interface 620 may represent a group of 8 data pins, where the 8 data pins of the I / O interface 620 may be part of an individual I / O component or a collective I / O component on the host device 610. In some cases, each group of 8 data pins at the memory device 605 or host device 610 may be associated with one or more auxiliary pins that may be used for encoding, tracking, error checking, etc., such as reference Figure 2 Each auxiliary pin at the memory device 605 can be coupled to a corresponding auxiliary pin at the host device 610 via a corresponding auxiliary line (not shown). Various auxiliary pins and related auxiliary line configurations that can be implemented in the communication configuration 600 are shown in FIG. Figures 3 to 5 Describe in more detail.

[0104] In the communication configuration 600, 4 channels may be used to transfer data between the memory device 605 and the host device 610, such that each channel may be associated with (e.g., include) ¼ of the total number of data lines 615 coupled to the memory device 605 and the host device 610. In some examples, a number of channels greater or less than 4 channels may be used to transfer data between the memory device 605 and the host device 610. In some examples, the host device 610 may transfer data to or receive data from multiple memory devices 605 over one or more channels.

[0105] In one example, each channel can be associated with 8 data pins, one or more auxiliary pins (such as DBI, EDC and / or other auxiliary pins), and corresponding data and auxiliary lines. The pins corresponding to one channel or one memory die 625 can be based on the reference Figures 3 to 5 In such a case, auxiliary pins (including DBI, EDC, and / or other auxiliary pins) may be dedicated to the eight data lines 615 for each channel.

[0106] As shown, a set of data lines 615-a associated with a first channel (e.g., channel A) can couple an I / O interface 620-a of a host device 610 with a memory die 625-a of a memory device 605 (e.g., the devices can be coupled via corresponding lines and pins). Similarly, a set of data lines 615-b associated with a second channel can couple an I / O interface 620-b with a memory die 625-b, and so on for data lines 615-c and 615-d. Thus, each of the four channels can be associated with a separate memory die 625-a to 625-d, respectively, and each channel can be associated with eight data lines 615. By using the communication configuration 600, a lower number of data lines 615 can be associated with one channel, and one access command can maintain a specific data rate and packet size, i.e., a higher number of bits are transmitted using each access command signal.

[0107] Figure 7 An example of a communication configuration 700 supporting multiple memory die technology according to examples disclosed herein is illustrated. The communication configuration 700 may be implemented by a host device 710 (e.g., an external memory controller of the device) and one or more memory devices 705 (e.g., memory devices 705-a and 705-b), wherein data or information may be transferred between the host device 710 and one or both of the memory devices 705 via one or more channels. In some cases, the memory device 705 may be, include, or be included in an instance of the memory device 110, 200, 305, 405, 505, or 605, as described with reference to FIG. Figures 1 to 6705-a and 705-b may be DRAMs located at the top of the PCB. In some examples, memory devices 705-b may be DRAMs located at the bottom of the PCB (e.g., in a clamshell layout). Memory devices 705-a, 705-b, and host devices 710, and systems including memory devices 705 and host devices 710, may implement communication configuration 700 to read and write data when operating in a semi-I / O mode (e.g., as part of a clamshell mode). In some cases, host device 710 may be coupled with more than two memory devices 705 to implement a semi-I / O mode.

[0108] As reference Figure 3 As described above, the memory device 705 may be configured with a number of data pins (e.g., as fixed by physical constraints). The host device 710 or the memory device 705 may transfer data in semi-I / O mode using channels (e.g., independently configured data transfer entities), where each channel may include or be associated with a certain number of data lines 715 (e.g., 8 data lines 715). In one example, the memory device 705 may be configured with 32 data pins, which may be grouped into four groups of 8 data pins. Additionally or alternatively, the memory device 705 may be configured with any number of data pins, such as multiple groups of 4 data pins or multiple groups of 8 data pins. As described in reference Figure 3 As depicted, each group of 8 data pins may represent data pins associated with memory die 725 .

[0109] According to the half I / O mode, half of the data pins (e.g., 4 data pins) in each set of 8 data pins may be coupled to a corresponding set of 4 data lines 715 that may be included in the same channel. Half of the data pins (e.g., 4 data pins) in each set of 8 data pins on another memory device 705 may be coupled to a corresponding set of 4 data lines 715 that may be included in the same channel. In some cases, two sets of 4 data lines 715 from two separate memory devices 705 (e.g., memory devices 705-a and 705-b) may be associated with the same channel such that the channel may include a total of 8 data lines 715, with 4 data lines 715 coupled to each memory device 705. The 4 data lines 715 associated with the same channel and coupled to the memory devices 705 may be coupled to the same memory die 725 of the memory devices such that half of the data pins associated with the memory die are coupled to the data lines 715 (e.g., in the half I / O mode). Thus, each memory die 725 may be coupled with half of the number of data lines 715 corresponding to a channel (eg, 4 data lines 715).

[0110] The host device 710 may also be configured with data pins (e.g., as part of an I / O interface 720) that may be coupled to a data line 715 (e.g., a data line 715 associated with a channel). Thus, the I / O interface 720 of the host device 710 may be coupled to one or more memory dies 725 of the memory device 705. In some examples, each I / O interface 720 may represent a group of 8 data pins, where the 8 data pins of the I / O interface 720 may be part of an individual I / O component or a collective I / O component on the host device 710. In some cases, each group of 8 data pins at the memory device 705 or host device 710 may be associated with one or more auxiliary pins that may be used for encoding, tracking, error checking, etc., such as reference Figure 2 Each auxiliary pin at the memory device 705 can be coupled to a corresponding auxiliary pin at the host device 710 via a corresponding auxiliary line (not shown). Auxiliary pins and related auxiliary line configurations that can be used for the communication configuration 700 are shown in FIG. Figures 3 to 5 Describe in more detail.

[0111] In the communication configuration 700, 4 channels may be used to transfer data between the memory device 705 and the host device 710, such that each channel may be associated with (e.g., include) ¼ of the total number of data lines 715 coupled to the memory device 705 and the host device 710. In some examples, a number of channels greater or less than 4 channels may be used to transfer data between the memory device 705 and the host device 710. In some examples, the host device 710 may transfer data to or receive data from multiple memory devices 705 via one or more channels.

[0112] In one example, each channel can be associated with 8 data pins, one or more auxiliary pins (such as DBI, EDC and / or other auxiliary pins), and corresponding data and auxiliary lines. The pins corresponding to one channel or one memory die 725 can be based on the reference Figures 3 to 5 In such a case, auxiliary pins (including DBI, EDC, and / or other auxiliary pins) can be dedicated to the four data lines 715 for each channel coupled to one memory die 725.

[0113] As shown, in half I / O mode, a set of data lines 715-a associated with a first channel (e.g., channel A) can couple an I / O interface 720-a of a host device 710 with a memory die 725-a of a memory device 705-a and a memory die 725-e of a memory device 705-b (e.g., the devices can be coupled via corresponding lines and pins). Similarly, a set of data lines 715-b associated with a second channel can couple an I / O interface 720-b with memory dies 725-b and 725-f, and data lines 715-c and 715-d, and so on. Thus, each of the four channels can be associated with two separate memory dies 725, and each channel can be associated with eight data lines 715 (e.g., where four data lines 715 are coupled to each of the two memory dies 725). A channel can be associated with a first segment 730 of each memory die 725 and a corresponding I / O interface 720 of the host device 710, as described with reference to Figure 4 and 5 For example, segment 730-a of memory die 725-a may be coupled to four data lines 715 and corresponding auxiliary lines (e.g., via pins associated with segment 730-a), while segment 735-a of memory die 725-a may not be coupled to any data lines 715. By using communication configuration 700, a lower number of data lines 715 may be associated with one channel, and one access command may maintain a particular data rate and packet size, i.e., a higher number of bits may be transmitted using each access command signal.

[0114] Figure 8 A block diagram 800 is shown of a memory device 805 supporting multiple memory die technology according to examples disclosed herein. The memory device 805 may be a reference Figures 1 to 7 Memory device 805 may include a communication manager 810, a data manager 815, a mode manager 820, a decoder 825, and an EDC component 830. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

[0115] The communication manager 810 may communicate first data between the first memory die and the host device via a first set of four data pins and communicate channel encoding information for the first data via a first auxiliary pin corresponding to the first set of four data pins. In some examples, the communication manager 810 may communicate second data between the second memory die and the host device via a second set of four data pins and communicate channel encoding information for the second data via a second auxiliary pin corresponding to the second set of four data pins.

[0116] The data manager 815 may receive the first data via the first set of four data pins. In some examples, the data manager 815 may identify the first data based on channel coding information of the first data, wherein the channel coding information of the first data may include data coding information of the first data. In such cases, the first auxiliary pin may include a data coding pin.

[0117] The mode manager 820 may determine a first mode for a first set of four data pins based on one or more access commands, wherein the first data is transmitted based on the first mode. In some examples, the mode manager 820 may determine a second mode for a second set of four data pins based on one or more access commands, wherein the second data is transmitted based on the second mode. In some cases, the first mode and the second mode each include at least one of a transmission mode, a reception mode, or a silent mode.

[0118] The decoder 825 may decode the first data based on the channel coding information of the first data, wherein the channel coding information of the first data includes EDC information of the first data, data coding information of the first data, or any combination thereof.

[0119] The EDC component 830 may transmit EDC information from the first memory die to the host device via the EDC pins of the first set of four data pins, wherein the EDC information is based on identifying the first data.

[0120] Fig. 9 A flowchart illustrating one or more methods 900 of supporting multi-memory die technology according to aspects of the present invention is shown. The operations of the method 900 may be implemented by a memory device or components thereof described herein. For example, the operations of the method 900 may be implemented by reference to Figure 8 The memory device described herein performs. In some examples, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0121] At 905, the memory device may communicate first data between the first memory die and the host device via a first set of four data pins and communicate channel encoding information for the first data via a first auxiliary pin corresponding to the first set of four data pins. Operation 905 may be performed according to the methods described herein. In some examples, aspects of operation 905 may be described with reference to Figure 8 Describes the communication manager implementation.

[0122] At 910, the memory device may communicate second data between the second memory die and the host device via a second set of four data pins and communicate channel encoding information for the second data via a second auxiliary pin corresponding to the second set of four data pins. Operation 910 may be performed according to methods described herein. In some examples, aspects of operation 910 may be described with reference to Figure 8 Describes the communication manager implementation.

[0123] In some examples, an apparatus described herein may perform one or more methods, such as method 900. An apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for communicating first data between a first memory die and a host device via a first set of 4 data pins and communicating channel encoding information for the first data via a first auxiliary pin corresponding to the first set of 4 data pins, and communicating second data between a second memory die and a host device via a second set of 4 data pins and communicating channel encoding information for the second data via a second auxiliary pin corresponding to the second set of 4 data pins.

[0124] In some examples of the method 900 and apparatus described herein, the method further includes: transmitting the first data may include an operation, feature, means, or instruction for receiving the first data via a first set of four data pins.

[0125] In some examples of the method 900 and apparatus described herein, the method further includes: transmitting the first data may include an operation, feature, means, or instruction for receiving the first data via a first set of four data pins.

[0126] Some instances of the method 900 and apparatus described herein may further include operations, features, components, or instructions for determining a first mode for a first group of four data pins based on one or more access commands (wherein transferring first data may be based on the first mode) and determining a second mode for a second group of four data pins based on one or more access commands (wherein transferring second data may be based on the second mode).

[0127] In some examples of the method 900 and apparatus described herein, the first mode and the second mode each include at least one of a transmission mode, a reception mode, or a silence mode.

[0128] Fig.10 A flowchart illustrating one or more methods 1000 of supporting multi-memory die technology according to aspects of the present invention is shown. The operations of the method 1000 may be implemented by a memory device or components thereof described herein. For example, the operations of the method 1000 may be implemented by reference to Figure 8 The memory device described herein performs. In some examples, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0129] At 1005, the memory device may communicate first data between the first memory die and the host device via a first set of four data pins and communicate channel encoding information for the first data via a first auxiliary pin corresponding to the first set of four data pins. Operation 1005 may be performed according to the methods described herein. In some examples, aspects of operation 1005 may be described with reference to Figure 8 Describes the communication manager implementation.

[0130] At 1010, the memory device may communicate second data between the second memory die and the host device via a second set of four data pins and communicate channel encoding information for the second data via a second auxiliary pin corresponding to the second set of four data pins. Operation 1010 may be performed according to methods described herein. In some examples, aspects of operation 1010 may be described with reference to Figure 8 Describes the communication manager implementation.

[0131] At 1015, the memory device may decode the first data based on channel coding information of the first data, wherein the channel coding information of the first data includes EDC information of the first data, data coding information of the first data, or any combination thereof. Operation 1015 may be performed according to the methods described herein. In some examples, aspects of operation 1015 may be described by reference to Figure 8 Describes the data manager implementation.

[0132] Fig.11 A flowchart illustrating one or more methods 1100 of supporting multi-memory die technology according to aspects of the present invention is shown. The operations of the method 1100 may be implemented by a memory device or components thereof described herein. For example, the operations of the method 1100 may be implemented by reference to Figure 8 The memory device described herein performs. In some examples, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0133] At 1105, the memory device may communicate first data between the first memory die and the host device via a first set of four data pins and communicate channel encoding information for the first data via a first auxiliary pin corresponding to the first set of four data pins. Operation 1105 may be performed according to the methods described herein. In some examples, aspects of operation 1105 may be described with reference to Figure 8 Describes the communication manager implementation.

[0134] At 1110, the memory device may communicate second data between the second memory die and the host device via a second set of four data pins and communicate channel encoding information for the second data via a second auxiliary pin corresponding to the second set of four data pins. Operation 1110 may be performed according to methods described herein. In some examples, aspects of operation 1110 may be described with reference to Figure 8 Describes the communication manager implementation.

[0135] At 1115, the memory device may identify the first data based on the channel coding information of the first data, the channel coding information of the first data including data coding information of the first data, wherein the first auxiliary pin includes the data coding pin. Operation 1115 may be performed according to the methods described herein. In some examples, aspects of operation 1115 may be described by reference to Figure 8 Describes the data manager implementation.

[0136] At 1120, the memory device may transmit EDC information from the first memory die to the host device via the EDC pins of the first set of four data pins, wherein the EDC information is based on identifying the first data. Operation 1120 may be performed according to the methods described herein. In some examples, aspects of operation 1120 may be described with reference to Figure 8 Describes the implementation of the EDC components.

[0137] It should be noted that the methods described herein describe possible implementations, and that operations and steps may be rearranged or otherwise modified, and other implementations are possible. In addition, parts from two or more of the methods may be combined.

[0138] An apparatus is described. The apparatus may include a memory device including a set of memory dies, each memory die in the set operable to communicate with a host device via: a set of 8 data pins including a first subset of 4 data pins and a second subset of 4 data pins, the first subset of 4 data pins and the second subset of 4 data pins being operable to be independently addressable; and an auxiliary pin operable to carry channel encoding information of the first subset of 4 data pins.

[0139] In some instances, the channel coding information of the first subset of 4 data pins includes EDC signaling of the first subset of 4 data pins, data coding signaling of the first subset of 4 data pins, or any combination thereof. In some instances, the data coding signaling and the EDC signaling may be encoded according to the same coding scheme. Some instances of the apparatus may include a second auxiliary pin operable to carry second channel coding information of the second subset of 4 data pins. Some instances of the apparatus may include a second auxiliary pin operable to carry second channel coding information of the first subset of 4 data pins.

[0140] In some instances, the auxiliary pin is operable to carry data encoding signaling of the first subset of four data pins, and the second auxiliary pin is operable to carry EDC signaling of the first subset of four data pins. In some instances, the data encoding signaling indicates DBI information of data passed via the first subset of four data pins. In some instances, the EDC signaling indicates tracking information, a retention model, a CRC code, or a combination thereof, of data passed via the first subset of four data pins. Some instances of the apparatus may include a second EDC pin operable to carry EDC signaling of the second subset of four data pins, wherein the auxiliary pin includes a first EDC pin.

[0141] Some instances of the apparatus may include a second data encoding pin operable to carry a second data encoding signaling of the second subset of 4 data pins, wherein the second auxiliary pin includes the first data encoding pin. In some instances, the auxiliary pin and the second auxiliary pin are further operable to carry the channel encoding information and the second channel encoding information of the group of 8 data pins. In some instances, the auxiliary pin is further operable to carry the second channel encoding information of the group of 8 pins, the second channel encoding information including EDC signaling and data encoding signaling of the group of 8 pins. Some instances of the apparatus may include: a first transceiver operable to transmit first data via the first subset of 4 data pins based on the channel encoding information of the first subset of 4 data pins; and a second transceiver operable to transmit second data via the second subset of 4 data pins based on the second channel encoding information of the second subset of 4 data pins.

[0142] An apparatus is described. The apparatus may include a host device operable to communicate with a group of memory dies, wherein the host device is operable to communicate with respective memory dies in the group via: a group of 8 data pins including a first subset of 4 data pins and a second subset of 4 data pins, the first subset of 4 data pins and the second subset of 4 data pins being operable to be independently addressable; and an auxiliary pin operable to carry channel encoding information of the first subset of 4 data pins.

[0143] In some examples, the channel coding information of the first subset of four data pins includes EDC signaling and data coding signaling for the first subset of four data pins, the data coding signaling and the EDC signaling being encoded according to the same coding scheme. Some examples of the apparatus may include a second auxiliary pin operable to carry second channel coding information for the first subset of four data pins, wherein the auxiliary pin is operable to carry data coding signaling for the first subset of four data pins, and the second auxiliary pin is operable to carry EDC signaling for the first subset of four data pins.

[0144] A system is described. The system may include: a memory device including a group of memory dies; and a host device coupled to the memory device, the system operable to: communicate data between the host device and a corresponding memory die in the group via a group of 8 data pins, the group of 8 data pins including a first subset of 4 data pins and a second subset of 4 data pins, the first subset of 4 data pins and the second subset of 4 data pins being operable to be independently addressable; and communicate channel encoding information of the first subset of 4 data pins with the corresponding memory die via an auxiliary pin.

[0145] In some examples, the system is further operable to communicate second channel encoded information of the second subset of four data pins between the host device and the respective memory die via second auxiliary pins.

[0146] In some examples, the system is further operable to communicate second channel encoded information of the first subset of four data pins between the host device and the respective memory die via a second auxiliary pin.

[0147] In some instances, the system may further include a second memory device coupled to the host device and including a second group of memory dies, the system being further operable to: communicate the data between the host device and the corresponding memory dies in the group via the first subset of 4 data pins and communicate second data between the host device and the corresponding second memory die in the second group via a third subset of 4 data pins in a second group of 8 data pins included at the second memory device; and communicate second channel encoding information of the second subset of 4 data pins with the corresponding second memory die via a second auxiliary pin.

[0148] An apparatus is described. The apparatus may include means for communicating first data between a first memory die and a host device via a first set of four data pins and communicating channel encoding information for the first data via first auxiliary pins corresponding to the first set of four data pins, and means for communicating second data between a second memory die and the host device via a second set of four data pins and communicating channel encoding information for the second data via second auxiliary pins corresponding to the second set of four data pins.

[0149] In some instances, communicating the first data may further include means for receiving the first data via the first set of four data pins, the apparatus further including means for decoding the first data based at least in part on the channel coding information of the first data, wherein the channel coding information of the first data includes error detection code (EDC) information of the first data, data encoding information of the first data, or any combination thereof. In some cases, communicating the first data may further include means for receiving the first data via the first set of four data pins, the apparatus further including: means for identifying the first data based at least in part on the channel coding information of the first data, the channel coding information of the first data includes data encoding information of the first data, wherein the first auxiliary pin includes a data encoding pin; and means for transmitting error detection code (EDC) information from the first memory die to the host device via an EDC pin of the first set of four data pins, wherein the EDC information is based at least in part on identifying the first data.

[0150] In some examples, the apparatus may further include: means for determining a first mode of the first set of four data pins based at least in part on one or more access commands, wherein communicating the first data is based at least in part on the first mode; and means for determining a second mode of the second set of four data pins based at least in part on the one or more access commands, wherein communicating the second data is based at least in part on the second mode. In some examples, the first mode and the second mode each include at least one of a transmission mode, a reception mode, or a silent mode.

[0151] Although in some cases aspects of the teachings herein may be illustrated by reference to examples consistent with one or more types of memory devices (e.g., DRAM devices), one of ordinary skill in the art will understand that the teachings herein may be applied to any type of memory device and any electronic system in which data is transferred (e.g., between devices within the system).

[0152] The information and signals described herein may be represented using any of a variety of different processes and technologies. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, one of ordinary skill in the art will understand that a signal may represent a signal bus, where the bus may have various bit widths.

[0153] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication with each other (or in conductive contact with each other or connected to each other or coupled to each other) if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, the conductive path between components that are in electronic communication with each other (or in conductive contact with each other or connected to each other or coupled to each other) may be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include intermediate components (such as switches, transistors, or other components). In some cases, the flow of signals between the connected components may be interrupted at a time, for example, using one or more intermediate components (such as switches or transistors).

[0154] The term "coupled" refers to a state of moving from an open circuit relationship between components (where signals cannot currently pass between components via conductive paths) to a closed circuit relationship between components (where signals can pass between components via conductive paths). When a component (e.g., a controller) couples other components together, the component causes a change that allows signals to flow between other components via conductive paths that previously did not permit signal flow.

[0155] The term "isolation" refers to a relationship between components where a signal cannot currently flow between the components. Components are isolated from one another if an open circuit exists between the components. For example, two components separated by a switch positioned between the components are isolated from one another when a switch is open. When a controller isolates two components, the controller effects a change that prevents a signal from flowing between the components using a conductive path that previously permitted the signal to flow.

[0156] As used herein, the term "electrode" may refer to an electrical conductor, and in some cases, may serve as an electrical contact to a memory cell or other component of a memory array. An electrode may include a trace, wire, conductive line, conductive layer, or the like that provides a conductive path between elements or components of a memory array.

[0157] The devices discussed herein, including memory arrays, may be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping with various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping may be performed by ion implantation during the initial formation or growth of the substrate or by any other doping method.

[0158] The switching components or transistors discussed herein may represent field effect transistors (FETs) and include three-terminal devices including a source, a drain, and a gate. The terminals may be connected to other electronic components by conductive materials such as metals. The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., most carriers are signals), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., most carriers are holes), the FET may be referred to as a p-type FET. The channel may be covered by an insulating gate oxide. Channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "activated". When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned off" or "deactivated".

[0159] The specific embodiments described herein in conjunction with the accompanying drawings describe example configurations and do not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "used as an example, instance, or illustration," rather than "preferred" or "superior to other examples." The detailed description includes specific details for providing an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0160] In the accompanying drawings, similar components or features may have the same reference label. In addition, various components of the same type may be distinguished by the reference label followed by a dash and a second label that distinguishes the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of the second reference label.

[0161] The various illustrative blocks and modules described in conjunction with the present invention may be implemented or performed by a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0162] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on a computer-readable medium as one or more instructions or codes or transmitted through a computer-readable medium as one or more instructions or codes. Other examples and implementations are within the scope of the present invention and the appended claims. For example, due to the nature of software, the functions described herein may be implemented using software, hardware, firmware, hard wiring, or any combination of these executed by a processor. The features of the implementation functions may also be physically located at various locations, including being distributed so that parts of the functions are implemented at different physical locations. Moreover, as used herein (included in the claims), the "or" used in a list of items (e.g., a list of items beginning with a phrase such as "at least one of..." or "one or more of...") indicates an inclusive list, such that (for example) a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Moreover, as used herein, the phrase "based on" should not be interpreted as referring to a set of closed conditions. For example, the exemplary steps described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present invention. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0163] Computer-readable media include both non-transitory computer storage media and communication media, which include any media that facilitates the transfer of computer programs from one place to another.Non-transitory storage media can be any available media that can be accessed by a general or special computer.By example and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage device, magnetic disk storage device or other magnetic storage device or can be used to carry or store the desired program code components in the form of instructions or data structures and can be accessed by a general or special computer or a general or special processor.In addition, any connection is appropriately referred to as computer-readable media.For example, if coaxial cable, optical fiber cable, twisted pair, digital subscriber line (DSL) or wireless technology (such as infrared, radio and microwave) are used to transmit software from a website, server or other remote source, then coaxial cable, optical fiber cable, twisted pair, digital subscriber line (DSL) or wireless technology (such as infrared, radio and microwave) are included in the definition of media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0164] The description herein is provided to enable one skilled in the art to make or use the invention. Various modifications of the invention will be apparent to one skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the invention. Therefore, the invention is not limited to the examples and designs described herein, but should be in the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An electronic memory device comprising: A memory device comprising a set of memory dies, each memory die in the set of memory dies being operable to communicate with a host device via: a set of eight data pins, comprising a first subset of four data pins and a second subset of four data pins, the first subset of four data pins and the second subset of four data pins being operable to be independently addressable; and an auxiliary pin operable to carry channel coded information of the first subset of four data pins, the channel coded information comprising: Error detection code EDC signaling, which indicates tracking information of data transmitted via the first subset of 4 data pins, a retention model, a cyclic redundancy check CRC code or a combination thereof; Data encoded signaling indicating data bus inversion (DBI) information for data transmitted via the first subset of four data pins; or Both the EDC signaling and the data encoding signaling.

2. The electronic memory device of claim 1, wherein the data encoding signaling and the EDC signaling are encoded according to a same encoding scheme.

3. The electronic memory device of claim 1 , further comprising: A second auxiliary pin is operable to carry second channel encoded information of the second subset of four data pins.

4. The electronic memory device of claim 1 , further comprising: A second auxiliary pin is operable to carry second channel encoded information of the first subset of four data pins.

5. The electronic memory device of claim 4, wherein: The auxiliary pin is operable to carry the data encoding signaling of the first subset of four data pins; and The second auxiliary pin is operable to carry the EDC signaling of the first subset of four data pins.

6. The electronic memory device of claim 4, further comprising: A second EDC pin is operable to carry EDC signaling for the second subset of four data pins, wherein the auxiliary pins include the first EDC pin.

7. The electronic memory device of claim 6, further comprising: Second data encoding pins are operable to carry second data encoding signaling of the second subset of four data pins, wherein the second auxiliary pins include the first data encoding pin.

8. The electronic memory device of claim 4, wherein the auxiliary pin and the second auxiliary pin are further operable to carry the channel encoding information and the second channel encoding information of the set of 8 data pins.

9. The electronic memory device of claim 1, wherein the auxiliary pin is further operable to carry second channel encoding information for the set of eight data pins, the second channel encoding information comprising EDC signaling and data encoding signaling for the set of eight data pins.

10. The electronic memory device of claim 1, further comprising: a first transceiver operable to communicate first data via the first subset of four data pins based at least in part on the channel coding information of the first subset of four data pins; and A second transceiver is operable to communicate second data via the second subset of four data pins based at least in part on second channel encoding information of the second subset of four data pins.

11. An electronic memory device comprising: A host device operable to communicate with a set of memory dies, wherein the host device is operable to communicate with respective memory dies of the set of memory dies via: a set of eight data pins, comprising a first subset of four data pins and a second subset of four data pins, the first subset of four data pins and the second subset of four data pins being operable to be independently addressable; and an auxiliary pin operable to carry channel coded information of the first subset of four data pins, the channel coded information comprising: Error detection code EDC signaling, which indicates tracking information of data transmitted via the first subset of 4 data pins, a retention model, a cyclic redundancy check CRC code or a combination thereof; Data encoded signaling indicating data bus inversion (DBI) information for data transmitted via the first subset of four data pins; or Both the EDC signaling and the data encoding signaling.

12. The electronic memory device of claim 11, wherein the channel encoding information of the first subset of four data pins comprises the EDC signaling and the data encoding signaling, the data encoding signaling and the EDC signaling being encoded according to a same encoding scheme.

13. The electronic memory device of claim 11, further comprising: A second auxiliary pin operable to carry second channel coded information of the first subset of four data pins, wherein: The auxiliary pin is operable to carry the data encoding signaling for the first subset of 4 data pins; and The second auxiliary pin is operable to carry the EDC signaling of the first subset of four data pins.

14. A method for multiple memory operations, comprising: First data is transmitted between the first memory die and the host device via a first set of four data pins and channel encoding information of the first data is transmitted via a first auxiliary pin corresponding to the first set of four data pins, wherein the channel encoding information of the first data includes: A first error detection code EDC signaling, which indicates tracking information of the first data, a retention model, a cyclic redundancy check CRC code or a combination thereof; A first data encoding signaling indicating data bus inversion DBI information of the first data; or both the first EDC signaling and the first data encoding signaling; and The second data is transmitted between the second memory die and the host device via a second set of four data pins and channel coding information of the second data is transmitted via a second auxiliary pin corresponding to the second set of four data pins, wherein the channel coding information of the second data includes: A second error detection code EDC signaling, which indicates tracking information of the second data, a retention model, a cyclic redundancy check CRC code or a combination thereof; A second data encoding signaling indicating data bus inversion DBI information of the second data; or Both the second EDC signaling and the second data encoding signaling.

15. The method of claim 14, wherein transmitting the first data comprises: Receiving the first data via the first group of four data pins, the method further comprising: The first data is decoded based at least in part on the channel encoding information of the first data.

16. The method of claim 14, wherein transmitting the first data comprises: Receiving the first data via the first group of four data pins, the method further comprising: identifying the first data based at least in part on the channel coding information of the first data, the channel coding information of the first data comprising data coding information of the first data, wherein the first auxiliary pin comprises a data coding pin; and EDC information is transmitted from the first memory die to the host device via EDC pins of the first set of four data pins, wherein the EDC information is based at least in part on identifying the first data.

17. The method of claim 14, further comprising: determining a first pattern of the first set of four data pins based at least in part on one or more access commands, wherein communicating the first data is based at least in part on the first pattern; and A second pattern of the second set of four data pins is determined based at least in part on the one or more access commands, wherein communicating the second data is based at least in part on the second pattern.

18. The method of claim 17, wherein the first mode and the second mode each comprise at least one of a transmission mode, a reception mode, or a silence mode.

19. A system for memory operation, comprising: a memory device comprising a set of memory dies; and a host device coupled to the memory device, the system being operable to: communicating data between the host device and a corresponding memory die in the set of memory dies via a set of eight data pins, the set of eight data pins comprising a first subset of four data pins and a second subset of four data pins, the first subset of four data pins and the second subset of four data pins being operable to be independently addressable; and Channel coding information of the four data pins of the first subset is transmitted to the corresponding memory die via the auxiliary pin, the channel coding information comprising: Error detection code EDC signaling, which indicates tracking information of data transmitted via the first subset of 4 data pins, a retention model, a cyclic redundancy check CRC code or a combination thereof; Data encoded signaling indicating data bus inversion (DBI) information of data transmitted via the first subset of four data pins; or Both the EDC signaling and the data encoding signaling.

20. The system of claim 19, wherein the system is further operable to: Second channel encoded information of the second subset of four data pins is communicated between the host device and the corresponding memory die via a second auxiliary pin.

21. The system of claim 19, wherein the system is further operable to: Second channel encoded information of the first subset of four data pins is communicated between the host device and the corresponding memory die via a second auxiliary pin.

22. The system of claim 19, further comprising: a second memory device coupled to the host device and comprising a second set of memory dies, the system being further operable to: communicating the data between the host device and the corresponding memory die in the group of memory dies via the first subset of four data pins; communicating second data between the host device and a corresponding second memory die in the second group of memory dies via a third subset of four data pins included in a second group of eight data pins at the second memory device; and The second channel encoding information of the second subset of four data pins is communicated to the corresponding second memory die via the second auxiliary pin.

23. An electronic memory device comprising: Means for communicating first data between a first memory die and a host device via a first set of four data pins and communicating channel-encoded information for the first data via a first auxiliary pin corresponding to the first set of four data pins, wherein the channel-encoded information for the first data comprises: A first error detection code EDC signaling, which indicates tracking information of the first data, a retention model, a cyclic redundancy check CRC code or a combination thereof; A first data encoding signaling indicating data bus inversion DBI information of the first data; or both the first EDC signaling and the first data encoding signaling; and means for communicating second data between a second memory die and the host device via a second set of four data pins and communicating channel coded information for the second data via second auxiliary pins corresponding to the second set of four data pins, wherein the channel coded information for the second data comprises: A second error detection code EDC signaling, which indicates tracking information of the second data, a retention model, a cyclic redundancy check CRC code or a combination thereof; A second data encoding signaling indicating data bus inversion DBI information of the second data; or Both the second EDC signaling and the second data encoding signaling.

24. The electronic memory device of claim 23, wherein the means for transferring the first data comprises: means for receiving the first data via the first set of four data pins, the electronic memory device further comprising: Means for decoding the first data based at least in part on the channel encoding information of the first data.

25. The electronic memory device of claim 23, wherein the means for transferring the first data comprises: means for receiving the first data via the first set of four data pins, the electronic memory device further comprising: means for identifying the first data based at least in part on the channel encoding information of the first data, the channel encoding information of the first data comprising data encoding information of the first data, wherein the first auxiliary pin comprises a data encoding pin; and means for transmitting EDC information from the first memory die to the host device via the EDC pins of the first set of four data pins, wherein the EDC information is based at least in part on identifying the first data.

26. The electronic memory device of claim 23, further comprising: means for determining a first pattern of the first set of four data pins based at least in part on one or more access commands, wherein communicating the first data is based at least in part on the first pattern; and means for determining a second pattern for the second set of four data pins based at least in part on the one or more access commands, wherein communicating the second data is based at least in part on the second pattern.

27. The electronic memory device of claim 26, wherein the first mode and the second mode each comprise at least one of a transmit mode, a receive mode, or a silent mode.

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