Prevent and detect integrated circuit theft and counterfeiting

Abstract

A mechanism for protecting integrated circuit devices is provided that combines a high degree of security with low overhead in both area and cost, thereby making it suitable for smaller, less expensive integrated circuits. A determination is made as to whether a device die is on a wafer or whether the device die is incorporated into a package. Functional logic of the device die may be activated only if the device die is incorporated into a package, and then only if a challenge-response query is satisfied. In some embodiments, a random number generator is used during wafer testing to form a pair of numbers and a die identifier that is unique to each device die. A final test is then performed in which the device die may be activated if the device die is incorporated into a package, and the die identifier-random number pair is authenticated.

Description

Technical Field

[0001] The present disclosure relates generally to preventing and detecting integrated circuit theft and counterfeiting, and more particularly to a challenge-response mechanism that can determine whether an integrated circuit die is in a package and perform certain tasks in response. Background Art

[0002] Counterfeit and stolen integrated circuit dies pose a serious problem for the semiconductor industry. It is estimated that at least one percent of semiconductors sold worldwide are counterfeit units. The sources of these counterfeit units vary and can be difficult to trace. Semiconductor fabs may overproduce wafers; wafers, dies, or packaged integrated circuits may be stolen; or wafers may be cloned. Regardless of the source, these goods may then be sold on the gray market.

[0003] The risks facing the semiconductor industry go beyond the sales value of stolen devices. Generally speaking, and especially for safety- and security-sensitive devices, the poor quality of counterfeit or incompletely tested integrated circuits in products can pose a risk to customers and can damage the reputation of the original semiconductor manufacturer.

[0004] To address these challenges to the industry, there are some methods that make the integrated circuit only work after it is enabled by the programming sequence in the final test step, and then ensure that only genuine integrated circuits can perform such programming. In order to prevent counterfeiters from copying the enable programming sequence, encrypted challenge-response exchanges or IC-specific passwords have been introduced. Encrypted challenge-response exchanges may require significant hardware and protection to prevent side-channel attacks on the encryption system. Therefore, this encrypted challenge-response method is not suitable for smaller, lower-priced integrated circuits. The use of IC-specific passwords may be easily stolen and played back on cloned integrated circuits, and is therefore not necessarily an effective anti-counterfeiting measure.

[0005] Therefore, a security mechanism for preventing or deterring theft and counterfeiting of integrated circuits is desired that avoids the shortcomings and cryptographic risks of current encrypted challenge-response exchanges and that, in any event, renders such theft or counterfeiting detectable where it cannot be prevented. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Embodiments of the present invention may be better understood by referring to the accompanying drawings.

[0007] Figure 1 is a simplified block diagram illustrating a system 100 that provides various stages of device testing and integrated circuit device certification in accordance with an embodiment of the present invention.

[0008] Figure 2is a simplified block diagram illustrating an example of an integrated circuit device 200 having available substrate thickness detection capabilities in accordance with an embodiment of the present invention.

[0009] Figure 3 is a simplified flow chart illustrating a wafer testing flow 300 according to an embodiment of the present invention.

[0010] Figure 4 is a simplified flow chart illustrating an example of post-processing performed on test results database 180 according to an embodiment of the present invention.

[0011] Figure 5 is a simplified flow chart illustrating a device package production final test flow 500 according to an embodiment of the present invention.

[0012] Figure 6 is a simplified flow chart illustrating an authentication process 600 according to an embodiment of the present invention.

[0013] Figure 7 is a simplified block diagram illustrating an example of functional blocks within a device die 700 that may be used in accordance with an embodiment of the present invention.

[0014] Unless otherwise indicated, the same reference numerals are used in different drawings to denote the same items. The drawings are not necessarily drawn to scale. DETAILED DESCRIPTION

[0015] Embodiments of the present invention provide a mechanism for protecting integrated circuit devices, which combines high security and low overhead in both area and cost, making it suitable for smaller, lower-priced integrated circuits. A mechanism is provided to determine whether a device die is still on a wafer or whether the device die is incorporated into a package. The functional logic of the device die can only be activated when the device die is incorporated into a package, and then only when a challenge-response query is satisfied. In some embodiments, a random number generator is used during wafer testing to form a pair of numbers, and a die identifier that is unique to each device die. A database of all valid die identifiers / generated random numbers of device dies that have passed wafer testing can also be provided. A final production test is then performed, in which the device die can be activated if the device die is incorporated into a package, and the die identifier-random number pair is authenticated. This combination of components can ensure significant security and low overhead (e.g., particularly avoiding the overhead of an encryption controller) to prevent counterfeiting, theft, and cloning.

[0016] Protecting integrated circuit device dies from theft, counterfeiting, and other unauthorized use is a significant challenge for the semiconductor industry. This is especially true for smaller, lower-priced integrated circuit devices, for which complex cryptographic authentication methods may result in an undesirable increase in device die size or significantly increase costs.

[0017] For smaller, lower-priced integrated circuit devices, embodiments deter copying or theft by forcing potential counterfeiters to perform some expensive testing and programming phases similar to those used in true production test flows and introducing detection risk for counterfeiters. These additional costs and risks may change the business case for these types of devices for potential counterfeiters, thereby making them unprofitable. For all integrated circuit devices, embodiments may supplement existing cryptographic challenge-response protections by providing additional defenses in the event that cryptographic authentication is compromised (e.g., by reverse engineering, leakage of private keys from a tester, or side-channel attacks).

[0018] The present system solves common counterfeiting scenarios in the industry. In the first scenario, it is assumed that the counterfeiter can steal the wafer test program, the final test program, and the test-related information (such as the die pad coordinates) to make its own test equipment. It is also assumed that the counterfeiter can eavesdrop on the communication between the device tester and the integrated circuit die during one or both of the wafer test and the final product test. However, it is unlikely that the counterfeiter has enough knowledge of the device die that the counterfeiter can change the one-time programmable (OTP) bits on the chip without using the OTP programming path on the chip. In the second scenario, the counterfeiter steals wafers or die that have been tested on the wafer, but those die do not pass the final production test (for example, the operator can report the wafer as damaged and steal the wafer; the operator can steal the device die marked as scrapped instead of the scrapped device die).

[0019] Integrated circuit device dies are tested at certain stages of the production process to determine whether the device operates within the expected specifications. Some initial testing occurs while the integrated circuit device dies are still on the wafer on which the device dies are manufactured. Subsequent testing may occur after the device dies have been removed from the wafer or singulated and integrated into a device package.

[0020] Figure 1 is a simplified block diagram illustrating a system 100 that provides various stages of device testing and integrated circuit device certification in accordance with an embodiment of the present invention. Figure 1 Three major stages of testing integrated circuit devices are shown: wafer test 110 , production test 120 , and certification test 130 .

[0021] During the wafer test phase 110, the wafer tester 112 receives the integrated circuit wafer 114. The wafer 114 may include a substrate, such as silicon, gallium arsenide, gallium nitride, silicon carbide, etc., on which microfabrication processes such as doping, ion implantation, etching, and thin film deposition are performed to form hundreds or thousands of integrated circuit devices. The wafer tester 112 is an automated test equipment for optically and functionally inspecting and testing integrated circuits. Functional defects of each individual integrated circuit on the wafer 114 are tested by applying special electronic test patterns to the integrated circuits via one or more probe contacts on the integrated circuits. The wafer tester 112 can store information about these test results for each of the dies. Device dies that fail the test are marked as discarded after singulation.

[0022] During production testing 120, production tester 112 receives production device package 124. As with wafer testing, various tests can be performed at this stage to ensure the functionality of the entire package incorporating the previously tested integrated circuit die. These tests can help ensure that the connections between the integrated circuit device die and other components of the package are properly completed and that all components work together as expected. Testing can include high stress testing, burn-in testing, electrical characteristics testing at operating temperature, and performance testing at higher temperatures. Packaged devices that do not pass these tests are marked as discarded after testing. Packaged devices that pass these tests can then be ready for shipment to customers.

[0023] Figure 1 Also presented is authentication testing 130. As will be discussed in greater detail below, authentication testing may be performed by law enforcement, customs, customers, etc. to determine whether an integrated circuit device die or a package incorporating an integrated circuit device die is a genuine and authorized device.

[0024] Different operations are performed during wafer test and production test. In addition, embodiments of the present invention perform different safety-level tasks at each of these test stages. In order to control the execution of these safety-level tasks, it is important to know whether the integrated circuit device die is on the wafer or incorporated into the package. Embodiments utilize a mechanism to determine the thickness of the integrated circuit device die and use that information to determine whether the device die is on the wafer (e.g., the device die is thicker) or incorporated into the package (e.g., the device die has been subjected to wafer back grinding, thereby making the die thinner).

[0025] Figure 22 is a simplified block diagram illustrating an example of an integrated circuit device 200 having available substrate thickness detection capabilities according to an embodiment of the present invention. The illustrated mechanism is provided by way of example. Embodiments of the present invention are not limited to any particular mechanism for determining the thickness of a semiconductor device die. The integrated circuit device 200 includes a semiconductor substrate 202 and an integrated circuit 204, a charge emitter 206, and a charge sensor 208. Although the illustrated integrated circuit device is illustrated as having certain components and described as having certain functionality, other embodiments of the integrated circuit device may include fewer or more components to implement the same, fewer, or more functionality.

[0026] The integrated circuit 204, the charge emitter 206 and the charge sensor 208 of the integrated circuit device 200 are embedded in the semiconductor substrate 202. The integrated circuit 204 performs the specified function of the integrated circuit device 200. The charge emitter 206 is configured to generate charge in the semiconductor substrate. The charge emitter can be a diode, a bipolar transistor or other suitable charge emitting device. In some embodiments, the charge emitter 206 is configured to emit charge into the semiconductor substrate. In some embodiments, the charge emitter is configured to generate light radiated into the semiconductor substrate, which causes the charge to be generated in the semiconductor substrate. The charge sensor 208 is used to collect or capture at least a portion of the charge or charge carriers injected into the semiconductor substrate by the charge emitter 206. The charge sensor 208 is configured to generate a response signal in response to the charge generated in the semiconductor substrate. The charge sensor 208 can be a diode, a bipolar transistor or other suitable charge receiving device.

[0027] The integrated circuit 204, the charge emitter 206, and the charge sensor 208 may be embedded in the semiconductor substrate 202 during the manufacturing process. Because the charge emitter and the charge sensor are embedded in the semiconductor substrate, the charge generated by the charge emitter travels through the semiconductor substrate before reaching the charge sensor. The magnitude of the charge reaching the charge sensor and therefore the magnitude of the response signal generated by the charge sensor depends on the thickness of the semiconductor substrate. For example, a portion of the charge generated by the charge emitter is typically collected by the charge sensor. The magnitude of the generated charge collected by the charge sensor depends on the geometric aspects of the integrated circuit device, including the distance between the charge emitter and the charge sensor, the thickness of the semiconductor substrate, and the size of the charge collector. Therefore, the magnitude of the charge collected by the charge sensor can be used as an indicator of the substrate thickness or substrate thickness variation. Using this substrate thickness determination mechanism, it can be determined whether the device die is on the wafer or in the package (i.e., due to the back grinding operation that occurs during and after wafer singulation, the device die thickness in the package will typically be less than the device die thickness on the wafer). More information on the above-described mechanism for determining substrate thickness can be found, for example, in U.S. Patent No. 10,250,258, "Device and Method for Detecting Semiconductor Substrate Thickness."

[0028] Figure 3 is a simplified flow chart showing a wafer test process 300 according to an embodiment of the present invention. The wafer test process 300 incorporates functions that occur in a wafer tester (e.g., wafer tester 112) and a device die on a wafer. As shown, the wafer tester performs various production wafer tests (305). The wafer tester performs these tests to ensure that the functionality of the device die is within specifications. If not all tests pass the specifications (310), the die is marked as bad (315) and testing continues to the next die. If all tests pass (310), the wafer tester can trigger the device die to continue safety operations (320).

[0029] Upon receiving a trigger from the wafer tester, the device die determines whether the die is on the wafer (325). Figure 2 As discussed, in one embodiment, the thickness of the device die is determined and indicates whether the device die is on the wafer. If the device die is not on the wafer, the security operation is aborted (330). By aborting the security operation, this prevents a potential counterfeiter from accessing or programming the security bits of the device die.

[0030] If the device die is on the wafer (325), the device die can generate true random numbers (335) that will be associated with security operations. A hardware random number generator can be incorporated into the integrated circuit device die to generate random numbers from unpredictable low-level random noise signals such as thermal noise, photoelectric effects, beam splitters, and other quantum phenomena. Once the random numbers have been generated, the device die can write the random numbers to a one-time programmable (OTP) memory (340) on the device die. Additionally, the device die can then transmit the random numbers to a wafer tester (345).

[0031] The wafer tester may additionally associate a unique die identifier with the integrated circuit device die (350). The wafer tester may then store the received random number associated with the die identifier (355) and then transmit the die identifier to the integrated circuit device die (360). The integrated circuit device die then writes the die identifier to the OTP memory (365).

[0032] Back to Figure 1 , the wafer tester 112 can be coupled to the data server 150 via the network 140. The network 140 can be a local area network or a wide area network within which secure communications can be provided between the wafer tester 112 and the data server 150. The data server 150 is coupled to a memory 160, which can store, among other things, an authorization database 170 and a test result database 180. The authorization database 170 provides entries including device die identifiers along with associated random numbers provided by the integrated circuit device die. The test result database 180 can include various information related to the tests performed by the wafer tester 112 on the integrated circuit device die on the wafer 114. The data server 150 can also be communicatively coupled to the production tester 122 and the certification tester 132 via the network 140. This enables the production tester and the certification tester to access the certification database 170 for additional operations.

[0033] Figure 4is a simplified flow chart illustrating an example of post-processing performed on the test results database 180 according to an embodiment of the present invention. An analysis is performed on the test results database (410) to determine whether there are any integrated circuit device dies that may have certain parameters associated with integrated circuit device dies that are indicative of potential faulty devices. For example, post-processing can be applied to screen out so-called good dies in a bad neighborhood, where an individual die passes all tests but is surrounded by several defective device dies and is therefore suspected of having a higher potential defect rate associated with a higher failure rate in the field. Such device dies should be discarded and information related to those device dies in the authentication database should be deleted, thereby preventing someone from taking the discarded device dies and passing them off as good dies (e.g., counterfeiting).

[0034] If the test results indicate that the device die is an outlier (420), the entry for the die is removed from the authorized database (440). If the device die is not an outlier (420), the next die is selected and the test results are analyzed (430).

[0035] Figure 5 is a simplified flow chart illustrating a device package production final test flow 500 according to an embodiment of the present invention. The production test flow 500 incorporates functionality present in a production tester (e.g., production tester 122) and in a device die incorporated into a production device package 124. The production tester performs various final tests on the device package to ensure that the packaged device performs within specifications (505). If all tests fail within specifications (510), the package is marked as bad (515) and testing continues to the next package. If all tests pass (510), the production tester can trigger the device die within the package to continue safety-related operations (520).

[0036] Upon receiving a trigger from the production tester, the device die determines whether the die is incorporated into the package (525). Figure 2 As discussed, in one embodiment, the thickness of the device die is determined and indicates whether the device die is incorporated into the package (e.g., less than the expected thickness of the device die on the wafer). If the device die is not incorporated into the package, the security operation is aborted (530). By aborting, the security operation prevents a potential counterfeiter from accessing or programming the security bits of the device die within the package.

[0037] If the device die is tested to be incorporated within the package (525), the device die may transmit a die identifier to the production tester (535). The die identifier is a value previously received and stored in the OTP memory of the device die during wafer testing and uniquely identifies the device die.

[0038] Upon receiving the die identifier, the production tester may retrieve a random number associated with the die identifier from the authentication database (540). Figure 1 As shown, the authentication database 170 can be served by the data server 150 and can be accessed by the production tester via the network 140. Alternatively, the production tester 122 can store an image of the authentication database locally. Once the random number associated with the die identifier is retrieved, the random number can be transmitted from the production tester to the device die (545).

[0039] Upon receiving the random number from the production tester, the device die may compare the random number received from the tester with the random number stored in the OTP memory of the device die (550). If the random number received from the tester matches the random number stored in the OTP memory, an activation bit may be set within the OTP memory of the device die (560). At this point, production functionality of the device die is verified by, for example, setting a functional enable bit. If the comparison of the random numbers produces a mismatch (550), security operations will be aborted to prevent the device die from being authorized for production functionality.

[0040] As discussed above, the security effectiveness of using embodiments of the present invention assumes that a potential counterfeiter cannot directly program the OTP memory bits within the integrated circuit device die. Therefore, in order to set the function enable bit, the counterfeiter will have to perform all wafer test and final test operations, because retrieving the random number generated by the device die is only possible during wafer test, and programming the function enable bit is only possible during final test. During each of those stages, the integrated circuit device die self-detects whether it is on the wafer or in the package. This is particularly effective in the case of wafer overproduction, wafer theft, and wafer cloning, where embodiments of the present invention can help detect and hinder device counterfeiting.

[0041] For purposes of this invention, "hindered" means that a counterfeiter will need to invest significant cost and effort in wafer testing and final testing, including programming sequences along with the hardware (e.g., testers) required for such testing. This is in stark contrast to the low-cost, low-effort mode of operation that counterfeiters prefer (e.g., assembling dies without wafer testing, and performing simple application testing using an application board with test sockets).

[0042] For purposes of this invention, "testing" means the process of determining whether an integrated circuit device die is authentic. For example, a test operation may be performed if a government customs agency notices a suspicious device, or if a customer (e.g., an original equipment manufacturer [OEM]) orders an integrated circuit device die from a supplier and wants to know whether the supplier obtained the device from the original semiconductor manufacturer. The integrated circuit device die or the package incorporating the device die may be analyzed using a verification tester, which is similar to the final test and programming procedures, but the difference is that the authentication bit is transmitted to the tester.

[0043] Figure 6 6 is a simplified flow chart illustrating a certification flow 600 according to an embodiment of the present invention. The certification flow 600 incorporates functionality present in a certification tester (eg, certification tester 132) and a device die incorporated in a device package (eg, 134).

[0044] The device die transmits the stored die identifier to the certification tester (605). This transmission may occur in response to a query of the die identifier by the certification tester. The die identifier is a unique number associated with the device die previously stored in the OTP memory of the device die during wafer testing.

[0045] Upon receiving the die identifier from the integrated circuit device die, the certification tester determines whether the die identifier is stored in the certification database (610). As discussed above with respect to production testing, the certification tester 132 may access the certification database 170 by communicating with the data server 150 via the network 140. Alternatively, the certification tester may store a local copy of the certification database. If the die identifier is not reflected in the certification database, it is determined that the device die is not true (615). If the die identifier is stored in the database (610), the certification tester may retrieve a random number associated with the die identifier from the certification database (620). The random number may then be transmitted to the device die (625).

[0046] Upon receiving the random number from the authentication tester, the device die may compare the tester random number with the random number stored in the device die OTP memory (630). If there is a mismatch, authentication fails and is aborted (635). If there is a match, an authentication confirmation may be transmitted by the device die to the authentication tester (640). Such an authentication confirmation may be a message that provides one or more bits of information desired by the application. Upon receiving the authentication confirmation, the authentication tester may display the authentication confirmation message or information related to the authentication confirmation message (645).

[0047] Figure 7is a simplified block diagram illustrating an example of functional blocks within a device die 700 that can be used according to an embodiment of the present invention. The integrated circuit device die 700 includes one or more test access port (TAP) controllers 710 through which a tester or other component can communicate with the circuit system within the device die. For some testing purposes, the TAP 710 may include debug and JTAG type communication pads. The TAP 710 is communicatively coupled to the control logic 720, which can manage the security operations discussed herein. The wafer / package detection circuit 730 is coupled to the control logic 720 and is configured to perform operations associated with determining whether the integrated circuit device die is on a wafer or incorporated into a package. In some embodiments, the wafer / package detection circuit 730 may be incorporated into the above-described Figure 2 The circuitry and functionality of the device die thickness sensor are discussed.

[0048] The integrated circuit device die 700 further includes a random number generator 740 configured to generate true random numbers to implement embodiments of the present invention. The random number generator 740 can store the random numbers in a random number register 752 of a one-time programmable (OTP) memory 750. The OTP 750 can include additional registers, such as a device die identifier register 754, which is configured to store a unique device die identifier supplied by a wafer tester. In addition, the OTP memory 750 can store a function enable bit 756, which can allow the function logic 770 of the device die 700 to function during normal operation.

[0049] The circuit device die 700 may also include a random number comparator 760 configured to perform a comparison between a random number supplied by a tester (e.g., the production tester 122 or the certification tester 132) and a value stored in the random number register 752. As discussed above, the result of such a comparison may be provided to the control logic 724 for security decision purposes.

[0050] It should now be appreciated that a method for authenticating an integrated circuit (IC) device die has been provided. The method includes a wafer test phase and a package test phase. The wafer test phase includes: determining by the integrated circuit device die whether the IC device die is on a wafer; if the IC device die is on the wafer, storing identification information on the IC device die, wherein the identification information uniquely identifies the IC device die; and if the IC device die is not on the wafer, aborting the wafer test phase. The package test phase includes: determining by the IC device die whether the IC device die is incorporated into a package; if the IC device die is incorporated into the package, determining whether the information stored on the IC device die corresponds to a genuine device; and if the IC device die is not incorporated into the package, aborting the package test phase.

[0051] In one aspect of the above-described embodiment, the determining during the packaging test phase whether the information stored on the IC device die corresponds to a genuine device further includes: comparing a first value stored on the IC device die with an authentication value provided by a first external node, wherein the information stored on the IC device die includes the first value; and if the comparison produces a match, setting a function enable bit. In another aspect, the information stored on the IC device die includes the identification information stored during the wafer test phase, and the first value includes a random number generated during the wafer test phase. In another additional aspect, the packaging test phase further includes: transmitting a second value to the first external node, wherein the information stored on the IC device die further includes the second value; and in response to the transmitting of the second value, receiving the authentication value from the external node. In still another aspect, the second value includes a die identifier value provided to the IC device die during the wafer test phase.

[0052] In another aspect of the above embodiment, the first external node is a package tester. In yet another aspect of the above embodiment, setting the function enable bit configures the IC device die to perform a functional operation.

[0053] In another aspect of the above embodiment, the wafer testing phase further includes generating a random number on the IC device die, wherein the identification information includes the random number. In another aspect, the method further includes: transmitting the random number to a second external node by the IC device die; and receiving a unique die identifier from the second external node by the IC device die in response to transmitting the random number, wherein the identification information further includes the unique die identifier. In still another aspect, the second external node includes a wafer tester.

[0054] In another aspect of the above embodiment, determining whether the IC device die is on a wafer and determining whether the IC device die is incorporated into a package includes determining a thickness of a semiconductor substrate included in the IC device die. In a further aspect, determining the thickness of the semiconductor substrate includes: generating a charge in the semiconductor substrate using a charge emitter embedded in the semiconductor substrate; and generating a response signal using a charge sensor embedded in the semiconductor substrate in response to the charge generated in the semiconductor substrate, wherein the magnitude of the response signal depends on the thickness of the semiconductor substrate.

[0055] Another embodiment of the present invention provides a system for authenticating an integrated circuit (IC) device die. The system includes a wafer tester and a package tester. The wafer tester is configured to: receive a semiconductor wafer including the IC device die; perform production wafer testing on the IC device die; trigger the IC device die to perform an on-wafer authentication phase in which all production wafer tests pass; receive a first value from the IC device die; associate a die identifier with the IC device die; store a die identification pair including the die identifier and the first value; and transmit the die identifier to the IC device die. The on-wafer authentication phase includes the IC device die determining whether the IC device die is on a wafer. The package tester is configured to: receive a packaged device including the IC device die; perform final tests on the packaged device; if all final tests pass, trigger the IC device die to perform an in-package authentication phase; receive a second value from the IC device die; determine whether the second value matches the die identifier; and if the second value matches the die identifier, transmit a third value associated with the die identifier to the IC device die. The in-package authentication phase includes the IC device die determining whether the IC device die is in a package. If the third value matches the first value, the device die authenticates the functionality.

[0056] In one aspect of the above embodiment, the system further includes a data server coupled to the wafer tester and the production tester via a network. The data server is configured to store a certification database including the die identification pair. In another aspect, the system further includes a certification tester coupled to the data server and configured to: receive the die identifier from the IC device die; compare the die identifier with an entry in the certification database; provide the IC device die with an associated value from the die identification pair including a match with the die identifier; and receive a certification confirmation from the IC device die.

[0057] Another embodiment of the present invention provides an integrated circuit device die, comprising: a communication interface, which is configured to transmit and receive signals from a node outside the IC device die; a wafer / package detection circuit, which is configured to determine whether the integrated circuit device die is on a wafer or incorporated in a package in response to a signal from the node outside the IC device die; a random number generator logic, which is coupled to the wafer / package detection circuit and is configured to generate a true random number in response to the wafer / package detection circuit determining that the IC device die is on a wafer; and a one-time programmable memory (OTP), which is coupled to the random number generator and is configured to store the true random number and a unique die identifier received from a node outside the IC device die.

[0058] In another aspect of the above embodiment, the IC device die further includes: comparator logic, the comparator logic is coupled to the OTP memory and the communication interface; and control logic, the control logic is configured to set a function enable bit in the OTP memory. The comparator logic is configured to compare the true random number with the value received from the node outside the IC device die. The function enable bit enables the function logic on the IC device die to operate in the device package. In another aspect of the above embodiment, the wafer / package detection circuit determines whether the IC device die is on a wafer or incorporated in a package by being configured to measure the thickness of the semiconductor substrate of the IC device die. In still another aspect, the wafer / package detection circuit includes: a charge emitter, the charge emitter is embedded in the semiconductor substrate of the IC device die and is configured to generate a charge in the semiconductor substrate; and a charge sensor, the charge sensor is embedded in the semiconductor substrate and is configured to generate a response signal in response to the charge generated in the semiconductor substrate, wherein the amplitude of the response signal corresponds to the thickness of the semiconductor substrate. In still further aspects of the above embodiments, the charge emitter is configured to generate light that radiates into the semiconductor substrate.

[0059] Because the apparatus implementing the present invention is largely composed of electronic components and circuits known to those skilled in the art, as described above, the circuit details will not be explained more than is deemed necessary in order to facilitate understanding and appreciation of the basic concepts of the present invention and to avoid obscuring or diverting attention away from the teachings of the present invention.

[0060] As used herein, the term "program" is defined as a sequence of instructions designed for execution on a computer system. A program or computer program may include subroutines, functions, procedures, object methods, object implementations, executable applications, applets, servlets, source code, object code, shared libraries / dynamically loaded libraries, and / or other sequences of instructions designed for execution on a computer system.

[0061] Some of the above embodiments (if applicable) can be implemented using a variety of different information processing systems. For example, although Figure 1 The present invention and the discussion thereof describe an exemplary information processing architecture, but this exemplary architecture is presented merely to provide a useful reference when discussing various aspects of the present invention. Of course, the description of the architecture has been simplified for the purposes of discussion, and the architecture is only one of many different types of suitable architectures that may be used in accordance with the present invention. Those skilled in the art will recognize that the boundaries between logic blocks are merely illustrative, and alternative embodiments may merge logic blocks or circuit elements or add alternative decompositions of functionality to individual logic blocks or circuit elements.

[0062] Therefore, it should be understood that the architectures depicted herein are merely exemplary, and that many other architectures that achieve the same functionality may in fact be implemented. In an abstract but still clear sense, any arrangement of components for achieving the same functionality is effectively "associated" so that the desired functionality is achieved. Therefore, any two components combined herein to achieve a particular functionality may be considered to be "associated" with each other so that the desired functionality is achieved, regardless of the architecture or intermediate components. Likewise, any two components so associated may also be considered to be "operably connected" or "operably coupled" to each other to achieve the desired functionality.

[0063] In addition, those skilled in the art will recognize that the boundaries between the functions of the operations described above are merely illustrative. The functions of multiple operations can be combined into a single operation, and / or the functions of a single operation can be distributed in other operations. In addition, alternative embodiments can include multiple instances of specific operations, and the order of operations can be changed in various other embodiments.

[0064] All or some of the software described herein may be received elements of system 100, for example, from local computer-readable media or other media on other computer systems (e.g., memory 160). Such computer-readable media may be permanently, removably, or remotely coupled to the information processing system. Computer-readable media may include, for example and without limitation, any number of the following media: magnetic storage media, including magnetic disk and tape storage media; optical storage media, such as optical disk media (e.g., CD-ROM, CD-R, etc.) and digital video disk storage media; non-volatile memory storage media, including semiconductor-based memory cells, such as FLASH memory, EEPROM, EPROM, ROM; ferromagnetic digital memory; MRAM; volatile storage media, including registers, buffers or caches, main memory, RAM, etc.; and data transmission media, including computer networks, point-to-point telecommunications equipment, and carrier transmission media, to name a few.

[0065] In one embodiment, system 100 can be incorporated into a computer system, such as a personal computer system. Other embodiments may include different types of computer systems or processors. A computer system is an information processing system that can be designed to provide independent computing capabilities to one or more users. A computer system can exist in many forms, including but not limited to mainframe computers, minicomputers, servers, workstations, personal computers, notebook computers, personal digital assistants, electronic games, automobiles and other embedded systems, cellular phones and various other wireless devices. A typical computer system includes at least one processing unit, an associated memory and a plurality of input / output (I / O) devices.

[0066] A computer system processes information according to a program and generates the resulting output information through an I / O device. A program is a list of instructions, such as a specific application and / or an operating system. Computer programs are typically stored internally on a computer-readable storage medium, or transmitted to a computer system via a computer-readable transmission medium. A computer process typically includes executing (running) a program or a portion of a program, current program values ​​and state information, and resources used by the operating system to manage process execution. A parent process can generate other child processes to help perform the overall functions of the parent process. Because a parent process specifically generates child processes to perform a portion of the overall functions of the parent process, the functions performed by child processes (and grandchild processes, etc.) can sometimes be described as being performed by the parent process.

[0067] Although the present invention is described herein with reference to specific embodiments, various modifications and changes may be made without departing from the scope of the present invention as set forth in the following claims. Therefore, the present specification and drawings should be regarded as illustrative rather than restrictive, and all such modifications are intended to be included within the scope of the present invention. Any benefits, advantages, or solutions described herein with respect to specific embodiments are not intended to be construed as key, required, or essential features or elements of any or all claims.

[0068] In addition, as used herein, the terms "a or an" are defined as one or more than one. Moreover, the use of introductory phrases such as "at least one" and "one or more" in a claim should not be interpreted as implying that another claim element introduced by the indefinite article "a or an" will limit any particular claim containing such introduced claim element to an invention containing only one such element, even when the same claim includes the introductory phrases "one or more" or "at least one" and an indefinite article such as "a or an". The same is true for the use of definite articles.

[0069] Unless stated otherwise, terms such as "first" and "second," etc., are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate a temporal or other prioritization of such elements.

Claims

1. A method for authenticating an integrated circuit device die, characterized in that: The method comprises: Wafer testing stage, the wafer testing stage includes: determining, from the integrated circuit (IC) device die, whether the IC device die is on a wafer; If the IC device die is on the wafer, storing identification information on the IC device die, wherein the identification information uniquely identifies the IC device die; and If the IC device die is not on the wafer, aborting the wafer testing phase; and The packaging and testing phase includes: determining, from the IC device die, whether the IC device die is incorporated in a package; If the IC device die is incorporated in a package, determining whether the information stored on the IC device die corresponds to an authentic device; and If the IC device die is not incorporated in a package, the package testing phase is aborted.

2. The method according to claim 1, characterized in that Determining during the package testing phase whether the information stored on the IC device die corresponds to an authentic device further comprises: comparing a first value stored on the IC device die to an authentication value provided by a first external node, wherein the information stored on the IC device die includes the first value; and If the comparison results in a match, the function enable bit is set.

3. The method according to claim 1, characterized in that The determining whether the IC device die is on a wafer and the determining whether the IC device die is incorporated in a package comprises: A thickness of a semiconductor substrate included in a die of the IC device is determined.

4. The method according to claim 3, characterized in that Determining the thickness of the semiconductor substrate includes: generating charge in the semiconductor substrate using a charge emitter embedded in the semiconductor substrate; and In response to the charges generated in the semiconductor substrate, a response signal is generated using a charge sensor embedded in the semiconductor substrate, wherein the magnitude of the response signal depends on the thickness of the semiconductor substrate.

5. A system for authenticating an integrated circuit device die, characterized in that: The system comprises: A wafer tester, the wafer tester being configured to: receiving a semiconductor wafer including the integrated circuit (IC) device die; performing production wafer testing on the IC device dies; If all production wafer tests pass, triggering the IC device die to perform an on-wafer certification phase, wherein the on-wafer certification phase includes the IC device die determining whether the IC device die is on wafer; receiving a first value from the IC device die; associating a die identifier with the IC device die; storing a die identification pair comprising the die identifier and the first value; and transmitting the die identifier to the IC device die; and A package tester, the package tester being configured to: receiving a packaged device including a die of the IC device; performing a final test on the packaged device; If all final tests pass, triggering the IC device die to perform an in-package authentication phase, wherein the in-package authentication phase includes the IC device die determining whether the IC device die is in a package; receiving a second value from the IC device die; determining whether the second value matches the die identifier; and If the second value matches the die identifier, a third value associated with the die identifier is transmitted to the IC device die, wherein the device die authenticates functionality if the third value matches the first value.

6. The system according to claim 5, characterized in that Also includes: A data server is coupled to the wafer tester and the production tester through a network, wherein the data server is configured to store a certification database including the die identification pairs.

7. The system according to claim 6, characterized in that Also includes: a certification tester coupled to the data server and configured to: receiving the die identifier from the IC device die; comparing the die identifier to an entry in the authentication database; providing to the IC device die an association value from the die identification pair including a match with the die identifier; and An authentication confirmation is received from the IC device die.

8. An integrated circuit device die, characterized in that: include: a communication interface configured to transmit and receive signals from a node external to the IC device die; wafer / package detection circuitry configured to determine whether the integrated circuit (IC) device die is on a wafer or incorporated in a package in response to a signal from the node external to the IC device die; a random number generator logic coupled to the wafer / package detection circuit and configured to generate a true random number in response to the wafer / package detection circuit determining that the IC device die is on a wafer; as well as a one-time programmable (OTP) memory coupled to the random number generator and configured to store the true random number and to store a unique die identifier associated with the IC device die received from a node external to the IC device die in response to the wafer / package detection circuitry determining that the IC device die is on a wafer; comparator logic coupled to the OTP memory and the communication interface and configured to compare the true random number with a value received from the node external to the IC device die; as well as Control logic configured to set a function enable bit in the OTP memory, wherein the function enable bit enables function logic on the IC device die to operate in a device package.

9. The IC device die according to claim 8, characterized in that: The wafer / package detection circuit comprises: a charge emitter embedded in a semiconductor substrate of the IC device die and configured to generate charge in the semiconductor substrate; and A charge sensor is embedded in the semiconductor substrate and is configured to generate a response signal in response to the charges generated in the semiconductor substrate, wherein a magnitude of the response signal corresponds to a thickness of the semiconductor substrate.

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