Vision-based assistance system and method

Abstract

The present disclosure relates to vision-based assistance systems and methods. Embodiments of vision-based assistance systems and methods are disclosed in which adaptive sub-tiles are applied to captured images for distortion correction. The captured image is processed to generate a corrected tile, and depending on the pixel density of an area of ​​the captured image, a selected number of sub-tiles are used to generate each of the corrected tiles. The corrected sub-tiles are combined to form a corrected tile, and the corrected tiles are combined to form a corrected image. The corrected image can be used to output a control signal so as to issue an action to a user of the system (e.g., a driver of a vehicle). For one embodiment, the corrected tiles are generated one at a time, and corrected sub-tiles for each corrected tile are also generated one at a time based on individual source data blocks determined by a predetermined sub-tile configuration. Efficient memory usage and data transfer are thereby provided.

Description

Technical Field

[0001] The technical field relates to systems for image correction and vision-based assistance. Background Art

[0002] Many vision-based systems require distortion correction for captured images. For example, many vehicles today have computer vision systems that operate as advanced driver assistance systems (ADAS). In such computer vision applications, geometric distortion correction is an important processing step if accurate object recognition is to be achieved for vision-based assistance. This distortion correction process involves mapping the pixels of the captured image from one projection to another, and is typically implemented using a dedicated hardware processor within a system-on-chip (SoC) integrated circuit. One approach to this remapping is to divide the distorted image into a series of tiles. For example, the image can be divided into 64×64 pixel tiles, but other tile sizes can also be used. The hardware processor reads the captured image data into local memory one tile at a time and performs remapping to remove or correct the geometric distortion. Correction for each tile typically involves remapping each pixel within the tile to a pixel of the corrected tile of the corrected image, and interpolating surrounding pixels as needed.

[0003] Compared to previous full-image distortion processing, this tile-based approach to generating corrected images reduces the bandwidth required to read from the source frame memory that stores the captured full image. However, the local processor memory required to store and process image tiles increases with the resolution and field of view (FOV) of the camera used to capture the image. This is because a larger camera FOV results in higher distortion in the captured image. Therefore, as the resolution and FOV in vision-based assistance systems increase, the silicon area required for integrated circuits used to process the image and correct distortion also increases significantly. Summary of the Invention

[0004] According to one aspect of the present invention, there is provided a system comprising:

[0005] camera;

[0006] a correction system coupled to receive image data representing the captured image from the camera and to correct distortion within the image data, the correction system comprising:

[0007] a memory coupled to store the image data;

[0008] a processor coupled to process the image data to correct distortion and output a corrected tile having a number of sub-tiles selected from a set of numbers based on pixel densities associated with different regions of the captured image; and

[0009] a memory coupled to store a corrected image based on the corrected tiles; and

[0010] A vision processor is coupled to receive the corrected image from the processor and cause one or more actions to be issued to a user of the system.

[0011] According to one or more embodiments of the present invention, the set number of sub-blocks includes one sub-block, four sub-blocks, sixteen sub-blocks, and sixty-four sub-blocks.

[0012] According to one or more embodiments of the present invention, at least one of the corrected tiles is generated using a plurality of different sub-tile sizes.

[0013] According to one or more embodiments of the present invention, different numbers of sub-image blocks are selected for generating the corrected image block.

[0014] According to one or more embodiments of the present invention, a central area of ​​the captured image has a higher pixel density than an edge area of ​​the captured image, and a larger number of sub-tiles are used for at least one corrected tile associated with the central area compared to another corrected tile associated with the edge area.

[0015] According to one or more embodiments of the invention, sub-tiles of each of the corrected tiles are generated by the processor one at a time, and wherein the sub-tiles are combined to form the corrected tile.

[0016] According to one or more embodiments of the invention, the sub-tile used by the processor depends on a predetermined sub-tile configuration stored within the system.

[0017] According to a second aspect of the present invention, there is provided a circuit for correcting distortion, comprising:

[0018] a memory coupled to store image data representing the captured image;

[0019] a processor coupled to process the image data to correct distortion and output a corrected tile having a number of sub-tiles selected from a set of numbers based on pixel densities associated with different regions of the captured image; and

[0020] A memory is coupled to store a corrected image based on the corrected sub-tiles.

[0021] According to one or more embodiments of the present invention, at least one of the corrected tiles is generated using a plurality of different sub-tile sizes.

[0022] According to one or more embodiments of the present invention, different numbers of sub-image blocks are selected for generating the corrected image block.

[0023] According to one or more embodiments of the present invention, a central area of ​​the captured image has a higher pixel density than an edge area of ​​the captured image, and a larger number of sub-tiles are used for at least one corrected tile associated with the central area compared to another corrected tile associated with the edge area.

[0024] According to one or more embodiments of the invention, sub-tiles of each of the corrected tiles are generated by the processor one at a time, and wherein the sub-tiles are combined to form the corrected tile.

[0025] According to one or more embodiments of the present invention, source data blocks from the image data associated with the sub-tile are stored in a source block memory for the processor, the source block memory having a fixed size.

[0026] According to one or more embodiments of the invention, the sub-tile used by the processor depends on a predetermined sub-tile configuration.

[0027] According to a third aspect of the present invention, there is provided a method for correcting image distortion, comprising:

[0028] storing image data from a camera in a memory, the image data representing the captured image;

[0029] generating a corrected tile using a number of sub-tiles selected from a set of numbers based on pixel densities associated with different regions of the captured image;

[0030] processing the image data to correct distortion and generate a corrected tile having a number of sub-tiles selected from a set of numbers based on pixel densities associated with different regions of the captured image; and

[0031] The corrected tiles are combined to output a corrected image.

[0032] According to one or more embodiments of the present invention, the method further includes causing one or more actions to be issued to a user based on the corrected image.

[0033] According to one or more embodiments of the invention, the processing includes generating the corrected tiles one at a time.

[0034] According to one or more embodiments of the present invention, the method further includes processing sub-blocks of each corrected block one at a time to generate corrected sub-blocks, and combining the corrected sub-blocks to generate the corrected block.

[0035] According to one or more embodiments of the present invention, a central area of ​​the captured image has a higher pixel density than an edge area of ​​the captured image, and a larger number of sub-tiles are used for at least one corrected tile associated with the central area compared to another corrected tile associated with the edge area.

[0036] According to one or more embodiments of the present invention, the method further includes accessing a predetermined sub-tile configuration to determine a plurality of sub-tiles used to generate each corrected tile. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] It should be noted that the drawings depict only example embodiments and are therefore not to be considered limiting of the scope of the invention. Elements shown in the figures are for simplicity and clarity and have not necessarily been drawn to scale.

[0038] Figure 1 is a block diagram of an example embodiment of a vehicle including a system for performing tile-based distortion correction using a selected number of sub-tiles within a captured image.

[0039] Figure 2 is a diagram of an example embodiment for processing a captured image using a selected number of sub-tiles based on pixel density within the captured image.

[0040] Figure 3 is a diagram of an example embodiment of selecting a selected number of sub-tiles for a captured image based on pixel density within the captured image.

[0041] Figure 4 is a process flow diagram of an example embodiment of tile-based image correction using a selected number of sub-tiles based on pixel density. DETAILED DESCRIPTION

[0042] Embodiments are disclosed for applying adaptive sub-tiles to captured images for distortion correction in vision-based assistance systems and methods. The captured image is processed using tiles, and each corrected tile is generated using a selected number of tiles, depending on the pixel density associated with the region of the captured image being processed. The sub-tiles may also be selected based on the nature of the distortion. Various embodiments may be implemented, with different features and variations, while still utilizing the techniques described herein.

[0043] For the disclosed embodiments, it should be recognized that the pixel density of the image region to be read and processed to remove distortion is not constant and may vary across different regions of the captured image. For the disclosed embodiments, the number of sub-tiles used to generate each corrected tile is selected based in part on pixel density, which generally depends on the location of the source data within the captured image. For most images captured by a camera's image sensor, pixel density is higher in the center of the image, while pixel density is lower at the edges of the image due to the camera lens, image sensor, and associated capture technology used. Therefore, for denser image regions, such as those in the center of the image, the tile requires more local memory for a given tile size. For less dense image regions, such as those at the edges of the image, the tile requires significantly less local memory for a given tile size. Therefore, the disclosed embodiments generate corrected tiles using a selected number of sub-tiles based on the pixel density of the particular region being processed within the captured image. The nature of the distortion can also affect the size of the sub-tiles. For example, vertical distortion may require the extraction of more rows than horizontal distortion. By providing adaptive sub-tile image processing, the disclosed embodiments thus provide increased flexibility and efficiency in processing and correcting distorted images.

[0044] Figure 11 is a block diagram of an example embodiment 100 of a vehicle 130 including a system 120 that provides vision-based assistance to a driver of the vehicle 130. System 120 includes a camera 102 that captures and stores an image 122. A correction system 105 reads and processes image data 103 of the captured image 122 to correct distortion within the captured image 122. Correction system 105 includes a processor 106 and a source frame memory 104 that stores the image data 103 of the captured image 122. Source frame memory 104 stores the image data 103 for at least one complete camera image or frame. For one example embodiment, pipelining is applied such that while geometric correction is being applied to the current frame, data for the next frame is stored to provide double buffering. Correction system 105 also includes a memory 108 that stores a corrected image 109, which is read by or otherwise provided to a vision processor 110. It should be noted that memory 108 may be implemented in the same memory device that provides source frame memory 104. For example, a single double data rate (DDR) dynamic random access memory (DRAM) device or other memory device may be used to provide source frame memory 104 and memory 108. It should also be noted that corrected image 109 may be processed to identify one or more features before being provided to vision processor 110. Vision processor 110 receives corrected image 109 and uses it to output one or more control signals to initiate one or more actions to a system user. For example, the actions may include vibrating the wheels of vehicle 130; vibrating the seats of vehicle 130; generating an alarm sound within vehicle 130; or causing one or more other alarms that can be sensed by the driver or user of the system. Other actions may also be initiated, such as direct intervention actions, including adjusting steering, engaging the emergency brake, or other direct interventions. For one embodiment, one or more vision-based auxiliary images may be displayed to the driver of vehicle 130 via display 112. Furthermore, system 120 may also include one or more user interfaces 114. In one embodiment, user interface 114 is implemented as part of display 112, for example, as a touch screen. Display 112 may be a heads-up display, a rear-view display, or other display. Furthermore, correction system 105 may be implemented at least in part as a system-on-chip (SoC) integrated circuit. For example, processor 106 and vision processor 110 may be implemented on a single integrated circuit, and source frame memory 104 and memory 108 may be implemented on a single memory device. Other variations may also be implemented while still utilizing the adaptive sub-tiling techniques described herein.

[0045] As described herein, the correction system 105 accesses and processes the image data 103 to generate a corrected image tile using adaptive sub-tiles. In operation, the captured image 122 is transmitted as the image data 103 and stored in the source frame memory 104 of the correction system 105. Figure 2 As further described, processor 106 reads and processes source data blocks 202 within image data 103 based on different numbers of sub-blocks 203 selected based on pixel densities associated with different regions of captured image 122. Processor 106 then corrects distortion within source data blocks 202 and outputs corrected sub-blocks, which are combined to form corrected blocks 240. During operation, processor 106 provides one or more control signals to access and process image data 103 using a series of data transfers from source frame memory 104 to source block memory 204. Source block memory 204 stores the source data required to generate a corrected block or sub-block. For one embodiment, the size of source block memory 204 is based on the expected highest density partition of captured image 122 and the corresponding sub-block to be used. Note that larger sub-blocks are used for less dense regions of captured image 122, and smaller sub-blocks are used for denser regions of captured image 122. Thus, improved, efficient or optimal usage of memory resources is achieved.

[0046] For one example embodiment, source frame memory 104 is a dynamic random access memory (DRAM), such as a double data rate (DDR) DRAM, that stores an entire frame of captured image 122. Image data 103 stored in source frame memory 104 is then processed to output one corrected tile at a time, and each corrected tile is generated by processing image data 104 to generate one corrected sub-tile at a time. The source data used to generate each corrected sub-tile is stored in a memory accessible by processor 106, such as Figure 2 The source block memory 204 in FIG. The source data blocks are processed to correct distortion and generate corrected sub-blocks, and the corrected sub-blocks are combined to form a corrected block. The corrected block, including the corrected sub-blocks, is stored in the memory 108, which can also be implemented as DDR DRAM. The corrected blocks are combined to form a corrected image 109.

[0047] Figure 2is a diagram of an example embodiment 200 for processing a captured image 122 using adaptive sub-tiles 203. As described above, the captured image 122 is stored as image data 103 within the source frame memory 104. In previous solutions, the corrected tiles were generated using the image data 103 of the captured image 122; however, the image data for all of the tiles was read and processed. In contrast, with the disclosed embodiment, the correction system 105 processes the image data 103 using source data blocks 202 that depend on a different number of sub-tiles 203. The sub-tiles 203 are selected based on the pixel density associated with different regions of the captured image 122. For one example embodiment, each source data block 202 is transferred from the source frame memory 104 to the source block memory 204 using an input direct memory access (DMA), such as that represented by input DMA 242. It should be noted that the source frame memory 104 can be implemented as a fixed size and used to store the image data 103 of the captured image 122 as described above. It should also be noted that the source block memory 204 of the processor 106 is used to store the source data blocks 202. The number of sub-tiles 203 used to generate the corrected tile 240 is selected from a set of numbers based on the pixel density associated with the image data 103. For one embodiment, the image data 103 of the captured image 122 is four (4) megabytes (MB) or larger, and the source block memory 204 is an on-chip synchronous random access memory (SRAM) or other memory having a fixed size between 16 kilobytes (KB) and 280 KB. Other sizes may also be used.

[0048] It should be noted that the adaptive subtiles for a particular solution are preferably generated offline, based on the known parameters of the camera 102 used within the particular solution. The resulting subtile configuration 250 identifies the number of subtiles to be used to generate each corrected tile for an image expected to be captured by the particular camera solution. The subtile configuration 250 also contains parameter data describing how the image data should be corrected to generate the corrected subtiles. This subtile configuration 250 includes data identifying the number of subtiles selected for each corrected tile 240 and is stored in memory for use by the control circuitry 230 and processor 106 during operation of the correction system 105. During operation, the control circuitry 230 accesses the subtile configuration 250 and provides information to the processor 106, which selects a particular number of subtiles 203 for use in generating the corrected tile 240 associated with the image data 103 stored in the source frame memory 104. It should be noted that the processor 106 can also be configured to access the subtile configuration 250. As further described below, processor 106 corrects the distortion within the sub-tiles and then stores the corrected sub-tiles in output tile buffer 260 before transferring them to memory 108. The corrected sub-tiles are combined to form corrected tiles 240, and corrected tiles 240 are combined to form corrected image 109. After processing the entire image, corrected image 109 is ultimately output for further processing. The disclosed embodiments provide significant flexibility in the trade-off between memory size and the bandwidth required to access and process the image data 103 of the captured image 122.

[0049] As the processor 106 processes the source data block 202 within the source frame memory 104, the number of sub-tiles 203 used is selected from a set of numbers, and each corrected sub-tile is generated for a particular corrected tile 240 one at a time. The source data block 202 associated with each of the sub-tiles 203 is stored in the source block memory 204 for processing by the processor 106. The number of sub-tiles 203 is selected based on a sub-tile configuration 250 that depends on the pixel density of the captured image 122. For the example embodiment depicted, a set of four different numbers of sub-tiles is used, with a first number of sub-tiles 206 being one (1) sub-tile, a second number of sub-tiles 208 being four (4) sub-tiles, a third number of sub-tiles 210 being sixteen (16) sub-tiles, and a fourth number of sub-tiles 212 being sixty-four (64) sub-tiles. A larger number of sub-tiles is used for areas with higher pixel density, while a smaller number of sub-tiles is used for areas with lower pixel density or resolution. It should be noted that different numbers can be used, and more or fewer than four different numbers of sub-tiles can be used as a set number. Furthermore, multiple different sub-tile sizes can be used to generate the corrected tile instead of a single sub-tile size, such that a mixture of sub-tile sizes is used to generate the corrected tile. Other variations can also be implemented while still utilizing the sub-tile techniques described herein.

[0050] Depending on the number of sub-blocks 203 used to generate a particular corrected block 240, a different number of data transfers and associated processing steps will be used to process the image data 103. For example, where a first number of sub-blocks 206 are used, a source data block 202 is transferred from the source frame memory 104 to the source block memory 204 using a single transfer 213. Where a second number of sub-blocks 208 are used, four source data blocks 202 are transferred from the source frame memory 104 to the source block memory 204 using four data transfers 214. Where a third number of sub-blocks 210 are used, sixteen source data blocks 202 are transferred from the source frame memory 104 to the source block memory 204 using sixteen data transfers 216. Where a fourth number of sub-blocks 212 are used, sixty-four source data blocks 202 are transferred from the source frame memory 104 to the source block memory 204 using sixty-four (64). Once the processor 106 has processed and corrected the previous sub-block (eg, by remapping pixels), each data transfer for sub-block numbers 208, 210, and 212 is performed one after the other.

[0051] It should also be noted that the size of source block memory 204 can be selected based on the highest density area of ​​captured image 122 in a particular camera solution. For example, as part of circuitry included in a single SoC integrated circuit, source block memory 204 preferably remains fixed. Thus, even when the FOV or resolution of the camera sensor increases or decreases during operation, source block memory 104 will generally remain fixed. However, as the pixel density of the image area being processed changes, a different number of subtiles 203 is used based on subtile configuration 250. As described above, subtile configuration 250 provides a predetermined selection of the number of subtiles to use for each corrected tile 240 based on the camera solution, and subtile configuration 250 is stored for access by processor 106 during the distortion correction process. For example, subtile configuration 250 is stored in a memory accessible by processor 106. Other variations may also be implemented.

[0052] Processor 106 may implement one or more correction algorithms 220 to provide distortion correction. For example, correction algorithm 220 may implement one or more geometric distortion correction algorithms to remap pixels of source data block 202 to pixels within a corrected sub-block. For example, pixels within source data block 202 of a first number of sub-blocks 206 (only a single sub-block 206) are remapped by correction algorithm 220 to pixels within corrected sub-block 231, which also serves as corrected block 238. Pixels within each source data block 202 associated with a second number of sub-blocks 208 are remapped by correction algorithm 220 to pixels within corrected sub-block 224, and once all sub-blocks have been processed, the corrected sub-blocks are combined to form corrected block 232. Pixels within each source data block 202 associated with the third number of sub-blocks 210 are remapped to pixels within corrected sub-blocks 226 by correction algorithm 220, and once all sub-blocks are processed, the corrected sub-blocks are combined to form corrected block 234. Pixels within each source data block 202 associated with the fourth number of sub-blocks 212 are remapped to pixels within corrected sub-blocks 228 by correction algorithm 220, and once all sub-blocks are processed, the corrected sub-blocks are combined to form corrected block 236. The corrected sub-blocks of the selected sub-block configuration (which may be 224, 226, 228, or 231) are assembled into a complete corrected block in output tile buffer 260. For one example embodiment, output tile buffer 260 is implemented as on-chip SRAM. Once the complete corrected block is assembled, the data is copied from tile buffer 260 to memory 108 using output DMA 244. Output DMA 244 is controlled by control circuitry 230. For an example embodiment, the output tile buffer 260 is sized to hold data for more than one corrected tile to allow data for the current tile to be transferred using the output DMA 244 while sub-tiles of the next tile are processed and assembled in the output buffer 260 .

[0053] It should be noted that control circuitry 230 may also be included within correction system 105. Control circuitry 230 is coupled to input DMA 242, processor 106 including source block memory 204, output DMA 244, and memory 108 to facilitate data transfer and control of the operation of correction system 105. For one embodiment, correction system 105, including processor 106 and control circuitry 230, is implemented using dedicated digital hardware logic circuitry to implement the functions described herein. Correction system 105 may also be implemented as a microcontroller, microprocessor, programmable logic device, or other programmable circuitry that executes program instructions stored in a non-volatile data storage medium to perform the control actions and functions described herein. Additionally, source frame memory 104, source block memory 204, output tile buffer 260, and memory 108 may be implemented as one or more data storage media configured to store the data described herein. For one embodiment, source block memory 204 and output tile buffer 260 are included as on-chip SRAM within a SoC integrated circuit along with processor 106, while source frame memory 104 and memory 108 are included within a single memory integrated circuit, such as DDR DRAM. Other variations may also be implemented while still utilizing the techniques described herein.

[0054] Figure 3 is a diagram of an example embodiment 300 of selecting different numbers of sub-tiles for an example captured image 122. Figure 3 , assume that for the pixel density of the captured image 122, the pixel density of the central region of the captured image 122 is higher than the pixel density of the edge region of the captured image 122. Therefore, using the above example embodiment with four different numbers of sub-tiles, for the middle tile within the central region of the captured image 122, the fourth number of sub-tiles 212 with the most sub-tiles is selected. The third number of sub-tiles 210 is selected for the second layer tile adjacent to the middle tile. The second number of sub-tiles 208 is selected for the third layer tile adjacent to the second layer tile. For the edge tile having the edge region of the captured image 122, the first number of sub-tiles 208 with the fewest sub-tiles is selected. It should be noted again that different numbers of sub-tiles, and optionally different numbers of groups, can be used while still utilizing the techniques described herein.

[0055] As described above, predetermined configuration data for the number of subtiles can be determined based on FOV, resolution, or other parameters associated with camera 102 for a particular solution. Furthermore, this subtile configuration data can be stored within correction system 105 as subtile configuration 250, and processor 106 or control circuitry 230 can use the subtile configuration data to determine the number of subtiles 203 for each corrected tile 240. As described above, this subtile selection also determines the transfer of data from source frame memory 104 to source block memory 204. For example, predetermined subtile configuration 250 can be stored in a memory or storage medium accessible by correction system 105. Other variations can also be implemented.

[0056] Figure 4 The present invention is a process flow diagram of an example embodiment 400 of tile-based image correction that generates a corrected tile using a selected number of sub-tiles based on pixel density. In block 402, an image is captured using a camera. In block 404, image data from the camera is stored in a source frame memory, and the image data represents the captured image. In block 406, generation of corrected tiles for the corrected image begins. In block 408, the number of sub-tiles to be used to generate the corrected tile is determined based on the pixel density of the image region being processed within the image data. In block 410, source data blocks for the sub-tiles are transferred, for example, from source frame memory 104 to source block memory 204. In block 412, distortion correction is applied, and corrected sub-tiles are generated and output. In block 414, a determination is made as to whether all sub-tiles of a particular corrected tile have been processed. If not, the process returns to block 410. If yes, the process proceeds to block 416. In block 416, the corrected sub-tiles are combined, and the corrected tile is output using the corrected sub-tiles. In block 418, a determination is made as to whether all tiles have been processed. If not, the process returns to block 406 to generate the next corrected tile of the corrected image. If yes, the process proceeds to block 420, where the corrected tiles are combined and the corrected image is output using the corrected tiles. It should be noted that additional or different process steps may be used while still utilizing the techniques described herein.

[0057] As described herein, various embodiments may be implemented, and different features and variations may be implemented as desired.

[0058] It should also be noted that the functional blocks, components, systems, devices, or circuits described herein can be implemented using hardware, software, or a combination of hardware and software, as well as analog circuits, as needed. For example, the disclosed embodiments can be implemented using one or more integrated circuits that are programmed to perform the functions, tasks, methods, actions, or other operational features described herein for the disclosed embodiments. For example, the one or more integrated circuits may include one or more processors or configurable logic devices (CLDs) or a combination thereof. For example, the one or more processors may be one or more central processing units (CPUs), control circuits, microcontrollers, microprocessors, hardware accelerators, ASICs (application specific integrated circuits), or other integrated processing devices. For example, the one or more CLDs may be one or more CPLDs (complex programmable logic devices), FPGAs (field programmable gate arrays), PLAs (programmable logic arrays), reconfigurable logic circuits, or other integrated logic devices. In addition, the integrated circuits including one or more processors may be programmed to execute software, firmware, code, or other program instructions embodied in one or more non-transitory tangible computer-readable media to perform the functions, tasks, methods, actions, or other operational features described herein for the disclosed embodiments. An integrated circuit including one or more CLDs may also be programmed using logic code, logic definitions, hardware description languages, configuration files, or other logic instructions embodied in one or more non-transitory tangible computer-readable media to perform the functions, tasks, methods, actions, or other operational features described herein with respect to the disclosed embodiments. Furthermore, for example, the one or more non-transitory tangible computer-readable media may include one or more data storage devices, memory devices, flash memory, random access memory, read-only memory, programmable memory devices, reprogrammable storage devices, hard drives, floppy disks, DVDs, CD-ROMs, or any other non-transitory tangible computer-readable media. Other variations may also be implemented while still utilizing the techniques described herein.

[0059] Unless otherwise stated, terms such as "first" and "second" are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of these elements.

[0060] In view of this description, further modifications and alternative embodiments of the described systems and methods will be apparent to those skilled in the art. Therefore, it will be appreciated that the described systems and methods are not limited to these example arrangements. It should be understood that the forms of the systems and methods shown and described herein are to be regarded as example embodiments. Various changes may be made in the embodiments. Therefore, although the present invention is described herein with reference to specific embodiments, various modifications and changes may be made without departing from the scope of the present invention. Therefore, this specification and the accompanying drawings should be regarded as illustrative rather than restrictive, and such modifications are intended to be included within the scope of the present invention. In addition, any benefits, advantages, or solutions to problems described herein with respect to specific embodiments are not intended to be interpreted as key, necessary, or essential features or elements of any or all claims.

Claims

1. A distortion correction circuit, characterized in that: include: a first memory coupled to store image data representing the captured image; a processor coupled to process the image data to correct distortion and output a corrected tile, comprising: reading and processing a source data block within the image data based on different numbers of sub-tiles, the different numbers of sub-tiles being selected based on pixel densities associated with different regions of the captured image, wherein larger sub-tiles are used for less dense regions of the captured image and smaller sub-tiles are used for denser regions of the captured image; correcting distortion within the source data block and outputting corrected sub-tiles; combining the corrected sub-tiles to form a corrected tile, the corrected tile having a number of sub-tiles selected from a set of numbers based on pixel densities associated with different regions of the captured image; as well as A second memory is coupled to store a corrected image based on the corrected tiles.

2. The circuit according to claim 1, wherein: The set number of sub-blocks includes one sub-block, four sub-blocks, sixteen sub-blocks, and sixty-four sub-blocks.

3. The circuit according to claim 1, wherein: At least one of the corrected tiles is generated using a plurality of different sub-tile sizes.

4. The circuit according to claim 1, wherein: Different numbers of sub-tiles are selected for generating the corrected tile.

5. The circuit according to claim 4, characterized in that A central region of the captured image has a higher pixel density than an edge region of the captured image, and wherein a greater number of sub-tiles is used for at least one corrected tile associated with the central region than for another corrected tile associated with the edge region.

6. The circuit according to claim 1, wherein: Sub-tiles of each of the corrected tiles are generated by the processor one at a time, and wherein the sub-tiles are combined to form the corrected tile.

7. The circuit according to claim 1, wherein: The sub-tiles used by the processor depend on a predetermined sub-tile configuration stored within the system.

8. A vision-based assistance system, characterized in that: include: A circuit according to any of the preceding items; camera; as well as Vision processor; wherein the circuitry is coupled to receive image data representing a captured image from the camera and to correct distortion within the image data; as well as Wherein the vision processor is coupled to receive the corrected image from the processor and cause one or more actions to be issued to a user of the system.

9. The vision-based assistance system according to claim 8, characterized in that At least one of the corrected tiles is generated using a plurality of different sub-tile sizes.

10. A method for correcting image distortion, characterized in that: include: storing image data from the camera in a memory, the image data representing a captured image; reading and processing blocks of source data within the image data based on different numbers of sub-tiles selected based on pixel densities associated with different areas of the captured image, with larger sub-tiles used for less dense areas of the captured image and smaller sub-tiles used for more dense areas of the captured image; generating a corrected tile using a number of sub-tiles selected from a set of numbers based on pixel densities associated with different regions of the captured image; processing the image data to correct distortion and generate a corrected tile, comprising: correcting distortion within a source data block and outputting corrected sub-tiles; combining the corrected sub-tiles to form a corrected tile; the corrected tile having a number of sub-tiles selected from a set of numbers based on pixel densities associated with different regions of the captured image; and The corrected tiles are combined to output a corrected image.

Images