Pixels and display devices including pixels

Abstract

A pixel and a display device including the pixel are disclosed. The pixel includes: a first electrode and a second electrode spaced apart from each other; a light-emitting element electrically connected to the first electrode and the second electrode; a first pixel circuit connected to a first power supply and generating a driving current based on a scan signal and a data signal; and a first selection circuit controlling an electrical connection between the first pixel circuit and the first electrode and an electrical connection between a second power supply and the second electrode based on a first selection signal.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2019 - 0094307, filed on August 2, 2019, with the Korean Intellectual Property Office, the entire content of which is incorporated herein by reference. Technical field

[0003] Embodiments relate to a display device, and more particularly, to a pixel including a light - emitting element and a display device including the pixel. Background art

[0004] In recent years, technologies for manufacturing micro - light - emitting elements using materials having a highly reliable inorganic crystal structure and manufacturing light - emitting devices using the light - emitting elements have been developed. For example, technologies for manufacturing micro - light - emitting elements having small sizes in the range from nanometers to micrometers and forming pixels of a display device using the micro - light - emitting elements have been developed.

[0005] It will be understood that this background art section is partly intended to provide a useful background for understanding the technology. However, this background art section may also include ideas, concepts, or cognitions that are not known or understood by those skilled in the relevant art before the effective filing date of the corresponding disclosure of the subject matter. Summary of the invention

[0006] Embodiments provide a pixel in which an electrode connected to a second power supply can be determined according to an alignment ratio of light - emitting elements.

[0007] In an embodiment, a display device may include a pixel in which an electrode connected to a second power supply can be determined according to an alignment ratio of light - emitting elements.

[0008] However, it should be understood that the present invention may not be limited by the foregoing, but various extensions may be made without departing from the spirit and scope of the present invention.

[0009] A pixel according to an embodiment may include a first electrode and a second electrode spaced apart from each other, and a light - emitting element electrically connected to the first electrode and the second electrode. The pixel may include: a first pixel circuit connected to a first power supply and generating a driving current based on a scan signal and a data signal; and a first selection circuit that can control an electrical connection between the first pixel circuit and the first electrode and an electrical connection between a second power supply different from the first power supply and the second electrode based on a first selection signal.

[0010] In an embodiment, the pixel may further include: a second pixel circuit connected to a first power supply and generating a driving current based on a scan signal and a data signal; and a second selection circuit configured to control an electrical connection between the second pixel circuit and a second electrode and an electrical connection between a second power supply and a first electrode based on a second selection signal.

[0011] In an embodiment, the first selection circuit may include: a first selection transistor connected between the first pixel circuit and the first electrode and including a gate electrode connected to a first node; a second selection transistor connected between the second power supply and the second electrode and including a gate electrode connected to the first node; a storage element connected to the first node; and a third selection transistor connected between a first selection line for supplying the first selection signal and the storage element and including a gate electrode connected to a control line for supplying a control signal.

[0012] In an embodiment, the storage element may include a first inverter and a second inverter that are connected in feedback with each other between the first node and the third selection transistor.

[0013] In an embodiment, the first inverter may include: a first inverter transistor connected between the first node and a low power supply and including a gate electrode connected to a second node; and a second inverter transistor connected between the first node and a high power supply and including a gate electrode connected to the second node.

[0014] In an embodiment, the second inverter may include: a third inverter transistor connected between the second node and the low power supply and including a gate electrode connected to the first node; and a fourth inverter transistor connected between the second node and the high power supply and including a gate electrode connected to the first node.

[0015] In an embodiment, the storage element may include a capacitor coupled between the first node and a third power supply.

[0016] In an embodiment, the control signal may be substantially the same as the scan signal.

[0017] In an embodiment, the second selection circuit may include: a first selection transistor connected between the second pixel circuit and the second electrode and including a gate electrode connected to the first node; a second selection transistor connected between the second power supply and the first electrode and including a gate electrode connected to the first node; a storage element connected to the first node; and a third selection transistor connected between a second selection line for supplying the second selection signal and the storage element and having a gate electrode connected to the control line for supplying the control signal.

[0018] In an embodiment, each of the light-emitting elements may be a first-polarity-direction light-emitting element or a second-polarity-direction light-emitting element. The first-polarity-direction light-emitting element and the second-polarity-direction light-emitting element may have opposite polarity directions.

[0019] In an embodiment, when the number of first-polarity-direction light-emitting elements is greater than or equal to the number of second-polarity-direction light-emitting elements, the first pixel circuit may be electrically connected to the light-emitting element in response to a first selection signal. The second pixel circuit may not be electrically connected to the light-emitting element.

[0020] In an embodiment, when the number of first-polarity-direction light-emitting elements is less than the number of second-polarity-direction light-emitting elements, the second pixel circuit may be electrically connected to the light-emitting element in response to a second selection signal. The first pixel circuit may not be electrically connected to the light-emitting element.

[0021] In an embodiment, when the ratio of the number of first-polarity-direction light-emitting elements to the number of second-polarity-direction light-emitting elements is greater than or equal to a reference ratio, the first pixel circuit may be electrically connected to the light-emitting element. When the ratio of the number of first-polarity-direction light-emitting elements to the number of second-polarity-direction light-emitting elements is less than the reference ratio, the second pixel circuit may be electrically connected to the light-emitting element.

[0022] In an embodiment, when the first pixel circuit is electrically connected to the light-emitting element, the voltage of a second power supply may be supplied to a second electrode. When the second pixel circuit is electrically connected to the light-emitting element, the voltage of the second power supply may be supplied to a first electrode.

[0023] In an embodiment, each of the first pixel circuit and the second pixel circuit may include: a first transistor configured to control a driving current supplied to the light-emitting element based on a voltage applied to a gate electrode of the first transistor; and a second transistor connected between a data line for supplying a data signal and the first transistor and including a gate electrode connected to a scan line for supplying a scan signal.

[0024] A display device according to an embodiment may include pixels, each pixel including a light-emitting element electrically connected to a first electrode and a second electrode. The display device may include: a scan driver configured to supply a scan signal to the pixels via scan lines and supply a control signal to the pixels via control lines; a data driver configured to supply a data signal to the pixels via data lines; and a selection signal driver configured to supply a first selection signal to the pixels via a first selection signal line and supply a second selection signal to the pixels via a second selection signal line. Each of the pixels may include: a first pixel circuit connected to a first power supply and including a first driving transistor configured to generate a driving current based on the scan signal and the data signal; a first selection circuit configured to electrically connect the first pixel circuit and the first electrode in response to the first selection signal and electrically connect a second power supply and the second electrode. Each of the pixels may include: a second pixel circuit connected to the first power supply and including a second driving transistor configured to generate a driving current based on the scan signal and the data signal; and a second selection circuit configured to electrically connect the second pixel circuit and the second electrode in response to the second selection signal and electrically connect the second power supply and the first electrode.

[0025] In an embodiment, the scan driver may perform a scan once during a period in which the display device is driven to supply the control signal to the control lines, and then may stop supplying the control signal.

[0026] In an embodiment, the selection signal driver may supply the first selection signal and the second selection signal to each of the pixel columns via the first selection signal line and the second selection signal line in response to the control signal. The second selection signal may be an inverted signal of the first selection signal.

[0027] In an embodiment, each of the light-emitting elements may be a first-polarity-direction light-emitting element or a second-polarity-direction light-emitting element. The first-polarity-direction light-emitting element and the second-polarity-direction light-emitting element may have opposite polarity directions.

[0028] In an embodiment, a pixel may include: a first pixel including a first electrode connected to the first pixel circuit and a second electrode connected to a second power supply; and a second pixel including a first electrode connected to the second power supply and a second electrode connected to the second pixel circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a schematic block diagram showing a display device according to an embodiment.

[0030] Figure 2A and Figure 2B are a schematic perspective view and a schematic cross-sectional view showing a light-emitting element according to an embodiment.

[0031] Figure 3A and Figure 3Bis a schematic perspective view and a schematic cross-sectional view showing a light-emitting element according to an embodiment.

[0032] Figure 4A and Figure 4B is a schematic perspective view and a schematic cross-sectional view showing a light-emitting element according to an embodiment.

[0033] Figure 5 is a schematic plan view showing a display device according to an embodiment.

[0034] Figure 6 is a schematic view showing a light-emitting element in a pixel according to an embodiment.

[0035] Figure 7 is a schematic view showing a pixel according to an embodiment.

[0036] Figure 8 is a schematic graphical view of signal waveforms for explaining the operation of a pixel according to an embodiment.

[0037] Figure 9 is a schematic circuit diagram showing a storage element according to an embodiment.

[0038] Figure 10A is a schematic graphical view of signal waveforms for explaining the operation of a display device according to an embodiment.

[0039] Figure 10B is a schematic view showing the connection relationship between pixels according to an embodiment.

[0040] Figure 10C is a schematic block diagram showing a scan driver according to an embodiment.

[0041] Figure 11 is a schematic graphical view of signal waveforms for solving the operation of a display device according to an embodiment.

[0042] Figure 12 is a schematic view showing a pixel according to an embodiment.

[0043] Figure 13 is a schematic graphical view of signal waveforms for explaining the operation of a display device according to an embodiment.

[0044] Figure 14 is a schematic circuit diagram showing a pixel circuit according to an embodiment.

[0045] Figure 15 is a schematic graphical view of signal waveforms for explaining the operation of a pixel according to an embodiment.

[0046] Figure 16is a schematic circuit diagram showing a pixel circuit according to an embodiment. Detailed Embodiment

[0047] Hereinafter, embodiments will be described in more detail with reference to the accompanying drawings. In the description of the drawings, the same reference numerals always denote the same elements, and redundant descriptions of similar components may be omitted.

[0048] In the drawings, for clarity and ease of description, the dimensions and thicknesses of elements may be exaggerated. However, the present disclosure is not limited to the dimensions and thicknesses shown.

[0049] The term "and / or" is intended to include any combination of the terms "and" and "or" for the purpose of its meaning and illustration. For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in a combined or disjunctive sense and may be understood to be equivalent to "and / or". When listing possible attributes (e.g., "X may include A, B, and C", "X may be formed of A, B, or C", etc.), it is intended to include individual attributes as well as possible combinations of attributes for the purpose of meaning and illustration.

[0050] The term "overlap" or "overlapped" means that a first object may be above or below or to the side of a second object, and conversely, the second object may be above or below or to the side of the first object. Additionally, the term "overlap" may include layer, stack, face or facing, extend over, cover or partially cover or any other suitable term that one of ordinary skill in the art will understand and appreciate.

[0051] As used herein, "about" or "substantially" includes the recited value and may mean within an acceptable deviation range of the specific value as determined by one of ordinary skill in the art considering measurement issues and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system). For example, "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±5% of the recited value.

[0052] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an ideal or overly formal sense unless clearly defined in this specification.

[0053] Figure 1 is a schematic block diagram showing a display device according to an embodiment.

[0054] Refer to Figure 1, the display device 1000 may include a display portion 100, a scan driver 200, a data driver 300, a selection signal driver 400, and a timing controller 500.

[0055] The display device 1000 may be, for example, a flat display device, a flexible display device, a curved display device, a foldable display device, and / or a bendable display device. The display device 1000 may be applied as, for example, a transparent display device, a head-mounted display device, a wearable display device, etc.

[0056] The display portion 100 may include scan lines SL, control lines CL, data lines DL, and selection signal lines SEL1 and SEL2. The display portion 100 may include pixels PXL, and the pixels PXL are connected to the scan lines SL, control lines CL, data lines DL, and selection signal lines SEL1 and SEL2. The display portion 100 may be formed inside the display panel.

[0057] For example, the pixel PXL disposed in the i-th row and the j-th column (where i and j may be natural numbers) may be connected to the i-th scan line SLi, the i-th control line CLi, the j-th data line DLj, the j-th first selection signal line SEL1j, and the j-th second selection signal line SEL2j.

[0058] The pixel PXL may include a light-emitting element according to Figures 2A to 4B the embodiments. For example, the pixel PXL may include a micro light-emitting element having a small size ranging from the nanoscale to the microscale. In an example, each pixel PXL may include Figure 2A and Figure 2B the light-emitting elements therein, and these light-emitting elements may be connected in parallel with each other between the pixel electrode and / or the power line to constitute the light source or the light source portion of the pixel PXL.

[0059] In an example, the pixel PXL may include a first pixel circuit, a first selection circuit, a second pixel circuit, a second selection circuit, and a light-emitting element.

[0060] The timing controller 500 may generate a first control signal SCS, a second control signal CCS, a third control signal DCS, and a fourth control signal SECS in response to an external synchronization signal. The first control signal SCS and the second control signal CCS may be supplied to the scan driver 200. The third control signal DCS may be supplied to the data driver 300. The fourth control signal SECS may be supplied to the selection signal driver 400. The timing controller 500 may rearrange the input image data supplied from the outside into image data DATA, and may supply the image data DATA to the data driver 300.

[0061] The first control signal SCS may include a scan start pulse and a clock signal. The scan start pulse may control a first timing of the scan signal. The clock signal may be used to shift the scan start pulse.

[0062] The second control signal CCS may include a control start pulse and a clock signal. The control start pulse may control a first timing of the control signal. The clock signal may be used to shift the control start pulse.

[0063] The third control signal DCS may include a source start pulse and a clock signal. The source start pulse may control a sampling start time point of data. The clock signal may be used to control a sampling operation.

[0064] The fourth control signal SECS may include a start pulse of a selection signal and a clock signal.

[0065] The scan driver 200 may receive the first control signal SCS from the timing controller 500, and may supply a scan signal to the scan line SL based on the first control signal SCS. For example, the scan driver 200 may sequentially supply the scan signal to the scan line SL. In a case where the scan signal may be sequentially supplied, pixels PXL in a horizontal line portion (or a pixel row portion) may be selected.

[0066] The scan driver 200 may receive the second control signal CCS from the timing controller 500, and may supply a control signal to the control line CL based on the second control signal CCS. For example, the scan driver 200 may sequentially supply the control signal to the control line CL. Here, the control signal may be a signal for controlling an operation of a selection circuit included in the pixel PXL.

[0067] In an embodiment, the scan driver 200 may have a separate circuit configuration for outputting the scan signal and the control signal.

[0068] The data driver 300 may receive the third control signal DCS and image data DATA from the timing controller 500. The data driver 300 may supply a data signal to the data line DL in response to the third control signal DCS. The data signal supplied to the data line DL may be supplied to the pixel PXL selected by the scan signal. To this end, the data driver 300 may supply the data signal to the data line DL in synchronization with the scan signal.

[0069] The selection signal driver 400 may supply a first selection signal to the pixel PXL through a first selection signal line SEL1, and may supply a second selection signal to the pixel PXL through a second selection signal line SEL2. The first selection signal may be a signal for electrically connecting a first pixel circuit and a light emitting element included in the pixel PXL, and the second selection signal may be a signal for electrically connecting a second pixel circuit and a light emitting element. The first selection signal and the second selection signal may be supplied to the pixel PXL selected by the control signal.

[0070] For example, the scan line SL and the control line CL may be connected to the pixels PXL in the pixel row portion. The data line DL, the first selection signal line SEL1, and the second selection signal line SEL2 may be connected to the pixels PXL in the pixel column portion.

[0071] In an embodiment, the second selection signal may be an inverted signal of the first selection signal. Therefore, in one pixel PXL, one of the first pixel circuit and the second pixel circuit may be electrically connected to the light emitting element through the first selection signal and the second selection signal.

[0072] In an implementation, the display device 1000 may further include an emission driver configured to supply an emission control signal to the pixel PXL and / or a power supplier configured to supply power sources VDD and VSS to the pixel PXL.

[0073] Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A and Figure 4B It is shown that it can be included in Figure 1 Schematic perspective view and schematic cross-sectional view of an example of a light emitting element in a pixel of a display device.

[0074] Figures 2A to 4B , a rod-shaped light emitting element LD having a cylindrical shape is shown, but the type and / or shape of the light emitting element LD is not limited thereto.

[0075] First, refer to Figure 2A and Figure 2B , the light emitting element LD according to the embodiment may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 interposed between the first semiconductor layer 11 and the second semiconductor layer 13. In an example, the light emitting element LD may be formed as a stacked body in which the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 may be stacked (e.g., sequentially stacked) in a direction of the length L1.

[0076] According to an embodiment, the light-emitting element LD may be provided in a rod shape extending in one direction. Considering that the extending direction of the light-emitting element LD may be the direction of the length L1, the light-emitting element LD may have one end and the other end in the direction of the length L1.

[0077] According to an embodiment, one of the first semiconductor layer 11 and the second semiconductor layer 13 may be provided at an end of the light-emitting element LD, and the other of the first semiconductor layer 11 and the second semiconductor layer 13 may be provided at the other end of the light-emitting element LD.

[0078] According to an embodiment, the light-emitting element LD may be a rod-shaped light-emitting diode manufactured in a rod shape. In this specification, the term "rod shape" may include rod-like shapes and bar-like shapes, such as cylinders and polygonal columns, which may be long in the direction of the length L1 (i.e., having an aspect ratio greater than one). The shape of the cross-section of the rod shape is not particularly limited. For example, the length L1 of the light-emitting element LD may be greater than its diameter D (or the width of the cross-section).

[0079] According to an embodiment, the light-emitting element LD may have a small size ranging from the nanoscale to the microscale. The light-emitting element LD may have a diameter D and / or a length L1 that may vary from the nanoscale to the microscale. For example, the length L1 of the light-emitting element LD may be in the range of about 100 nm to about 10 μm, and the aspect ratio of the light-emitting element LD may be in the range of about 1.2 to about 100. However, the size of the light-emitting element LD is not limited thereto. For example, the size of the light-emitting element LD may be differently changed according to the design conditions of various devices, such as display devices (e.g., Figure 1 "1000" in).

[0080] In an example, the first semiconductor layer 11 may include an n-type semiconductor layer. For example, the first semiconductor layer 11 may include an n-type semiconductor layer, which may include a semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN and may be doped with a first-conductivity-type dopant such as silicon (Si), germanium (Ge), or tin (Sn). However, the material constituting the first semiconductor layer 11 is not limited thereto, and the first semiconductor layer 11 may also be made of various materials. The active layer 12 may be provided on the first semiconductor layer 11 and may be formed to have a single quantum well structure or a multi-quantum well structure. In an embodiment, a cladding layer (not shown) doped with a conductive dopant may be formed on and / or below the active layer 12. In an example, the cladding layer may be formed as an AlGaN layer or an InAlGaN layer. According to an embodiment, materials such as AlGaN or InAlGaN may be used to form the active layer 12. The active layer 12 may also be made of various materials.

[0081] When a voltage greater than or equal to a threshold voltage can be applied to both ends of the light-emitting element LD, electrons and holes can be combined with each other, and thus, the light-emitting element LD emits light. By controlling the light emission of the light-emitting element LD using this principle, the light-emitting element LD can be used as a light source for various light-emitting devices including pixels (e.g., Figure 1 "PXL" in

[0082] The second semiconductor layer 13 may be provided on the active layer 12 and may include a semiconductor layer having a type different from that of the first semiconductor layer 11. For example, the second semiconductor layer 13 may include a p-type semiconductor layer. For example, the second semiconductor layer 13 may include a p-type semiconductor layer, the p-type semiconductor layer may include a semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may be doped with a dopant of a second conductivity type such as magnesium (Mg). However, the material constituting the second semiconductor layer 13 is not limited thereto, and the second semiconductor layer 13 may be made of various materials.

[0083] According to an embodiment, the light-emitting element LD may further include an insulating film INF provided on its surface. The insulating film INF may be formed on the surface of the light-emitting element LD to surround the outer circumferential surface of the active layer 12. The insulating film INF may also surround the regions of each of the first semiconductor layer 11 and the second semiconductor layer 13. However, the insulating film INF may expose both ends of the light-emitting element LD. The ends of the light-emitting element LD may have different polarities. For example, the insulating film INF may not cover and may expose the ends of each of the first semiconductor layer 11 and the second semiconductor layer 13 provided at both ends of the light-emitting element LD in the direction of length L1. For example, both base sides of a cylinder (e.g., Figure 2A and Figure 2B the upper surface and the lower surface of the light-emitting element LD in

[0084] According to an embodiment, the insulating film INF may include at least one insulating material selected from SiO2, Si3N4, Al2O3, and TiO2, but the present invention is not limited thereto. The structural material of the insulating film INF is not particularly limited, and the insulating film INF may be made of various insulating materials that may be currently known.

[0085] In an embodiment, in addition to the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and / or the insulating film INF, the light-emitting element LD may further include additional components. For example, the light-emitting element LD may additionally include at least one fluorescent layer, active layer, semiconductor layer, and / or electrode layer provided at one end side of the first semiconductor layer 11, the active layer 12, and / or the second semiconductor layer 13.

[0086] For example, as Figure 3Aand Figure 3B As shown in Figure 3B , the light-emitting element LD may further include at least one electrode layer 14 provided at an end side of the second semiconductor layer 13. According to an embodiment, as Figure 4A and Figure 4B shown in Figure 4B , the light-emitting element LD may further include another electrode layer 15 provided at an end side of the first semiconductor layer 11.

[0087] Each of the electrode layers 14 and 15 may be an ohmic contact electrode, but the electrode layers 14 and 15 are not limited thereto. For example, the electrode layers 14 and 15 may be Schottky contact electrodes. The electrode layers 14 and 15 may include a metal or a metal oxide. For example, chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), and their oxides or alloys may be used alone or in a mixture thereof. The electrode layers 14 and 15 may be substantially transparent or translucent. Thus, the light generated in the light-emitting element LD may pass through the electrode layers 14 and 15 and may be emitted to the outside of the light-emitting element LD.

[0088] According to an embodiment, the insulating film INF may or may not surround at least a part of the outer circumferential surface of each of the electrode layers 14 and 15. For example, the insulating film INF may be selectively formed on the surface of each of the electrode layers 14 and 15. The insulating film INF may be formed to expose both ends of the light-emitting element LD. The ends of the light-emitting element LD may have different polarities. For example, the insulating film INF may expose at least one region of each of the electrode layers 14 and 15. In another embodiment, the insulating film INF may not be provided.

[0089] When the insulating film INF may be provided on the surface of the light-emitting element LD, particularly on the surface of the active layer 12, a short circuit between the active layer 12 and an electrode or the like can be prevented. For example, a short circuit with a contact electrode that can be connected to both ends of the light-emitting element LD can be prevented. Thus, the electrical stability of the light-emitting element LD can be ensured.

[0090] Since the insulating film INF may be formed on the surface of the light-emitting element LD, surface defects of the light-emitting element LD can be minimized, thereby improving the lifespan and efficiency of the light-emitting element LD. In the case where the insulating film INF is formed in each of the light-emitting elements LD, even when the light-emitting elements LD may be arranged close to each other, an undesired short circuit between the light-emitting elements LD can be prevented.

[0091] The light-emitting element LD can be manufactured by a surface treatment process. For example, in the case where the light-emitting elements LD are mixed in a flowable solution (or solvent) and supplied to each light-emitting region (e.g., the light-emitting region of each pixel), the light-emitting elements LD can each be surface-treated to be uniformly dispersed rather than unevenly aggregated in the solution.

[0092] The light-emitting device including the light-emitting element LD can be used in various types of devices that require a light source (the device can be a display device). For example, one or more light-emitting elements LD (e.g., light-emitting elements LD each having a size ranging from the nanoscale to the microscale) can be provided in each pixel region of the display panel, thereby constituting a light source (or a light source portion). However, the application of the light-emitting element LD is not limited to display devices. For example, the light-emitting element LD can be used in other types of devices that require a light source, such as lighting devices.

[0093] Figure 5 is a schematic plan view showing Figure 1 an example of the display device.

[0094] The display panel PNL that can be included in a display device (e.g., Figure 1 "1000" in) is shown as an example of a device that can use the light-emitting element LD described with reference to Figures 2A to 4B In the example, the pixel PXL of the display panel PNL can include the light-emitting element LD.

[0095] For convenience, the structure of the display panel PNL is briefly shown for the display region DA in Figure 5 . However, according to an embodiment, at least one driving circuit (e.g., at least one scan driver (e.g., Figure 1 "200" in)) and / or wirings that are not shown can also be provided in the display panel PNL.

[0096] Referring to Figure 5 , the display panel PNL according to an embodiment can include a base layer BSL and pixels PXL provided on the base layer BSL. Specifically, the display panel PNL and the base layer BSL for forming the display panel PNL can include a display region DA for displaying an image and a non-display region NDA other than the display region DA. The pixels PXL can be provided in the display region DA of the base layer BSL.

[0097] According to an embodiment, the display region DA can be provided in the central region of the display panel PNL, and the non-display region NDA can be provided in the edge region of the display panel PNL to surround the display region DA. However, the positions of the display region DA and the non-display region NDA are not limited thereto, but can be changed. The display region DA can constitute a screen on which an image can be displayed.

[0098] The base layer BSL can form a base member of the display panel PNL. According to an embodiment, the base layer BSL can be a rigid or flexible substrate or film, and its material or physical properties are not particularly limited. In an example, the base layer BSL can be a rigid substrate made of glass or tempered glass, a flexible substrate (or film) made of plastic or metal material, or an insulating film including at least one layer. The material and / or physical properties of the base layer BSL are not particularly limited.

[0099] The base layer BSL can be transparent, but is not limited thereto. In an example, the base layer BSL can be a transparent, opaque, or reflective base member.

[0100] One region of the base layer BSL can be defined as the display region DA, and thus, the pixel PXL can be disposed in the display region DA. The remaining region of the base layer BSL can be defined as the non-display region NDA. For example, the base layer BSL can include: a display region DA including a pixel region in which the pixel PXL can be formed; and a non-display region NDA disposed at the periphery of the display region DA. Various wirings and / or embedded circuits connected to the pixel PXL in the display region DA can be disposed in the non-display region NDA.

[0101] According to an embodiment, the pixel PXL can be distributed and disposed in the display region DA. In an example, the pixel PXL can be arranged in a stripe or pentile array structure in the display region DA. However, the present invention is not limited thereto. For example, the pixel PXL can be arranged in various array structures that can be currently known in the display region DA.

[0102] Figure 6 is a schematic diagram showing a light-emitting element according to an embodiment. The light-emitting element can be aligned in the pixel.

[0103] Referring to Figures 1 to 6 , the pixel PXL can include a first electrode ET1, a second electrode ET2, and light-emitting elements LD1 and LD2.

[0104] As described with reference to Figures 2A to 4B , in an embodiment, each of the light-emitting elements LD1 and LD2 can be a diode element. For example, one electrode layer (e.g., Figure 4B one of "14" and "15" in Figure 4B ) of each of the light-emitting elements LD1 and LD2 can be an anode electrode AE, and its other electrode layer (e.g.,

[0105] The first electrode ET1 and the second electrode ET2 may be disposed on the insulating layer INS. A pixel circuit, a selection circuit, and wirings for driving the pixel PXL may be formed and disposed under the insulating layer INS. The pixel circuit and the selection circuit may be electrically connected to the first electrode ET1 or the second electrode ET2 through contact holes that penetrate the insulating layer INS.

[0106] The first electrode ET1 and the second electrode ET2 may be spaced apart from each other. Generally, the voltage of a first power supply ( Figure 1 “VDD”) having a high electric potential may be supplied to the first electrode ET1, and the voltage of a second power supply ( Figure 1 “VSS”) having a low electric potential may be supplied to the second electrode ET2.

[0107] In an embodiment, the light-emitting elements LD1 and LD2 may be disposed in a display portion 100 where the first electrode ET1 and the second electrode ET2 may be disposed. For example, the light-emitting elements LD1 and LD2 may be formed in a form dispersed in a solution, and thus may be disposed on the first electrode ET1 and the second electrode ET2 using an inkjet method or the like. When an alignment voltage (or alignment signal) is applied to the first electrode ET1 and the second electrode ET2 and an electric field may be formed between the first electrode ET1 and the second electrode ET2, the light-emitting elements LD1 and LD2 may be aligned between the first electrode ET1 and the second electrode ET2. After the light-emitting elements LD1 and LD2 are aligned, the solvent may be evaporated or removed by other methods to stably align the light-emitting elements LD1 and LD2 between the first electrode ET1 and the second electrode ET2.

[0108] However, the polar directions of the light-emitting elements LD1 and LD2 may be randomly determined according to a probability distribution (e.g., a Gaussian probability distribution). For example, as Figure 6 shown, the light-emitting elements LD1 and LD2 may include a first-polarity-direction light-emitting element LD1 and a second-polarity-direction light-emitting element LD2.

[0109] The first-polarity-direction light-emitting element LD1 may be a light-emitting element connected in the forward direction. For example, the anode electrode AE of the first-polarity-direction light-emitting element LD1 may be electrically connected to the first electrode ET1, and its cathode electrode CE may be electrically connected to the second electrode ET2. Figure 6 It is shown that the anode electrodes AE and the cathode electrodes CE of the light-emitting elements LD1 and LD2 may be in direct contact with the first electrode ET1 and the second electrode ET2, but the present invention is not limited thereto. The anode electrodes AE and the cathode electrodes CE and the first electrode ET1 and the second electrode ET2 may also be connected through another conductive layer or conductive material.

[0110] The light-emitting element LD2 in the second polar direction may be a light-emitting element connected in the opposite direction. For example, the anode electrode AE of the second polar direction light-emitting element LD2 may be electrically connected to the second electrode ET2, and its cathode electrode CE may be electrically connected to the first electrode ET1. Therefore, the second polar direction light-emitting element LD2 may not emit light.

[0111] The light-emitting elements LD1 and LD2 may be randomly aligned, and for each pixel PXL, the ratio of the first polar direction light-emitting element LD1 and the second polar direction light-emitting element LD2 may be different. For example, as Figure 6 shown, four first polar direction light-emitting elements LD1 and five second polar direction light-emitting elements LD2 may be provided in the pixel PXL. The light-emitting elements LD1 and LD2 may be provided in other pixels PXL in different ratios or numbers. Such alignment deviation may cause brightness deviation of the display device 1000. For example, in the case where only the second polar direction light-emitting element LD2 is included in one pixel PXL, this pixel PXL may not emit light and may be regarded as a dark spot.

[0112] Since the ratio of the second polar direction light-emitting element LD2 in the pixel PXL may increase, the drain voltage of the driving transistor of the pixel PXL may increase, and thus, the driving transistor may be driven in the linear region. Therefore, the brightness may be reduced.

[0113] To solve the problem that the driving transistor may be driven in the linear region, a large voltage difference may be applied between the voltage of the first power supply VDD (see Figure 1 ) and the voltage of the second power supply VSS (see Figure 1 ). For example, the voltage difference may be set to about 80V or more. Regardless of the number or ratio of the second polar direction light-emitting elements LD2, the probability that the driving transistor is driven in the saturation region may be increased. However, due to the very large voltage difference between the voltage of the first power supply VDD and the voltage of the second power supply VSS, the power consumption and heat generation may increase.

[0114] To solve these problems, in the pixel according to an embodiment (see Figure 1 "PXL" in), the circuit configuration that can be connected to the first electrode ET1 and the second electrode ET2 may be different and may be determined according to the polar ratio of the light-emitting elements LD1 and LD2.

[0115] Figure 7 is a schematic diagram showing a pixel according to an embodiment.

[0116] Refer to Figure 1 and Figure 7, the pixel PXL may include a first electrode ET1, a second electrode ET2, light-emitting elements LD1 and LD2, a first pixel circuit PXC1, a first selection circuit SC1, a second pixel circuit PXC2, and a second selection circuit SC2.

[0117] The light-emitting elements LD1 and LD2 may be defined as a light source unit LSU. For example, the light source unit LSU included in the pixel PXL may include the light-emitting elements LD1 and LD2. In an embodiment, the light-emitting elements LD1 and LD2 may be connected in parallel with each other, but the present invention is not limited thereto. For example, in another embodiment, the light-emitting elements LD1 and LD2 may be connected in a series-parallel hybrid structure between the first electrode ET1 and the second electrode ET2. In addition, the number and ratio of the first-polarity-direction light-emitting element LD1 and the second-polarity-direction light-emitting element LD2 included in the light source unit LSU may be determined randomly.

[0118] In an embodiment, the first pixel circuit PXC1 and the second pixel circuit PXC2 may be formed to be connected to one light source unit LSU and may have substantially the same structure. One of the first pixel circuit PXC1 and the second pixel circuit PXC2 may be electrically connected to the light source unit LSU.

[0119] The first power supply VDD and the second power supply VSS may have different electric potentials such that the light-emitting element LD (see Figures 2A to 4B , in Figure 7 's embodiment, for the light-emitting elements LD1 and LD2) emits light. In an example, the first power supply VDD may be set as a high-potential power supply, and the second power supply VSS may be set as a low-potential power supply. During the light-emitting period of the pixel PXL, the potential difference between the first power supply VDD and the second power supply VSS may be set to be greater than or equal to the threshold voltage of the light-emitting element LD.

[0120] The first pixel circuit PXC1 and the second pixel circuit PXC2 of the pixel PXL may be connected to a scan line SL and a data line DL (see Figure 1 ). In an example, when the pixel PXL is disposed in the i-th row and the j-th column (where i and j may be natural numbers), the first pixel circuit PXC1 and the second pixel circuit PXC2 may be connected to the i-th scan line SLi and the j-th data line DLj.

[0121] According to an embodiment, the first pixel circuit PXC1 may include a first transistor T1, a second transistor T2, and a storage capacitor Cst.

[0122] The first transistor T1 (also referred to as the "driving transistor") may be connected between the first power supply VDD and the light source section LSU. The gate electrode of the first transistor T1 may be connected to the first pixel node PN1. The first transistor T1 may control the driving current supplied to the light source section LSU in response to the voltage of the first pixel node PN1.

[0123] In an embodiment, one electrode (e.g., the source electrode) of the first transistor T1 may be connected to the first selection circuit SC1.

[0124] The second transistor T2 (also referred to as the "switching transistor") may be connected between the j-th data line DLj and the first pixel node PN1. The gate electrode of the second transistor T2 may be connected to the i-th scan line SLi. When the scan signal can be supplied, the second transistor T2 may be turned on to electrically connect the j-th data line DLj and the first pixel node PN1.

[0125] The storage capacitor Cst may be charged with a voltage corresponding to the data signal. One electrode of the storage capacitor Cst may be connected to the first power supply VDD, and its other electrode may be connected to the first pixel node PN1. The storage capacitor Cst may be charged with a voltage corresponding to the data signal supplied to the first pixel node PN1 during each frame period.

[0126] In an embodiment, the second pixel circuit PXC2 may include a first transistor T1' and a second transistor T2' and a storage capacitor Cst'. The configuration of the second pixel circuit PXC2 may be substantially the same as the configuration of the first pixel circuit PXC1. Therefore, redundant descriptions are omitted.

[0127] The first selection circuit SC1 of the pixel PXL may be connected to the control line CL and the first selection signal line SEL1 (see Figure 1 ). In an example, the first selection circuit SC1 of the pixel PXL in the i-th row and the j-th column may be connected to the i-th control line CLi and the j-th first selection signal line SEL1j.

[0128] The second selection circuit SC2 of the pixel PXL may be connected to the control line CL and the second selection signal line SEL2 (see Figure 1 ). In an example, the second selection circuit SC2 of the pixel PXL in the i-th row and the j-th column may be connected to the i-th control line CLi and the j-th second selection signal line SEL2j.

[0129] The first selection circuit SC1 may control the electrical connection between the first pixel circuit PXC1 and the first electrode ET1 and the electrical connection between the second power supply VSS and the second electrode ET2 based on the first selection signal.

[0130] In an embodiment, the first selection circuit SC1 may include a first selection transistor ST1, a second selection transistor ST2, a third selection transistor ST3, and a storage element ME1. The first selection circuit SC1 may be formed together with the first pixel circuit PXC1 under a light source portion LSU of a display region (e.g., Figure 5 "DA" in

[0131] The first selection transistor ST1 may be connected between the first pixel circuit PXC1 and the first electrode ET1. A gate electrode of the first selection transistor ST1 may be connected to the first node N1. The first selection transistor ST1 may electrically connect the first transistor T1 and the first electrode ET1 in response to a voltage applied to its gate electrode.

[0132] The second selection transistor ST2 may be connected between the second electrode ET2 and the second power supply VSS. A gate electrode of the second selection transistor ST2 may be connected to the first node N1. The second selection transistor ST2 may electrically connect the second electrode ET2 and the second power supply VSS in response to a voltage applied to its gate electrode.

[0133] The third selection transistor ST3 may be connected between the j-th first selection signal line SEL1j and the second node N2. A gate electrode of the third selection transistor ST3 may be connected to the i-th control line CLi for supplying a control signal. In a case where a control signal having a gate turn-on voltage is supplied to the i-th control line CLi, the third selection transistor ST3 may be turned on to transmit a first selection signal of the j-th first selection signal line SEL1j to the second node N2 (i.e., the storage element ME1).

[0134] The storage element ME1 may be connected between the first node N1 and the second node N2. In an embodiment, the storage element ME1 may include a first inverter IV1 and a second inverter IV2, which may be connected in a feedback manner to each other between the first node N1 and the second node N2. As Figure 7 shown, for example, the first inverter IV1 and the second inverter IV2 are connected to each other such that an output of the first inverter IV1 is input to the second inverter IV2, and an output of the second inverter IV2 is input to the first inverter IV1.

[0135] The first inverter IV1 can be driven by being connected to the high power supply VGH and the low power supply VGL, and can invert the signal of the second node N2 to supply the inverted signal to the first node N1. The second inverter IV2 can be driven by being connected to the high power supply VGH and the low power supply VGL, and can invert the signal of the first node N1 to supply the inverted signal to the second node N2. Thus, when the third selection transistor ST3 is turned on and a logic low voltage is supplied to the second node N2, a logic high voltage can be supplied to the first node N1. When the third selection transistor ST3 is turned on and a logic high voltage is supplied to the second node N2, a logic low voltage can be supplied to the first node N1.

[0136] In an embodiment, the configurations of the first inverter IV1 and the second inverter IV2 can perform a memory function. Thus, due to the mutual feedback between the first inverter IV1 and the second inverter IV2, the inverted signal of the first selection signal supplied to the second node N2 can be continuously supplied to the first node N1. The voltage level of the inverted signal of the first selection signal can be maintained at the first node N1 until the supply of the voltages of the high power supply VGH and the low power supply VGL can be cut off.

[0137] For example, when a first selection signal having a logic high level is supplied to the second node N2, a logic low voltage can be supplied to the gate electrodes of the first selection transistor ST1 and the second selection transistor ST2. Thus, the first pixel circuit PXC1 can be connected to the first electrode ET1, and the second power supply VSS can be connected to the second electrode ET2. Thus, the first-polarity-direction light-emitting element LD1 can emit light normally.

[0138] For example, when the first pixel circuit PXC1 is selected by the first selection circuit SC1, the light source part LSU can emit light through the drive current generated by the first pixel circuit PXC1.

[0139] The second selection circuit SC2 can control the electrical connection between the second pixel circuit PXC2 and the second electrode ET2 and the electrical connection between the second power supply VSS and the first electrode ET1.

[0140] Similar to the first selection circuit SC1, the second selection circuit SC2 can include a first selection transistor ST1’, a second selection transistor ST2’, a third selection transistor ST3’ and a storage element ME2.

[0141] The first selection transistor ST1’ can be connected between the second pixel circuit PXC2 and the second electrode ET2. The gate electrode of the first selection transistor ST1’ can be connected to the third node N3. The first selection transistor ST1’ can electrically connect the first transistor T1’ and the second electrode ET2 in response to the voltage applied to its gate electrode.

[0142] The second selection transistor ST2' may be connected between the first electrode ET1 and the second power supply VSS. The gate electrode of the second selection transistor ST2' may be connected to the third node N3. The second selection transistor ST2' may electrically connect the first electrode ET1 and the second power supply VSS in response to a voltage applied to its gate electrode.

[0143] The third selection transistor ST3' may be connected between the j-th second selection signal line SEL2j and the fourth node N4. The gate electrode of the third selection transistor ST3' may be connected to the i-th control line CLi for supplying a control signal. When a control signal having a gate turn-on voltage is supplied to the i-th control line CLi, the third selection transistor ST3' may turn on to transmit the second selection signal of the j-th second selection signal line SEL2j to the fourth node N4 (i.e., the storage element ME2).

[0144] The storage element ME2 may be connected between the third node N3 and the fourth node N4. In an embodiment, the storage element ME2 may include a first inverter IV1' and a second inverter IV2', which may be connected in mutual feedback between the third node N3 and the fourth node N4.

[0145] Since the configurations and operation methods of the second selection circuit SC2 and the first selection circuit SC1 may be substantially the same, redundant descriptions thereof will be omitted.

[0146] According to an embodiment, when a second selection signal having a logic high level is supplied to the fourth node N4, a logic low level voltage may be supplied to the gate electrodes of the first selection transistor ST1' and the second selection transistor ST2'. Accordingly, the second pixel circuit PXC2 may be connected to the second electrode ET2, and the second power supply VSS may be connected to the first electrode ET1.

[0147] For example, the voltages applied to the first electrode ET1 and the second electrode ET2 may be changed. Accordingly, the second polarity direction light emitting element LD2 may emit light normally.

[0148] For example, when the second pixel circuit PXC2 is selected by the second selection circuit SC2, the light source unit LSU may emit light through the drive current generated by the second pixel circuit PXC2.

[0149] The first selection circuit SC1 and the second selection circuit SC2 can operate complementarily. For example, when a logic low voltage is supplied to the first node N1, a logic high voltage can be supplied to the third node N3. When a logic high voltage can be supplied to the first node N1, a logic low voltage can be supplied to the third node N3. Therefore, when the first pixel circuit PXC1 is electrically connected to the light source unit LSU, the second pixel circuit PXC2 may not be used. Conversely, when the second pixel circuit PXC2 is electrically connected to the light source unit LSU, the first pixel circuit PXC1 may not be used.

[0150] Figure 7 All transistors are shown as PMOS transistors in the figure, but the present invention is not limited thereto. At least some of the transistors may be replaced by NMOS transistors.

[0151] Figure 8 is a schematic graphical view of signal waveforms for explaining the operation of a pixel (e.g., Figure 7 the pixel) according to an embodiment.

[0152] Referring to Figure 7 and Figure 8 , the pixel PXL provided in the i-th row and the j-th column may be connected to the i-th scan line SLi, the i-th control line CLi, the j-th data line DLj, the j-th first selection signal line SEL1j, and the j-th second selection signal line SEL2j.

[0153] In an embodiment, Figure 8 the timing diagram corresponds to a case where the number of light emitting elements LD1 in the first polarity direction included in the light source unit LSU may be greater than the number of light emitting elements LD2 in the second polarity direction. Therefore, the first selection signal that can be supplied to the pixel PXL has a logic high level H and the second selection signal has a logic low level L.

[0154] However, this is merely an example, and when the first pixel circuit PXC1 is selected, the first selection signal may have a gate cutoff level for turning off the first selection transistor ST1. For example, when the first selection transistor ST1 is an NMOS transistor, the first selection signal may have a logic low level.

[0155] In an embodiment, the scan signal and the control signal may be supplied to the pixel PXL at substantially the same timing. However, this is merely an example, and the timing for supplying the scan signal and the control signal is not limited thereto.

[0156] The data signal Di corresponding to the above pixel PXL can be supplied in synchronization with the scan signal supplied to the i-th scan line SLi. Similarly, the data signal Di-1 corresponding to the pixel PXL in the (i-1)-th row and j-th column can be supplied in synchronization with the scan signal supplied to the (i-1)-th scan line (not shown), and the data signal Di+1 corresponding to the pixel PXL in the (i+1)-th row and j-th column can be supplied in synchronization with the scan signal supplied to the (i+1)-th scan line (not shown).

[0157] When the scan signal can be supplied to the i-th scan line SLi, the second transistor T2 of the first pixel circuit PXC1 and the second transistor T2' of the second pixel circuit PXC2 can be turned on, and the data signal Di can be supplied to each of the first pixel circuit PXC1 and the second pixel circuit PXC2.

[0158] When the control signal can be supplied to the i-th control line CLi, the third selection transistor ST3 of the first selection circuit SC1 and the third selection transistor ST3' of the second selection circuit SC2 can be turned on. The first selection signal having a logic high level H can be supplied to the second node N2, and the second selection signal having a logic low level L can be supplied to the fourth node N4.

[0159] The logic low level L can be supplied to the first node N1 through the operation of the storage element ME1, and the first selection transistor ST1 and the second selection transistor ST2 of the first selection circuit SC1 can be turned on. Thus, the first pixel circuit PXC1 can be connected to the first electrode ET1, and the second power supply VSS can be connected to the second electrode ET2. At the same time, the logic high level H can be supplied to the third node N3 through the operation of the storage element ME2, and the first selection transistor ST1' and the second selection transistor ST2' of the second selection circuit SC2 can be turned off. Thus, the second pixel circuit PXC2 and the light source unit LSU can be disconnected from each other, and the second power supply VSS and the first electrode ET1 can also be disconnected from each other.

[0160] Therefore, by driving the first pixel circuit PXC1 according to Figure 8 the waveform diagram, the pixel PXL can emit light.

[0161] Conversely, in the case where the first selection signal and the second selection signal are supplied conversely to Figure 8 that, by driving the second pixel circuit PXC2, the pixel PXL can emit light.

[0162] Figure 9 is a schematic circuit diagram showing a storage element according to an embodiment (for example, a storage element included in the pixel of Figure 7 ).

[0163] Refer toFigure 7 and Figure 9 ,the storage element ME1 may include a first inverter IV1 and a second inverter IV2 that can be connected in a feedback manner to each other.

[0164] In an embodiment, the storage element ME1 included in the first selection circuit SC1 may be disposed between the first node N1 and the third selection transistor ST3, and may determine the voltage of the first node N1 in response to the first selection signal SE1.

[0165] The first inverter IV1 may include a first inverter transistor IT1 and a second inverter transistor IT2 of different types. The first inverter transistor IT1 may be an NMOS transistor and the second inverter transistor IT2 may be a PMOS transistor.

[0166] The first inverter transistor IT1 may be connected between the first node N1 and the low power supply VGL. The gate electrode of the first inverter transistor IT1 may be connected to the second node N2. When the first inverter transistor IT1 can be turned on, the voltage of the low power supply VGL may be supplied to the first node N1.

[0167] The second inverter transistor IT2 may be connected between the first node N1 and the high power supply VGH. The gate electrode of the second inverter transistor IT2 may be connected to the second node N2. When the second inverter transistor IT2 can be turned on, the voltage of the high power supply VGH may be supplied to the first node N1.

[0168] The second inverter IV2 may include a third inverter transistor IT3 and a fourth inverter transistor IT4 of different types. The third inverter transistor IT3 may be an NMOS transistor and the fourth inverter transistor IT4 may be a PMOS transistor.

[0169] The third inverter transistor IT3 may be connected between the first node N1 and the low power supply VGL. The gate electrode of the third inverter transistor IT3 may be connected to the first node N1. When the third inverter transistor IT3 can be turned on, the voltage of the low power supply VGL may be supplied to the second node N2.

[0170] The fourth inverter transistor IT4 may be connected between the second node N2 and the high power supply VGH. The gate electrode of the fourth inverter transistor IT4 may be connected to the first node N1. When the fourth inverter transistor IT4 can be turned on, the voltage of the high power supply VGH may be supplied to the second node N2.

[0171] The storage element ME1 may store the first selection signal SE1 supplied in response to the control signal. The voltage level corresponding to the inverted signal of the first selection signal SE1 may be continuously supplied to the first node N1. The storage element ME1 may operate until the supply of power from the high power supply VGH and the low power supply VGL is cut off.

[0172] Figure 10A is a schematic graphical view of a signal waveform for explaining the operation of a display device (e.g., a display device including Figure 7 pixels of Figure 1 ). Figure 10B is a schematic diagram showing the connection relationship of pixels (e.g., some pixels corresponding to the signal waveform of Figure 10A ) according to an embodiment. Referring to Figure 1 , Figure 7 , Figure 8 , Figure 10A and Figure 10B , during a period (or frame period 1F), scan signals may be sequentially supplied to scan lines SL1 to SLn, where n may be a natural number greater than one.

[0173] In an embodiment, during a preparation period P1 corresponding to one frame period 1F, control signals may be sequentially supplied to control lines CL1 to CLn. According to an embodiment, the control signals may be supplied synchronously with the scan signals. The control signals and the scan signals may be output from the same scan driver (see Figure 1 "200" of

[0174] ), for example, output from the same-stage circuit included in the scan driver. Figure 1 In an embodiment, the preparation period P1 may include a wake-up period after the display device (see

[0175] "1000" of

[0176] Figure 10A Figure 1 Figure 7

[0177] Figure 7 "LD1" and "LD2" of

[0177] For example, during the manufacturing process of a display device, an inspection process for checking the number or ratio of light-emitting elements LD1 in the first polarization direction and light-emitting elements LD2 in the second polarization direction in each light source section LSU can be performed. The inspection process can be carried out by an optical imaging method, an image analysis method, or the like.

[0178] In a pixel PXL, when the number of light-emitting elements LD1 in the first polarization direction is greater than or equal to the number of light-emitting elements LD2 in the second polarization direction, the corresponding first selection signal can have a logic high level. The second selection signal can be the inverted signal of the first selection signal and can have a logic low level. Therefore, the pixel PXL can be driven by the first pixel circuit PXC1. The second pixel circuit PXC2 may not be electrically connected to the light-emitting element.

[0179] Conversely, when the number of light-emitting elements LD1 in the first polarization direction is less than the number of light-emitting elements LD2 in the second polarization direction, the corresponding first selection signal can have a logic low level. The second selection signal can be the inverted signal of the first selection signal and can have a logic high level. Therefore, the pixel PXL can be driven by the second pixel circuit PXC2. The first pixel circuit PXC1 may not be electrically connected to the light-emitting element.

[0180] For example, as Figure 10B shown, the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 can have light-emitting elements with different arrangement ratios. The first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 can be respectively connected to the first scan line SL1, the second scan line SL2, and the third scan line SL3.

[0181] The first pixel PXL1 may mainly include light-emitting elements LD2 in the second polarization direction. For example, the first pixel PXL1 can include two light-emitting elements LD1 in the first polarization direction and three light-emitting elements LD2 in the second polarization direction. During the first time t1, by overlapping the control signal supplied to the first control line CL1 with the scan signal supplied to the first scan line SL1, a first selection signal with a logic low level and a second selection signal with a logic high level can be supplied. Therefore, the second electrode ET2 can be connected to the second pixel circuit PXC2, and the first electrode ET1 can be connected to the second power supply VSS.

[0182] The second pixel PXL2 may include three light-emitting elements LD1 in a first polarization direction and two light-emitting elements LD2 in a second polarization direction. During a second time t2, by overlapping a control signal supplied to a second control line CL2 with a scan signal supplied to a second scan line SL2, a first selection signal having a logic high level and a second selection signal having a logic low level may be supplied. Accordingly, a first electrode ET1 may be connected to a first pixel circuit PXC1, and a second electrode ET2 may be connected to a second power supply VSS.

[0183] The third pixel PXL3 may include one light-emitting element LD1 in a first polarization direction and four light-emitting elements LD2 in a second polarization direction. During a third time t3, by overlapping a control signal supplied to a third control line CL3 with a scan signal supplied to a third scan line SL3, a first selection signal having a logic low level and a second selection signal having a logic high level may be supplied. Accordingly, a second electrode ET2 may be connected to a second pixel circuit PXC2, and a first electrode ET1 may be connected to a second power supply VSS.

[0184] During a frame period 1F, such pixel circuit selection driving may be sequentially performed in a pixel row portion. Thereafter, a control signal at an end of a preparation period P1 may be maintained at a logic high level (or a gate cutoff level). Accordingly, a third selection transistor ST3 and a third selection transistor ST3' may be in an off state, and a connection relationship of pixel circuits PXC1 and PXC2 may be maintained by storage elements ME1 and ME2. For example, driving of the pixel circuit PXC1 or PXC2 selected by the storage elements ME1 and ME2 once may be continuously maintained.

[0185] In Figure 10A and Figure 10B it has been described that the first selection signal and the second selection signal are determined according to the numbers of the light-emitting elements LD1 in the first polarization direction and the light-emitting elements LD2 in the second polarization direction, but the present invention is not limited thereto.

[0186] In an embodiment, when a ratio of a number of light-emitting elements LD1 in a first polarization direction included in a first pixel PXL1 to a number of light-emitting elements LD2 in a second polarization direction is greater than or equal to a reference ratio, a first pixel circuit PXC1 may be electrically connected to the light-emitting elements LD1 and LD2 of the first pixel PXL1. For example, the reference ratio may be determined as 2:1, 3:1, etc. Conversely, when the ratio of the number of light-emitting elements LD1 in the first polarization direction included in the first pixel PXL1 to the number of light-emitting elements LD2 in the second polarization direction is less than the reference ratio, a second pixel circuit PXC2 may be electrically connected to the light-emitting elements LD1 and LD2 of the first pixel PXL1.

[0187] As described above, in the pixel PXL and the display device 1000 including the pixel PXL according to the embodiment, the circuits to which the first electrode ET1 and the second electrode ET2 can be selectively connected and the power supplies VDD and VSS can be determined to be opposite to each other according to the ratio of the arrangement directions of the light-emitting elements LD (see Figures 2A to 4B , and in the Figure 10A and Figure 10B embodiment, for the light-emitting elements LD1 and LD2). Accordingly, the voltage difference between the first power supply VDD and the second power supply VSS can be reduced to reduce power consumption, and the luminance deviation and image blurring caused by randomly aligned light-emitting elements LD can be reduced.

[0188] Figure 10C FIG. is a schematic block diagram showing a scan driver according to an embodiment (e.g., a scan driver included in the Figure 1 display device).

[0189] Referring to Figure 1 , Figure 10A and Figure 10C , the scan driver 200 may include a first scan driver 220 and a second scan driver 240.

[0190] In an embodiment, in a case where all scan signals and control signals are supplied to the pixels (e.g., Figure 1 "PXL" in

[0191] one frame period 1F), the scan signals and the control signals may be generated and output from different scan drivers, respectively.

[0192] The first scan driver 220 may supply (e.g., sequentially supply) scan signals to the scan lines SL in response to a first control signal SCS.

[0193] The second scan driver 240 may supply (e.g., sequentially supply) control signals to the control lines CL in response to a second control signal CCS.

[0194] Since the second scan driver 240 may operate separately from the first scan driver 220, the supply of the control signals may not be affected by the scan signals. Accordingly, the supply timing, supply period, etc. of the control signals can be freely set according to the display device 1000. Figure 1After the “1000” in [the figure] is turned on until it is turned off, after one scan is performed, the control signal may not be supplied. The second scan driver 240 may perform one scan to supply (or sequentially supply) the control signal to the control line CL during the period of driving the display device, and then stop supplying the control signal. Accordingly, the first selection signal and the second selection signal may also be supplied only during the preparation period P1.

[0195] Figure 11 is a schematic graphical view of signal waveforms for explaining the operation of a display device (e.g., a display device including Figure 7 pixels of Figure 1 ) according to an embodiment.

[0196] Since, except for the period during which the control signal can be supplied, Figure 11 the operation of [the device] can be the same as the operation of Figure 10A the display device of [the other device], the same reference numerals will be used to denote the same or corresponding components, and redundant descriptions will be omitted.

[0197] Referring to Figure 1 , Figure 7 and Figure 11 , during the preparation period P1 (where n may be a natural number greater than one), the control signal may be supplied (e.g., sequentially supplied) to the control lines CL1 to CLn, and during the display period P2, the scan signal may be supplied (e.g., sequentially supplied) to the scan lines SL1 to SLn.

[0198] During the preparation period P1, the scan signal may not be supplied to the display section 100. During the preparation period P1, in response to the first selection signal and the second selection signal supplied to the selection circuits SC1 and SC2 through the control signal, the first pixel circuit PXC1 or the second pixel circuit PXC2 may be selected for each pixel PXL. The power supply or circuit connected to the first electrode ET1 and the second electrode ET2 may be determined for each pixel PXL.

[0199] Thereafter, during the display period P2, all of the control signal, the first selection signal, and the second selection signal may be invalidated, and the driving of the components that generate these signals may also be invalidated. During the display period P2, the scan signal may be supplied (e.g., sequentially supplied), and an image may be displayed.

[0200] Figure 12 is a schematic view showing a pixel (e.g., Figure 7 pixels of Figure 13 is for explaining a display device (e.g., including Figure 12 pixels of Figure 1A schematic graphical view of a signal waveform of an operation of a display device).

[0201] Since, in addition to the configuration of the storage element, Figure 12 the pixels of can be the same as the pixels of Figure 7 the same or corresponding components will be denoted by the same reference numerals, and redundant descriptions will be omitted.

[0202] Referring to Figure 1 、 Figure 12 and Figure 13 the pixel PXL may include a first electrode ET1, a second electrode ET2, light-emitting elements LD1 and LD2, a first pixel circuit PXC1, a first selection circuit SC1’, a second pixel circuit PXC2, and a second selection circuit SC2’.

[0203] The first selection circuit SC1’ may control the electrical connection between the first pixel circuit PXC1 and the first electrode ET1 and the electrical connection between the second power supply VSS and the second electrode ET2 based on a first selection signal.

[0204] In an embodiment, the first selection circuit SC1’ may include a first selection transistor ST1, a second selection transistor ST2, a third selection transistor ST3, and a capacitor C1 corresponding to the storage element.

[0205] The capacitor C1 may be connected between a first node N1 and a third power supply VGL’. The third power supply VGL’ may be a constant voltage power supply or a ground power supply.

[0206] In an embodiment, the gate electrode of the third selection transistor ST3 may be connected to the i-th scan line SLi. For example, the gate electrode of the second transistor T2 and the gate electrode of the third selection transistor ST3 may be commonly connected to the i-th scan line SLi and may receive a scan signal simultaneously.

[0207] Accordingly, the third selection transistor ST3 may be turned on within each frame, and the voltage of the first selection signal supplied to the j-th first selection signal line SEL1j may be stored in the capacitor C1.

[0208] For example, in the case where the first pixel circuit PXC1 is to be selected, the first selection signal may have a logic low level. The logic low level voltage may be stored in the capacitor C1, and the first selection transistor ST1 and the second selection transistor ST2 may be maintained in an on state during a frame period 1F by the voltage stored in the capacitor C1.

[0209] In contrast, in the case where the second pixel circuit PXC2 is to be selected, the first selection signal may have a logic high level. The logic high level voltage may be stored in the capacitor C1, and the first selection transistor ST1 and the second selection transistor ST2 may be maintained in an off state during the frame period 1F by the voltage stored in the capacitor C1.

[0210] Similar to the first selection circuit SC1’, the second selection circuit SC2’ may also include a capacitor C1’ that stores the voltage of the second selection signal supplied to the j-th second selection signal line SEL2j.

[0211] Therefore, within each frame period 1F, one of the first pixel circuit PXC1 and the second pixel circuit PXC2 may be selected in response to the supply of the scan signal to display an image. Thus, components and control lines for generating separate control signals may be removed. However, as Figure 13 shown, within each frame period 1F, the first selection signal and the second selection signal may be supplied to select the pixel circuit.

[0212] As described above, since the storage elements are implemented only by the capacitors C1 and C1’, the pixel structure and wiring in the display area (see “DA” in Figure 5 ) may be further simplified.

[0213] Figure 14 is a schematic circuit diagram showing a pixel circuit according to an embodiment (e.g., the pixel circuit included in the pixel of Figure 7 ). Figure 15 is a schematic graphical view of signal waveforms for explaining the operation of a pixel according to an embodiment (e.g., the pixel of Figure 14 ).

[0214] Figure 14 An example of the first pixel circuit is shown. However, the second pixel circuit may also have a configuration that is substantially the same as the configuration of the first pixel circuit.

[0215] Referring to Figure 7 , Figure 14 and Figure 15, the first pixel circuit PXC1-1 may also be connected to at least one scan line other than the i-th scan line SLi of the corresponding horizontal line. In an example, the first pixel circuit PXC1-1 of the pixel PXL set in the i-th row may also be connected to the (i-1)-th scan line SLi-1 and / or the (i+1)-th scan line SLi+1. According to an embodiment, in addition to the first power supply VDD and the second power supply VSS, the first pixel circuit PXC1-1 may also be connected to a third power supply. For example, the first pixel circuit PXC1-1 may also be connected to the initialization power supply Vint. According to an embodiment, the first pixel circuit PXC1-1 may include a first transistor T1 to a seventh transistor T7 and a storage capacitor Cst.

[0216] The first transistor T1 may be electrically connected between the first power supply VDD and Figure 7 the light source part LSU. For example, one electrode (e.g., the source electrode) of the first transistor T1 may be connected to the first power supply VDD through the fifth transistor T5, and the other electrode (e.g., the drain electrode) of the first transistor T1 may be connected to one electrode (e.g., the first electrode of the corresponding pixel PXL) of the light source part LSU through the sixth transistor T6 and the first selection circuit (see Figure 7 "SC1", e.g., the first selection transistor ST1). The gate electrode of the first transistor T1 may be connected to the first pixel node PN1.

[0217] The second transistor T2 may be connected between the j-th data line DLj and one electrode of the first transistor T1. The gate electrode of the second transistor T2 may be connected to the i-th scan line SLi. When the scan signal can be supplied from the i-th scan line SLi, the second transistor T2 may be turned on to electrically connect the j-th data line DLj to one electrode of the first transistor T1.

[0218] The third transistor T3 may be connected between the other electrode of the first transistor T1 and the first pixel node PN1. The gate electrode of the third transistor T3 may be connected to the i-th scan line SLi. When the scan signal can be supplied from the i-th scan line SLi, the third transistor T3 may be turned on to connect the first transistor T1 in the form of a diode.

[0219] The fourth transistor T4 may be connected between the first pixel node PN1 and the initialization power supply Vint. The gate electrode of the fourth transistor T4 may be connected to a scan line, for example, the (i-1)th scan line SLi-1. When a scan signal can be supplied from the (i-1)th scan line SLi-1, the fourth transistor T4 may be turned on to transfer the voltage of the initialization power supply Vint to the first pixel node PN1. According to an embodiment, when the first transistor T1 is a p-type transistor, the voltage of the initialization power supply Vint for initializing the gate voltage of the first transistor T1 may be less than or equal to the lowest voltage of the data signal.

[0220] The fifth transistor T5 may be connected between the first power supply VDD and the first transistor T1. The gate electrode of the fifth transistor T5 may be connected to a corresponding emission control line, for example, the ith emission control line ELi.

[0221] The sixth transistor T6 may be connected between the first transistor T1 and the second pixel node PN2. The gate electrode of the sixth transistor T6 may be connected to the ith emission control line ELi.

[0222] The seventh transistor T7 may be connected between the second pixel node PN2 and the initialization power supply Vint. The gate electrode of the seventh transistor T7 may be connected to any one of the subsequent scan lines, for example, the (i+1)th scan line SLi+1. The seventh transistor T7 may be turned on to transfer the voltage of the initialization power supply Vint to one electrode of the light source unit LSU. Thus, during each initialization period while the voltage of the initialization power supply Vint can be transferred to the light source unit LSU, the voltage of one electrode of the light source unit LSU may be initialized. The control signal for controlling the operation of the seventh transistor T7 may be changed differently. For example, in another embodiment, the gate electrode of the seventh transistor T7 may also be connected to the scan line of the corresponding horizontal line, that is, the ith scan line SLi.

[0223] The storage capacitor Cst may be connected to the first power supply VDD and the first pixel node PN1. The storage capacitor Cst may store a voltage corresponding to the data signal and the threshold voltage of the first transistor T1 during each frame period 1F.

[0224] In an embodiment, as Figure 15 shown, the control signals supplied to the selection circuits SC1 and SC2 of the pixel PXL through the ith control line CLi may be synchronized with the scan signal supplied to the ith scan line SLi and may be supplied. However, this is only an example, and the timing for supplying the control signals is not limited thereto.

[0225] The transistors included in the first pixel circuit PXC1-1, such as the first transistor T1 to the seventh transistor T7, are in Figure 14All are shown as p-type transistors, but the present invention is not limited thereto. For example, at least one of the first transistor T1 to the seventh transistor T7 may be changed to an n-type transistor.

[0226] Some of the first transistor T1 to the seventh transistor T7 may be LTPS transistors including a low-temperature polysilicon (LTPS) active layer based on polysilicon, and the rest may be oxide semiconductor transistors including an oxide semiconductor active layer.

[0227] Figure 16 is a schematic circuit diagram showing a pixel circuit according to an embodiment (e.g., a pixel circuit included in a pixel of Figure 7 .

[0228] Since the pixel circuit of Figure 16 may be the same as the pixel circuit of Figure 7 except for the type of transistor and the configuration of the third transistor, the same or corresponding components will be denoted by the same reference numerals, and redundant descriptions will be omitted.

[0229] Referring to Figure 7 and Figure 16 , Figure 16 the pixel circuit PXC1-2 of

[0230] may include a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor Cst.

[0231] The third transistor T3 may be connected between the readout line RLj and an electrode of the first transistor T1 (e.g., the second pixel node PN2). The gate electrode of the third transistor T3 may be connected to the sense line SSLi. The third transistor T3 may transmit a sense current to the readout line RLj in response to a sense signal transmitted through the sense line SSLi. The sense current may be used to calculate the change amounts of the mobility and threshold voltage of the first transistor T1. A plurality of pieces of information regarding the mobility and threshold voltage may be calculated based on the relationship between the sense current and the sense voltage. In an embodiment including a light source portion LSU including light-emitting elements LD1 and LD2, the sense current may be converted into a voltage form and may be used for an operation of compensating a data voltage.

[0232] The storage capacitor Cst may be connected between the first pixel node PN1 and the second pixel node PN2. The storage capacitor Cst may store the voltage of the first pixel node PN1.

[0233] The transistors T1, T2, and T3 are shown as NMOS transistors in Figure 16 , but the present invention is not limited thereto. At least some of the transistors may be replaced with PMOS transistors.

[0234] As described above, pixel circuits having various structures can be applied to pixels including a selection circuit.

[0235] As described above, in a pixel and a display device including the pixel according to an embodiment, a circuit to which a first electrode and a second electrode can be selectively connected and a first power supply and a second power supply can be determined to be opposite to each other according to a ratio of arrangement directions of light-emitting elements. Accordingly, a voltage difference between the first power supply and the second power supply can be reduced to reduce power consumption, and luminance deviation and image blurring due to randomly aligned light-emitting elements can be reduced.

[0236] In a pixel and a display device according to an embodiment, a circuit and a power supply to which a first electrode and a second electrode can be selectively connected can be determined to be opposite to each other according to a ratio of arrangement directions of light-emitting elements. Accordingly, a voltage difference between the first power supply and the second power supply can be reduced to reduce power consumption, and luminance deviation and image blurring due to randomly aligned light-emitting elements can be reduced.

[0237] However, the effects of the embodiments are not limited to the above effects, but various modifications can be made without departing from the spirit and scope of the present invention.

[0238] Although the present invention has been described with reference to exemplary embodiments, those skilled in the art will understand that various modifications and variations can be made to the present invention without departing from the spirit or scope of the present invention described in the appended claims.

Claims

1. A pixel, comprising: A first electrode and a second electrode spaced apart from each other; A light-emitting element electrically connected to the first electrode and the second electrode; A first pixel circuit connected to a first power supply and generating a driving current based on a scan signal and a data signal; A first selection circuit controlling an electrical connection between the first pixel circuit and the first electrode and an electrical connection between a second power supply and the second electrode based on a first selection signal; A second pixel circuit connected to the first power supply and generating a driving current based on the scan signal and the data signal; And A second selection circuit controlling an electrical connection between the second pixel circuit and the second electrode and an electrical connection between the second power supply and the first electrode based on a second selection signal, wherein the first selection circuit includes: A first selection transistor connected between the first pixel circuit and the first electrode, the first selection transistor including a gate electrode connected to a first node; A second selection transistor connected between the second power supply and the second electrode, the second selection transistor including a gate electrode connected to the first node; A first storage element connected to the first node; and A third selection transistor connected between a first selection line for supplying the first selection signal and the first storage element, the third selection transistor including a gate electrode connected to a control line for supplying a control signal, and wherein the first storage element includes a first inverter and a second inverter connected in mutual feedback between the first node and the third selection transistor.

2. The pixel according to claim 1, wherein, The first inverter includes: A first inverter transistor connected between the first node and a low power supply, the first inverter transistor including a gate electrode connected to a second node; and A second inverter transistor connected between the first node and a high power supply, the second inverter transistor including a gate electrode connected to the second node.

3. The pixel according to claim 2, wherein, The second inverter includes: A third inverter transistor connected between the second node and the low power supply, the third inverter transistor including a gate electrode connected to the first node; and A fourth inverter transistor connected between the second node and the high power supply, the fourth inverter transistor including a gate electrode connected to the first node.

4. The pixel according to claim 1, wherein, The second selection circuit includes: A fourth selection transistor connected between the second pixel circuit and the second electrode, the fourth selection transistor including a gate electrode connected to a third node; A fifth selection transistor connected between the second power supply and the first electrode, the fifth selection transistor including a gate electrode connected to the third node; A second storage element connected to the third node; and A sixth selection transistor connected between a second selection line for supplying the second selection signal and the second storage element, the sixth selection transistor including a gate electrode connected to a control line for supplying a control signal.

5. The pixel according to claim 1, wherein, Each of the light-emitting elements is a first-polarity-direction light-emitting element or a second-polarity-direction light-emitting element, and the first-polarity-direction light-emitting element and the second-polarity-direction light-emitting element have opposite polarity directions.

6. The pixel according to claim 5, wherein, When the number of the first-polarity-direction light-emitting elements is greater than or equal to the number of the second-polarity-direction light-emitting elements, the first pixel circuit is electrically connected to the light-emitting elements in response to the first selection signal.

7. The pixel according to claim 5, wherein, When the number of the first-polarity-direction light-emitting elements is less than the number of the second-polarity-direction light-emitting elements, the second pixel circuit is electrically connected to the light-emitting elements in response to the second selection signal.

8. The pixel according to claim 5, wherein, When the ratio of the number of the first-polarity-direction light-emitting elements to the number of the second-polarity-direction light-emitting elements is greater than or equal to a reference ratio, the first pixel circuit is electrically connected to the light-emitting elements, and wherein, when the ratio of the number of the first-polarity-direction light-emitting elements to the number of the second-polarity-direction light-emitting elements is less than the reference ratio, the second pixel circuit is electrically connected to the light-emitting elements.

9. The pixel according to claim 5, wherein, When the first pixel circuit is electrically connected to the light-emitting elements, the voltage of the second power supply is supplied to the second electrode, and when the second pixel circuit is electrically connected to the light-emitting elements, the voltage of the second power supply is supplied to the first electrode.

10. The pixel according to claim 1, wherein, Each of the first pixel circuit and the second pixel circuit includes: a first transistor that controls the driving current supplied to the light-emitting element based on the voltage applied to the gate electrode of the first transistor; and a second transistor connected between the data line for supplying the data signal and the first transistor, and the second transistor includes a gate electrode connected to the scan line for supplying the scan signal.

11. A pixel, comprising: a first electrode and a second electrode spaced apart from each other; a light-emitting element electrically connected to the first electrode and the second electrode; a first pixel circuit connected to a first power supply and generating a driving current based on a scan signal and a data signal; a first selection circuit that controls the electrical connection between the first pixel circuit and the first electrode and the electrical connection between the second power supply and the second electrode based on a first selection signal; a second pixel circuit connected to the first power supply and generating a driving current based on the scan signal and the data signal; and a second selection circuit that controls the electrical connection between the second pixel circuit and the second electrode and the electrical connection between the second power supply and the first electrode based on a second selection signal, wherein the first selection circuit includes: a first selection transistor connected between the first pixel circuit and the first electrode, and the first selection transistor includes a gate electrode connected to a first node; a second selection transistor connected between the second power supply and the second electrode, and the second selection transistor includes a gate electrode connected to the first node; a first storage element connected to the first node; and A third selection transistor is connected between a first selection line for supplying the first selection signal and the first storage element. The third selection transistor includes a gate electrode connected to a control line for supplying a control signal, and wherein the first storage element includes a capacitor coupled between the first node and a third power supply.

12. The pixel according to claim 11, wherein, The control signal is the same as the scan signal.

13. A display device includes: Pixels, each including a light-emitting element electrically connected to a first electrode and a second electrode; A scan driver that supplies a scan signal to the pixels through scan lines and supplies a control signal to the pixels through a control line; A data driver that supplies a data signal to the pixels through data lines; And A selection signal driver that supplies a first selection signal to the pixels through a first selection signal line and supplies a second selection signal to the pixels through a second selection signal line, wherein each of the pixels includes: A first pixel circuit connected to a first power supply and including a first driving transistor that generates a driving current based on the scan signal and the data signal; A first selection circuit that electrically connects the first pixel circuit and the first electrode in response to the first selection signal and electrically connects a second power supply and the second electrode; A second pixel circuit connected to the first power supply and including a second driving transistor that generates a driving current based on the scan signal and the data signal; and A second selection circuit that electrically connects the second pixel circuit and the second electrode in response to the second selection signal and electrically connects the second power supply and the first electrode, wherein the first selection circuit includes: A first selection transistor connected between the first pixel circuit and the first electrode. The first selection transistor includes a gate electrode connected to a first node; A second selection transistor connected between the second power supply and the second electrode. The second selection transistor includes a gate electrode connected to the first node; A storage element connected to the first node; and A third selection transistor connected between a first selection line for supplying the first selection signal and the storage element. The third selection transistor includes a gate electrode connected to the control line, and wherein the storage element includes a first inverter and a second inverter that are connected in mutual feedback between the first node and the third selection transistor.

14. The display device according to claim 13, wherein, The scan driver performs one scan during a period when the display device is driven to supply the control signal to the control line, and then stops supplying the control signal.

15. The display device according to claim 13, wherein, The selection signal driver supplies the first selection signal and the second selection signal to each of the pixel columns through the first selection signal line and the second selection signal line in response to the control signal, and wherein the second selection signal is an inverted signal of the first selection signal.

16. The display device according to claim 13, wherein, Each of the light-emitting elements is a first-polarity-direction light-emitting element or a second-polarity-direction light-emitting element. The first-polarity-direction light-emitting element and the second-polarity-direction light-emitting element have opposite polarity directions.

17. The display device according to claim 13, wherein, The pixel includes: A first pixel, including: A first electrode, connected to the first pixel circuit; and A second electrode, connected to the second power supply; and A second pixel, comprising: A first electrode, connected to the second power supply; and A second electrode, connected to the second pixel circuit.

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