Semiconductor devices

Abstract

The present invention relates to a semiconductor device. A semiconductor device is provided that can suppress repeated introduction or leakage of continuous audio data when mixing sound data read from a memory with continuous audio data, thereby improving the sound quality of reproduced sound. A semiconductor device 200 is provided, characterized in that it has: a timing generation unit 210 that generates a synchronization signal in accordance with the input timing of continuous audio data input from the outside; a reproduction processing (decoding) unit 120 that reads sound data from a memory 140 based on the synchronization signal to perform sound reproduction processing and output multiple channel information; and a mixing unit 130 that mixes the multiple channel information with the continuous audio data to generate a sound signal.

Description

Technical Field

[0001] The present invention relates to mixing continuous audio input data input from the outside such as I2S (Inter-IC Sound) in a semiconductor device that reads and reproduces audio data from a memory built into an LSI (Large Scale Integration) or a memory outside the LSI. Background Art

[0002] Figure 1 FIG. 1 is a diagram showing a configuration example of a semiconductor device 100 that outputs a sound signal. Figure 1 As shown in FIG. 1 , the timing generating unit 110, the reproduction processing (decoding) unit 120, the mixing unit 130, and the memory 140 are configured. The timing generating unit 110 uses the basic clock inside the semiconductor device 100 to operate the counter to generate a sampling cycle. For example, the timing generating unit 110 is as follows: Figure 2 As shown in FIG. 1 , an arbitrary counter expiration value n is set to count the basic clock, and a counter coincidence signal is outputted by the rise of the nth basic clock, thereby generating a signal (fssync signal) synchronized with its cycle. Figure 3 As shown, the timing generation unit 110 generates an fssync signal (1), the reproduction processing (decoding) unit 120 uses the fssync signal as a trigger to time-divide the reproduction channel and read the sound data from the memory 140 (2), decodes the read sound data (3), and the mixing unit 130 finally mixes and outputs the decoded sound data (4).

[0003] When the semiconductor device 100 performs mixing with continuous audio data such as I2S, Figure 4 In this way, the reading and reproduction processing from the memory 140 is reduced from 4 channels to 2 channels, so that the sound produced by the memory reading is reproduced as 2 channels and the continuous audio data (Lch / Rch) is mixed as 4 channels in total.

[0004] Furthermore, Patent Document 1 discloses a clock generation device that is adjusted so that BCLK generated based on a system clock is synchronized with the rising or falling edge of LRCLK.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Application Publication No. 2007-235526. Summary of the invention

[0008] Problems to be solved by the invention

[0009] However, when one wants to perform a mixed reproduction of continuous audio data input using I2S or the like and sound data read from a memory, if there is a deviation between the sampling period of the continuous audio input and the sampling period generated inside the LSI, there is a problem of reduced sound quality of the reproduced sound due to repeated introduction or loss of the continuous audio input.

[0010] The present invention has been made in view of the above-mentioned points, and an object of the present invention is to provide a semiconductor device capable of improving the sound quality of reproduced sound by suppressing duplicate introduction or loss of continuous audio data when mixing sound data read out from a memory with continuous audio data.

[0011] Solutions to Solve Problems

[0012] A semiconductor device of a first embodiment of the present invention comprises: a timing generation unit that generates a synchronization signal in coordination with the input timing of continuous audio data input from the outside; a reproduction processing unit that reads sound data from a memory based on the synchronization signal to perform sound reproduction processing and output a plurality of channel information; and a mixing unit that mixes the plurality of channel information with the continuous audio data to generate a sound signal.

[0013] A semiconductor device according to a second aspect of the present invention is the semiconductor device according to the first aspect, wherein the timing generating section detects a rise or fall of a channel switching clock of the continuous audio data, and generates the synchronization signal based on the detection.

[0014] The third-type semiconductor device of the present invention is the first-type semiconductor device, wherein the timing generating unit maintains the value of the counter increased according to the basic clock as the counter expiration value at the timing when the rising or falling timing of the channel switching clock of the continuous audio data is detected, and generates the synchronization signal at the timing when the value of the counter is consistent with the counter expiration value.

[0015] A semiconductor device according to a fourth aspect of the present invention is the semiconductor device according to the third aspect, wherein the timing generating unit updates the counter expiration value at a predetermined period.

[0016] Effects of the Invention

[0017] According to the present invention, a semiconductor device can be provided which can generate a synchronization signal in accordance with the input timing of the continuous audio data when mixing the sound data read from the memory with the continuous audio data, thereby suppressing the duplication or loss of the continuous audio input and achieving improved sound quality of the reproduced sound. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a block diagram of a semiconductor device 100 according to the prior art.

[0019] Figure 2 It is a timing diagram of fssync signal generation in the prior art.

[0020] Figure 3 is a timing chart of the semiconductor device 100 in the related art.

[0021] Figure 4 is a timing chart of the semiconductor device 100 in the related art.

[0022] Figure 5 It is a diagram for explaining a problem of a conventional semiconductor device 100 .

[0023] Figure 6 It is a diagram for explaining a problem of a conventional semiconductor device 100 .

[0024] Figure 7 It is a block diagram showing the structure of a semiconductor device 200 according to an embodiment of the present invention.

[0025] Figure 8 FIG. 1 is a timing diagram of fssync signal generation according to an embodiment of the present invention.

[0026] Fig. 9 It is a timing chart of the semiconductor device 200 according to the embodiment of the present invention. DETAILED DESCRIPTION

[0027] Below, while referring to the attached Figure 1 An example of an embodiment of the present invention is described. In addition, the same reference numerals are used for the same or equivalent components and parts in each drawing. In addition, the dimensional ratios of the drawings are exaggerated for the convenience of description and may be different from the actual ratios.

[0028] First, the reason why the sampling period of continuous audio input and the sampling period generated inside the LSI deviate when trying to perform mixed reproduction of continuous audio data input from the outside using I2S or the like and sound data read from the internal memory is explained.

[0029] Figure 5 This is a timing chart for explaining the mixed reproduction of continuous audio data input from the outside and sound data read from the internal memory. LRCLK is a clock for switching the channel of continuous audio data. Figure 5 2 shows an example in which the cycle of continuous audio data (LRCLK cycle) is longer than the cycle of the fssync signal generated based on the internal basic clock of the semiconductor device.

[0030] When the LRCLK cycle is longer than the fssync signal cycle, the timing of the rise of the LRCLK cycle pulse and the timing of the fssync signal rise may gradually deviate, and the fssync signal may rise twice in one LRCLK cycle. Figure 5 In the example shown in FIG. 1 , in the (n+3)th sample of the continuous audio data, the fssync signal rises twice in one cycle of LRCLK.

[0031] When the fssync signal rises twice in one cycle of LRCLK, the sampling of continuous audio data is repeatedly introduced. Figure 5 In the example, in the n+3th sample of the continuous audio data, the fssync signal rises twice in one cycle of LRCLK, so the semiconductor device imports the n+2th sample of the previous continuous audio data twice. This is repeated import of samples. Therefore, when the LRCLK cycle is longer than the cycle of the fssync signal, the sound quality deteriorates.

[0032] Figure 6 It is a time chart illustrating mixed reproduction of continuous audio data and sound data read from a memory. Figure 6 2 shows an example in which the cycle of continuous audio data (LRCLK cycle) is shorter than the cycle of the fssync signal generated based on the internal basic clock of the semiconductor device.

[0033] When the LRCLK cycle is shorter than the fssync signal cycle, the timing of the rise of the pulse of the LRCLK cycle and the timing of the rise of the fssync signal may gradually deviate, and the fssync signal may not rise in one LRCLK cycle. Figure 6 In the example shown in FIG. 1 , in the (n+3)th sample of the continuous audio data, the fssync signal does not rise in one cycle of LRCLK.

[0034] As described above, when the fssync signal does not rise during one cycle of LRCLK, continuous audio data sampling is lost. Figure 6 In the example, in the n+3th sample of the continuous audio data, the fssync signal does not rise in one cycle of LRCLK, so the semiconductor device cannot import the n+2th sample of the continuous audio data one cycle ago. That is, the semiconductor device misses the n+2th sample of the continuous audio data one cycle ago. This is a sample loss. Therefore, when the LRCLK cycle is shorter than the fssync signal cycle, the sound quality deteriorates in the same way as when it is longer.

[0035] That is, when one wants to perform a mixed reproduction of continuous audio data input from the outside using I2S or the like and sound data read from an internal memory, when a deviation occurs between the LRCLK cycle and the fssync signal cycle, deterioration in sound quality occurs due to repeated introduction or loss of continuous audio data.

[0036] Therefore, in view of the above points, the inventors of the present application have conducted intensive discussions on a technology that can prevent repeated introduction or leakage of continuous audio data and improve sound quality even when a deviation occurs between the LRCLK cycle and the fssync signal cycle. As a result, the inventors of the present application have designed and completed a technology that can prevent repeated introduction or leakage of continuous audio data and improve sound quality even when a deviation occurs between the LRCLK cycle and the fssync signal cycle as described below.

[0037] Figure 7 1 is a diagram showing a configuration example of a semiconductor device 200 according to an embodiment of the present invention. Figure 7 The semiconductor device 200 shown in FIG. 1 outputs a sound signal. Figure 7 As shown, the system includes a timing generation unit 210 , a reproduction processing (decoding) unit 120 , a mixing unit 130 , and a memory 140 .

[0038] In the semiconductor device 200 of the present embodiment, when mixing with continuous audio data input from the outside using I2S or the like, a signal synchronized with the edge of LRCLK of the continuous audio data is used as a signal synchronized with the sampling period, and this signal is used as a trigger to reproduce the sound data stored in the memory 140 and mix with the continuous audio data.

[0039] The timing generation unit 210 generates an fssync signal using a basic clock in conjunction with the input timing of continuous audio data input from the outside using I2S or the like. For example, the timing generation unit 210 detects the edge of LRCLK of the continuous audio data, i.e., the rise or fall of LRCLK, and generates an fssync signal for causing the reproduction processing (decoding) unit 120 to read the audio data from the memory 140 based on the detected timing.

[0040] The reproduction processing (decoding) unit 120 reads the audio data stored in the memory 140 at the rising timing of the fssync signal generated by the timing generation unit 210, decodes the read audio data, and outputs it to the mixing unit 130. In this embodiment, the reproduction processing (decoding) unit 120 reads the audio data for two channels from the memory 140 and decodes it.

[0041] The mixing unit 130 mixes the audio data decoded by the reproduction processing (decoding) unit 120 with the continuous audio data of two left and right channels (Lch / Rch). In the present embodiment, the mixing unit 130 mixes the audio data of two channels with the continuous audio data of two channels.

[0042] Figure 8 2 is a timing chart of fssync signal generation according to an embodiment of the present invention. The semiconductor device 200 according to the present embodiment detects the rise of LRCLK and generates an fssync signal that rises at the timing of the rise of LRCLK. Figure 8 In the example of , although the fssync signal that rises at the timing of the rise of LRCLK is generated, the timing generation unit 210 may generate the fssync signal that rises at the timing of the fall of LRCLK.

[0043] The semiconductor device 200 reads out and decodes the audio data for two channels from the memory 140 in response to the rise of the fssync signal. Then, the semiconductor device 200 mixes the decoded audio data for two channels with the continuous audio data for two channels.

[0044] Fig. 9 This is a timing diagram of the semiconductor device 200 according to an embodiment of the present invention. When the timing generation unit 210 detects the rise of LRCLK, it makes the LRCLK edge detection signal "H" in synchronization with the internal basic clock. The timing generation unit 210 clears the sampling period counter at the timing when the LRCLK edge detection signal is "H", and makes the fssync signal "H". The internal circuit, namely the reproduction processing (decoding) unit 120 and the mixing unit 130, uses the timing when the fssync signal becomes "H" as a trigger, and reads out the sound data from the memory 140 as usual, and performs the reproduction processing and mixing processing. In addition, in Fig. 9 In the timing chart shown, the counter coincidence signal is fixed at "L".

[0045] As described above, according to the present embodiment, the rise of LRCLK is detected, and the fssync signal that rises at the timing of the rise of LRCLK is generated, thereby synchronizing the LSI with the input of continuous audio data. That is, according to the present embodiment, the LSI can be synchronized with the input of continuous audio data, so that the repeated introduction or loss of continuous audio data can be prevented.

[0046] exist Figure 8In the timing diagram of the semiconductor device 200 shown, although 2 channels of sound data and 2 channels of continuous audio data are mixed, the present invention is not limited to such an example. The continuous audio data to be mixed may be either Lch or Rch. When the continuous audio data to be mixed is either Lch or Rch, the semiconductor device 200 mixes a maximum of 3 channels of sound data and 1 channel of continuous audio data.

[0047] In addition, Figure 8 In the timing chart of the semiconductor device 200 shown, although the audio data of channel 1 and channel 2 are read out from the memory 140 and mixed with the continuous audio data, the channels of the audio data read out from the memory 140 are not limited to channel 1 and channel 2 .

[0048] In addition, Fig. 9 In the timing diagram of the semiconductor device 200 shown in FIG. 1 , the rise of LRCLK is detected at each cycle of LRCLK, and an fssync signal that rises at the timing of the rise is generated, but the present invention is not limited to such an example. For example, the timing generation unit 210 may keep the value of the sampling cycle counter at the timing of detecting the rise or fall of LRCLK as the counter expiration value, and generate an fssync signal that rises at the timing when the counter value and the counter expiration value are consistent. That is, the timing generation unit 210 may make the counter consistency signal "H" at the timing when the counter value and the counter expiration value are consistent, and generate an fssync signal that rises at the timing when the counter consistency signal becomes "H". By generating an fssync signal that rises at the timing when the value of the sampling cycle counter is consistent with the counter expiration value, the semiconductor device 200 does not need to detect the rise of LRCLK at each cycle.

[0049] Furthermore, the timing generation unit 210 may update the counter expiration value at a predetermined period while maintaining the value of the counter at the sampling period at the timing of detecting the rise or fall of LRCLK as the counter expiration value. For example, the timing generation unit 210 may detect the rise of LRCLK once every 10 periods of the LRCLK period and update the counter expiration value. The semiconductor device 200 periodically detects the rise of LRCLK to update the counter expiration value, thereby being able to mix the voice data and the continuous audio data with higher accuracy.

[0050] When the sampling period of LRCLK is shorter than the sampling period of the internal basic clock, the semiconductor device 200 can be configured to complete the memory readout, reproduction processing, and mixing processing sufficiently earlier than the deviation of LRCLK so that the memory sound processing and mixing processing are completed. Specifically, when the sampling period of LRCLK is faster than the sampling period of the internal basic clock, the period of LRCLK can be defined as LSI in such a way that a waiting period before the next fssync signal is sufficiently vacated so as to catch up with the processing.

[0051] When the sampling period of LRCLK is longer than the sampling period of the internal basic clock, the semiconductor device 200 starts the waiting period when the internal processing is completed and starts the processing of the next sampling at the input timing of the next continuous audio, so no particular problem occurs.

[0052] As described above, the semiconductor device 200 of the present embodiment is configured to start internal processing at each rising edge of LRCLK, thereby being able to achieve synchronization with asynchronous continuous audio input even when a misalignment occurs between the LRCLK cycle and the fssync signal cycle.

[0053] Furthermore, the present invention can also be applied to mixing a device such as a sound source or a sound generator having a function of reproducing sound in synchronization with a sampling period with input of continuous audio data such as I2S.

[0054] Description of Reference Numerals

[0055] 100, 200 semiconductor devices

[0056] 110, 210 timing generation unit

[0057] 120 Reproduction processing (decoding) unit

[0058] 130 Mixing Unit

[0059] 140 Memory.

Claims

1. A semiconductor device, characterized in that: have: A timing generating unit generating a synchronization signal in accordance with the input timing of continuous audio data input from the outside; a reproduction processing unit that reads out the sound data from the memory based on the synchronization signal, performs sound reproduction processing, and outputs a plurality of channel information; as well as a mixing unit, mixing the plurality of channel information with the continuous audio data to generate a sound signal, The timing generation unit detects the rise or fall of the channel switching clock of the continuous audio data, maintains the value of the counter whose value increases according to the basic clock as the counter expiration value at the timing when the rise or fall of the channel switching clock of the continuous audio data is detected, and generates the synchronization signal at the timing when the value of the counter matches the counter expiration value.

2. The semiconductor device according to claim 1, wherein The timing generating unit updates the expiration value of the counter at a predetermined period.

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