Memory device with read disturbance reduction and method of operating the memory device

Abstract

A memory device includes an array of memory cells including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, row control circuitry including a plurality of row switches corresponding to the word lines, column control circuitry including a plurality of column switches corresponding to the bit lines, and control logic circuitry configured to control a pre-charge operation of a word line and a bit line of a selected memory cell during a data read operation and to perform a control operation to float the word line and the bit line together after a pre-charge period. One of the word line and the bit line is floated after the pre-charge period, and the other of the word line and the bit line is pseudo-floated after the pre-charge period.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of priority to Korean Patent Application No. 10-2019-0089794, filed on July 24, 2019, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present invention relates to memory devices, and more specifically, to memory devices with reduced read interference and methods for reading such memory devices. Background Technology

[0004] For non-volatile memory devices such as flash memory, resistive memory devices such as phase-change RAM (PRAM), nanofloating gate memory (NFGM), polymer RAM (PoRAM), magnetic RAM (MRAM), ferroelectric RAM (FeRAM), and / or resistive RAM (RRAM) are known. Resistive memory devices combine the high speed of dynamic random access memory (DRAM) with the non-volatility of flash memory.

[0005] The memory cells of a resistive memory device can have a resistance distribution that depends on the programmed data. As an example of a read operation, a current readout scheme can be performed by applying a constant current to the memory cell and reading the voltage that varies according to the resistance of the memory cell. However, in such a current readout scheme, the characteristics of the resistance distribution may be unintentionally altered when the temperature rises significantly, potentially leading to read interference errors. Specifically, the word lines and bit lines connected to the memory cell may each have a capacitive component. As the capacitance value of the capacitive component increases, read interference errors may further increase, thus potentially reducing the number of read cycles with guaranteed reliability. Summary of the Invention

[0006] The present invention provides a memory device capable of reducing read interference by improving read operations, and a method for operating such a memory device.

[0007] According to one aspect of the present invention, a memory device is provided, comprising: a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines; row control circuitry including a plurality of row switches corresponding to word lines and configured to perform selection operations on word lines; column control circuitry including a plurality of column switches corresponding to bit lines and configured to perform selection operations on bit lines; and control logic circuitry configured to control a pre-charge operation on the word line and bit line of the selected memory cell during a data read operation, and to perform a control operation after the pre-charge period to float the word line and the bit line together. One of the word line and the bit line is floated after the pre-charge period, and the other of the word line and the bit line is pseudo-floated after the pre-charge period.

[0008] According to one aspect of the present invention, a memory device is provided, comprising: a selected memory cell configured to store data; a first line and a second line connected to the selected memory cell; a first switch configured to control an electrical connection between a first driver driving the first line and the first line in response to a first switch control signal; and a second switch configured to control an electrical connection between a second driver driving the second line and the second line in response to a second switch control signal. A data read operation for the selected memory cell includes a precharge period, a float period, and a data readout period. During the precharge period, the memory device is configured to provide a first precharge voltage corresponding to a negative target voltage to the first line, a second precharge voltage corresponding to a positive target voltage to the second line, precharge the first line to the negative target voltage, and precharge the second line to a level below the positive target voltage. During the float period, the memory device is configured to float the first line and pseudo-float the second line.

[0009] According to one aspect of the present invention, a method of operating a memory device is provided, the method comprising: receiving a read command; precharging a word line of a selected memory cell to a first level corresponding to a first target voltage, the selected memory cell being configured to store data; precharging a bit line of the selected memory cell to a second level different from a second target voltage; floating the word line by controlling a row switch connected to the word line; pseudo-floating the bit line by controlling a column switch to weakly turn on a column switch connected to the bit line; and performing data readout based on a result of detecting the voltage of the word line by electrically connecting the word line to a sense amplifier. At least a portion of the floating period of the word line overlaps with the pseudo-floating period of the bit line.

[0010] According to one aspect of the present invention, a memory module is provided, comprising: a module board; a plurality of memory chips mounted on the module board; and a non-volatile memory mounted on the module board and communicating with the memory chips. Each of the memory chips includes: a memory cell array comprising a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines; row control circuitry comprising a plurality of row switches corresponding to word lines and configured to perform selection operations on word lines; column control circuitry comprising a plurality of column switches corresponding to bit lines and configured to perform selection operations on bit lines; and control logic circuitry configured to control a pre-charge operation on the word line and bit line of the selected memory cell during a read operation, and to perform control operations to float one of the word line and the bit line after the pre-charge period and to continue providing a pre-charge voltage to the other of the word line and the bit line after the pre-charge period. Attached Figure Description

[0011] The embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 This is a block diagram of a memory system including a memory device according to an embodiment of the present invention.

[0013] Figure 2A and Figure 2B yes Figure 1 A circuit diagram illustrating an implementation example of a memory cell array;

[0014] Figure 3 yes Figure 1 A block diagram illustrating an implementation example of the read controller;

[0015] Figure 4 This is a flowchart of a method for operating a memory device according to an exemplary embodiment of the present invention;

[0016] Figure 5 This is a timing diagram of a data read operation according to an exemplary embodiment of the present invention;

[0017] Figure 6 This is a block diagram of an example implementation of a memory device according to an exemplary embodiment of the present invention.

[0018] Figure 7A , Figure 7B and Figure 7C The circuit diagram and waveform diagram are examples of read operations of the memory device of the present invention.

[0019] Figure 8A , Figure 8B and Figure 8CThis is a block diagram of a data read operation and a memory device for performing the data read operation, based on an exemplary embodiment of the present invention.

[0020] Figure 9 and Figure 10 This is a block diagram of an example implementation of a memory device according to another exemplary embodiment of the concept of the present invention;

[0021] Figure 11 and Figure 12 This is a timing diagram of a data read operation performed according to an exemplary embodiment of the present invention;

[0022] Figure 13 This is a flowchart of a method for operating a memory device according to various exemplary embodiments of the present invention;

[0023] Figure 14A , Figure 14B , Figure 15A and Figure 15B The figures illustrate an example of applying an embodiment of the inventive concept to a three-dimensional memory device;

[0024] Figure 16 This is a circuit diagram illustrating an example of compensating for leakage current during a data read operation.

[0025] Figure 17 This is a block diagram illustrating an example of applying a memory device according to an embodiment of the present invention to an SSD system;

[0026] Figure 18 These are block diagrams illustrating implementation examples of memory systems according to various embodiments of the present invention; and

[0027] Figure 19 This is a block diagram illustrating an example of using a memory device, according to an embodiment of the present invention, as a buffer for a controller. Detailed Implementation

[0028] Figure 1This is a block diagram of a memory system 10 including a memory device 200 according to an embodiment of the present invention. In some embodiments of the present invention, the memory device 200 may be referred to as a resistive memory device because the memory device 200 may include resistive memory cells. In some embodiments of the present invention, the memory device 200 may include various other types of memory cells. Furthermore, in some embodiments, the memory cells may be arranged in a region including multiple first signal lines and multiple second signal lines, and the memory device 200 may be referred to as a cross-point memory device. For example, the memory device 200 may include multiple layers and may be configured such that adjacent layers may share at least one signal line. In the embodiments below, it will be assumed that the memory device 200 is a resistive memory device. However, embodiments of the present invention can also be applied to various types of memory devices, such as volatile memory devices and flash memory devices.

[0029] In addition, it can be implemented in various forms. Figure 1 The memory device 200. For example, in some embodiments, the memory device 200 may be a device implemented as a single memory chip. In some embodiments, the memory device 200 may be implemented as multiple memory chips. For example, the memory device 200 may be a memory module in which multiple memory chips are mounted on a board. However, embodiments of the inventive concept are not limited thereto, and the memory device 200 may be implemented in various forms such as a semiconductor package including one or more memory wafers.

[0030] Reference Figure 1 The memory system 10 may include a memory controller 100 and a memory device 200. The memory device 200 may include a memory cell array 210, read / write circuitry 220, a voltage generator 230, and control logic 240. The memory controller 100 may include a processor 110, and under the control of the processor 110, the memory controller 100 may control various memory operations of the memory device 200 based on hardware, software, and / or combinations thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0031] The memory controller 100 can control the memory device 200 to read data stored in the memory device 200 and / or write data to the memory device 200 in response to write / read requests from the host. Specifically, the memory controller 100 can provide the memory device 200 with an address (ADD), a command (CMD), and / or a control signal (CTRL) to control programming (or writing), reading, and / or erasing operations for the memory device 200. Furthermore, data to be written (DATA) and data to be read (DATA) can be sent and received between the memory controller 100 and the memory device 200.

[0032] The memory controller 100 can communicate with the host via various protocols. For example, the memory controller 100 can be configured to communicate with the host via at least one of various protocols such as Universal Serial Bus (USB), Multimedia Card (MMC), Peripheral Component Rapid Interconnect (PCI-E), Advanced Technology Accessory (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Device Interface (ESDI), and / or Integrated Drive Electronics (IDE).

[0033] The memory cell array 210 may include a plurality of memory cells (not shown) arranged in areas where a plurality of first signal lines and a plurality of second signal lines intersect each other. In embodiments, the first signal lines may be either bit lines or word lines, and the second signal lines may be either bit lines or word lines. Furthermore, each memory cell may be a single-level cell (SLC) capable of storing one bit of data or a multi-level cell (MLC) capable of storing at least two bits of data. Moreover, depending on the number of bits stored in each memory cell, the memory cells may have multiple resistance profiles. For example, when one bit of data is written to a memory cell, these memory cells may have two resistance profiles. When two bits of data are stored in a memory cell, these memory cells may have four resistance profiles.

[0034] Additionally, the memory cell array 210 may include resistive memory cells, each of which includes a variable resistor element (not shown). For example, when the variable resistor element is a phase change material (e.g., Ge-Sb-Te(GST)) and the resistance of the phase change material varies with temperature, the resistive memory device may be a PRAM. In another example, when the variable resistor element includes an upper electrode, a lower electrode, and a composite metal oxide therebetween, the resistive memory device may be an RRAM. In yet another example, when the variable resistor element is composed of an upper electrode comprising a magnetic material, a lower electrode comprising a magnetic material, and a dielectric material therebetween, the resistive memory device may be an MRAM.

[0035] Control logic 240 can perform memory operations such as writing and / or reading data by controlling various components of memory device 200. For example, read / write circuitry 220 may include row control circuitry for controlling word lines of memory cell array 210 and column control circuitry for controlling bit lines of memory cell array 210. Row control circuitry may include row switches that perform selection operations on word lines, and column control circuitry may include column switches that perform selection operations on bit lines. As used herein, control logic may also be referred to as control logic circuitry.

[0036] Control logic 240 can output a switch control signal Ctrl_sw, which is used to control the row and column switches of read / write circuit 220 for selection operations of memory cells. Furthermore, depending on the memory operation of memory device 200, voltages of various levels can be applied to word lines and bit lines via read / write circuit 220, and control logic 240 can output a voltage control signal Ctrl_v for controlling voltage generator 230.

[0037] According to an example embodiment, control logic 240 may include a read controller 241, which may control a series of operations related to reading data from memory device 200. For example, a switch control signal Ctrl_sw and a voltage control signal Ctrl_v may be control signals generated by read controller 241. In some embodiments, the switch control signal Ctrl_sw and the voltage control signal Ctrl_v may be generated by another component (not shown) in control logic 240 based on control operations of read controller 241.

[0038] During a read operation of the memory cell array 210, read voltages can be provided to selected word lines (hereinafter referred to as word lines) and selected bit lines (hereinafter referred to as bit lines) connected to the selected memory cell, respectively. For example, a first precharge voltage can be provided to the word line, and a second precharge voltage can be provided to the bit line, such that the voltage between the word line and the bit line has a level difference corresponding to a specific set value. In addition, after the precharge operation for the word line and the bit line is completed, the voltage detected from at least one of the word line and the bit line can vary according to the programming state of the selected memory cell (e.g., set state or reset state).

[0039] For example, when performing an operation to read data using a voltage detected from a word line, the level of the voltage detected from the word line can vary depending on the programming state of the selected memory cell. When the voltage detected from the word line is greater than a specific reference level, the selected memory cell is in a set state, and therefore data "0" can be read. When the voltage detected from the word line is less than the specific reference level, the selected memory cell is in a reset state, and therefore data "1" can be read. In various embodiments, the memory device 200 can be implemented to read data using a voltage detected from a bit line. In some embodiments, the memory device 200 can be implemented such that data "1" is read when the selected memory cell is in a set state, and data "0" is read when the selected memory cell is in a reset state.

[0040] During the read operation described above, word lines and bit lines can each have large capacitance values. As a result, current can flow through the memory cell depending on the level difference between the word lines and bit lines, and read interference errors may occur as the temperature of the memory cell increases. For example, word lines and bit lines may have large capacitance values ​​due to their own capacitance components, capacitance components caused by adjacent lines, capacitance components caused by the connected memory cells, and / or capacitance components caused by peripheral circuitry connected to the word lines and bit lines (e.g., driver circuitry and / or readout circuitry). According to an exemplary embodiment of the invention, during a data read operation, the capacitance values ​​can be reduced by electrically isolating the word lines and bit lines from peripheral circuitry and / or reducing the strength of the electrical connections between the word lines and bit lines and peripheral circuitry, thereby reducing read interference errors. As a result, the reliability of the read cycle can be increased.

[0041] For example, a data read operation may include a precharge period, a float period, and a data read period, and the capacitance value can be reduced by controlling the row switches of the word lines connected to the selected memory cell and the column switches of the bit lines connected to the selected memory cell. The switch control signal Ctrl_sw may include a first control signal for controlling the row switches and a second control signal for controlling the column switches, and the capacitance value can be reduced by controlling the row switches and column switches during the float period.

[0042] In the example of a data read operation, since the word line is precharged to a first target voltage and the bit line is precharged to a second target voltage, the voltage between the word line and the bit line can have a level difference corresponding to a specific set value. Either the first target voltage or the second target voltage can correspond to a positive (+) target voltage, and the other can correspond to a negative (-) target voltage. In the following, it will be assumed that the first target voltage of the word line corresponds to a negative (-) target voltage, and the second target voltage of the bit line corresponds to a positive (+) target voltage.

[0043] During the precharge period, a first precharge voltage corresponding to a first target voltage can be provided to the word line, and a second precharge voltage corresponding to a second target voltage can be provided to the bit line. At this time, when the voltage difference between the word line and the bit line becomes greater than a specific reference voltage during the precharge period, the memory cell can be turned on (or placed in an on-cell state) and current can flow. Therefore, during the precharge period, the voltage difference between the word line and the bit line can be maintained below the specific reference voltage. According to an embodiment, during the precharge period, the voltage of the word line can be changed to a level corresponding to the first target voltage, while the voltage of the bit line can be changed to a level lower than the second target voltage. For example, the bit line can have a larger capacitive component (or load) than the word line, and even when the precharge periods of the word line and the bit line are the same, the voltage of the bit line can change more slowly. In some embodiments, by adjusting the precharge period of the bit line, the voltage of the bit line can be controlled to change to a level lower than the second target voltage during the precharge period.

[0044] Subsequently, during the floating period, floating operations for both word lines and bit lines can be performed simultaneously, thereby reducing the capacitance values ​​of the word lines and bit lines. In the example operation, a word line whose level rises to a first target voltage can be floating by turning off the row switch. Additionally, the resistance caused by the column switch can be increased by weakly turning on the column switch, thereby reducing the strength of the electrical connection between the bit line and the peripheral circuitry. As used herein, a “weakly turned-on” switch refers to a switch that is biased such that current flows through it, but with higher resistance across it. In some embodiments, a “weakly turned-on” switch may include providing a control signal to the switch having a level between logic high and logic low. For example, if the switch is implemented as a metal-oxide-semiconductor field-effect transistor (MOSFET), weakly turning on the switch may involve keeping the switch in the linear operating mode of the MOSFET. The state of the bit line according to the column switch operation described above can be referred to as a pseudo-floating state.

[0045] During the floating period as described above, the word line voltage can be maintained at a first target voltage, and the bit line voltage can gradually increase to a second target voltage. For example, when the pre-charged bit line voltage is at a first level during the pre-charge period and the second target voltage is a second level higher than the first level, the pseudo-floating bit line can rise from the first level to the second level during the floating period. In other words, since a second pre-charge voltage corresponding to the second target voltage is continuously supplied to the bit line, and the bit line receives the second pre-charge voltage through a column switch forming a relatively large resistance during the floating period, the bit line voltage can gradually rise from the first level to the second level. The resistance of the column switch can vary depending on the degree of pseudo-floating, and as the resistance increases, the degree of electrical connection disconnection increases. Furthermore, the floating period time can be increased as the voltage level increases more slowly. On the other hand, as the resistance of the column switch decreases, the degree of electrical connection disconnection decreases, but the voltage level increases more rapidly. Therefore, the floating period time can be reduced.

[0046] After the word line voltage reaches a first target voltage and the bit line voltage reaches a second target voltage, the memory device can enter a data readout period and detect the voltages of the word lines and / or bit lines, thus enabling a data readout operation. During the data readout period, the row and column switches can be controlled in various ways. For example, the row switches can be turned on, allowing the word lines to be electrically connected to the sense amplifier. Furthermore, as the column switches are turned on and the charge on the bit lines is discharged, the voltage of the bit lines can be changed to 0V. In some embodiments, the column switches can be maintained in a weakly turned-on state.

[0047] According to the exemplary embodiment of the inventive concept described above, during the precharge period, the voltage level difference between the word line and the bit line can be maintained at a level lower than a specific reference voltage. Therefore, during the precharge period, the memory cell can be prevented from entering the enabled state. Furthermore, since the word line and bit line float together during the float period, the capacitance values ​​of the word line and bit line can decrease together during data read operations, thus reducing read interference errors.

[0048] In the above embodiments, the terms "float" and "pseudo-float" can be used interchangeably in some cases. For example, pseudo-float of a bit line causes the bit line to have floating characteristics, and pseudo-float of a bit line can be described as a type of floating. Furthermore, regarding pseudo-float word lines and / or bit lines, the floating period can also be referred to as the pseudo-float period.

[0049] In some embodiments, the memory controller 100 and the memory device 200 may be implemented as separate semiconductor devices. In some embodiments, the memory controller 100 and the memory device 200 may be integrated into a single semiconductor device. For example, the memory controller 100 and the memory device 200 may be integrated into a single semiconductor device to constitute a memory card. For example, the memory controller 100 and the memory device 200 may be integrated into a single semiconductor device and constitute a PCMCIA card, a Compact Flash (CF) card, a Smart Media Card (SM / SMC), a Memory Stick, a Multimedia Card (MMC, RS-MMC, or MMCmicro), a Secure Digital Card (SD, miniSD, or microSD), a Universal Flash Memory (UFS), etc.

[0050] Figure 2A and Figure 2B yes Figure 1 A circuit diagram illustrating an implementation example of a memory cell array. Figure 2A and Figure 2B This illustrates the case where the resistive memory cell is a PRAM. Figure 2A The storage cell array 210 shown can correspond to a cell block.

[0051] The memory cell array 210 can be a two-dimensional memory cell array with a horizontal structure, and can include multiple word lines WL1 to WLn, multiple bit lines BL1 to BLm, and multiple memory cells MC, where m and n are natural numbers. Each memory cell array can include multiple memory blocks. In each memory block, multiple memory cells MC can be arranged in rows and columns. Here, the number of word lines WL, the number of bit lines BL, and the number of memory cells MC can vary according to embodiments of the present invention. However, the present invention is not limited thereto. In some embodiments, the memory cell array 210 can be a three-dimensional memory cell array with a vertical structure.

[0052] According to this embodiment, each memory cell MC may include a variable resistor element R and a switching element SW. Here, the variable resistor element R may be referred to as a variable resistive material, and the switching element SW may be referred to as a selection element.

[0053] In one embodiment, the variable resistor element R may be connected between one of the bit lines BL1 to BLm and the switching element SW, and the switching element SW may be connected between the variable resistor element R and one of the word lines WL1 to WLn. However, the inventive concept is not limited thereto, and the switching element SW may be connected between one of the bit lines BL1 to BLm and the variable resistor element R, and the variable resistor element R may be connected between the switching element SW and one of the word lines WL1 to WLn.

[0054] A switching element SW can be connected between any of the word lines WL1 to WLn and the variable resistor element R, and the switching element SW can control the current supply to the variable resistor element R according to the voltage applied to the corresponding word line and bit line connected to the switching element SW. Figure 2A In this embodiment, the switching element SW can include various types of components. For example, the switching element SW can include Ovonic threshold switch (OTS) material. In some embodiments, the switching element SW can include a diode such as a PN junction diode or a Schottky diode. Moreover, in some embodiments, the switching element SW can be replaced by another switchable component.

[0055] Reference Figure 2B The storage cell MC may include a variable resistor element R and a switching element SW. The switching element SW may be implemented using various components such as transistors and diodes. The variable resistor element R may include a phase change film 11 (which includes a mixture of germanium, antimony and tellurium (Ge-Sb-Te(GST))), an upper electrode 12 above the phase change film 11, and a lower electrode 13 below the phase change film 11.

[0056] The upper electrode 12 and the lower electrode 13 may comprise various metals, metal oxides, and / or metal nitrides. The upper electrode 12 and the lower electrode 13 may comprise aluminum (Al), copper (Cu), titanium nitride (TiN), titanium aluminum nitride (Ti), etc. x Al y N z ), iridium (Ir), platinum (Pt), silver (Ag), gold (Au), polycrystalline silicon, tungsten (W), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), nickel (Ni), cobalt (Co), chromium (Cr), antimony (Sb), iron (Fe), molybdenum (Mo), palladium (Pd), tin (Sn), zirconium (Zr), zinc (Zn), iridium oxide (IrO2), strontium zirconate (StZrO3), etc.

[0057] The phase change film 11 may include a bipolar resistive storage material and / or a unipolar resistive storage material. The bipolar resistive storage material can be programmed to a set state or a reset state according to the polarity of the current, and perovskite-based materials can be used as the bipolar resistive storage material. In some embodiments, the unipolar resistive storage material can be programmed to a set state or a reset state by a current having the same polarity, and materials such as NiO can be used. x or TiO x Transition metal oxides are used as unipolar resistive storage materials.

[0058] GST materials can be programmed between an amorphous state with relatively high resistivity and a crystalline state with relatively low resistivity. GST materials can be programmed by heating them. The magnitude and duration of heating determine whether the GST material remains amorphous or crystalline. Heating can be performed using a separate heater, or, when no heater is available, by the Joule heat generated when current flows through the memory cell. In some embodiments, high resistivity and low resistivity can be represented by programmed logic values ​​0 and 1, respectively, and can be read out by measuring the resistivity of the GST material. In some embodiments, high resistivity and low resistivity can be represented by programmed logic values ​​1 and 0, respectively.

[0059] Figure 3 yes Figure 1 A block diagram illustrating an implementation example of the read controller.

[0060] Reference Figure 1 and Figure 3 The control logic 240 may include a read controller 241, which may generate various control signals according to the above embodiments. In example operation, the read controller 241 may receive various types of timing information Info_T related to the read operation and generate control signals based on the timing information Info_T for controlling pre-charge operations and / or floating operations of each word line and bit line. Furthermore, the read controller 241 may generate a voltage control signal Ctrl_v, which is used to adjust the voltage levels supplied to the word lines and bit lines in relation to the read operation.

[0061] The read controller 241 may include a row switch controller 241_1, a column switch controller 241_2, and a precharge voltage controller 241_3. The row switch controller 241_1 may output a row switch control signal Ctrl_sw_R for controlling the switching of the row switch transmitted to the word line, and the column switch controller 241_2 may output a column switch control signal Ctrl_sw_C for controlling the switching of the column switch transmitted to the word line.

[0062] During the precharge period, the row and column switches are activated via the row switch control signal Ctrl_sw_R and the column switch control signal Ctrl_sw_C, respectively, and precharge operations can be performed on word lines and bit lines. During the float period, word lines can float because the row switch can be deactivated via the row switch control signal Ctrl_sw_R, and bit lines can pseudo-float because the column switch can be weakly activated via the column switch control signal Ctrl_sw_C. In the operational example, during the data readout period, the row switch can be activated via the row switch control signal Ctrl_sw_R, and the bit lines can be activated via the column switch control signal Ctrl_sw_C, or the bit lines can be continuously pseudo-floated.

[0063] According to the example embodiment, the voltage of the bit line can be changed to a level lower than the second target voltage during the precharge period and can be increased to the second target voltage during the float period. At this time, the voltage of the bit line can be adjusted by changing the level of the precharge voltage supplied to the bit line. For example, the precharge voltage controller 241_3 can output a voltage control signal Ctrl_v to the voltage generator 230 based on timing information Info_T, thus providing a precharge voltage with a level lower than the second target voltage to the bit line during the precharge operation and a precharge voltage with a level corresponding to the second target voltage to the bit line during the float period.

[0064] Figure 4 This is a flowchart of a method for operating a memory device according to an exemplary embodiment of the present invention.

[0065] Reference Figure 4 The memory device can perform data read operations based on requests from an external host. For example, a memory controller included in the memory system can provide a read command to the memory device based on a request from the host. The memory device can receive the read command (operation S11) and decode the address provided by the read command to determine the selected memory cell. Furthermore, for the word lines and bit lines connected to the selected memory cell, the memory device can precharge the word lines to a first voltage during a precharge period (operation S12) and precharge the bit lines to a second voltage (operation S13).

[0066] To read data, the voltage between the word line and the bit line can have a level difference corresponding to a specific set value. For example, this level difference can be achieved when the voltage of the word line has a first target voltage corresponding to a negative target voltage and the voltage of the bit line has a second target voltage corresponding to a positive target voltage. During the precharge period, the first voltage can correspond to the first target voltage, and when the memory device enters the floating period, the word line can be floating (operation S14). On the other hand, the second voltage of the bit line precharged during the precharge period can be lower than the second target voltage. When the memory device enters the floating period, the column switch connected to the bit line can be weakly turned on, and during the floating period, the voltage of the bit line can be changed to a third voltage corresponding to the second target voltage (operation S15). In addition, during the floating period, the column switch can form a large resistance, thereby reducing the strength of the electrical connection between the bit line and the peripheral circuit. Moreover, the capacitive component of the bit line can be reduced.

[0067] As described above, the voltage level difference between the word line and the bit line can be terminated by a floating period corresponding to the specific setting value mentioned above, and then a data readout operation (operation S16) can be performed.

[0068] Figure 5 This is a timing diagram of a data read operation according to an example embodiment of the present invention. Figure 5 The status of the word line WL and bit line BL connected to the selected memory cell and the detected voltage level are illustrated.

[0069] Reference Figure 5 When a memory device receives a read command, it can perform a series of operations to read data stored in the selected memory cell, and can perform precharge operations on the word line WL and bit line BL during the precharge period t0 to t1. For example, a negative target voltage can be applied to the word line WL, and a positive target voltage can be applied to the bit line BL, and the voltages of the word line WL and bit line BL can change during the precharge period t0 to t1. In the operational example, a greater number of memory cells are connected to the bit line BL than the number of memory cells connected to the word line WL. Therefore, the capacitive component (or load) of the bit line BL can be greater than the capacitive component (or load) of the word line WL, and although the voltage of the word line WL can quickly reach the negative target voltage, the voltage of the bit line BL can rise slowly. Although for ease of illustration, Figure 5 The voltage of word line WL is shown to become the negative target voltage at time t0, but due to the capacitive component of word line WL, the voltage level of word line WL can change with a relatively large slope.

[0070] During the precharge period t0 to t1, the voltage of bit line BL becomes lower than the positive target voltage. Therefore, the voltage level difference between word line WL and bit line BL can be a level difference that prevents the memory cell from being turned on. Thereafter, during the floating period t1 to t2, word line WL and bit line BL can be floated together. According to an embodiment, word line WL can be switched to a floating state, and bit line BL can be switched to a pseudo-floating state.

[0071] The column switch connected to bit line BL can be weakly turned on, and a pre-charge voltage corresponding to a positive target voltage from peripheral circuitry (e.g., a bit line driver) can be provided to bit line BL via the column switch. Therefore, during the float period t1 to t2, the voltage level of bit line BL can reach the positive target voltage. Additionally, during the float period t1 to t2, depending on the resistance state (set state or reset state) of the selected memory cell, the selected memory cell can have either on-cell or off-cell characteristics. When the selected memory cell is in the set state, it can have on-cell characteristics as the level of bit line BL increases. Therefore, the charge on bit line BL flows through the selected memory cell to word line WL, thus increasing the voltage level of word line WL. In other words, the voltage level detected from word line WL of the selected memory cell in the set state during the float period t1 to t2 can be greater than the voltage level detected when word line WL of the selected memory cell is in the reset state.

[0072] When the voltages of the word line WL and bit line BL are changed to a level suitable for reading data during the floating period t1 to t2, the voltage of the word line WL can be detected during the data reading period t2 to t3, thereby reading the data. Furthermore, the column switch can be controlled in various ways. For example, when the column switch is turned on and the bit line BL is discharged, the voltage of the bit line BL can be changed to 0V.

[0073] although Figure 5 An example of reading data by detecting the voltage of word line WL is shown, but embodiments of the present invention are not limited thereto. Data readout operations can be performed according to various other embodiments. For example, the voltage level of bit line BL can be maintained during the data readout period t2 to t3, and data can be read based on the voltage level difference between bit line BL and word line WL.

[0074] The terminology defined in the above embodiments is merely illustrative, and the embodiments of the inventive concept are not limited thereto. For example, in the above embodiments, the description of a word line may correspond to a bit line, and the description of a bit line may correspond to a word line (e.g., the names of word line and bit line may be interchanged). Moreover, a first line may be defined as either a word line or a bit line, and a second line may be defined as the other of a word line and a bit line.

[0075] Although the foregoing describes the word line WL and bit line BL being floated simultaneously in the above embodiments, the embodiments of the present invention are not limited thereto. The word line WL and / or bit line BL can be floated at various points in time. For example, a pseudo-floating of the bit line BL can be initiated during the period when the word line WL is floated. Furthermore, in the above examples, the terms "precharge period" and "floating period" are used together for both the word line WL and the bit line BL. In some embodiments, the word line WL and bit line BL can be controlled separately at different timings, and the aforementioned precharge period and floating period can be divided into a word line WL precharge period, a word line WL floating period, a bit line BL precharge period, and a bit line BL floating period.

[0076] Figure 6 This is a block diagram of an exemplary embodiment of a memory device 300 according to an exemplary embodiment of the present invention.

[0077] Reference Figure 6 The memory device 300 may include a memory cell array 310, row control circuitry 320, control logic 330, write driver / read amplifier (WD / SA) 340, column control circuitry 350, and voltage generator 360. Furthermore, the memory device 300 may also include various other components related to memory operation.

[0078] Control logic 330 can control memory operations based on various signals from the memory controller. For example, control logic 330 can control memory operations such as writing and / or reading data based on commands CMD from the memory controller, and can select memory cells based on addresses ADD provided by the memory controller. In some embodiments, control logic 330 can also receive control signals CTRL from the memory controller. Address ADD can include a row address for selecting the word line WL of the memory cell array 310 and a column address for selecting the bit line BL of the memory cell array 310. Moreover, write driver / read amplifier 340 can be connected to the word line WL via row control circuitry 320, and write data DATA to or read data DATA from memory cells based on internal control signals from control logic 330.

[0079] Row control circuit 320 may include a word line driver that supplies one or more voltages to word lines WL and / or a row switch that performs a selection operation on word lines WL. The row switches may include a plurality of row switches arranged corresponding to each word line WL. When each row switch is turned on, voltages from the word line driver can be supplied to the word lines WL via the row switches. Similarly, column control circuit 350 may include a bit line driver that supplies one or more voltages to bit lines BL and / or a column switch that performs a selection operation on bit lines BL. In the above embodiment, a pseudo-floating operation on bit lines BL can be performed by weakly turning on (or weakly turning off) the column switches included in column control circuit 350.

[0080] According to an exemplary embodiment of the present invention, during the precharge period and / or floating period according to the above embodiments, control logic 330 can control a series of operations for reading data and perform control operations on word line WL and bit line BL. For example, control logic 330 can output a voltage control signal Ctrl_v to voltage generator 360 and control voltage generator 360 to generate a precharge voltage. Voltage generator 360 can provide a first precharge voltage Vol_R to row control circuit 320 and a second precharge voltage Vol_C to column control circuit 350. For example, according to the above embodiments, a first precharge voltage Vol_R corresponding to a negative target voltage can be provided to row control circuit 320, and a second precharge voltage Vol_C corresponding to a positive target voltage can be provided to column control circuit 350.

[0081] Additionally, control logic 330 can provide the row switch control signal Ctrl_sw_R to the row control circuit 320 to control the row switch, and can also provide the column switch control signal Ctrl_sw_C to the column control circuit 350 to control the column switch. According to the above embodiment, during the floating period, the row switch connected to the selected memory cell can be turned off in response to the row switch control signal Ctrl_sw_R, and the column switch connected to the selected memory cell can be weakly turned on in response to the column switch control signal Ctrl_sw_C. Furthermore, during the data read period, the write driver / read amplifier 340 can detect the voltage from the word line connected to the selected memory cell, amplify the voltage, and output the read data DATA.

[0082] The configuration and operation of the memory device 300 in the above embodiments can be modified in various ways. For example, the degree of bit line floating can vary depending on the strength of the column switch being turned on during the floating period. The weaker the switch is turned on, the greater the resistance formed by the column switch becomes. Therefore, when the column switch is weakly turned on, the capacitive component of the bit line can be significantly reduced, while the voltage level applied to the bit line rises slowly. Thus, the floating period can be longer. In other words, by controlling the strength of the column switch, the degree of disconnection of the electrical connection between the bit line and the peripheral circuit can be changed, and the time spent reading data can also be changed by adjusting the floating period.

[0083] Figure 7A , Figure 7B and Figure 7C The circuit diagram and waveform diagram are examples of read operations of the memory device of the present invention.

[0084] Reference Figure 7A The bit line driver Driver_B can be connected to the bit line BL of the selected memory cell via the column switch CS, and the word line driver Driver_W can be connected to the word line WL of the selected memory cell via the row switch WS. Additionally, control logic (not shown) included in the memory device can generate various control signals related to data read operations. For example, the column switch CS can be controlled by the column switch control signal Ctrl_sw_C, and the row switch WS can be controlled by the row switch control signal Ctrl_sw_R. The sense amplifier SA can detect the voltage applied to a node of the word line WL and can perform a data read operation based on this detection.

[0085] A first precharge voltage Vol_R can be provided to word line WL via word line driver Driver_W, and a second precharge voltage Vol_C can be provided via bit line driver Driver_B. Furthermore, according to the above embodiment, the first precharge voltage Vol_R can have a negative target voltage, and the second precharge voltage Vol_C can have a positive target voltage. Figure 7A An example is shown where the first precharge voltage Vol_R corresponds to -2.4V and the second precharge voltage Vol_C corresponds to 2.4V, but the inventive concept is not limited thereto. During the precharge period of the above embodiment, the word line WL can be precharged to -2.4V, while the bit line BL can be precharged to a level below 2.4V.

[0086] Figure 7B Examples of the waveforms for the row switch control signal Ctrl_sw_R and the column switch control signal Ctrl_sw_C are shown. Although Figure 7AThe illustration shows a case where the row switch WS is implemented as an NMOS transistor and the column switch CS is implemented as a PMOS transistor, but the embodiments of the present invention are not limited thereto, and various modifications can be made therein.

[0087] Reference Figure 7B During the precharge period t0 to t1, the row switch control signal Ctrl_sw_R is at a logic high level, and the column switch control signal Ctrl_sw_C is at a logic low level. Therefore, the row switch WS and column switch CS can be turned on, and a precharge operation can be performed on the word line WL and bit line BL. Next, during the floating period t1 to t2, the row switch control signal Ctrl_sw_R has a voltage level corresponding to a logic low level. Therefore, the row switch WS can be turned off, while the column switch control signal Ctrl_sw_C can have a voltage level between logic high and logic low, thus the column switch CS can be weakly turned on to correspond to a pseudo-floating state.

[0088] Subsequently, during the data readout period t2 to t3, the row switch WS and column switch CS can be controlled in various ways. For example, when Figure 7A When the readout amplifier SA and word line driver Driver_W are connected to word line WL via row switch WS, the row switch control signal Ctrl_sw_R has a logic high level, thus enabling row switch WS to be turned on. Additionally, according to the example embodiment, when column switch CS is turned on during the data readout period t2 to t3, a discharge operation can be performed on bit line BL.

[0089] Figure 7C An embodiment for reducing the capacitive component of the word line WL due to the sense amplifier SA during a data readout operation is shown, wherein an additional switch (e.g., a sense amplifier selection switch SS) may be provided between the word line WL and the sense amplifier SA, and the sense amplifier selection switch SS may be controlled by an additional control signal Ctrl_sw_S.

[0090] According to the above embodiment, during the data readout period t2 to t3, the word line WL and the sense amplifier SA can be electrically connected to each other. At this time, the sense amplifier selection switch SS is controlled to a pseudo-floating state, so that while the sense amplifier SA is reading the voltage of a node of the word line WL, the capacitive component of the word line WL can decrease. In other words, according to the exemplary embodiment of the present invention, the pseudo-floating states of the word line WL and the bit line BL can be controlled together.

[0091] Figure 8A , Figure 8B and Figure 8C This is a block diagram of a data read operation and a memory device for performing the data read operation, based on an exemplary embodiment of the present invention. Figure 8A, Figure 8B and Figure 8C This illustrates a scenario where reading data is performed by varying the level of the precharge voltage applied to the word line and / or bit line. Additionally, in Figure 8A , Figure 8B and Figure 8C In the middle, the word lines are precharged to the negative target voltage, and the bit lines are precharged to the positive target voltage.

[0092] Reference Figure 8A Before the precharge period t0 to t1, the voltage vWL of the word line and the voltage vBL of the bit line connected to the selected memory cell may have a value of 0V. During the precharge period t0 to t1, the levels of the word line voltage vWL and the bit line voltage vBL can be changed. For example, during the precharge period t0 to t1, a precharge voltage of -2.4V corresponding to a negative target voltage can be provided to the word line WL, and the voltage vWL of the word line WL can become -2.4V. Alternatively, during the precharge period t0 to t1, a precharge voltage having a voltage less than the positive target voltage (i.e., 1.4V) can be provided to the bit line BL, and the voltage vBL of the bit line BL can rise to a level of 1.4V.

[0093] Subsequently, during the floating period t1 to t2, the word line WL can be floating, the bit line BL can be pseudo-floating, and a pre-charge voltage of 2.4V corresponding to the positive target voltage can be provided to the bit line BL. Therefore, during the floating period t1 to t2, the voltage of the bit line BL can rise to 2.4V. Furthermore, according to the above embodiment, during the data readout period t2 to t3, voltages with different levels can be detected from the word line WL based on the resistance state of the selected memory cell, and data can be read out through the word line WL.

[0094] Figure 8B This is a graph showing the on-cell or off-cell characteristics based on the resistance distribution, where the horizontal axis represents the voltage level difference between the word line WL and the bit line BL, and the vertical axis represents the number of memory cells. For example, a memory cell in the set state can have on-cell characteristics when the difference between the voltage level of the word line WL and the voltage level of the bit line BL is greater than approximately 3.8V, and a memory cell in the reset state can have off-cell characteristics when the difference between the voltage level of the word line WL and the voltage level of the bit line BL is greater than 4.8V. Furthermore, the voltage level difference V_diff between the word line WL and the bit line BL for reading data can be set to a value approximately equal to the median of the distribution for the set and reset states.

[0095] According to the above embodiments, by maintaining the voltage level difference V_diff between the word line WL and the bit line BL at or below 3.8V during the precharge period, it is possible to prevent the memory cell from exhibiting on-cell characteristics during the precharge operation. Furthermore, during the float period, the voltage level difference V_diff between the word line WL and the bit line BL can have a value that allows for the identification of memory cells in a set state and memory cells in a reset state.

[0096] Figure 8C An example is shown of the variation in voltage levels supplied to the word lines and bit lines during a data read operation. For example... Figure 8C As shown, the memory device 400 may include a voltage generator 410, control logic 420, a selector (MUX) 430, and column control circuitry 440.

[0097] Control logic 420 can change the level of the pre-charge voltage output from voltage generator 410 by controlling voltage generator 410. Furthermore, control logic 420 can select the pre-charge voltage supplied to column control circuit 440 by controlling MUX 430. Additionally, according to the above embodiment, column control circuit 440 includes a column switch (not shown), and control logic 420 can control the column switch to adjust its on / off state, floating state, and pseudo-floating state.

[0098] According to the above embodiments, voltage generator 410 can generate a pre-charge voltage of 1.4V and a pre-charge voltage of 2.4V. During the pre-charge period, MUX 430 can selectively provide the 1.4V pre-charge voltage to column control circuit 440 in response to selection signal Ctrl_M. Additionally, during the floating period, MUX 430 can selectively provide the 2.4V pre-charge voltage to column control circuit 440 in response to selection signal Ctrl_M, and based on the control logic 420, the column switch connected to the bit line can be weakly activated.

[0099] Figure 9 and Figure 10 This is a block diagram of an example embodiment of a memory device 500 according to another example embodiment of the concept of the present invention. Figure 9 and Figure 10 An example of word line pseudo-floating is shown during a data read operation.

[0100] Reference Figure 9The memory device 500 includes a memory cell array 510, row control circuitry 520, control logic 530, voltage generator 540, column control circuitry 550, and write driver / read amplifier 560. According to the above embodiment, the row control circuitry 520 may include a word line driver and a row switch, and the column control circuitry 550 may include a bit line driver and a column switch. Furthermore, the control logic 530 can receive commands CMD, addresses ADD, and control signals CTRL from the memory controller and control the memory operations of the memory device 500 based on them. Figure 9 Other components and those described in this article Figure 6 The components described are similar, and repeated descriptions will be omitted for the sake of brevity.

[0101] exist Figure 9 In the illustrated embodiment, data can be read out by detecting the voltage of the bit line connected to the selected memory cell. According to the above embodiment, a positive target voltage can be provided to the bit line, and a negative target voltage can be provided to the word line. According to this embodiment, during the pre-charge period, the voltage of the word line can be changed to a negative voltage higher than the negative target voltage, while the voltage of the bit line can be changed to a level higher than the negative target voltage. Furthermore, during the float period, the bit line can be floated and the word line can be pseudo-floated; therefore, during the float period, the voltage of the word line can be changed to the negative target voltage.

[0102] For reference Figure 10 In this embodiment, during the precharge period t0 to t1, a precharge operation can be performed on the word lines and bit lines connected to the selected memory cell. During the precharge period t0 to t1, the bit line voltage vBL can be changed to 2.4V corresponding to the positive target voltage (e.g., from 0V to 2.4V), while the word line voltage vWL can be changed to -1.4V, which is higher than the negative target voltage (e.g., from 0V to -1.4V).

[0103] Subsequently, during the float period t1 to t2, the bit line can switch to a float state, and the word line can switch to a pseudo-float state. Furthermore, during the float period t1 to t2, the word line voltage vWL can be changed to -2.4V, corresponding to the negative target voltage (e.g., from -1.4V to -2.4V). Additionally, during the float period t1 to t2, the voltage level difference between the word line and the bit line can be increased, and the selected memory cell can have on-cell characteristics when the resistance state of the selected memory cell is in the set state. Therefore, the bit line voltage vBL can be changed. For example, the bit line voltage vBL of the selected memory cell in the set state can be less than the bit line voltage vBL of the selected memory cell in the reset state. During the data read period t2 to t3, the write driver / read amplifier 460 can read the data of the selected memory cell based on the voltage level detected from the bit line.

[0104] However, the embodiments of the present invention are not limited to those described herein. Figure 10 The waveforms of the voltage levels shown are illustrated. For example, the voltage level variations of word line WL and bit line BL can differ from those shown. Figure 10 The waveforms shown. For example, the voltage levels of word line WL and bit line BL can be correlated with the capacitance components of word line WL and bit line BL. Figure 10 The voltage levels shown are different.

[0105] Furthermore, although the above embodiments describe that the control word line and bit line can have the same timing, the embodiments of the present invention are not limited to this. For example, the word line WL and bit line BL can be controlled separately, so at least one of the pre-charge period and floating period of the word line WL can be different from each other. For example, the pre-charge operation can be performed on the word line WL and bit line BL at different timings, and the pre-charge operation can also be completed at different timings.

[0106] The following section describes an example of performing a data read operation by controlling the precharge period and the float period. Figure 11 and Figure 12 This is a timing diagram of a data read operation performed according to an exemplary embodiment of the present invention. In the following embodiments, it will be assumed that the target voltage of the word line used to read data corresponds to -2.4V and the target voltage of the bit line corresponds to 2.4V, but the present invention is not limited thereto.

[0107] Reference Figure 11 The word lines and bit lines connected to the selected memory cells can be controlled separately, thus allowing for different adjustments to the precharge and float periods for each word line and bit line. For example, Figure 11An example is shown where the bit line has a larger capacitance component than the word line, so the voltage of the bit line changes slowly compared to the voltage of the word line during the precharge period.

[0108] During the pre-charge period t0 to t1 of the word line, a pre-charge voltage of -2.4V corresponding to the negative target voltage is provided to the word line, and the voltage of the word line can be changed to -2.4V during the pre-charge period t0 to t1. On the other hand, the pre-charge period t0 to t2 of the bit line can be longer than the pre-charge period t0 to t1 of the word line, and even when a pre-charge voltage of 2.4V corresponding to the positive target voltage is provided to the bit line, the voltage of the bit line can rise to 1.4V during the pre-charge period t0 to t2.

[0109] Simultaneously, the word line can be floated earlier than the bit line (e.g., at time t1), and the bit line can be pseudo-floated during the bit line float period t2 to t3. Furthermore, during the bit line float period t2 to t3, the bit line voltage can be slowly increased to 2.4V (e.g., from 1.4V to 2.4V). Subsequently, during the data read period t3 to t4, a data read operation can be performed, and according to the above embodiment, the word line voltage can have different levels depending on the resistance state of the selected memory cell.

[0110] Reference Figure 12 A precharge voltage of -2.4V corresponding to a negative target voltage can be provided to the word lines, and a precharge voltage of 2.4V corresponding to a positive target voltage can be provided to the bit lines. During the precharge period, the voltage levels of the word lines and bit lines can be varied. For example, since the voltage level variation of the word lines is greater than that of the bit lines during the precharge period, the precharge period t0 to t2 of the word lines can be longer than the precharge period t0 to t1 of the bit lines. During the precharge period t0 to t2 of the word lines, the voltage of the selected word line can be changed to -2.4V. Furthermore, the word lines can enter a floating period t2 to t3 after the precharge period t0 to t2.

[0111] Simultaneously, the pre-charge period t0 to t1 of the bit line can be relatively short, so the bit line voltage can be pre-charged to a level lower than 2.4V corresponding to the positive target voltage (e.g., 1.4V). When the bit line voltage is lower than the positive target voltage, the bit line can enter the floating period t1 to t3. According to the above embodiment, the bit line can be pseudo-floating during the floating period t1 to t3, and the bit line voltage can be increased to 2.4V (e.g., from 1.4V to 2.4V). Thereafter, a data readout operation can be performed during the data readout period t3 to t4.

[0112] Although examples of adjusting the timing for pseudo-floating bit lines relative to word lines have been described in the above embodiments, the timing of each time period according to the present invention can be adjusted in various ways. For example, in the case of multiple bit lines, each bit line may have different capacitive components due to various factors such as distance to peripheral circuitry. Therefore, different interval timings can be applied to each bit line separately, and different strengths (or electrical connection strengths) for turning on column switches can be applied to each bit line separately.

[0113] According to the example embodiment, the timing for the pseudo-floating bit line can be adjusted by taking into account the characteristics of the memory cells. For example, memory cells can be turned on at different timings based on the threshold voltage of the switching element. This may result in self-induced read disturb (SIRD) between different memory cells. According to the above embodiment, SIRD caused by the capacitive component can be reduced, and the differences in SIRD between memory cells can be compensated by the timing adjustment as described above.

[0114] Figure 13 This is a flowchart of a method for operating a memory device according to various exemplary embodiments of the present invention.

[0115] Reference Figure 13 The memory device may include multiple memory cells and multiple word lines and multiple bit lines connected to the memory cells. The word lines and bit lines connected to a selected memory cell to read data from that selected memory cell can be precharged together (operation S21). The word lines and bit lines of the memory device can be controlled separately, and the precharge operation can determine whether the voltage of the word line has reached a first level corresponding to a target voltage (e.g., a negative target voltage) (operation S22). When the voltage of the word line has not yet reached the first level ("No" in operation S22), the precharge operation can continue and / or be repeated. When the voltage of the word line reaches the first level, the precharge period of the word line can be terminated, and the word line can be switched to a floating state (operation S23).

[0116] Simultaneously, operations for detecting the bit line voltage can be performed. For example, a pre-charge operation can be used to determine whether the bit line voltage has risen to a second level below a target voltage (e.g., a positive target voltage) (operation S24). When the bit line voltage has not yet reached the second level ("No" in operation S24), the pre-charge operation can continue and / or be repeated. When the bit line voltage reaches the second level, the pre-charge period of the bit line can be terminated, and the bit line can be switched to a pseudo-floating state (operation S25).

[0117] Subsequently, the bit line voltage can be increased during the float period, and it can be determined whether the bit line voltage has increased to the third level corresponding to the target voltage (operation S26). If the bit line voltage has not yet reached the third level ("No" in operation S26), the float period can continue. When the bit line voltage reaches the third level, the memory device enters the data read period, and therefore data can be read (operation S27).

[0118] In the above embodiments, examples have been described of detecting the levels of word lines and bit lines and the memory device entering various segments related to reading data; however, embodiments of the present invention are not limited thereto. For example, voltage detection operations may be performed only on one of the word lines and bit lines, and entry into the float period and data readout period may be controlled based on the voltage detection operations.

[0119] Figure 14A , Figure 14B , Figure 15A and Figure 15B This is a diagram illustrating an example of applying an embodiment of the inventive concept to a three-dimensional (3D) memory device. Figure 14A and Figure 14B The memory device 900A is shown to include a first layer 920A and a second layer 930A, but more layers may be provided in the memory device 900A without departing from the inventive concept.

[0120] Reference Figure 14A The memory device 900A may include a peripheral layer 910A in which a peripheral region including peripheral circuitry is arranged, a first layer 920A (Layer 1) and a second layer 930A (Layer 2) in which memory cells are arranged. The first layer 920A and the second layer 930A may each include a plurality of memory cells and word lines and bit lines connected to the memory cells. Additionally, although in Figure 14A An example of an outer layer 910A including a write driver / read amplifier (WD / SA) and control logic is shown, but various types of peripheral circuitry related to memory operations can be provided in the outer layer 910A. Furthermore, in some embodiments, the write driver / read amplifier can be shared by the first layer 920A and the second layer 930A.

[0121] Figure 14B An example is shown where the first layer 920A and the second layer 930A share at least one line in a 3D memory device 900A. Although Figure 14BAn example of a first-layer 920A and a second-layer 930A sharing word lines is shown, but the first-layer 920A and the second-layer 930A can also share bit lines. For example, the first-layer 920A can read data by controlling bit lines BL0(1) and BL1(1) and word lines WL0(1,2) and WL1(1,2). Similarly, the second-layer 930A can read data by controlling bit lines BL0(2) and BL1(2) and word lines WL0(1,2) and WL1(1,2).

[0122] In the multiple layers constituting the stacked structure, the word lines and / or bit lines of the second layer 930A may have a larger capacitance component (or a larger load) than the word lines and / or bit lines of the first layer 920A. According to an exemplary embodiment of the invention, during a data read operation, the word lines and / or bit lines of the second layer 930A may be controlled differently from those of the first layer 920A.

[0123] Figure 15A and Figure 15B This illustrates an example of controlling bit lines differently from one layer to another. (See reference...) Figure 15A During data read operations, the precharge period of the bit lines of Layer 2 (930A) can be longer than that of the bit lines of Layer 1 (920A). In other words, by setting a longer precharge period for the bit lines of Layer 2 (930A), which have a relatively large capacitance component, the bit lines of Layer 2 (930A) can be precharged to 1.4V.

[0124] According to an embodiment, due to the characteristics of the multiple layers in the stacked structure, the threshold voltage (or voltage difference, to have turn-on cell characteristics) of the memory cell in the second layer 930A can be larger than that in the case of the first layer 920A. Therefore, during the precharge period, the bit line of the second layer 930A can be precharged to a higher level (e.g., 1.6V) than the bit line of the first layer 920A.

[0125] although Figure 15A The diagram shows that the pseudo-float period of the first layer 920A and the pseudo-float period of the second layer 930A have the same length, but the lengths of the pseudo-float periods can be set differently. Furthermore, in each of the first layer 920A and the second layer 930A, data readout can be performed after the bit line voltage changes to the target voltage.

[0126] Figure 15BAn example of a column switch control signal Ctrl_sw_C for controlling the column switches in the first layer 920A and the second layer 930A is shown. For example, as described above, the bit line of the second layer 930A can have a relatively large load, so the column switch can be more strongly turned on than the column switch of the first layer 920A during the pseudo-float period t2 to t4 of the second layer 930A. In other words, assuming the column switch is implemented as a PMOS transistor, the level of the column switch control signal Ctrl_sw_C provided to the second layer 930A during the pseudo-float period t2 to t4 of the second layer 930A can be lower than the level of the column switch control signal Ctrl_sw_C provided to the first layer 920A during the pseudo-float period t1 to t3 of the first layer 920A.

[0127] Figure 16 This is a circuit diagram illustrating an example of compensating for leakage current during a data read operation.

[0128] According to the above embodiments, the word line WL can be floated during data read operations, and due to various factors (e.g., multiple memory cells connected to the word line WL), leakage current may occur at the floating word line WL, thus changing the voltage level of the word line WL.

[0129] To compensate for the effects of leakage current, control operations can be performed on the row switch WS, or the compensation switch SW1 and the current source can be further connected to a node connected to the sense amplifier. Switching of the compensation switch SW1 can be controlled by the compensation control signal Ctrl_BC. Although in Figure 16 An example is shown in which the row switch WS and the compensation switch SW1 are both implemented as NMOS transistors, but embodiments of the present invention are not limited thereto.

[0130] To compensate for leakage current occurring in the floating word line WL, the row switch control signal Ctrl_sw_C, which controls the row switch WS during the floating period, can be changed from logic low level L to a higher level (e.g., intermediate level M) (e.g., from L to M). Therefore, the row switch WS can be weakly connected, a first precharge voltage Vol_R is provided to the word line WL, and leakage current can be compensated.

[0131] Furthermore, to compensate for leakage current, the compensation control signal Ctrl_BC can be changed from logic low L to logic high H (e.g., from L to H), thus electrically connecting the word line WL to a current source. As a result, the charge leaking from the word line WL can be compensated by the current source.

[0132] exist Figure 16In the illustrated embodiments, operations for compensating for leakage current can be performed in various ways. For example, based on the result of detecting the voltage of the word line WL, a compensation operation using at least one of a row switch WS and a current source can be performed. In some embodiments, the characteristics of the word line WL can be determined during the manufacturing and / or testing process of the memory device, and the memory device can be configured to apply the compensation operation when initially driving the memory device.

[0133] Figure 17 This is a block diagram illustrating an example of applying a memory device according to an embodiment of the present invention to an SSD system 600.

[0134] Reference Figure 17 The SSD system 600 may include a host 610 and an SSD 620. The SSD 620 exchanges signals SGL with the host 610 via a signal connector and receives power PWR via a power connector. The SSD 620 may include an SSD controller 621, an auxiliary power supply 622, and multiple memory systems (MEMs) 623, 624, and 625. The SSD controller 621 may be connected to the memory systems 623, 624, and 625 via multiple channels Ch1 to Chn, and each of the memory systems 623, 624, and 625 may include a memory controller and a resistive memory device. Furthermore, according to an exemplary embodiment of the present invention, the resistive memory device may include the memory device according to the above embodiments; therefore, during data read operations of the memory systems 623, 624, and 625, word lines and bit lines connected to selected word lines can be controlled according to the above embodiments.

[0135] Figure 18 This is a block diagram illustrating an embodiment of a memory system 700 according to various embodiments of the present invention. Figure 18 An example of a memory system 700 including a memory module 720 and a memory controller 710 is shown. The memory module 720 may correspond to the memory device of the above embodiments and / or may include multiple memory devices of the above embodiments.

[0136] Reference Figure 18 The memory controller 710 may include a processor that controls the overall operation of the memory system 700. Although in Figure 18 Not shown, but the memory controller 710 may also include various other components, such as a command / address generator, a host interface and / or a memory interface, as components for controlling memory operations.

[0137] Memory module 720 may include a plurality of memory chips mounted on a module board. For example, memory module 720 may include first memory chips 721_1 to Nth memory chips 721_N. Each of the first memory chips 721_1 to Nth memory chips 721_N may correspond to a memory device according to the above embodiments, and therefore, each of the first memory chips 721_1 to Nth memory chips 721_N may include a read controller that performs various control operations related to reading data in the above embodiments. For example, during a data read operation for the first memory chips 721_1 to Nth memory chips 721_N, a floating operation may be performed together on the word lines and bit lines connected to the selected memory cell.

[0138] The memory module 720 can be implemented as a single in-line memory module (SIMM) or a dual in-line memory module (DIMM). Furthermore, the memory module 720 can correspond to various types of DIMMs. For example, various types of DIMMs (e.g., fully buffered DIMMs (FB-DIMMs) and / or load-reduced DIMMs (LR-DIMMs)) can be applied to the memory module 720. In some embodiments, the memory module 720 can correspond to a non-volatile DIMM (NVDIMM), in which non-volatile memory 722 (e.g., flash memory) is installed to address the problem of volatile memory where data is lost when power is off.

[0139] Furthermore, as various types of modules, when the memory module 720 includes PRAM as resistive memory, the memory module 720 can be referred to as a P_DIMM. Embodiments of the inventive concept can be applied to various other types of modules. For example, when the memory module 720 includes a crosspoint memory chip with three-dimensional resistive memory cells, the memory module 720 can also be referred to as an XPoint DIMM (or 3D XPoint DIMM).

[0140] When memory module 720 corresponds to NVDIMM, it can operate based on various types of specifications such as NVDIMM-N and NVDIMM-P. Therefore, non-volatile memory 722 can be used for data storage and / or buffering. Additionally, each of the first memory chip 721_1 to the Nth memory chip 721_N can operate based on Double Data Rate (DDR) to send and receive data on both the rising and falling edges of the clock. Furthermore, in some embodiments, the memory device conceived according to the present invention can also be used to implement the non-volatile memory 722 of memory module 720.

[0141] Figure 19This is a block diagram illustrating an example of using a memory device from an embodiment of the present invention as a buffer for a controller 810.

[0142] Reference Figure 19 The memory system 800 may include a controller 810 and a flash memory device 820, and the flash memory device 820 may include flash memory cells 821 and control logic 822. The controller 810 may include a flash translation layer (FTL) 811 and may include a buffer 812 for temporarily storing data (DATA) and metadata (meta) provided to the flash memory device 820. The controller 810 may control the flash memory device 820 to read data stored in the flash memory cell 821 and / or program data into the flash memory cell 821 in response to write / read requests from the host. Specifically, the controller 810 may provide an address (ADD), a command (CMD), and / or a control signal (CTRL) to the flash memory device 820 to control programming, reading, and / or erasing operations of the flash memory device 820.

[0143] Buffer 812 may include a memory device according to the above embodiments, and therefore buffer 812 may include a resistive memory device. Additionally, according to the above embodiments, a data read operation may be performed based on a pseudo-float operation of word lines and / or bit lines to temporarily store data DATA and / or metadata meta in the resistive memory device and to read data DATA and / or metadata meta from the resistive memory device.

[0144] In the above embodiments, the memory device has been described as including a resistive memory device; however, the embodiments of the present invention are not limited thereto. For example, the embodiments of the present invention can be applied to various types of memory devices that perform data readout based on pre-charge operations on word lines and / or bit lines, and can also be applied to various types of volatile and non-volatile memory, such as DRAM, SRAM, flash memory devices, etc.

[0145] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it should be understood that various changes in form and detail may be made without departing from the scope of the appended claims.

Claims

1. A memory device, comprising: A memory cell array comprising multiple memory cells connected to multiple word lines and multiple bit lines; A row control circuit includes a plurality of row switches corresponding to the plurality of word lines and configured to perform a selection operation on the plurality of word lines; A column control circuit includes a plurality of column switches corresponding to the plurality of bit lines and configured to perform selection operations on the plurality of bit lines; as well as Control logic circuitry is configured to control a precharge operation on word lines among the plurality of word lines and bit lines among the plurality of bit lines connected to a selected memory cell during a data read operation, and to perform a control operation after the precharge period to float the word lines and bit lines together. Wherein, the word line is floated after the pre-charge period, and the bit line is pseudo-floating after the pre-charge period, and The control logic circuit is further configured to: pseudo-float the bit line by weakly turning on the column switch by providing a column switch control signal to the column switch connected to the bit line, the column switch control signal having a level between logic high and logic low.

2. The memory device according to claim 1, further comprising: A voltage generator is configured to provide a first pre-charge voltage to the row control circuit and a second pre-charge voltage to the column control circuit; as well as A write driver / read amplifier is configured to provide write data to the memory cell array via the row control circuitry and to output read data from the memory cell array. The row control circuit includes a word line driver configured to provide the first pre-charge voltage to the word line, and wherein one of the plurality of row switches is configured to control the electrical connection between the word line driver and the word line. The column control circuit includes a bit line driver configured to provide the second precharge voltage to the bit line, and wherein one of the plurality of column switches is configured to control the electrical connection between the bit line driver and the bit line.

3. The memory device according to claim 1, wherein, The storage unit includes a phase change storage unit, which includes a mixture of germanium, antimony, and tellurium.

4. The memory device according to claim 1, wherein, The control logic circuit is also configured to float the word line by providing a row switch control signal to the row switch connected to the word line.

5. The memory device according to claim 1, wherein, The data read operation also includes a floating period and a data readout period following the pre-charging period, and During the pre-charge period, the word line is pre-charged to a first level corresponding to a negative target voltage, and the bit line is pre-charged to a third level lower than a second level corresponding to a positive target voltage.

6. The memory device according to claim 5, wherein, During the pre-charge period, a pre-charge voltage having a third level lower than the positive target voltage is provided to the bit line.

7. The memory device according to claim 5, wherein, The bit line includes a first capacitance component that is greater than the second capacitance component of the word line, and During the pre-charge period, a pre-charge voltage having a second level corresponding to the positive target voltage is provided to the bit line, and the bit line is pre-charged to a third level lower than the second level due to the load based on the first capacitance component.

8. The memory device according to claim 5, wherein, During the floating period, while the bit line is in pseudo-floating, the voltage level of the bit line rises to a second level corresponding to the positive target voltage.

9. The memory device according to claim 1, wherein, The word lines and the bit lines are configured to be controlled separately from each other. During the pre-charging period, the word lines are floated and the bit lines are pseudo-floated. During the period when the word line is floating, the bit line begins to be pseudo-floating.

10. The memory device according to claim 1, wherein, The selected memory cell's resistor state includes either a set state or a reset state, and During the pre-charge period, the voltage level difference between the word line and the bit line is maintained below or equal to a reference value, so that the selected memory cell maintains its off cell characteristics in both the set state and the reset state.

11. The memory device of claim 1, further comprising: Compensation switches and current sources are connected to the nodes of the word lines. The compensation switch is configured to turn on during the period when the word line is floating to electrically connect the current source to the word line.

12. The memory device according to claim 1, wherein, The memory cells are arranged in a vertically stacked first and second layer, and the bit lines of the second layer include a larger capacitance component compared to the bit lines of the first layer. During the data read operation, the first time point used to pseudo-float the bit line of the second layer is different from the second time point used to pseudo-float the bit line of the first layer.

13. The memory device of claim 12, further comprising: The third layer, which is located above the first and second layers, The third layer includes peripheral circuitry configured to control write and read operations of the storage cells in the first and second layers.

14. A memory device, comprising: The selected storage unit is configured to store data; The first and second lines are connected to the selected storage units; A first switch is configured to control the electrical connection between a first driver that drives the first line and the first line in response to a first switch control signal. as well as A second switch is configured to control the electrical connection between the second driver driving the second line and the second line in response to a second switch control signal. The data read operation for the selected storage cell includes a precharge period, a float period, and a data readout period. During the pre-charge period, the memory device is configured to provide a first pre-charge voltage corresponding to a negative target voltage to the first line, and a second pre-charge voltage corresponding to a positive target voltage to the second line, pre-charging the first line to the negative target voltage and pre-charging the second line to a level lower than the positive target voltage. During the floating period, the memory device is also configured to float the first line and pseudo-float the second line, and During the floating period, the memory device is also configured to weakly turn on the second switch to pseudo-float the second line in response to the second switch control signal, the second switch control signal having a level between logic high and logic low.

15. The memory device according to claim 14, wherein, At least a portion of the time period during which the first line is floating overlaps with the time period during which the second line is pseudo-floating.

16. The memory device of claim 14, wherein, During the floating period, the memory device is also configured to turn off the first switch in response to the first switch control signal.

17. The memory device according to claim 14, wherein, During the floating period, the memory device is also configured to raise the voltage of the second line to a level corresponding to the positive target voltage, and Wherein, after the voltage of the second line rises to the positive target voltage, the memory device is further configured to read the data by detecting the voltage of the first line during the data readout period.

18. The memory device according to claim 14, wherein, The first switch and the second switch are controlled separately from each other, and The memory device is further configured to begin pseudo-floating the second line during the period when the first line is floating.

19. A memory module, comprising: Module board; Multiple memory chips are mounted on the module board; as well as A non-volatile memory, mounted on the module board and configured to communicate with the memory chip. Each of the memory chips includes: A memory cell array comprising multiple memory cells connected to multiple word lines and multiple bit lines; A row control circuit includes a plurality of row switches corresponding to the plurality of word lines and configured to perform a selection operation on the plurality of word lines; A column control circuit includes a plurality of column switches corresponding to the plurality of bit lines and configured to perform selection operations on the plurality of bit lines; and Control logic circuitry is configured to control precharge operations on word lines among the plurality of word lines and bit lines among the plurality of bit lines connected to a selected memory cell during a read operation, and to perform control operations to float one of the word lines and the bit lines after the precharge period and to continue providing a precharge voltage to the other of the word lines and the bit lines after the precharge period. The read operation further includes a floating period and a data readout period following the pre-charging period. During the pre-charging period, the word line is pre-charged to a first level corresponding to the negative target voltage, and the bit line is pre-charged to a third level lower than the second level corresponding to the positive target voltage.

20. The memory module according to claim 19, wherein, During the floating period, the voltage level of the bit line rises to a second level corresponding to the positive target voltage.

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