Fin field effect transistor device and method for forming the same

Abstract

The present disclosure relates to a fin field effect transistor device and a method for forming the same. A semiconductor device includes: a first fin, a second fin, and a third fin, which protrude above a substrate, wherein the third fin is located between the first fin and the second fin; a gate dielectric layer, which is located above the first fin, the second fin, and the third fin; a first work function layer, which is located above the gate dielectric layer and in contact with the gate dielectric layer, wherein the first work function layer extends along a first sidewall and a first upper surface of the first fin; a second work function layer, which is located above the gate dielectric layer and in contact with the gate dielectric layer, wherein the second work function layer extends along a second sidewall and a second upper surface of the second fin, wherein the first work function layer and the second work function layer include different materials; and a first gate electrode, a second gate electrode, and a third gate electrode, wherein the first gate electrode is located above the first fin, the second gate electrode is located above the second fin, and the third gate electrode is located above the third fin.

Description

Technical Field

[0001] The present disclosure relates to fin field effect transistor devices and methods of forming the same. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the continuous improvement in the integration density of various electronic components, such as transistors, diodes, resistors, capacitors, etc. In most cases, this increase in integration density comes from the continuous reduction in minimum feature size, which allows more components to be integrated into a given area.

[0003] Fin field effect transistor (FinFET) devices are becoming widely used in integrated circuits. FinFET devices have a three-dimensional structure that includes a semiconductor fin protruding from a substrate. A gate structure configured to control the flow of charge carriers within a conductive channel of the FinFET device surrounds the semiconductor fin. For example, in a tri-gate FinFET device, the gate structure surrounds three sides of the semiconductor fin, thereby forming a conductive channel on the three sides of the semiconductor fin. Summary of the invention

[0004] According to an embodiment of the present disclosure, a method for forming a semiconductor device is provided, the method comprising: forming a dummy gate structure over a first fin, a second fin, and a third fin between the first fin and the second fin; forming a dielectric layer around the dummy gate structure; removing the dummy gate structure to form a groove in the dielectric layer, wherein the groove exposes the first fin, the second fin, and the third fin; forming a first work function layer and a second work function layer in the groove, wherein the first work function layer extends along a first side wall and a first upper surface of the first fin, and the second work function layer extends along a second side wall and a second upper surface of the second fin, wherein the first work function layer extends along a third side wall of the third fin and along a first portion of a third upper surface of the third fin, and the second work function layer extends along a fourth side wall of the third fin and along a second portion of the third upper surface of the third fin; and filling the groove by forming a conductive material over the first work function layer and over the second work function layer.

[0005] According to another embodiment of the present disclosure, a method for forming a semiconductor device is provided, the method comprising: forming a fin protruding above a substrate; forming a dummy gate structure above the fin; surrounding the dummy gate structure with a dielectric layer; and replacing the dummy gate structure with a metal gate, wherein the replacement comprises: removing the dummy gate structure to form a first gate trench, a second gate trench, and a third gate trench in the dielectric layer, wherein the third gate trench is located between the first gate trench and the second gate trench; forming a dummy gate structure along the sidewall and bottom of the first gate trench and along the third gate trench; A first work function layer is formed in a first area of ​​the first side wall and the bottom; a second work function layer is formed along the side wall and the bottom of the second gate trench and along the second area of ​​the second side wall and the bottom of the third gate trench, wherein the first work function layer and the second work function layer are work function layers of the same type; a third work function layer is formed in the first gate trench, the second gate trench and the third gate trench, wherein the third work function layer extends along the first work function layer and the second work function layer; and the first gate trench, the second gate trench and the third gate trench are filled with a conductive material.

[0006] According to another embodiment of the present disclosure, a semiconductor device is provided, including: a first fin, a second fin, and a third fin, wherein the first fin, the second fin, and the third fin protrude higher than a substrate, wherein the third fin is located between the first fin and the second fin; a gate dielectric layer, wherein the gate dielectric layer is located above the first fin, the second fin, and the third fin; a first work function layer, wherein the first work function layer is located above the gate dielectric layer and in contact with the gate dielectric layer, wherein the first work function layer extends along a first side wall and a first upper surface of the first fin; a second work function layer, wherein the second work function layer is located above the gate dielectric layer and in contact with the gate dielectric layer, wherein the second work function layer extends along a second side wall and a second upper surface of the second fin, wherein the first work function layer and the second work function layer include different materials; and a first gate electrode, a second gate electrode, and a third gate electrode, wherein the first gate electrode is located above the first fin, the second gate electrode is located above the second fin, and the third gate electrode is located above the third fin. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the present disclosure can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1A perspective view of a fin field effect transistor (FinFET) device is shown in accordance with some embodiments.

[0009] Figure 2-Figure 6 , Fig. 7A and Figure 7B Various views of a FinFET device at various stages of fabrication are shown according to one embodiment.

[0010] Figure 7C and Fig.7D In some embodiments, Fig. 7A Various cross-sectional views of the FinFET device shown in .

[0011] Figure 8-Figure 24 shows an additional stage of manufacture according to one embodiment Fig. 7A Various cross-sectional views of FinFET devices.

[0012] Fig.25A and Fig.25B A cross-sectional view of a semiconductor device at a stage of fabrication in one embodiment is shown.

[0013] Fig.26A and Fig.26B A cross-sectional view of a semiconductor device at a stage of fabrication in one embodiment is shown.

[0014] Fig.27A and Fig.27B A cross-sectional view of a semiconductor device at a stage of fabrication in one embodiment is shown.

[0015] Fig.28A and Fig.28B A cross-sectional view of a semiconductor device at a stage of fabrication in one embodiment is shown.

[0016] Fig.29A and Fig.29B A cross-sectional view of a semiconductor device at a stage of fabrication in one embodiment is shown.

[0017] Fig. 30A and Fig. 30B A cross-sectional view of a semiconductor device at a stage of fabrication in one embodiment is shown.

[0018] Fig.31A and Fig.31B A cross-sectional view of a semiconductor device at a stage of fabrication in one embodiment is shown.

[0019] Fig.32A and Fig.32B A cross-sectional view of a semiconductor device at a stage of fabrication in one embodiment is shown.

[0020] Figure 33-Figure 46Various views of a FinFET device at various stages of fabrication are shown according to one embodiment.

[0021] Fig.47 A flow chart of a method of manufacturing a semiconductor device according to some embodiments is shown. DETAILED DESCRIPTION

[0022] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact.

[0023] In addition, spatially relative terms (e.g., "below," "below," "below," "above," "upper," etc.) may be used herein to facilitate description of the relationship of one element or feature shown in the figures relative to another (some) elements or features. These spatially relative terms are intended to cover different orientations of the device in use or operation other than the orientation shown in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein should also be interpreted accordingly. Throughout the discussion herein, unless otherwise stated, the same or similar figure numbers in different figures represent the same or similar components formed by (one or more) the same or similar formation methods and using (one or more) the same or similar materials.

[0024] Embodiments of the present disclosure are discussed in the context of forming a FinFET device, and in particular, in the context of forming a work function layer of a FinFET device. Although the disclosed embodiments are discussed using FinFET devices as an example, the disclosed methods can also be used for other types of devices, such as planar devices.

[0025] Embodiments of the present disclosure include methods for forming different work function layer stacks in different transistors of a FinFET device. A selective wet etching process is used to remove a target material (e.g., a work function metal) without attacking other materials. The selective wet etching process and the disclosed deposition process allow for great flexibility in forming and adjusting the work function layer of each individual transistor in a FinFET device. In addition, the mixed work function layer stack allows for increased flexibility in the structure of the work function layer of the transistor. For example, the disclosed method allows for the formation of three different work function layers using two different work function materials.

[0026] Figure 1 An example of a FinFET 30 is shown in perspective view. The FinFET 30 includes a substrate 50 and a fin 64 protruding above the substrate 50. An isolation region 62 is formed on opposite sides of the fin 64, wherein the fin 64 protrudes above the isolation region 62. A gate dielectric 66 is along the sidewalls of the fin 64 and is located above the top surface of the fin 64, and a gate 68 is located above the gate dielectric 66. A source / drain region 80 is located in the fin 64 and on opposite sides of the gate dielectric 66 and the gate 68. Figure 1 Reference cross sections used in subsequent figures are also shown. Cross section BB extends along the longitudinal axis of gate 68 of FinFET 30. Cross section AA is perpendicular to cross section BB and along the longitudinal axis of fin 64 and in the direction of current flow, for example, between source / drain regions 80. Cross section CC is parallel to cross section BB and spans source / drain regions 80. For clarity, subsequent figures refer to these reference cross sections.

[0027] Figure 2-Figure 6 , Fig. 7A and Figure 7B Various views (eg, cross-sectional views, top views) of a FinFET device 100 are shown at various stages of fabrication according to one embodiment. The FinFET device 100 is similar to Figure 1 The FinFET 30 in FIG. 1 is similar to the FinFET 30 in FIG. 1 , but has multiple fins and multiple gate structures. Figure 2-Figure 5 A cross-sectional view of the FinFET device 100 along cross section BB is shown. Figure 6 , Fig. 7A , Figure 8 and Fig. 9 A cross-sectional view of the FinFET device 100 along cross section AA is shown. Figure 7B Shows Fig. 7A A top view of the FinFET device 100, and Figure 7C and Fig.7D Shows Fig. 7A 2 and 3. Various embodiments of the FinFET device 100 are cross-sectional views, but along cross section CC. Figure 10-Figure 18 The FinFET device 100 is shown along the cross section BB (see Figure 7B ) cross-sectional view. Fig.19 , Fig. 20 and Fig.21 The FinFET device 100 is shown along cross sections DD, EE and FF (see FIG. Figure 7B ) cross-sectional view. Fig. 22 , Fig.23 and Fig.24Cross-sectional views of the FinFET device 100 along cross sections DD, EE, and FF are shown, respectively.

[0028] Figure 2 A cross-sectional view of a substrate 50 is shown. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., doped with a P-type or N-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate includes a semiconductor material layer formed on an insulating layer. For example, the insulating layer may be a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate (typically a silicon substrate or a glass substrate). Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0029] refer to Figure 3 , using techniques such as photolithography and etching to pattern Figure 2 5. For example, a mask layer, such as a pad oxide layer 52 and an overlying pad nitride layer 56, is formed over the substrate 50. The pad oxide layer 52 may be a thin film including silicon oxide such as formed using a thermal oxidation process. The pad oxide layer 52 may serve as an adhesion layer between the substrate 50 and the overlying pad nitride layer 56. In some embodiments, the pad nitride layer 56 is formed of silicon nitride, silicon oxynitride, silicon carbonitride, etc. or a combination thereof, and may be formed using a process such as low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD).

[0030] The mask layer may be patterned using photolithography techniques. Typically, photolithography techniques utilize a photoresist material that is deposited, irradiated (exposed), and developed to remove a portion of the photoresist material. The remaining photoresist material protects the underlying material (e.g., the mask layer in this example) from subsequent processing steps (e.g., etching). In this example, the photoresist material is used to pattern the pad oxide layer 52 and the pad nitride layer 56 to form a patterned mask 58, as shown in FIG. Figure 3 shown.

[0031] The exposed portions of the substrate 50 are then patterned using a patterned mask 58 to form trenches 61, thereby defining semiconductor fins 64 (eg, 64A, 64B, and 64C) between adjacent trenches 61, as shown in FIG. Figure 3As shown. For simplicity, semiconductor fins 64A, 64B, and 64C may be collectively referred to as semiconductor fins 64, and each of semiconductor fins 64A, 64B, and 64C may be referred to as semiconductor fins 64. In some embodiments, semiconductor fins 64 are formed by etching trenches in substrate 50 using a process such as reactive ion etching (RIE), neutral beam etching (NBE), or the like, or a combination thereof. The etching may be anisotropic. In some embodiments, trenches 61 may be strips parallel to each other (viewed from the top) and closely spaced from each other. In some embodiments, trenches 61 may be continuous and surround semiconductor fins 64. Semiconductor fins 64 may also be referred to as fins 64 hereinafter.

[0032] The fins 64 may be patterned by any suitable method. For example, the fins 64 may be patterned using one or more photolithography processes, including double patterning or multi-patterning processes. Typically, the double patterning or multi-patterning process combines photolithography and self-alignment processes, allowing for the creation of patterns having a pitch smaller than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels may then be used to pattern the fins.

[0033] Figure 4 An insulating material is shown formed between adjacent semiconductor fins 64 to form isolation regions 62. The insulating material may be an oxide (e.g., silicon oxide), a nitride, etc., or a combination thereof, and may be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system, and post-curing to convert it to another material, such as an oxide), etc., or a combination thereof. Other insulating materials and / or other formation processes may be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process may be performed. A planarization process (e.g., chemical mechanical polishing (CMP)) may remove any excess insulating material and form coplanar top surfaces of the isolation regions 62 and the top surfaces of the semiconductor fins 64 (not shown). The patterned mask 58 may also be removed by a planarization process (see Figure 3 ).

[0034] In some embodiments, the isolation region 62 includes a liner, such as a liner oxide (not shown), at the interface between the isolation region 62 and the substrate 50 / semiconductor fin 64. In some embodiments, the liner oxide is formed to reduce crystal defects at the interface between the substrate 50 and the isolation region 62. Similarly, the liner oxide can also be used to reduce crystal defects at the interface between the semiconductor fin 64 and the isolation region 62. The liner oxide (e.g., silicon oxide) can be a thermal oxide formed by thermal oxidation of a surface layer of the substrate 50, but other suitable methods can also be used to form the liner oxide.

[0035] Next, the isolation region 62 is recessed to form a shallow trench isolation (STI) region 62. The isolation region 62 is recessed so that the upper portion of the semiconductor fin 64 protrudes from between adjacent STI regions 62. The top surface of the STI region 62 may have a flat surface (as shown), a convex surface, a concave surface (e.g., concave), or a combination thereof. By appropriate etching, the top surface of the STI region 62 may be formed to be flat, convex, and / or concave. The isolation region 62 may be recessed using an acceptable etching process (e.g., an etching process that is selective to the material of the isolation region 62). For example, dry etching or wet etching using diluted hydrofluoric acid (dHF) may be performed to recess the isolation region 62.

[0036] Figures 2 to 4 An embodiment of forming fins 64 is shown, but the fins can be formed in a variety of different processes. For example, the top of substrate 50 can be replaced with a suitable material (e.g., an epitaxial material suitable for the expected type (e.g., N-type or P-type) of semiconductor device to be formed). Thereafter, substrate 50 with the epitaxial material on the top is patterned to form semiconductor fins 64 including the epitaxial material.

[0037] As another example, a dielectric layer may be formed over a top surface of the substrate; trenches may be etched through the dielectric layer; homoepitaxial structures may be epitaxially grown in the trenches; and the dielectric layer may be recessed such that the homoepitaxial structures protrude from the dielectric layer to form fins.

[0038] In yet another example, a dielectric layer may be formed over a top surface of a substrate; trenches may be etched through the dielectric layer; a heteroepitaxial structure may be epitaxially grown in the trenches using a material different than the substrate; and the dielectric layer may be recessed such that the heteroepitaxial structure protrudes from the dielectric layer to form a fin.

[0039] In embodiments where epitaxial material(s) or epitaxial structures (e.g., heteroepitaxial structures or homoepitaxial structures) are grown, the grown material(s) or structures may be doped in situ during growth, which may avoid prior and subsequent implants, but in situ and implant doping may be used together. Additionally, it may be advantageous to epitaxially grow a different material in the NMOS region than in the PMOS region. In various embodiments, the fins 64 may include silicon germanium (Si x Ge 1-x , where x can be between 0 and 1), silicon carbide, pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. For example, available materials for forming III-V compound semiconductors include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, etc.

[0040] Figure 5 A dummy gate structure 75 is shown formed over the semiconductor fin 64. In some embodiments, the dummy gate structure 75 includes a gate dielectric 66 and a gate 68. A mask 70 may be formed over the dummy gate structure 75. To form the dummy gate structure 75, a dielectric layer is formed on the semiconductor fin 64. The dielectric layer may be, for example, silicon oxide, silicon nitride, multiple layers thereof, etc., and may be deposited or thermally grown.

[0041] A gate layer is formed over the dielectric layer, and a mask layer is formed over the gate layer. The gate layer may be deposited over the dielectric layer and then planarized, such as by CMP. The mask layer may be deposited over the gate layer. The gate layer may be formed, for example, of polysilicon, but other materials may also be used. The mask layer may be formed, for example, of silicon nitride.

[0042] After forming the layers (e.g., dielectric layer, gate layer, and mask layer), the mask layer may be patterned using acceptable photolithography and etching techniques to form mask 70. Then, the pattern of mask 70 may be transferred to the gate layer and the dielectric layer by acceptable etching techniques to form gate 68 and gate dielectric 66, respectively. Gate 68 and gate dielectric 66 cover the corresponding channel regions of semiconductor fin 64. Gate 68 may also have a length direction substantially perpendicular to the length direction of the corresponding semiconductor fin 64.

[0043] exist Figure 5In the example of FIG. 6 , gate dielectric 66 is shown as being formed over fin 64 (e.g., over the top surface and sidewalls of fin 64) and over STI region 62. In other embodiments, gate dielectric 66 may be formed by thermal oxidation of a material such as fin 64, and thus may be formed over fin 64 but not over STI region 62. These and other variations are fully intended to be included within the scope of the present disclosure.

[0044] Figure 6 , Fig. 7A , Figure 8 and Fig. 9 A further processed cross-sectional view of the FinFET device 100 along cross section AA (along the longitudinal axis of the fin 64 ) is shown. Figure 7B Shows Fig. 7A FIG. 1 is a top view of a FinFET device 100 . Figure 7C and Fig.7D Shows Fig. 7A FIG. 1 is a cross-sectional view of various embodiments of the FinFET device 100 , but along cross section CC. Note that Figure 6 , Fig. 7A , Figure 7B and Figure 8 , three dummy gate structures 75 (eg, 75A, 75B, and 75C) are formed over fin 64. Those skilled in the art will appreciate that more or less than three dummy gate structures may be formed over fin 64, and these and other variations are fully intended to be included within the scope of the present disclosure.

[0045] like Figure 6 As shown, a lightly doped drain (LDD) region 65 is formed in the fin 64. The LDD region 65 may be formed by a plasma doping process. The plasma doping process may include forming and patterning a mask such as a photoresist to cover the area of ​​the FinFET to be protected from the plasma doping process. The plasma doping process may implant N-type or P-type impurities in the fin 64 to form the LDD region 65. For example, a P-type impurity (e.g., boron) may be implanted in the fin 64 to form an LDD region 65 for a P-type device. As another example, an N-type impurity (e.g., phosphorus) may be implanted in the fin 64 to form an LDD region 65 for an N-type device. In some embodiments, the LDD region 65 is adjacent to the channel region of the FinFET device 100. Portions of the LDD region 65 may extend under the gate 68 and into the channel region of the FinFET device 100. Figure 6A non-limiting example of an LDD region 65 is shown. Other configurations, shapes, and methods of forming the LDD region 65 are also possible and are fully intended to be included within the scope of the present disclosure. For example, the LDD region 65 may be formed after forming the gate spacer 76. In some embodiments, the LDD region 65 is omitted.

[0046] Still reference Figure 6 , after forming the LDD region 65, a gate spacer 76 is formed on the gate structure. The gate spacer 76 may include a first gate spacer 72 and a second gate spacer 74. For example, the first gate spacer 72 may be a gate sealing spacer and is formed on the opposite sidewalls of the gate 68 and the opposite sidewalls of the gate dielectric 66. The second gate spacer 74 is formed on the first gate spacer 72. The first gate spacer 72 may be formed of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, etc. or a combination thereof, and may be formed using a deposition process such as thermal oxidation, chemical vapor deposition (CVD) or other suitable deposition processes. The second gate spacer 74 may be formed of silicon nitride, silicon carbonitride, a combination thereof, etc. using a suitable deposition method.

[0047] In an exemplary embodiment, the gate spacer 76 is formed by first conformally depositing a first gate spacer layer over the FinFET device 100, and then conformally depositing a second gate spacer layer over the deposited first gate spacer layer. Next, an anisotropic etching process (e.g., a dry etching process) is performed to remove a first portion of the second gate spacer layer disposed on an upper surface of the FinFET device 100 (e.g., an upper surface of the mask 70), while maintaining a second portion of the second gate spacer layer disposed along the sidewall of the dummy gate structure 75. The second portion of the second gate spacer layer remaining after the anisotropic etching process forms the second gate spacer 74. The anisotropic etching process also removes a portion of the first gate spacer layer disposed outside the sidewall of the second gate spacer 74, and the remaining portion of the first gate spacer layer forms the first gate spacer 72.

[0048] like Figure 6 The shapes and formation methods of the gate spacers 76 shown in are only non-limiting examples, and other shapes and formation methods are possible. These and other variations are fully intended to be included within the scope of the present disclosure.

[0049] Next, if Fig. 7AAs shown, source / drain regions 80 are formed. The source / drain regions 80 are formed by etching the fins 64 (e.g., in the LDD regions 65) to form recesses, and epitaxially growing material in the recesses using a suitable method (e.g., metal organic CVD (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), etc., or a combination thereof).

[0050] like Fig. 7A As shown, the epitaxial source / drain regions 80 may have surfaces that are raised from the corresponding surfaces of the fins 64 (e.g., raised above the non-recessed portions of the fins 64) and may have facets. The source / drain regions 80 of adjacent fins 64 may merge to form a continuous epitaxial source / drain region 80 (see Figure 7C In some embodiments, the source / drain regions 80 of adjacent fins 64 are not merged together and remain separate source / drain regions 80 (see Fig.7D ). Figure 7C and Fig.7D Also shown are spacers 76 ′ along opposing sidewalls of the fin 64 , which may have the same or similar structure as the gate spacers 76 and may be formed in the same process step(s) as the gate spacers 76 .

[0051] The epitaxial source / drain regions 80 may be implanted with dopants to form the source / drain regions 80, followed by an annealing process. The implantation process may include forming and patterning a mask (e.g., a photoresist) to cover the areas of the FinFET to be protected from the implantation process. The source / drain regions 80 may have a thickness of about 1E19 cm -3 to about 1E21 cm -3 The impurity (e.g., dopant) concentration may be within a range of . P-type impurities (e.g., boron or indium) may be implanted in the source / drain region 80 of a P-type transistor. N-type impurities (e.g., phosphorus or arsenide) may be implanted in the source / drain region 80 of an N-type transistor. In some embodiments, the epitaxial source / drain region may be doped in situ during growth.

[0052] Figure 7B Shows Fig. 7A FIG. 1 is a top view of the FinFET device 100. Figure 7B 64 (eg, 64A, 64B, and 64C), wherein three dummy gate structures 75 (eg, 75A, 75B, and 75C) are formed over the fins 64. Figure 7B Not all features of the FinFET device 100 are shown. For example, the gate spacer 76 and the source / drain regions 80 are not shown. Figure 7BCross sections DD, EE, and FF are also shown, which are parallel to cross section AA and cut dummy gate structure 75C along fins 64A, 64B, and 64C, respectively. Figure 7B Cross sections D2 - D2 and D3 - D3 are also shown, which are parallel to cross section AA and cut along fin 64A along dummy gate structures 75B and 75A, respectively.

[0053] Next, in Figure 8 In the embodiment, a first interlayer dielectric (ILD) 90 is formed over the substrate 50 and over the dummy gate structures 75 (e.g., 75A, 75B, 75C). In some embodiments, the first ILD 90 is formed of a dielectric material (e.g., silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.), and may be deposited by any suitable method (e.g., CVD, PECVD, or FCVD). A planarization process (e.g., a CMP process) may be performed to remove the mask 70 (see FIG. 1 ). Fig. 7A After the planarization process, the top surface of the first ILD 90 is flush with the top surface of the gate 68. Figure 8 shown.

[0054] An embodiment gate-last process (sometimes referred to as a replacement gate process) is then performed to replace each dummy gate structure 75 with an active gate structure (also referred to as a replacement gate or metal gate). Thus, gate 68 and gate dielectric 66 are considered dummy gate structures in the gate-last process.

[0055] refer to Fig. 9 , the dummy gate structures 75A, 75B, and 75C are removed to form recesses 69A, 69B, and 69C in the first ILD 90, respectively. For simplicity, recesses 69A, 69B, and 69C may be collectively referred to as recesses 69, and each of recesses 69A, 69B, and 69C may be referred to as recesses 69. According to some embodiments, gate 68 and gate dielectric 66 directly below gate 68 are removed in (one or more) etching steps, so that recesses 69 (e.g., 69A, 69B, and 69C) are formed between gate spacers 76. Each recess 69 exposes a channel region of a corresponding fin 64. During dummy gate removal, when dummy gate 68 is etched, dummy gate dielectric 66 may be used as an etch stop layer. Dummy gate dielectric 66 may then be removed after dummy gate 68 is removed. Since a replacement gate is subsequently formed in recess 69, recess 69 is also referred to as gate trench 69.

[0056] Next, in Fig.10In the embodiment of the present invention, the gate dielectric layer 82 is conformally deposited in the recess 69 (e.g., on the top surface and sidewalls of the fin 64), and on the sidewalls of the gate spacer 76. The gate dielectric layer 82 may also be formed on the top surface of the first ILD 90. According to some embodiments, the gate dielectric layer 82 includes silicon oxide, silicon nitride, or multiple layers thereof. In other embodiments, the gate dielectric layer 82 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 82 may have a k value greater than about 7.0 and may include metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The formation method of the gate dielectric layer 82 may include molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD, etc.

[0057] After forming the gate dielectric layer 82, a P-type work function layer 84 is formed over the gate dielectric layer 82 (e.g., conformally). Exemplary P-type work function metals include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable P-type work function materials, or combinations thereof. In the illustrated embodiment, the P-type work function layer 84 is formed of a titanium-containing material such as titanium nitride (TiN) or titanium (Ti). The thickness of the P-type work function layer 84 is between about 10 angstroms and about 30 angstroms. The work function value is associated with the material composition of the work function layer, and therefore, the material of the work function layer is selected to adjust its work function value so that a target threshold voltage Vt is achieved in the device to be formed. The work function layer can be deposited by CVD, physical vapor deposition (PVD), ALD, or other suitable processes.

[0058] Next, in Fig.11 in Fig.10 A photoresist including a bottom anti-reflective coating (BARC) 86 and a top photoresist 88 is formed above the FinFET device 100. The photoresist may further include an intermediate layer (not shown). After forming the photoresist, the photoresist fills the space between the fins 64, such as Fig.11As shown. Next, the top photoresist 88 is patterned to form an opening 71 that is located above (e.g., directly above) a portion (e.g., the right portion) of the fin 64B and above the fin 64C. In one embodiment, the top photoresist 88 is patterned by exposing the top photoresist 88 to a patterned energy source (e.g., light) through, for example, an intermediate mask. The impact of the energy will cause a chemical reaction in those portions of the photosensitive material that are affected by the patterned energy source, thereby changing the physical properties of the exposed portions of the photoresist, so that the physical properties of the exposed portions of the top photoresist 88 are different from the physical properties of the unexposed portions of the top photoresist 88. The top photoresist 88 can then be developed with, for example, a developer to separate the exposed portions of the top photoresist 88 from the unexposed portions of the top photoresist 88.

[0059] Next, in Fig.12 In the embodiment, the pattern of the top photoresist 88 extends toward the substrate 50 and is transferred to the BARC layer 86 using an isotropic etching process (e.g., a plasma etching process) such that a portion of the P-type work function layer 84 located below the opening 71 is exposed. The top photoresist 88 can also be removed by an anisotropic etching process.

[0060] Next, a wet etching process 81 is performed to selectively remove the exposed portion of the P-type work function layer 84. The wet etching process 81 uses a first etching chemical W1 that is selective to the P-type work function layer 84 (e.g., has a higher etching rate for the P-type work function layer 84). In some embodiments, the first etching chemical W1 includes an etchant and an oxidant. In one embodiment, the etchant is an acid, such as hydrogen chloride (HCl), phosphoric acid (H3PO4), etc. In another embodiment, the etchant is a base, such as ammonium hydroxide (NH4OH). The oxidant used in the first etching chemical W1 may be, for example, hydrogen peroxide (H2O2). In some embodiments, an etchant (e.g., a base or an acid) and an oxidant are mixed in an aqueous solution (e.g., in deionized water (DIW)) to form the first etching chemical W1. The concentration (e.g., volume concentration) of the etchant and the oxidant in the first etching chemical W1 is higher than about 1%, for example, between about 1% and about 10%. The wet etching process 81 may be performed at a temperature between about 40°C and about 70°C, and the duration is between about 1 minute and about 5 minutes. Due to the etching selectivity of the wet etching process 81, the exposed portion of the P-type work function layer 84 is removed (see Fig.13 ) without substantially corroding the underlying gate dielectric layer 82.

[0061] Next, in Fig.13, BARC layer 86 is removed using a suitable removal method (e.g., ashing). The remaining portions of P-type work function layer 84 are exposed, which are disposed over fin 64A and over a portion (e.g., the left portion) of fin 64B. Portions of gate dielectric layer 82 located over the right portion of fin 64B and over fin 64C are also exposed.

[0062] Next, in Fig.14 in Fig.13 A P-type work function layer 83 is conformally formed above the FinFET device 100. Fig.14 In the example of FIG. 1 , the P-type work function layer 83 is located above and in contact with the P-type work function layer 84 (the remaining portion) and the exposed portion of the gate dielectric layer 82. The P-type work function layer 83 is formed of a P-type work function material that is different from the P-type work function material of the P-type work function layer 84. In the illustrated embodiment, the P-type work function layer 83 is formed of a tungsten-containing material (e.g., tungsten, tungsten nitride, tungsten carbide, or tungsten oxide) and can be formed by a suitable deposition method (e.g., CVD, PVD, ALD, etc.). The thickness of the P-type work function layer 83 can be between about 10 angstroms and about 30 angstroms.

[0063] Next, in Fig.13 A photoresist including a bottom anti-reflective coating (BARC) 86 and a top photoresist 88 is formed above the FinFET device 100. The photoresist may further include an intermediate layer (not shown). After forming the photoresist, the photoresist fills the space between the fins 64, such as Fig.14 Next, top photoresist 88 is patterned to form opening 73 that is located over (eg, directly over) a portion (eg, the left portion) of fin 64B and over fin 64A.

[0064] Next, in Fig.15 In the embodiment, the pattern of the top photoresist 88 extends toward the substrate 50 and is transferred to the BARC layer 86 using an isotropic etching process (e.g., a plasma etching process) such that a portion of the P-type work function layer 83 located below the opening 73 is exposed. The top photoresist 88 may also be removed by an anisotropic etching process.

[0065] Next, in Fig.16In the embodiment of the present invention, a wet etching process 111 is performed to selectively remove the exposed portion of the P-type work function layer 83. The wet etching process uses a second etching chemical W2 that is selective to the P-type work function layer 83. In some embodiments, the second etching chemical W2 includes an etchant and an oxidant. In one embodiment, the etchant is an acid, such as hydrogen chloride (HCl), phosphoric acid (H3PO4), bicarbonate, etc. The oxidant used in the second etching chemical W2 can be, for example, ozone (O3). In some embodiments, an etchant (e.g., an acid) and an oxidant are mixed in an aqueous solution (e.g., in deionized water (DIW)) to form a second etching chemical W2. The concentration (e.g., volume concentration) of the etchant and the oxidant in the second etching chemical W2 is higher than about 1%, for example, between about 1% and about 10%. The wet etching process 111 can be performed at room temperature and lasts for between about 1 minute and about 5 minutes. Due to the etching selectivity of the wet etching process 111, the exposed portion of the P-type work function layer 83 is removed without substantially corroding the underlying gate dielectric layer 82.

[0066] Next, in Fig.17 In the embodiment, the BARC layer 86 is removed using a suitable removal method (e.g., ashing). The (remaining portions of) the P-type work function layers 84 and 83 extend along the gate dielectric layer 82 and contact the gate dielectric layer 82. Fig.17 In the example of FIG. 1 , P-type work function layer 84 extends along the sidewall and upper surface of fin 64A, along the left sidewall of fin 64B, and along the left portion of the upper surface of fin 68B. P-type work function layer 83 extends along the sidewall and upper surface of fin 64C, along the right sidewall of fin 64B, and along the right portion of the upper surface of fin 68B.

[0067] Next, in Fig.18 , the N-type work function layer 85 is conformally formed over and in contact (e.g., physically in contact) with the P-type work function layers 84 and 83. Exemplary N-type work function metals include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable N-type work function materials, or combinations thereof. In the illustrated embodiment, the N-type work function layer 85 is formed of an aluminum-containing material (e.g., aluminum, aluminum carbide, or aluminum nitride) and is formed by a suitable formation method (e.g., PVD, CVD, ALD, etc.). As an example, the thickness of the N-type work function layer 85 can be between about 10 angstroms and about 30 angstroms.

[0068] Next, a glue layer 87 is conformally formed over the N-type work function layer 85. The glue layer 87 may serve as an adhesion layer between the N-type work function layer 85 and the subsequently formed conductive material 93. The glue layer 87 may be formed of a suitable material (e.g., titanium, titanium nitride, or tantalum nitride) using any suitable formation method. In some embodiments, the glue layer 87 is omitted.

[0069] Next, a conductive material 93 is formed over the N-type work function layer 85, and if the conductive material 93 is formed, the conductive material 93 is located over the glue layer 87. The conductive material 93 (also referred to as a filling metal) fills the groove 69 (see, for example, FIG. 1 ). Fig. 9 69A, 69B and 69C in FIG. 69A and 69B) and form a gate electrode of a metal gate. In one embodiment, the conductive material 93 is tungsten, but other suitable conductive materials may also be used, such as cobalt, gold, copper, aluminum, combinations thereof, etc. The conductive material 93 may be formed using a suitable formation method (e.g., electroplating, CVD, PVD, ALD, etc.).

[0070] In some embodiments, a cut metal gate process is performed to cut the conductive material 93 and various underlying layers (e.g., 87, 85, 84, 83, and 82) to form separate metal gates 97A, 97B, and 97C over the fins 64A, 64B, and 64C, respectively. For simplicity, the metal gates 97A, 97B, and 97C may be collectively referred to as metal gates 97, and each of the metal gates 97A, 97B, and 97C may be referred to as metal gates 97. In the exemplary cut metal gate process, Fig.18 In the cross-sectional view of FIG. 1 , openings (e.g., vias) are formed between adjacent fins 64, the openings cutting through the conductive material 93 (e.g., in the top view) and extending from the conductive material 93 to the STI region 62. Dielectric material(s) (e.g., silicon nitride, silicon oxide, etc.) are formed in the openings to form dielectric cutting patterns 107, which cut the conductive material 93 and various underlying layers (e.g., 87, 85, 84, 83, and 82) to form separate metal gates 97A, 97B, and 97C.

[0071] exist Fig.18In the example of , metal gate 97A has a P-type work function layer 84 extending along the sidewall and upper surface of fin 64A, and an N-type work function layer 85 located above the P-type work function layer 84. Metal gate 97C has a P-type work function layer 83 extending along the sidewall and upper surface of fin 64C, and an N-type work function layer 85 located above the P-type work function layer 83. Metal gate 97B has a P-type work function layer 84 / 83 extending along and in contact with gate dielectric layer 82, and has an N-type work function layer 85 located above the P-type work function layer 84 / 83. In particular, metal gate 97B has a first sidewall (e.g., Fig.18 ) and along a first portion of an upper surface of fin 64B (eg, Fig.18 In addition, the metal gate 97B has a P-type work function layer 84 extending along the second sidewall of the fin 64B (eg, Fig.18 ) and along a second portion of the upper surface of fin 64B (eg, Fig.18 The P-type work function layer 83 extending from the right side of the metal gate (in the figure). The various work function layers in the metal gate are collectively referred to as a work function layer stack. Due to the mixing of the P-type work function layers 84 / 83, the metal gate 97B is referred to as having a mixed work function layer stack.

[0072] The embodiments disclosed herein allow different metal gates (e.g., 97A, 97B, and 97C) to have different combinations of work function layers. The disclosed wet etching process is highly selective, which allows the removal of a specific work function layer (one or more layers) without attacking other layers in the metal gate. This allows for flexible selection of work function layers in different metal gates, which in turn allows for different threshold voltages and performance for different metal gates.

[0073] Fig.19 Shows Fig.18 The metal gate 97A is taken along the cross section DD (see Figure 7B ) cross-sectional view. Fig. 20 Shows Fig.18 A cross-sectional view of the metal gate 97B along the cross section EE (see Figure 7B ). Fig.21 Shows Fig.18 The metal gate 97C is taken along the cross section FF (see Figure 7B ) cross-sectional view.

[0074] Fig.19 The gate trench is shown (see, for example, Fig. 9 The conductive material 93 fills the metal gate 97A in the upper surface of the first ILD 90 and the metal gate 97A in the upper surface of the first ILD 90 (for example, 82, 84, 85, 87 and 93). Fig.19In some embodiments, when the gate trench is too narrow, the gate trench is completely filled after the glue layer 87 is formed, and thus, the conductive material 93 is formed over the upper surface of the glue layer 87. In other words, in some embodiments where the gate trench is too narrow, the conductive material 93 is not formed in the region where the gate trench is located. Fig.19 The portion shown below the dashed line 87A (which is along the upper surface of the glue layer 87), and instead, the glue layer 87 fills the central portion of the gate trench. Similar modifications to the metal gate due to the narrow gate trench are possible for other metal gates (e.g., 97B, 97C), and the details are not repeated below.

[0075] Fig. 20 The gate trench is shown (see, for example, Fig. 9 69A, 69B, 69C in FIG. 69B ) and various layers (e.g., 82, 83, 84, 85, 87, and 93) of the metal gate 97B above the upper surface of the first ILD 90. Note that the metal gate 97B has two different P-type work function layers 84 and 83 that extend along the gate dielectric layer 82 and contact the gate dielectric layer 82.

[0076] Fig.21 The gate trench is shown (see, for example, Fig. 9 69A, 69B, 69C) and various layers (eg, 82, 83, 85, 87, and 93) of the metal gate 97C above the upper surface of the first ILD 90. The P-type work function layer 83 of the metal gate 97C is different from the P-type work function layer 84 of the metal gate 97A.

[0077] Fig. 22 , Fig.23 and Fig.24 After the additional process Fig.19 , Fig. 20 and Fig.21 . In particular, a planarization process (e.g., CMP) is performed to remove excess portions of a metal gate 97 disposed above an upper surface of a first ILD 90. Next, a second ILD 92 is formed over the first ILD 90, and a contact 102 (also referred to as a contact plug) electrically coupled to an underlying conductive feature (e.g., source / drain region 80 or metal gate 97) is formed. Details will be discussed below.

[0078] refer to Fig. 22 , Fig.23 and Fig.24, a second ILD 92 is formed over the first ILD 90. In an embodiment, the second ILD 92 is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD 92 is formed of a dielectric material (e.g., PSG, BSG, BPSG, USG, etc.) and can be deposited by any suitable method (e.g., CVD and PECVD).

[0079] Next, contact openings are formed through the second ILD 92 to expose the metal gates 97 (eg, 97A, 97B, 97C). Contact openings are also formed through the first ILD 90 and the second ILD 92 to expose the source / drain regions 80. The contact openings may be formed using photolithography and etching.

[0080] After forming the contact openings, a silicide region 95 is formed over the source / drain region 80. In some embodiments, the silicide region 95 is formed by first depositing a metal capable of reacting with a semiconductor material (e.g., silicon, germanium) over the exposed portion of the source / drain region 80 to form a silicide or germanide region, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or alloys thereof, and then performing a thermal annealing process to form the silicide region 95. The unreacted portion of the deposited metal is then removed, for example, by an etching process. Although the region 95 is referred to as a silicide region, the region 95 may also be a germanide region or a silicon germanide region (e.g., a region including silicide and germanide).

[0081] Next, contacts 102 (e.g., 102A or 102B) are formed in the contact openings. In the illustrated embodiment, each contact 102 includes a barrier layer 101, a seed layer 103, and a conductive material 105, and is electrically coupled to an underlying conductive feature (e.g., a metal gate 97 or a silicide region 95). The contact 102A electrically coupled to the metal gate 97 may be referred to as a gate contact, and the contact 102B electrically coupled to the silicide region 95 may be referred to as a source / drain contact.

[0082] In some embodiments, barrier layer 101 is conformally formed along the sidewalls and bottom of the contact opening. Barrier layer 101 may include a conductive material, such as titanium nitride, but other materials, such as tantalum nitride, titanium, tantalum, etc., may alternatively be used. Barrier layer 101 may be formed using a CVD process such as PECVD. However, other alternative processes, such as sputtering, metal organic chemical vapor deposition (MOCVD), or ALD may alternatively be used.

[0083] Next, a seed layer 103 is conformally formed over the barrier layer 101. The seed layer 103 may include copper, titanium, tantalum, titanium nitride, tantalum nitride, etc., or a combination thereof, and may be deposited by ALD, sputtering, PVD, etc. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer including multiple sublayers formed of different materials. For example, the seed layer 103 may include a titanium layer and a copper layer located above the titanium layer.

[0084] Next, a conductive material 105 is deposited over the seed layer 103 and fills the remaining portion of the contact opening. The conductive material 105 may be made of a metal-containing material (e.g., gold, aluminum, tungsten, cobalt, etc.), a combination thereof, or multiple layers thereof, and may be formed by, for example, electroplating, electroless plating, or other suitable methods. After forming the conductive material 105, a planarization process such as CMP may be performed to remove excess portions of the barrier layer 101, the seed layer 103, and the conductive material 105, which are located above the top surface of the second ILD 92. Thus, the resulting remaining portions of the barrier layer 101, the seed layer 103, and the conductive material 105 form the contact 102 of the resulting FinFET device 100.

[0085] Variations to the disclosed embodiments are possible and are fully intended to be included within the scope of this disclosure. Fig.18 In the example of FIG. 5 , the sidewall 84S of the P-type work function layer 84 abuts (e.g., physically contacts or connects) the sidewall 83S of the P-type work function layer 83 at the upper surface of the fin 64B. However, due to process variations and / or inaccuracies of a photolithography process (e.g., a photolithography process used to form the patterned top photoresist 88), the location where the P-type work function layer 84 / 83 is connected and / or the shape of the P-type work function layer 84 / 83 at the location where the P-type work function layer 84 / 83 is connected may be different from the sidewall 84S of the P-type work function layer 84 at the upper surface of the fin 64B. Fig.18 (and Fig. 20 Various alternative embodiments are discussed below.

[0086] Fig.25A and Fig.25B Cross-sectional views of the FinFET device 100A along different cross sections at fabrication stages in one embodiment are shown. For simplicity, only a portion of the FinFET device 100A surrounding the fin 64 is shown. Additionally, details of certain features such as the gate spacer 76 may be simplified. Fig.25A The FinFET device 100A shown in FIG. 1 is similar to Fig.18 The FinFET device 100 is shown in FIG. Fig.25B Shows Fig.25A 1 and 2 are corresponding cross-sectional views of the gate trenches of the metal gates 97A, 97B and 97C shown in FIG.

[0087] exist Fig.25A and Fig.25B In the embodiment of the present invention, at the position where the P-type work function layers 84 and 83 are adjacent, a portion of the P-type work function layer 83 extends above the upper surface 84U of the P-type work function layer 84. As a result, the first side wall 83S1 of the P-type work function layer 83 is in physical contact with the side wall of the P-type work function layer 84, and the second side wall 83S2 of the P-type work function layer 83 is disposed above the upper surface 84U of the P-type work function layer 84.

[0088] Fig.26A and Fig.26B Cross-sectional views of a FinFET device 100B along different cross sections at fabrication stages in one embodiment are shown. Fig.26A and Fig.26B An embodiment similar to Fig.25A and Fig.25B However, the P-type work function layers 83 and 84 are not connected to each other above the upper surface of the fin 64B, and there is a gap between the P-type work function layers 83 and 84. As a result, a portion of the N-type work function layer 85 fills the gap and physically contacts the gate dielectric layer 82 and the corresponding sidewalls of the P-type work function layers 83 / 84.

[0089] Fig.27A and Fig.27B Cross-sectional views of a FinFET device 100C along different cross sections at fabrication stages in one embodiment are shown. Fig.27A and Fig.27B An embodiment similar to Fig.25A and Fig.25B However, if Fig.27A As shown, the P-type work function layer 83 extends along the first sidewall (eg, right sidewall) and upper surface of the fin 64B, and the P-type work function layer 84 extends along the second sidewall (eg, left sidewall) of the fin 64B, but not along the upper surface of the fin 64B.

[0090] Fig.28A and Fig.28B Cross-sectional views along different cross sections of a FinFET device 100D at fabrication stages in one embodiment are shown. Fig.28A and Fig.28B An embodiment similar to Fig.25A and Fig.25B However, if Fig.28A As shown, the P-type work function layer 83 extends along the first side wall (e.g., right side wall), the upper surface, and the upper portion of the second side wall (e.g., left side wall) of the fin 64B, and the P-type work function layer 84 extends along the lower portion of the second side wall of the fin 64B, but does not extend along the upper surface of the fin 64B. Therefore, the P-type work function layer 84 is adjacent to the P-type work function layer 83 at a position close to the second side wall of the fin 64B.

[0091] Fig.29A and Fig.29B Cross-sectional views of a FinFET device 100E along different cross sections at fabrication stages in one embodiment are shown. Fig.29A and Fig.29B An embodiment similar to Fig.28A and Fig.28B However, with Fig.28A and Fig.28B Unlike the embodiment of the present invention, the P-type work function layer 84 does not abut the P-type work function layer 83 at a position close to the second sidewall of the fin 64B. Instead, there is a gap between the P-type work function layers 83 and 84, and therefore, the N-type work function layer 85 fills the second sidewall close to the fin 64B (e.g., Fig.29A The gap at the position of the left side wall).

[0092] Fig. 30A and Fig. 30B Cross-sectional views of a FinFET device 100F along different cross sections at fabrication stages in one embodiment are shown. Fig. 30A An embodiment similar to Fig.18 Embodiment of the invention. Fig. 30B Shows Fig. 30A An embodiment of a cross-sectional view of a gate trench of a FinFET device. Fig. 30A and Fig. 30B In the embodiment of the present invention, before forming the P-type work function layer 84 / 83, a layer 89 is conformally formed above the gate dielectric layer 82. In some embodiments, layer 89 is a P-work function layer or a barrier layer and is formed of a tantalum-containing material (e.g., tantalum or tantalum nitride) or a titanium-containing material (e.g., titanium nitride). In some embodiments, layer 89 is an etch stop layer and is formed of a silicon-based material (e.g., silicon nitride or silicon oxide). The thickness of layer 89 can be between about 10 angstroms and about 30 angstroms. A suitable formation method (e.g., CVD, PVD, ALD, etc.) can be used to form layer 89.

[0093] Fig.31A and Fig.31B Cross-sectional views of a FinFET device 100G along different cross sections at fabrication stages in one embodiment are shown. Fig.31A An embodiment similar to Fig.18 Embodiment of the invention. Fig.31B Shows Fig.31A An embodiment of a cross-sectional view of a gate trench of a FinFET device. Fig.31A and Fig.31BIn the embodiment, the cap layer 91 is formed directly above the P-type work function layer 83 and contacts the P-type work function layer 83. The sidewalls of the cap layer 91 are vertically aligned with the corresponding sidewalls of the P-type work function layer 83. The first sidewall (e.g., left sidewall) of the cap layer 91 and the first sidewall (e.g., left sidewall) of the P-type work function layer 83 contact the corresponding sidewalls of the P-type work function layer 84. The cap layer 91 can be formed of a silicon-containing material (e.g., silicon nitride or silicon) and can be formed by a suitable method such as ALD. The thickness of the cap layer 91 is about 10 angstroms or less.

[0094] Fig.32A and Fig.32B Cross-sectional views of a FinFET device 100H along different cross sections at fabrication stages in one embodiment are shown. Fig.32A An embodiment similar to Fig.18 Embodiment of the invention. Fig.32B Shows Fig.32A An embodiment of a cross-sectional view of a gate trench of a FinFET device. Fig.32A and Fig.32B In the embodiment of the present invention, before forming the N-type work function layer 85, a P-type work function layer 99 is conformally formed on the P-type work function layer 83 / 84. In some embodiments, the P-type work function layer 99 is formed of a titanium-containing material (e.g., titanium or titanium nitride) by a suitable formation method (e.g., CVD or ALD). The thickness of the P-type work function layer 99 is between about 10 angstroms and about 30 angstroms.

[0095] Figure 33-Figure 46 Various views of a FinFET device 200 at various stages of fabrication are shown in accordance with one embodiment. Figure 33-Figure 45 Each of the fins shows three cross-sectional views showing three gate trenches 69 (e.g., 69A, 69B, and 69C) and / or metal gates 97 (e.g., 97A, 97B, and 97C) formed in the gate trenches, wherein the three cross-sectional views correspond to cross-sections of the gate trenches in the same fin, for example, along the fin in one embodiment. Figure 7B However, depending on the design of the FinFET device 200, Figure 33-Figure 45 The three cross-sectional views in each of the fins may optionally correspond to cross-sections of gate trenches in different fins (eg, 64A, 64B, and 64C), for example, along Figure 7B The following discussion uses an example in which the three cross-sectional views correspond to cross-sections of a gate trench in the same fin (e.g., 64A) along cross-sections D3-D3, D2-D2, and DD. Note that for simplicity, only a portion of the FinFET device 200 located near the gate trench is shown, and certain features (e.g., gate spacer 76) are simplified in the figures. Fig.46 Shows Fig.45 , but along cross section BB.

[0096] Reference now Fig.33 , gate trenches 69A, 69B, and 69C are formed in the fin 64 between the corresponding gate spacers 76. The gate trenches 69A, 69B, and 69C may follow a method such as Figure 2-Figure 6 , Fig. 7A , Figure 8 and Fig. 9 Next, the gate dielectric layer 82, the layer 89, the P-type work function layer 83 and the cap layer 91 are continuously formed (e.g., conformally formed) in the gate trenches 69A, 69B and 69C, over the upper surface of the gate spacer 76, and the first ILD 90 ( Fig.33 Not shown, see for example Fig. 9 ) is above the upper surface. The materials and formation methods of the various layers (eg, 82, 89, 83, and 91) are the same or similar to those discussed above, and thus the details are not repeated.

[0097] Next, in Fig.34 in Fig.33 A photoresist including a BARC layer 86 and a top photoresist 88 is formed over the FinFET device 200. After it is formed, the top photoresist 88 is patterned, and the pattern of the top photoresist 88 is transferred to the BARC layer 86 by an anisotropic etching process (e.g., a plasma etching process). After the anisotropic etching process, portions of the capping layer 91 (e.g., portions in the gate trench 69A, and portions along the left side wall and left bottom portion of the gate trench 69B) are exposed.

[0098] Next, in Fig.35 In the embodiment of the present invention, a wet etching process 113 is performed to selectively remove the exposed portion of the cap layer 91 and the portion of the P-type work function layer 83 directly below the exposed portion of the cap layer 91. In some embodiments, the wet etching process 113 uses an etching chemical W2, the details of which are described above and are not repeated here. Due to the etching selectivity of the etching process, the wet etching process 113 removes a portion of the cap layer 91 and a portion of the P-type work function layer 83 without substantially corroding the underlying layer 89.

[0099] Next, in Fig.36 In the embodiment of the present invention, the photoresist (e.g., 86, 88) is removed, and a P-type work function layer 84 is conformally formed in the gate trenches 69A, 69B, and 69C. The P-type work function layer 84 physically contacts the upper surface of the layer 89 and the upper surface of the cap layer 91, as shown in FIG. Fig.36 shown.

[0100] Next, in Fig.37 in Fig.36 A patterned photoresist including a BARC layer 86 and a top photoresist 88 is formed over the FinFET device 200. The top photoresist 88 may be patterned using photolithography and etching techniques. Next, the pattern of the top photoresist 88 is transferred to the BARC layer 86 by an anisotropic etching process such as a plasma etching process. After the anisotropic etching process, a portion of the P-type work function layer 84 disposed above the cap layer 91 is exposed.

[0101] Next, in Fig.38 In the embodiment of the present invention, a wet etching process 115 is performed to selectively remove the exposed portion of the P-type work function layer 84. In some embodiments, the wet etching process 115 uses an etching chemical W1, the details of which are described above and are not repeated here. Due to the etching selectivity of the etching process, the wet etching process 115 removes the exposed portion of the P-type work function layer 84 without substantially corroding the cap layer 91 below.

[0102] Next, in Fig.39 In the process, the photoresist (eg, 86, 88) is removed using a suitable method (eg, ashing, etching, CMP, etc., or a combination thereof). After the photoresist is removed, the P-type work function layer 84 and the cap layer 91 are exposed.

[0103] Next, in Fig.40 In the embodiment of the present invention, a P-type work function layer 99 and an N-type work function layer 94 are continuously (e.g., conformally) formed in the gate trench 69, above the P-type work function layer 84 (e.g., in contact with the P-type work function layer 84), and above the cap layer 91. In some embodiments, the N-type work function layer 94 is formed of an aluminum-containing material (e.g., aluminum, aluminum carbide, or aluminum nitride) and is formed by a suitable method (e.g., CVD, PVD, ALD, etc. or a combination thereof). Note that, compared to the N-type work function layer 85, the proportion (e.g., atomic ratio) of aluminum (Al) in the N-type work function layer 94 is different from the proportion of aluminum (Al) in the N-type work function layer 85, which allows the threshold voltage of different transistors of the formed FinFET device 200 to be adjusted.

[0104] After forming the N-type work function layer 94, a patterned photoresist including the BARC layer 86 and the top photoresist 88 is formed over the N-type work function layer 94. Next, the pattern of the top photoresist 88 is transferred to the BARC layer 86 by an anisotropic etching process (e.g., a plasma etching process). After the anisotropic etching process, portions of the N-type work function layer 94 (e.g., portions in the gate trench 69A, and portions along the left side wall and left bottom portion of the gate trench 69B) are exposed.

[0105] Next, in Fig.41 In the embodiment of the present invention, a wet etching process 117 is performed to selectively remove the exposed portion of the N-type work function layer 94. In some embodiments, the wet etching process 117 uses a fourth etching chemical W4 that is selective to the N-type work function layer 94. In some embodiments, the fourth etching chemical W4 includes an etchant and an oxidant. In one embodiment, the etchant is an acid, such as hydrogen chloride (HCl), phosphoric acid (H3PO4), bicarbonate, etc. The oxidant used in the fourth etching chemical W4 can be, for example, ozone (O3). In some embodiments, an etchant (e.g., an acid) and an oxidant are mixed in an aqueous solution (e.g., in DIW) to form a fourth etching chemical W4. The concentration (e.g., volume concentration) of the etchant and the oxidant in the fourth etching chemical W4 is higher than about 1%, for example, between about 1% and about 10%. The wet etching process 117 can be performed at room temperature and lasts for between about 1 minute and about 5 minutes. Due to the etching selectivity of the wet etching process 117, the exposed portion of the N-type work function layer 94 is removed without substantially corroding the underlying P-type work function layer 99.

[0106] Next, in Fig.42 In the process, the photoresist (eg, 86, 88) is removed using a suitable method (eg, ashing, etching, CMP, etc., or a combination thereof). After the photoresist is removed, the P-type work function layer 99 and the N-type work function layer 94 are exposed.

[0107] Next, in Fig.43 In the embodiment of the present invention, an N-type work function layer 85 is conformally formed in the gate trench 69, for example, above and in contact with the P-type work function layer 99 and the N-type work function layer 94. Next, a patterned photoresist including a BARC layer 86 and a top photoresist 88 is formed above the N-type work function layer 85. The top photoresist 88 can be patterned using photolithography and etching techniques. The pattern of the top photoresist 88 is then transferred to the BARC layer 86 by an anisotropic etching process (e.g., a plasma etching process). After the anisotropic etching process, a portion of the N-type work function layer 85 disposed above the N-type work function layer 94 is exposed.

[0108] Next, in Fig.44 In some embodiments, the wet etching process 119 is performed to selectively remove the exposed portion of the N-type work function layer 85. In some embodiments, the wet etching process 119 uses a third etching chemical W3 that is selective to the N-type work function layer 85. In some embodiments, the third etching chemical W3 includes an etchant and an oxidant. In one embodiment, the etchant is an acid, such as hydrogen chloride (HCl), phosphoric acid (H3PO4), etc. In another embodiment, the etchant is a base, such as ammonium hydroxide (NH4OH). The oxidant used in the third etching chemical W3 may be, for example, hydrogen peroxide (H2O2). In some embodiments, an etchant (e.g., a base or an acid) and an oxidant are mixed in an aqueous solution (e.g., in DIW) to form a third etching chemical W3. The concentration (e.g., volume concentration) of the etchant and the oxidant in the third etching chemical W3 is higher than about 1%, for example, between about 1% and about 10%. The wet etching process 119 can be performed at a temperature between about 40°C and about 70°C, and the duration is between about 1 minute and about 5 minutes. Due to the etch selectivity of the wet etch process 119 , the exposed portion of the N-type work function layer 85 is removed without substantially corroding the underlying N-type work function layer 94 .

[0109] Next, in Fig.45 , the photoresist (e.g., 86, 88) is removed. A glue layer 87 is conformally formed in the gate trench 69. Next, a conductive material 93 is formed to fill the remaining portion of the gate trench 69. The respective layers in the gate trenches 69A, 69B, and 69C form metal gates 97A, 97B, and 97C, respectively.

[0110] Fig.46 Shows Fig.45 97A, 97B and 97C in FIG. 1 , but along cross section BB. Fig.45 and Fig.46As shown, metal gates 97A, 97B, and 97C have different structures (e.g., different work function layers). For example, metal gate 97A has a first work function layer stack, which includes a P-type work function layer 89, a P-type work function layer 84, a P-type work function layer 99, and an N-type work function layer 85. Metal gate 97C has a second work function layer stack, which includes a P-type work function layer 89, a P-type work function layer 83 (with a cap layer 91 on top), a P-type work function layer 99, and an N-type work function layer 94. Metal gate 97B has a third work function layer stack, which is a mixture of the first work function layer stack and the second work function layer stack. Specifically, the first half (e.g., the left half) of the third work function layer stack is the same as the first work function layer stack, and the second half (e.g., the right half) of the third work function layer stack is the same as the second work function layer stack. Therefore, metal gate 97B is also referred to as having a mixed work function layer stack. It can be seen in Fig.45 and Fig.46 The illustrated process is followed by additional processes such as forming a second ILD 92 and forming a contact plug 102. The details are not discussed here.

[0111] Variations on the disclosed embodiments are possible and are fully intended to be included within the scope of the present disclosure. For example, the number of fins and / or the number of gate structures in the FinFET device may be changed in the illustrated example without departing from the spirit of the present disclosure. As another example, although the gate trenches 69 (e.g., 69A, 69B, 69C) are shown as being disposed in the same fin along the same cross-section, each of the gate trenches 69 may be disposed in a different fin and along a different cross-section, depending on the design of the FinFET device. As yet another example, a P-type work function layer in a FinFET device of different embodiments may be changed to an N-type work function layer, and vice versa, to form a FinFET device having a stack of different work function layers.

[0112] Fig.47 1 shows a flow chart of a method for manufacturing a semiconductor structure according to some embodiments. It should be understood that Fig.47 The embodiment methods shown in are merely examples of many possible embodiment methods. Those skilled in the art will recognize many variations, substitutions, and modifications. For example, the following may be added, removed, replaced, rearranged, and repeated. Fig.47 The various steps shown.

[0113] refer to Fig.47At step 1010, a dummy gate structure is formed over the first fin, the second fin, and the third fin between the first fin and the second fin. At step 1020, a dielectric layer is formed around the dummy gate structure. At step 1030, the dummy gate structure is removed to form a groove in the dielectric layer, wherein the groove exposes the first fin, the second fin, and the third fin. At step 1040, a first work function layer and a second work function layer are formed in the groove, wherein the first work function layer extends along the first sidewall and the first upper surface of the first fin, and the second work function layer extends along the second sidewall and the second upper surface of the second fin, wherein the first work function layer extends along the third sidewall of the third fin and along the first portion of the third upper surface of the third fin, and the second work function layer extends along the fourth sidewall of the third fin and along the second portion of the third upper surface of the third fin. At step 1050, the groove is filled by forming a conductive material over the first work function layer and over the second work function layer.

[0114] Embodiments can achieve advantages. Various wet etching processes and etching chemistries (e.g., W1, W2, W3, and W4) disclosed herein achieve precise control of the etching process and excellent etching selectivity. For example, wet etching process 81 (see Fig.12 ) selectively removes the exposed P-type work function layer 84 without attacking the underlying gate dielectric layer 82, and the wet etching process 111 (see Fig.16 ) selectively removes the exposed P-type work function layer 83 without corroding the underlying P-type work function layer 84. This allows the work function metal of each metal gate to be independently formed and adjusted. The increased flexibility in the selection of materials for the work function layers, and the selection of different thicknesses for different layers, allows the formation of semiconductor devices with different threshold voltages (for different transistors). The disclosed method also allows the removal and deposition of different layers in narrow gate trenches, which is important for advanced process nodes because the size of the gate trenches is reduced in advanced process nodes. In addition, the disclosed method allows the use of two work function metals to form three different work function layers, which are composed of, for example, Fig.17 As shown, fin 68B has a mixture of two different work function metals (eg, 84, 83) to form a mixed work function metal.

[0115] In one embodiment, a method of forming a semiconductor device includes: forming a dummy gate structure over a first fin, a second fin, and a third fin between the first fin and the second fin; forming a dielectric layer around the dummy gate structure; removing the dummy gate structure to form a groove in the dielectric layer, wherein the groove exposes the first fin, the second fin, and the third fin; forming a first work function layer and a second work function layer in the groove, wherein the first work function layer extends along a first sidewall and a first upper surface of the first fin, and the second work function layer extends along a second sidewall and a second upper surface of the second fin, wherein the first work function layer extends along a third sidewall of the third fin and along a first portion of a third upper surface of the third fin, and the second work function layer extends along a fourth sidewall of the third fin and along a second portion of a third upper surface of the third fin; and filling the groove by forming a conductive material over the first work function layer and over the second work function layer. In one embodiment, the first work function layer and the second work function layer are N-type work function layers or P-type work function layers, wherein the first work function layer and the second work function layer are formed of different materials. In one embodiment, the method further comprises: before filling the groove, forming a third work function layer in the groove above the first work function layer and above the second work function layer. In one embodiment, the third work function layer is a work function layer of a different type from the first work function layer and the second work function layer. In one embodiment, the first work function layer, the second work function layer and the third work function layer are work function layers of the same type. In one embodiment, the method further comprises: before forming the first work function layer and the second work function layer, conformally forming a layer in the groove above the first fin, the second fin and the third fin, wherein the first work function layer extends along the upper surface of the layer and contacts the upper surface of the layer, wherein the second work function layer extends along the upper surface of the layer and contacts the upper surface of the layer. In one embodiment, the layer is a gate dielectric layer. In one embodiment, the layer is a third work function layer. In one embodiment, the first work function layer, the second work function layer and the third work function layer are the same N-type or P-type work function layer, wherein at least the first work function layer and the second work function layer are formed of different materials. In one embodiment, wherein forming the first work function layer and the second work function layer comprises: forming the first work function layer in the groove above the first fin, the second fin, and the third fin; forming a first patterned mask layer above the first work function layer, the first patterned mask layer exposing a first portion of the first work function layer, the first portion being disposed above the second fin and above the second portion of the third upper surface of the third fin; using a first etching process to selectively remove the exposed first portion of the first work function layer; and removing the first patterned mask layer after the first etching process. In one embodiment, the first etching process is a first wet etching process.In one embodiment, forming the first work function layer and the second work function layer further comprises: forming the second work function layer in the groove above the first fin, the second fin, and the third fin after removing the first patterned mask layer; forming a second patterned mask layer above the second work function layer, the second patterned mask layer exposing a second portion of the second work function layer, the second portion being disposed above the first fin and above the first portion of the third upper surface of the third fin; using a second etching process to selectively remove the exposed second portion of the second work function layer; and removing the second patterned mask layer after the second etching process. In one embodiment, the second etching process is a second wet etching process.

[0116] In one embodiment, a method for forming a semiconductor device includes: forming a fin protruding above a substrate; forming a dummy gate structure above the fin; surrounding the dummy gate structure with a dielectric layer; and replacing the dummy gate structure with a metal gate, wherein the replacement includes: removing the dummy gate structure to form a first gate trench, a second gate trench, and a third gate trench in the dielectric layer, wherein the third gate trench is located between the first gate trench and the second gate trench; forming a first work function layer along the sidewall and bottom of the first gate trench and along a first area of ​​the first sidewall and bottom of the third gate trench; forming a second work function layer along the sidewall and bottom of the second gate trench and along a second area of ​​the second sidewall and bottom of the third gate trench, wherein the first work function layer and the second work function layer are work function layers of the same type; forming a third work function layer in the first gate trench, the second gate trench, and the third gate trench, wherein the third work function layer extends along the first work function layer and the second work function layer; and filling the first gate trench, the second gate trench, and the third gate trench with a conductive material. In one embodiment, the replacement further includes forming another layer in the first gate trench, the second gate trench, and the third gate trench before forming the first work function layer and the second work function layer, wherein the first work function layer and the second work function layer extend along the other layer and contact the other layer. In one embodiment, the replacement further includes: forming a cap layer on the first work function layer but not on the second work function layer, wherein the cap layer is formed between the first work function layer and the third work function layer. In one embodiment, the method further includes: forming a fourth work function layer and a fifth work function layer above the third work function layer, wherein the third work function layer is located between the first work function layer and the fourth work function layer, and between the second work function layer and the fifth work function layer.

[0117] In one embodiment, a semiconductor device includes: a first fin, a second fin, and a third fin protruding above a substrate, wherein the third fin is located between the first fin and the second fin; a gate dielectric layer located above the first fin, the second fin, and the third fin; a first work function layer located above and in contact with the gate dielectric layer, wherein the first work function layer extends along a first sidewall and a first upper surface of the first fin; a second work function layer located above and in contact with the gate dielectric layer, wherein the second work function layer extends along a second sidewall and a second upper surface of the second fin, wherein the first work function layer and the second work function layer include different materials; and a first gate electrode, a second gate electrode, and a third gate electrode, wherein the first gate electrode is located above the first fin, the second gate electrode is located above the second fin, and the third gate electrode is located above the third fin. In one embodiment, the first work function layer extends along a first sidewall of the third fin, and the second work function layer extends along a second sidewall of the third fin opposite to the first sidewall of the third fin. In one embodiment, the first work function layer extends along a first portion of an upper surface of the third fin, and the second work function layer extends along a second portion of an upper surface of the third fin.

[0118] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis to design or modify other processes and structures for achieving the same purpose and / or achieving the same advantages of the embodiments introduced here. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications here without departing from the spirit and scope of the present disclosure.

[0119] Example 1. A method for forming a semiconductor device, the method comprising: forming a dummy gate structure above a first fin, a second fin, and a third fin between the first fin and the second fin; forming a dielectric layer around the dummy gate structure; removing the dummy gate structure to form a groove in the dielectric layer, wherein the groove exposes the first fin, the second fin, and the third fin; forming a first work function layer and a second work function layer in the groove, wherein the first work function layer extends along a first side wall and a first upper surface of the first fin, and the second work function layer extends along a second side wall and a second upper surface of the second fin, wherein the first work function layer extends along a third side wall of the third fin and along a first portion of a third upper surface of the third fin, and the second work function layer extends along a fourth side wall of the third fin and along a second portion of the third upper surface of the third fin; and filling the groove by forming a conductive material above the first work function layer and above the second work function layer.

[0120] Example 2. The method according to Example 1, wherein the first work function layer and the second work function layer are N-type work function layers or P-type work function layers, and wherein the first work function layer and the second work function layer are formed of different materials.

[0121] Example 3. The method according to Example 2 further includes: before filling the groove, forming a third work function layer in the groove above the first work function layer and above the second work function layer.

[0122] Example 4. The method of Example 3, wherein the third work function layer is a work function layer of a different type than the first work function layer and the second work function layer.

[0123] Example 5. The method of Example 3, wherein the first work function layer, the second work function layer, and the third work function layer are work function layers of the same type.

[0124] Example 6. The method according to Example 1 further includes: before forming the first work function layer and the second work function layer, conformally forming a layer in the groove above the first fin, the second fin and the third fin, wherein the first work function layer extends along the upper surface of the layer and contacts the upper surface of the layer, and wherein the second work function layer extends along the upper surface of the layer and contacts the upper surface of the layer.

[0125] Example 7. The method of Example 6, wherein the layer is a gate dielectric layer.

[0126] Example 8. The method of Example 6, wherein the layer is a third work function layer.

[0127] Example 9. The method according to Example 8, wherein the first work function layer, the second work function layer and the third work function layer are the same N-type or P-type work function layer, wherein at least the first work function layer and the second work function layer are formed of different materials.

[0128] Example 10. A method according to Example 1, wherein forming the first work function layer and the second work function layer includes: forming the first work function layer in the groove above the first fin, the second fin and the third fin; forming a first patterned mask layer above the first work function layer, the first patterned mask layer exposing a first portion of the first work function layer, the first portion being disposed above the second fin and above the second portion of the third upper surface of the third fin; using a first etching process to selectively remove the exposed first portion of the first work function layer; and removing the first patterned mask layer after the first etching process.

[0129] Example 11. The method of Example 10, wherein the first etching process is a first wet etching process.

[0130] Example 12. A method according to Example 11, wherein forming the first work function layer and the second work function layer further includes: after removing the first patterned mask layer, forming the second work function layer in the groove above the first fin, the second fin and the third fin; forming a second patterned mask layer above the second work function layer, the second patterned mask layer exposing a second portion of the second work function layer, the second portion being arranged above the first fin and above the first portion of the third upper surface of the third fin; using a second etching process to selectively remove the exposed second portion of the second work function layer; and after the second etching process, removing the second patterned mask layer.

[0131] Example 13. The method of Example 12, wherein the second etching process is a second wet etching process.

[0132] Example 14. A method for forming a semiconductor device, the method comprising: forming a fin protruding above a substrate; forming a dummy gate structure above the fin; surrounding the dummy gate structure with a dielectric layer; and replacing the dummy gate structure with a metal gate, wherein the replacement comprises: removing the dummy gate structure to form a first gate trench, a second gate trench, and a third gate trench in the dielectric layer, wherein the third gate trench is located between the first gate trench and the second gate trench; forming a dummy gate structure along the sidewall and bottom of the first gate trench and along the first sidewall and the third gate trench; The invention relates to a method for forming a first work function layer in a first area at the bottom of the first gate trench; forming a second work function layer along the sidewall and bottom of the second gate trench and along the second sidewall of the third gate trench and the second area at the bottom, wherein the first work function layer and the second work function layer are work function layers of the same type; forming a third work function layer in the first gate trench, the second gate trench and the third gate trench, wherein the third work function layer extends along the first work function layer and the second work function layer; and filling the first gate trench, the second gate trench and the third gate trench with a conductive material.

[0133] Example 15. A method according to Example 14, wherein the replacement further includes: before forming the first work function layer and the second work function layer, forming another layer in the first gate trench, the second gate trench and the third gate trench, wherein the first work function layer and the second work function layer extend along the other layer and contact the other layer.

[0134] Example 16. The method of Example 14, wherein the replacement further comprises: forming a cap layer on the first work function layer but not on the second work function layer, wherein the cap layer is formed between the first work function layer and the third work function layer.

[0135] Example 17. The method according to Example 14 further includes: forming a fourth work function layer and a fifth work function layer above the third work function layer, wherein the third work function layer is located between the first work function layer and the fourth work function layer, and between the second work function layer and the fifth work function layer.

[0136] Example 18. A semiconductor device, comprising: a first fin, a second fin, and a third fin, wherein the first fin, the second fin, and the third fin protrude higher than a substrate, wherein the third fin is located between the first fin and the second fin; a gate dielectric layer, wherein the gate dielectric layer is located above the first fin, the second fin, and the third fin; a first work function layer, wherein the first work function layer is located above the gate dielectric layer and in contact with the gate dielectric layer, wherein the first work function layer extends along a first side wall and a first upper surface of the first fin; a second work function layer, wherein the second work function layer is located above the gate dielectric layer and in contact with the gate dielectric layer, wherein the second work function layer extends along a second side wall and a second upper surface of the second fin, wherein the first work function layer and the second work function layer include different materials; and a first gate electrode, a second gate electrode, and a third gate electrode, wherein the first gate electrode is located above the first fin, the second gate electrode is located above the second fin, and the third gate electrode is located above the third fin.

[0137] Example 19. The semiconductor device of Example 18, wherein the first work function layer extends along a first sidewall of the third fin, and the second work function layer extends along a second sidewall of the third fin opposite to the first sidewall of the third fin.

[0138] Example 20. The semiconductor device of Example 19, wherein the first work function layer extends along a first portion of an upper surface of the third fin, and the second work function layer extends along a second portion of the upper surface of the third fin.

Claims

1. A method for forming a semiconductor device, the method comprising: forming a dummy gate structure over a first fin, a second fin, and a third fin between the first fin and the second fin; forming a dielectric layer around the dummy gate structure; removing the dummy gate structure to form a recess in the dielectric layer, wherein the recess exposes the first fin, the second fin, and the third fin; forming a first work function layer and a second work function layer in the groove, wherein the first work function layer extends along a first sidewall and a first upper surface of the first fin, and the second work function layer extends along a second sidewall and a second upper surface of the second fin, wherein the first work function layer extends along a third sidewall of the third fin and along a first portion of a third upper surface of the third fin, and the second work function layer extends along a fourth sidewall of the third fin and along a second portion of the third upper surface of the third fin, wherein a first sidewall of the first work function layer above the third upper surface of the third fin contacts and extends along a second sidewall of the second work function layer above the third upper surface of the third fin, wherein an upper surface of the first work function layer away from the third fin is exposed by the second work function layer, and an upper surface of the second work function layer away from the third fin is exposed by the first work function layer; and The groove is filled by forming a conductive material over the first work function layer and over the second work function layer.

2. The method according to claim 1, wherein: The first work function layer and the second work function layer are N-type work function layers or P-type work function layers, wherein the first work function layer and the second work function layer are formed of different materials.

3. The method according to claim 2, further comprising: Before filling the groove, a third work function layer is formed in the groove over the first work function layer and over the second work function layer.

4. The method according to claim 3, wherein: The third work function layer is a work function layer of a different type than the first work function layer and the second work function layer.

5. The method according to claim 3, wherein: The first work function layer, the second work function layer, and the third work function layer are work function layers of the same type.

6. The method according to claim 1, further comprising: Before forming the first work function layer and the second work function layer, a layer is conformally formed in the groove above the first fin, the second fin and the third fin, wherein the first work function layer extends along the upper surface of the layer and contacts the upper surface of the layer, and wherein the second work function layer extends along the upper surface of the layer and contacts the upper surface of the layer.

7. The method according to claim 6, wherein: The layer is a gate dielectric layer.

8. The method according to claim 6, wherein: The layer is a third work function layer.

9. The method according to claim 8, wherein: The first work function layer, the second work function layer and the third work function layer are the same N-type or P-type work function layer, wherein at least the first work function layer and the second work function layer are formed of different materials.

10. The method according to claim 1, wherein: Forming the first work function layer and the second work function layer includes: forming the first work function layer in the groove over the first fin, the second fin, and the third fin; forming a first patterned mask layer over the first work function layer, the first patterned mask layer exposing a first portion of the first work function layer, the first portion being disposed over the second fin and over the second portion of the third upper surface of the third fin; selectively removing an exposed first portion of the first work function layer using a first etching process; and After the first etching process, the first patterned mask layer is removed.

11. The method according to claim 10, wherein: The first etching process is a first wet etching process.

12. The method according to claim 11, wherein: Forming the first work function layer and the second work function layer further includes: After removing the first patterned mask layer, forming the second work function layer in the groove over the first fin, the second fin, and the third fin; forming a second patterned mask layer over the second work function layer, the second patterned mask layer exposing a second portion of the second work function layer, the second portion being disposed over the first fin and over the first portion of the third upper surface of the third fin; selectively removing the exposed second portion of the second work function layer using a second etching process; and After the second etching process, the second patterned mask layer is removed.

13. The method according to claim 12, wherein: The second etching process is a second wet etching process.

14. A method of forming a semiconductor device, the method comprising: forming a fin protruding above the substrate; forming a dummy gate structure above the fin; Surrounding the dummy gate structure with a dielectric layer; as well as The dummy gate structure is replaced with a metal gate, wherein the replacement comprises: removing the dummy gate structure to form a first gate trench, a second gate trench, and a third gate trench in the dielectric layer, wherein the third gate trench is located between the first gate trench and the second gate trench; forming a first work function layer along a sidewall and a bottom of the first gate trench and along a first region of a first sidewall and a bottom of the third gate trench; forming a second work function layer along the sidewall and the bottom of the second gate trench and along the second sidewall and the second region of the bottom of the third gate trench, wherein a first sidewall of the first work function layer is located at the bottom of the third gate trench and contacts the second sidewall of the second work function layer, wherein the first work function layer and the second work function layer are work function layers of the same type; forming a third work function layer in the first gate trench, the second gate trench, and the third gate trench, wherein the third work function layer extends along the first work function layer and the second work function layer and contacts the first work function layer and the second work function layer; and The first gate trench, the second gate trench, and the third gate trench are filled with a conductive material.

15. The method according to claim 14, wherein: The replacement also includes: before forming the first work function layer and the second work function layer, forming another layer in the first gate trench, the second gate trench and the third gate trench, wherein the first work function layer and the second work function layer extend along the other layer and contact the other layer.

16. The method according to claim 14, wherein: The replacing further includes: forming a capping layer on the first work function layer but not on the second work function layer, wherein the capping layer is formed between the first work function layer and the third work function layer.

17. The method according to claim 14, further comprising: A fourth work function layer and a fifth work function layer are formed over the third work function layer, wherein the third work function layer is located between the first work function layer and the fourth work function layer, and between the second work function layer and the fifth work function layer.

18. A semiconductor device comprising: A first fin, a second fin and a third fin, wherein the first fin, the second fin and the third fin protrude higher than the substrate, wherein the third fin is located between the first fin and the second fin; a gate dielectric layer, the gate dielectric layer being located above the first fin, the second fin, and the third fin; a first work function layer, the first work function layer being located above the gate dielectric layer and contacting the gate dielectric layer, wherein the first work function layer extends along a first sidewall and a first upper surface of the first fin; a second work function layer, the second work function layer being located above the gate dielectric layer and contacting the gate dielectric layer, wherein the second work function layer extends along a second sidewall and a second upper surface of the second fin, wherein the first work function layer extends along a first sidewall of the third fin and a first portion of a third upper surface of the third fin, wherein the second work function layer extends along a second opposing sidewall of the third fin and a second portion of the third upper surface of the third fin, wherein the first sidewall of the first work function layer is located above the third upper surface of the third fin and contacting the second sidewall of the second work function layer, wherein a first upper surface of the first work function layer away from the substrate is free of the second work function layer, and a second upper surface of the second work function layer away from the substrate is free of the first work function layer, wherein the first work function layer and the second work function layer comprise different materials; and A first gate electrode, a second gate electrode and a third gate electrode, wherein the first gate electrode is located above the first fin, the second gate electrode is located above the second fin, and the third gate electrode is located above the third fin.

Images