Method of forming a semiconductor structure

Abstract

Embodiments of the present disclosure provide a method of forming a semiconductor structure with metal gates. The semiconductor structure is formed by first fabricating fins on a semiconductor substrate, and then forming source and drain recesses. Next, source and drain regions can be deposited in the source and drain recesses. A gate structure can be deposited in the regions between the fins. The gate structure includes dielectric and metal layers. In the regions between the fins, an insulating layer separates the gate structure from the source and drain regions.

Description

Technical Field

[0001] This disclosure relates to a semiconductor structure and a method for forming the same, and more particularly to a fin field-effect transistor and a method for forming the same. Background Technology

[0002] One of the goals of the semiconductor industry is to continuously shrink the size of individual field-effect transistors (FETs) and increase their speed. To achieve these goals, fin field-effect transistors (FinFETs) have been developed. FinFETs are variations of traditional metal-oxide-semiconductor (MOSFET) FETs, and include non-planar dual-gate transistors formed on silicon or silicon-on-insulator (SOI) substrates. The difference between FinFETs and MOSFETs lies in their thin silicon "fin" inversion channels located on the substrate, allowing the gate to contact the left and right sides of the fins.

[0003] Further miniaturization of transistors presents various challenges in the fabrication and design of fin field-effect transistors (FETs). For example, in fabricating FETs, metal gates can be used to replace typical polysilicon gate electrodes to improve device performance. One process for forming the metal gate structure is called replacement-gate or gate-last, where the final gate structure is fabricated last, thus reducing the number of subsequent processes, including high-temperature processing after gate formation. However, performing such a process presents many challenges, especially for miniaturized device components and complex surface topologies. One such challenge is forming the metal gate structure between closely spaced fins. Summary of the Invention

[0004] This disclosure provides a method for forming a semiconductor structure, the semiconductor structure including a semiconductor substrate, which includes fins separated by fin etch regions. The method includes: filling the fin etch regions with a first material to form a filled semiconductor structure; forming a top layer on a first portion of the filled semiconductor structure; etching source etch regions and drain etch regions from a second portion of the filled semiconductor structure; laterally etching a portion of the first material from the front and rear sidewalls of the first portion exposed by the source and drain etch regions to form front and rear sidewall trenches; depositing a second material into the front and rear sidewall trenches; forming a source region in the source etch region and a drain region in the drain etch region; removing the top layer to expose the top surface of the first portion; removing the first material and partially re-exposing the fin etch regions; depositing a gate dielectric layer conformally to the surface of the partially re-exposed fin etch regions; and depositing a conductive material into the remaining portion of the fin etch regions.

[0005] This disclosure also provides a method for forming a semiconductor structure, the semiconductor structure including a semiconductor substrate, which includes fins separated by fin etch regions. The method includes: depositing a first filler material to form a conforming layer on the surface of the fin etch regions; depositing a second filler material to form a filled semiconductor structure; forming a top layer on a first portion of the filled semiconductor structure; etching source etch regions and drain etch regions from a second portion of the filled semiconductor structure; laterally etching a portion of the first filler material from the front and rear sidewalls of the first portion exposed by the source and drain etch regions to form front and rear sidewall trenches; depositing a second material into the front and rear sidewall trenches; forming a source region in the source etch region and a drain region in the drain etch region; removing the top layer to expose the top surface of the first portion; removing the first and second filler materials and partially re-exposing the fin etch regions; depositing a gate dielectric layer conforming to the surface of the partially re-exposed fin etch regions; and depositing a conductive material into the remaining portion of the fin etch regions.

[0006] This disclosure also provides a semiconductor structure for forming a fin field-effect transistor device. The semiconductor structure includes: a fin region extending from a semiconductor substrate, the fin region including at least one pair of fins, wherein the pair of fins is separated by a filling region filled by a first material having a higher etch rate than the material used to form the at least one pair of fins, the first material being epitaxially grown to form the filling region, the fin region including a first set of surfaces and a second set of surfaces; and a source region and a drain region, the source region being adjacent to the first set of surfaces of the fin region, and the drain region being adjacent to the second set of surfaces of the fin region. Attached Figure Description

[0007] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the components can be arbitrarily enlarged or reduced to clearly demonstrate the features of the embodiments of this disclosure.

[0008] Figure 1A This is a three-dimensional schematic diagram of an exemplary semiconductor structure that can be used to form a fin field-effect transistor device, consistent with various exemplary embodiments.

[0009] Figure 1B This is a top view of an exemplary semiconductor structure that can be used to form a fin field-effect transistor device, consistent with various exemplary embodiments.

[0010] Figures 2A to 2C , Figure 6B , Figure 7C , Figure 8C , Figures 9C to 9F , Figures 10A to 10D , Figures 11C to 11E , Figures 13A to 13B , Figures 14A to 14B , Figures 15A to 15B , Figures 16 to 18 The figure is a cross-sectional view of an intermediate structure during the semiconductor structure formation step, consistent with various exemplary embodiments.

[0011] Figures 3A to 3B , Figures 4A to 4B , Figures 5A to 5B , Figure 6A , Figures 7A to 7B , Figures 8A to 8B , Figures 8D to 8E , Figures 9A to 9B , Figures 11A to 11B , Figures 12A to 12C , Figure 19 This is a perspective view of an intermediate structure during the semiconductor structure formation process, consistent with various exemplary embodiments.

[0012] Figure 20 It is a process flow diagram consistent with various exemplary embodiments.

[0013] Figure 21 This is an exemplary flowchart of a manufacturing process consistent with various exemplary embodiments.

[0014] Explanation of reference numerals in the attached figures:

[0015] 100, 500: Semiconductor Structure

[0016] 101: Embedded insulation layer

[0017] 102: Substrate

[0018] 103, 103G, 103H: Fins

[0019] 104: Quarantine Zone

[0020] 106: Gate dielectric layer

[0021] 108: Gate structure

[0022] 110A: Source Region

[0023] 110B: Drain region

[0024] 134: Fin erosion area

[0025] 140: Front

[0026] 142: Rear side

[0027] 144: Top section

[0028] 202: Fin pitch

[0029] 204,210: Altitude

[0030] 206,730,810,910: Width

[0031] 221: Mask

[0032] 221A, 221B: Film layers

[0033] 300, 600, 700, 800, 900, 1100, 1900: Structure

[0034] 310A, 310B, 501, 901A, 901B, 1802: Insulation layer

[0035] 400: Filled semiconductor structure

[0036] 401, 503, 801: Filled areas

[0037] 403, 1601, 1607: Top surface

[0038] 411, 412: Filler material

[0039] 601: Top Floor

[0040] 603, 605, 607: Sub-layer

[0041] 701: Fin area

[0042] 710A: Source electrode etched region

[0043] 710B: Drain erosion region

[0044] 720: Depth

[0045] 802,830,1011,1027,1028B,1711: Area

[0046] 805: Sectional Plane

[0047] 807, 807A, 807B: Surface

[0048] 825A: Front Groove

[0049] 825B: Rear Groove

[0050] 908A, 908B: Insulation Zone

[0051] 911A, 911B, 911C: Dielectric sublayer

[0052] 918, 919: Dielectric layer

[0053] 1010, 1040: Etched areas

[0054] 1015: Trench

[0055] 1017: Insulating spacer layer

[0056] 1101, 1101A, 1101B: Source / Drain Regions

[0057] 1103: Facets

[0058] 1201, 1901, 1902: Interlayer dielectric layers

[0059] 1203: Lining

[0060] 1221, 1235: Gaps

[0061] 1250: Plane

[0062] 1420: Notch

[0063] 1602: Sidewall surface

[0064] 1701, 1702: Sub-layer of the interface

[0065] 1703: Barrier Sub-layer

[0066] 1704: Metallic layer

[0067] 1801: Top conductive layer

[0068] 1904: Spacer layer

[0069] 2000: Technology

[0070] 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013, 2014: Steps

[0071] 2110: Device Design System

[0072] 2112: Device Design

[0073] 2114: Equipment Manufacturing System

[0074] 2116: Device

[0075] 2120: Circuit Design System

[0076] 2122: Circuit Design

[0077] 2124: Circuit Manufacturing System

[0078] 2126: Circuit

[0079] F-View: F-perspective

[0080] G-View: G-Perspective

[0081] R-View: R-view

[0082] T-View: T-Perspective Detailed Implementation

[0083] The following disclosure provides numerous embodiments or examples for implementing different elements of the provided subject matter. Specific examples of each element and its configuration are described below to simplify the description of embodiments of this disclosure. Of course, these are merely examples and are not intended to limit the embodiments of this disclosure. For example, if the description refers to a first element formed on a second element, it may include embodiments where the first and second elements are in direct contact, or embodiments where an additional element is formed between the first and second elements such that they are not in direct contact. Furthermore, reference values ​​and / or letters may be repeated in various examples of embodiments of this disclosure. Such repetition is for the purpose of brevity and clarity and is not intended to indicate a relationship between the different embodiments and / or configurations discussed.

[0084] Furthermore, spatially relative terms may be used, such as "below," "under," "below," "above," "on top of," "above," etc., to facilitate the description of the relationship between one or more components or features in the accompanying drawings and another component or feature(s). Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the accompanying drawings. When the device is turned to different orientations (rotated 90 degrees or other orientations), the spatially relative adjectives used will also be interpreted according to the orientation after the turn.

[0085] When comparing the distance between two regions in a semiconductor structure, and the semiconductor structure extends laterally and vertically by a characteristic length, width, and height, as used herein, unless otherwise specified, the terms "in proximity," "close to," and "proximate" refer to regions that are at most 10 percent of the characteristic length, characteristic width, or characteristic height. The term "characteristic length" refers to the maximum length dimension of the semiconductor structure, the term "characteristic width" refers to the maximum width dimension of the semiconductor structure, and the term "characteristic height" refers to the maximum height dimension of the semiconductor structure. When comparing multiple regions in a semiconductor structure, the terms "in proximity," "close to," and "proximate" may also refer to multiple adjacent regions (e.g., multiple regions in contact with another region, or multiple regions isolated from another region). As used herein, unless otherwise specified, the term "remote" refers to regions that are not adjacent to each other.

[0086] As used herein, unless otherwise specified, the term “thickness” refers to the minimum thickness measured at various points along the membrane, which may include variable thicknesses.

[0087] When comparing two values, and the first value is greater than the second value, as used herein, unless otherwise specified, the terms "greater than," "above," "greater than," "above," etc., mean that the first value is at least one percent greater than the second value. Similarly, when comparing two values, and the first value is less than the second value, unless otherwise specified, the terms "less than," "below," "less than," etc., mean that the first value is at least one percent less than the second value. When comparing two values, as used herein, unless otherwise specified, the terms "comparable," "similar," etc., mean that one value is between ten percent and one thousandth of the other value.

[0088] Furthermore, as used herein, unless otherwise specified, the term "set" refers to one or more (i.e., at least one), and the phrase "any solution" refers to any solution currently known or subsequently developed. Furthermore, when comparing the first set of values ​​with the second set of values, as used herein, unless otherwise specified, the term "substantially identical" means that the values ​​in the first set differ from the values ​​in the second set by at most 10 percent. Furthermore, when comparing the materials forming the regions, the term "substantially identical" means that the materials in the regions are identical, except for unintended variations caused by the manufacturing techniques used to form the regions.

[0089] Furthermore, when comparing two surfaces, as used herein, unless otherwise specified, the term "parallel" means, on average, that the two surfaces have an orientation parallel to each other, where "on average" means that the first normal and the second normal may be collinear, but differ from complete collinearity by a maximum of 10 degrees, the first normal being any point perpendicular to the first surface, and the second normal being any point perpendicular to the second surface. When comparing two surfaces, as used herein, unless otherwise specified, the term "non-parallel" means that the surfaces are not parallel as defined above.

[0090] Various embodiments generally relate to semiconductor devices, and particularly to semiconductor devices utilizing gates. For example, a semiconductor device may include a finned field-effect transistor device, and may include a plurality of fins formed in a wafer and a gate covering a portion of the fins. The portion of the fins covered by the gate may serve as a channel region of the device. A portion of the fins may also extend under the gate and may be part of the source and drain regions of the device.

[0091] According to various embodiments, a semiconductor structure and a method of forming the same are provided for fabricating fin field-effect transistors. Furthermore, some embodiments incorporate implementations for planar devices, such as planar field-effect transistors, and others incorporate implementations for gate all-around (GAA) devices, such as all-around gate field-effect transistors. Intermediate stages in forming the semiconductor structure are also described herein. Some embodiments discussed herein are discussed in the context of forming field-effect transistors using post-gate fabrication processes. Those skilled in the art to which this disclosure pertains will readily understand that other conceivable variations are possible within the scope of this disclosure. While the method embodiments are discussed according to a specific sequence of steps, various other method embodiments are possible with steps in any logical order, and these other various method embodiments may include fewer or more of the steps described herein.

[0092] In various embodiments, the semiconductor structure may include a substrate, a gate region, and various dielectric layers. Figure 1AAn example of a perspective view of a semiconductor structure 100 is shown, which can be used to form a semiconductor device such as a fin field-effect transistor. The semiconductor structure 100 may include a substrate 102, a buried insulating layer 101, and a plurality of fins 103 formed on the substrate 102. The fins 103 may be isolated by fin recess regions 134. The fin recess region 134 may refer to a plurality of recessed regions located between the individual fins 103. The structure 100 may include isolation regions 104, wherein the fins 103 protrude above the isolation regions 104. The isolation regions 104 may refer to a plurality of regions located between the individual fins 103. A gate dielectric layer 106 may be deposited along the sidewalls and top surface of the fins 103. A gate structure 108 formed of conductive material can be deposited on a first portion of substrate 102 and on gate dielectric layer 106, and source / drain regions 110A and 110B can be disposed on both sides of fin 103 relative to gate dielectric layer 106 and gate structure 108.

[0093] For the purposes of this disclosure, the structure 100 may be described with respect to the front portion 140, the rear portion 142, and the top portion 144. In many cases, the various elements of the front portion 140 of the structure 100 may be the same as or similar to the corresponding elements in the rear portion of the structure 100, and in such cases, only the elements of the front portion 140 of the structure 100 are shown; it should be understood that the same or similar elements exist in the rear portion of the structure. When it is necessary to distinguish between elements in the front portion and related elements in the rear portion of the structure 100, the elements in the front portion are designated with a number and the subtitle "A" (e.g., 15A, etc.), while the elements in the rear portion are designated with the same number and the subtitle "B" (e.g., 15B, etc.). For example, Figure 1A The source / drain regions in the figure are designated as 110A and 110B, but when generally referred to or when it is not necessary to distinguish between the components on the front and rear sides of structure 100, the source / drain regions may also be designated as 110. A specific number and cross-sectional orientation of the components shown in the figures are chosen to best illustrate the various embodiments described herein.

[0094] The various elements described in the following figures may include film layers and regions containing material. These elements are identified by numbers or numbers and subscripts. In various embodiments, the same numbers or numbers and subscripts used to refer to elements formed from these materials may be used to refer to the material forming these elements. If necessary, in some cases, the material forming the element may be identified using numbers (or numbers and subscripts) different from those used to identify individual elements. In various embodiments, elements may include regions containing cavities (e.g., notches, trenches, openings, etc.).

[0095] Figure 1AFurther cross-sectional views are shown in subsequent figures. The “G-view” cross-sectional view spans the channel of structure 100, the gate dielectric layer 106, and the gate structure 108. This cross-sectional view is referred to as the G-view when describing the relevant subsequent figures. The “F-view” cross-sectional view is perpendicular to the G-view and along the longitudinal axis of one of the fins 103, for example, in the direction of current between source / drain regions 110A and 110B. This cross-sectional view is referred to as the F-view when describing the relevant subsequent figures. The “R-view” cross-sectional view is parallel to the F-view and is shown through the fin recess 134. This cross-sectional view is referred to as the R-view when describing the relevant subsequent figures. For clarity, these reference cross-sectional views will be mentioned in subsequent figures. Planes of the cross-sectional views may be shown in some subsequent figures if necessary.

[0096] Figure 1B The diagram shows the top view of structure 100 from a "T-view" perspective, as well as cross-sectional views from the G, F, and R perspectives. (See diagram for reference.) Figure 1B As shown, the cross-sectional plane of the R-angle is located at the center of the fin recess 134. Various other R-angle planes that do not pass through the center of the fin recess 134 may also be used. Such R-angle planes will be described later in the context of the relevant figures.

[0097] Figure 1A and Figure 1B Various film layers that may be present in structure 100 are shown. When structure 100 is used to form a semiconductor device such as a finned field-effect transistor, other film layers such as spacer dielectric layers, interlayer dielectric layers, self-aligned contact layers, and / or contact electrodes may be deposited. (Not shown) Figure 1A and Figure 1B The various membrane layers described herein will be discussed in the context of the following figures.

[0098] Referring now to the accompanying drawings, similar components are indicated by similar numbers. Illustrative manufacturing steps for forming the semiconductor structure 100 are shown according to various embodiments and will be described in more detail below. It should be noted that some of the drawings show various cross-sectional views of the structure 100, with appropriate labeling used to indicate the cross-sectional views. Furthermore, it should be noted that while this specification refers to some components of the structure 100 in the singular, more than one component may be shown in the drawings. However, it should be noted that specific elements may be indicated by numbers and subscripts (e.g., 100A, etc.). Generally, when referring to these elements, only numbers (e.g., 100, etc.) will be used.

[0099] Figure 2A The substrate 102 and the fins 103 formed on the substrate 102 are shown. Figure 2AThe fin formation step is also shown. This step can be one of the steps in the process of manufacturing the semiconductor structure 100. The substrate 102 can be a semiconductor substrate such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or a similar substrate, and can be doped (e.g., using p-type or n-type dopants) or undoped. The substrate 102 can be a wafer such as a silicon wafer. Generally, a semiconductor-on-insulator substrate includes a layer of semiconductor material formed on an insulating layer. For example, the insulating layer can be a buried oxide (BOX) layer 101, which can be formed from silicon oxide or the like. The insulating layer is provided on the substrate, which is generally a silicon or glass substrate. Other substrates such as multi-layered substrates can also be used. In some embodiments, the semiconductor material of the substrate 102 may include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP or combinations thereof.

[0100] Figure 2A The diagram shows a portion of structure 100 from a G-view perspective, which includes a substrate 102 and fins 103. The fins 103 may have a height 204, a width 206, and a spacing between the fins, referred to as the fin pitch 202. For advanced fin field-effect transistor devices, the height 204, width 206, and fin pitch 202 can be measured in nanometers. In an exemplary embodiment, the height 204 may range from 10 to 200 nm, the width 206 may range from 1 to 50 nm, and the fin pitch 202 may range from 10 to 100 nm. Figure 2B An exemplary embodiment is shown in which an isolation region 104 is deposited between fins. The isolation region 104 may be formed of a dielectric insulating material. Figure 2B The height 210 of fin 103 is shown; height 210 is measured from the top surface of isolation region 104. (See diagram.) Figure 1A As shown, the portion of fin 103 that protrudes through the isolation region is the portion of the device that can be controlled by the gate structure 108.

[0101] This can be achieved by using self-aligned double patterning to form the pattern shown in [the diagram]. Figure 2A and Figure 2BThe fins 103 are etched together, and subsequent etching forms fin recess regions between the fins. An illustrative fin recess region 134 is shown in Figures 1B and 2B. The fin recess region 134 can be formed using any suitable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or a combination thereof. The etching can be anisotropic. Figure 2A An exemplary embodiment of the structure obtained by etching substrate 102 is shown. Before etching substrate 102, as... Figure 2A As shown, a mask 221 comprising a plurality of film layers (e.g., film layers 221A and 221B) can be formed on substrate 102. Film layer 221A of mask 221 can be a photoresist patterned using an acceptable optical lithography process or a similar process.

[0102] Alternatively, fins 103 can be formed through epitaxial growth. Figure 2B An exemplary embodiment of a structure obtained by epitaxial growth is shown. First, a mask 221 may be deposited on a substrate 102, and the mask 221 may be patterned using a method such as self-aligned double patterning to form a set of openings in the mask. Fins 103 may then be epitaxially grown in the aforementioned set of openings. For example, fins 103 may be formed by epitaxial growth using metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), or a combination thereof.

[0103] In various embodiments, the mask 221 can be removed after the fin 103 is formed. If the mask 221 is photoresist, it can be removed by an appropriate ashing process using oxygen plasma, for example. In other embodiments, the mask 221 can be removed by etching or a similar method.

[0104] In some embodiments, the fin may include a bottom portion and a top portion. The bottom portion may be etched as described above, and the top portion of the long fin 103 may be epitaxially formed. In some embodiments, the material of the top portion of the fin 103 may be different from the material of the bottom portion of the fin 103. In some embodiments, the bottom portion of the fin 103 may be formed of the material of the substrate 102, such as silicon, and the top portion of the fin 103 may be formed of a III-V compound semiconductor. The materials of the III-V compound semiconductor may include, but are not limited to, InAs, AlAs, GaAs, GaAsP, InP, GaInP (1-90% In percentage), AlInP (1-90% In percentage), GaN, InGaAs (1-90% In percentage), InAlAs (1-90% In percentage), InGaAlAs (1-90% In percentage), GaSb, AlSb, AlP, or GaP. In other embodiments, the top portion of the fin 103 may include other materials such as silicon, silicon carbide, germanium, or group II-VI compound semiconductors.

[0105] Before forming the fins 103 (by etching or epitaxial growth), a planarization process such as chemical mechanical polishing (CMP) can be used on the substrate 102 to polish the top surface of the substrate 102.

[0106] like Figure 2A and Figure 2B As shown, after the step of forming fin 103 by etching fin recess 134 (or the step of epitaxially growing fin to form recess 134), as Figure 2C As shown, insulating material for isolation region 104 can be deposited in fin recess 134. The insulating material for isolation region 104 can be an oxide such as silicon oxide, nitride, or a combination thereof, and can be deposited using high-density plasma CVD (HDP-CVD), flowable CVD (FCVD, e.g., a chemical vapor deposition method in a remote plasma system followed by post-curing to convert it into another material such as an oxide), or a combination thereof. Other insulating materials can be formed using any suitable process. Once the insulating material is formed, an annealing process can be performed. In various embodiments, isolation region 104 may include two or more sublayers formed of different insulating materials. For example, the first layer may be an oxide layer followed by a nitride layer. An exemplary embodiment of the above sublayers is described in... Figure 3BThe images show film layers 310A and 310B.

[0107] Figure 3A A perspective view of an exemplary structure 300 is shown, which includes fins 103, isolation regions 104, and masking layers 221A and 221B. In some cases, fins 103H and 103G may be formed at the boundaries of structure 300, but they are not used to fabricate fin field-effect transistors. Figure 3B An exemplary embodiment of structure 300 is shown, wherein isolation region 104 may include first and second insulating sublayers 310A and 310B. In various embodiments, more than two insulating sublayers may be used. In one exemplary embodiment, insulating layer 310A may be formed of silicon oxide, and insulating layer 310B may be formed of silicon nitride. In various embodiments, various insulating materials may be used. In some embodiments, insulating layer 310B may be an etch stop layer.

[0108] like Figures 2B to 3B As shown, after the step of depositing the insulating material of the isolation region 104 in the fin recessed region 134, a filling material can be deposited in the fin recessed region 134 to form a filling region 401, thereby forming as shown. Figure 4A The filling structure 400 shown is illustrated. In one exemplary embodiment, structure 400 may include a filling region 401 containing a filling material 412, films 221A and 221B, an isolation region 104, and a fin 103. Alternatively, films 221A and 221B may be removed before depositing the filling material 412. The filling material may be SiGe and may be formed by epitaxial growth using chemical vapor deposition, low-pressure chemical vapor deposition (LPCVD), ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy, and / or similar methods. Epitaxial growth of SiGe may result in a filling structure 400 free of voids and / or cracks. Other materials with high etch selectivity relative to the materials forming the fin 103 and the substrate 102 may be used. In one exemplary embodiment, the etch selectivity of the filling material relative to the material forming the fin 103 may be greater than 7. In some embodiments, the filling material may include silicon oxide or silicon nitride. Once the filled region 401 is formed, the annealing process can be carried out. Figure 4A The top surface 403 of the filled semiconductor structure 400 is shown. The top surface 403 can be fabricated using a planarization process such as chemical mechanical polishing to remove any excess filler material.

[0109] The epitaxial growth of filler material 412 may include forming a filler material with a target morphology. The term "morphology" refers to the material structure (i.e., the presence of nanostructure dislocations, point defects, impurities, cracks, shape and size variations, and a metric of material composition variation). In an exemplary embodiment, filler material 412 may comprise regions with different morphologies. For example, the filler material may comprise a first region having a first morphology and adjacent to (or near) the fin surface, while a second region distant from the fin surface may have a second morphology. For example, the first region may be formed to have a low dislocation density and / or a low point defect density, while the second region may be formed to have a higher dislocation density and / or a higher point defect density. In some embodiments, the first and second regions may experience tensile or compressive stress due to the presence of the second and first regions, respectively. The stress and dislocations present in the regions can affect the etching rate of these regions. In various embodiments, filler material 412 with high etch selectivity relative to the material forming fin 103 may be deposited. In some embodiments, the filler material can be etched at a higher etch rate than the etch rate of the material forming the fin 103. In some embodiments, the composition of germanium can be varied when epitaxially growing the filler region 401 formed of SiGe. In some embodiments, the molar fraction of germanium can be higher than or close to the adjacent fin surface, and in some embodiments, the molar fraction of germanium can be higher in regions far from the fin surface. The examples of compositional variations in the described germanium embodiments are merely illustrative, and various other variations can be used in the filler region 401. For example, in some embodiments, variations in the composition of the filler region 401 can be related to changes in the morphology of the filler region 401.

[0110] The morphological characteristics of the filled region 401 can be controlled by utilizing the parameters of the material used to form the filled region 401 through epitaxial growth. For example, during epitaxial growth, the morphological characteristics of the filled region 401 can be controlled by utilizing changes in temperature, pressure, and precursor concentration.

[0111] Figure 4BAn exemplary embodiment of structure 400 is shown, which has a filled region 401 using more than one filler material (e.g., filler materials 412 and 411). For example, filler material 412 may include SiGe, and filler material 412 may be deposited by epitaxial growth. In some embodiments, the film containing material 412 may be 1 to 100 nm thick. Filler material 411 may include insulating materials such as silicon oxide, silicon nitride, and / or similar materials or combinations thereof. The insulating material may be deposited using chemical vapor deposition, atomic layer deposition (ALD), and / or similar methods. In some embodiments, filler material 411 may be formed as follows: Figure 4B The insulating layer shown is located within the fin recess region 134. In some embodiments, the insulating layer may be 1 to 100 nm thick. In some embodiments, the thickness of the film formed by material 412 may be limited by the allowable stress present in this film. For example, SiGe formed on the fin surface may exhibit compressive stress due to lattice mismatch with the material forming fin 103.

[0112] Similar to the formation process of the filled region 401 formed by a single filler material, an annealing process can be performed on the filled region 401 formed by more than one filler material. Furthermore, in Figure 4B In this process, a planarization process such as chemical mechanical polishing can remove any excess filler material 412 and 411 to form the top surface 403 of the filled semiconductor structure 400. Although Figure 4B Only two filler materials, 412 and 411, are shown, but more than two materials may be present. For example, many insulating materials may be used to form insulating layer 411. In one exemplary embodiment, insulating layer 411 may include a sublayer of insulating material. In an exemplary embodiment, the sublayer may be formed of an insulating material with an etch rate similar to that of material 412.

[0113] After the step of forming the fill area 401, as follows Figure 5A and Figure 5B As shown, an insulating layer 501 can be formed by depositing an insulating material on surface 403. Figure 5A and Figure 5B An exemplary embodiment of a semiconductor structure 500 is shown, the semiconductor structure 500 including an insulating layer 501 formed on the top surface 403 of the filled semiconductor structure 400. Figure 5A Showing with Figure 4A Semiconductor structure 400 is related to semiconductor structure 500, and Figure 5B Showing with Figure 4B Semiconductor structure 400 is related to semiconductor structure 500. According to... Figure 5A and Figure 5BIn the exemplary embodiment shown, structure 500 may have a top surface 503. In some embodiments, insulating layer 501 may serve as an etch stop layer and / or provide other functions. Insulating layer 501 may include insulating materials such as SiN, SiO2, HFO2, ZnO, and / or ZrN. Film layer 501 may be formed using low-pressure chemical vapor deposition, chemical vapor deposition, atomic layer deposition, plasma-enhanced chemical vapor deposition (PECVD), or other known formation techniques. The thickness of insulating layer 501 may be between 1 nm and 100 nm.

[0114] After the step of forming the insulating layer 501, a top layer 601 can be deposited on a portion of the surface 503, and then a portion of the insulating layer 501 is etched to form the top layer 601, thereby forming a layer such as Figure 6A The structure 600 is shown. In an exemplary embodiment, film layer 501 may be an etch stop layer to prevent etching to underlying film layers. Top layer 601 may include sublayers 603, 605, and 607. Top layer 601 may cover a portion of top surface 503 of structure 500 and may be manufactured by depositing sublayers 603, 605, and 607 over top surface 503, masking a portion of sublayers 603, 605, and 607, and then etching the unmasked sublayers. Etching steps may include dry or wet etching. For example, dry etching processes may use chlorine-containing gases, fluorine-containing gases, other etching gases, or combinations thereof. Wet etching solutions may include NH4OH, HF (hydrofluoric acid) or diluted HF, deionized water, tetramethylammonium hydroxide (TMAH), other suitable wet etching solutions, or combinations thereof. In some embodiments, multiple etching steps may be performed. For example, in the first step, buffered oxide etching (BOE) can be performed to remove sublayers 605 and 607, followed by dry etching using chlorine-based plasma to remove sublayer 603. These possible etching steps are merely illustrative, and other etching steps may be used.

[0115] In an alternative embodiment, a mask layer may be deposited on the top surface 503, followed by an optical lithography step to form openings for depositing the top layer 601. In one exemplary embodiment, the top layer may be deposited within the openings formed in the mask layer. In one exemplary embodiment, the mask layer may be removed to expose the insulating layer 501. The exposed insulating layer 501 may be etched after the mask layer removal step.

[0116] According to various exemplary embodiments, various materials can be used to form the secondary layers 607, 605, and 603. For example, secondary layer 607 can be an oxide layer such as silicon oxide, secondary layer 605 can be an insulating material such as silicon nitride, and secondary layer 603 can be polycrystalline silicon. The materials mentioned are merely illustrative, and various other materials can be used.

[0117] Figure 6B An exemplary cross-sectional view F of structure 600 is shown. Structure 600 includes fins 103, the aforementioned film layers 221B and 221A, an insulating layer 501, and a top layer 601 having sublayers 603, 605, and 607. The top layer 601 may serve as a mask layer covering a first portion of the filled semiconductor structure 400. The filled semiconductor structure 400 may be etched in areas not covered by the top layer 601. Structure 400 may be etched using any suitable etching process such as reactive ion etching, neutron beam etching, or a combination thereof. In some embodiments, wet etching may be used, and wet etching may include tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or any other wet etchant capable of etching structure 400. Etching may be anisotropic and may only etch the portions of structure 400 not covered by the top layer 601.

[0118] After the step of forming the top layer 601, structure 400 can be etched (structure 400 as shown in the figure). Figure 4A and Figure 4B The portion not covered by the top layer 601 (as shown in the diagram) forms the source / drain etch region 710, thereby forming a... Figure 7A The stepped semiconductor structure 700 is shown. For clarity, the first portion of the semiconductor structure may be covered by the top layer 601, and the second portion of the semiconductor structure may be etched to form a stepped semiconductor structure as shown. Figure 7A The source / drain etched regions 710A and 710B are shown. Figure 7B Another exemplary embodiment is shown, wherein filler materials 411 and 412 are used between the fins. In one exemplary embodiment, depending on filler materials 411 and 412, Figure 7B The structure 700 shown may include etched regions 710A and 710B, which can be etched using various well-known techniques, such as... Figure 4A The structure 400 shown forms etched regions 710A and 710B. For example, etched regions 710A and 710B can be etched first using dry etching and then using wet etching.

[0119] Figure 7CThe diagram shows a structure 700 from an F-view perspective. Structure 700 includes a fin region 701, source / drain etched regions 710A and 710B (also collectively referred to herein as region 710) on the front and rear sides, and a top layer 601. The fin region 701 is formed after etching the aforementioned source / drain etched regions 710A and 710B. In some embodiments, region 710A is a source etched region, and region 710B is a drain etched region. In other embodiments, region 710A is a drain etched region, and region 710B is a source etched region.

[0120] Figure 7C The diagram shows that in various embodiments, the depth 720 of the source / drain etch region 710 can be selected to allow the semiconductor device formed by the structure 700 to achieve optimal performance. In one exemplary embodiment, from Figure 2B The top surface of the isolation region 104 shown is measured, and the depth 720 may be at least the same as or greater than the height 210 of the fin 103. In some embodiments, the etching process of the structure 700 may stop when it reaches the top surface of the isolation region 104, so that the depth 720 is... Figure 2B The fin height 210 shown is the same. In various embodiments, the width 730 of the source / drain etch region 710 may be selected so that the source / drain regions can be formed as further described below, and that the insulating spacer layer separating the source / drain regions from the gate structure can be formed as described below.

[0121] Etched structure 400 (structure 400 as shown) Figure 4A and Figure 4B After a part of the steps shown in the diagram, such as Figure 8A As shown, it can be partially etched laterally as Figure 4A Filled region 401. Figures 8A to 8C illustrate exemplary embodiments of the etched semiconductor structure 800. Figure 8A In one exemplary embodiment shown, structure 800 may include substrate 102, fin region 701, and etched fill region 801. In some embodiments, region 802 may not be etched (e.g., Figure 8B As shown in the figure), and in some embodiments, region 802 may be partially etched (e.g. Figure 8A As shown in the diagram. The etched isolation region 802 can be isolation region 104 ( Figure 1A The region 104 shown is in the etched source / drain recess 710 (as shown in the figure). Figure 7A The portion formed after (as shown in the figure), and the etched filling area 801 can be the filling area 401 (as shown in the figure). Figure 4A(As shown) is the portion formed after etching the source / drain recess 710 and the additional etching steps described herein. Additional etching steps may include etching the fill region 801 from the front side 140 and the rear side 142 to form... Figure 8A The front and rear sidewall grooves 825 are shown in the figure. Figure 8B Another exemplary embodiment of the etched filling region 801 is shown, which includes an etched insulating layer 411. Figure 8C Structure 800 is shown from Figure 8A The R-angle obtained from the cross-sectional plane 805 in the image. In an exemplary embodiment, Figure 8C The etched filling area 801 is shown to include a front trench 825A and a rear trench 825B. In various embodiments, the fin area 701 (e.g.) Figure 8A (shown) includes surface 807, surface 807 includes Figure 8A and Figure 8C The side surface of the groove 825 shown. The width 810 of the surface 807 corresponds to the depth of the front and rear grooves 825. Figure 8C The top layer 601 extends above the front and rear grooves. Return to... Figure 8B In some embodiments, material 412 may be etched instead of material 411. In some embodiments, such as Figure 8D and Figure 8E As shown, material 411 (such as...) can be partially etched. Figure 8A (as shown in the illustration). In some embodiments, such as Figure 8D and Figure 8E As shown, the insulating layer 411 can protrude into the trench 825, the amount of protrusion depending on the etching method used to form the trench 825.

[0122] For the purpose of clarity, Figure 8D and Figure 8E Show respectively Figure 8B The front and rear perspective views of area 830 specified herein. According to an exemplary embodiment, Figure 8D The area 830 shown includes parts such as the top layer 601, the etched fins 701, the front trench 825A, the surface 807A, and the insulating layer 411. Similarly, Figure 8E The rear perspective view of structure 800 is shown, and the surface 807B, the rear sidewall groove 825B, and the insulating layer 411 are also shown.

[0123] In various embodiments, it is possible to Figure 9A An insulating layer 901 is deposited in the front and rear trenches 825 shown. Figures 9A to 9C An exemplary embodiment of structure 900 obtained by depositing an insulating layer 901A to a front trench 825A is shown, wherein the insulating layer 901A is formed adjacent to region 710A. Figure 9CAccording to an exemplary embodiment, the R-view of structure 900 is shown, where the R-view is through... Figure 9B The cross-sectional plane of film layer 901A shown. In an exemplary embodiment, Figure 9C The insulating layers 901A and 901B are shown deposited on Figure 8D and Figure 8E The corresponding front and rear trenches 825A and 825B are shown in the diagram. In various embodiments, the width 910 of the insulating layer 901 is chosen to prevent conductivity through the insulating layer 901. Figure 9D An exemplary embodiment of an insulating layer 901A or 901B formed from a plurality of dielectric sublayers 911A to 911C is shown. Some exemplary materials for the dielectric sublayers may include SiO, LaO, AlO, AlN, AlON, ZrO, HfO, SiN, Si, ZnO, ZrN, TiO, TaO, ZrAlO, YO, TaCN, ZrSi, HfSi, SiOCN, SiOC, and SiCN. The dielectric sublayers may be formed using low-pressure chemical vapor deposition, chemical vapor deposition, atomic layer deposition, plasma-enhanced chemical vapor deposition, or other known formation techniques. In various embodiments, the insulating layer 901 may be formed of a material having high etch selectivity relative to the fill material of the filled region 401. Figure 9B This shows that insulating layer 901 is deposited in trench 825 containing insulating layer 411 (e.g. Figure 8B An exemplary embodiment of the trench 825A shown.

[0124] Alternatively, insulating material (e.g., the material forming insulating layer 901) may be deposited not only in trench 825 but also in portions of the source / drain etched regions 710A and 710B. Figure 9E In one exemplary embodiment shown, insulating material may be deposited in the etched region 710 and may form an insulating region 908. In some embodiments, the insulating region 908 may include, for example, Figure 9F The multilayer dielectric layers shown (e.g., 918 and 919) are deposited one layer on top of another. Figure 10A In one exemplary embodiment shown, a portion of the insulating region may be removed to form recessed region 1010 and region 1011. Recessed region 1010 may be formed using various known etching techniques for etching insulating materials (e.g., buffered oxide etching).

[0125] In an alternative embodiment, such as Figure 10B As shown in the example, trenches 1015 can be formed in the insulating region 908B, followed by deposition. Figure 10C The insulating spacer layer 1017 is shown. The insulating spacer layer 1017 can be formed of various materials and may include sublayers. Figure 10CIn one exemplary embodiment shown, regions 1027 and 1028B are adjacent to the insulating spacer layer 1017. In one exemplary embodiment, the film layer 1017 may be formed of a material with high etch selectivity relative to the material forming regions 1027 and 1028B. In an exemplary embodiment, such as Figure 10D As shown, it can be removed Figure 10C The material forming region 1027 shown is used to form etched region 1040. For example, etched region 1040 can be formed by etching the material of region 1027 using various known etching techniques. For example, buffer oxide etching can be performed to remove the material forming region 1027. Figure 10D The insulating spacer layer 1017 and region 1028B are shown. Figure 10C The membrane layer 1017 shown is the same as region 1028B.

[0126] like Figure 9A As shown in the example, after the step of depositing insulating layer 901, as Figure 11A As shown, the source / drain region 1101 can be formed in the source / drain etched region 710 (e.g., Figure 7C As shown in the figure. Figure 11C According to an exemplary embodiment, structure 1100 is shown in... Figure 11B The cross-sectional plane shown is viewed from the R-angle. Source / drain regions 1101A and 1101B may be epitaxially grown on fin 103 and adjacent to insulating layer 901. In various embodiments, source / drain regions 1101 may partially or completely fill source / drain etched regions 710.

[0127] The source / drain region 1101 can be formed of any suitable material, such as SiGe, SiGeB, Ge, or SeSn. The epitaxial source / drain region 1101 may have a surface raised from an individual surface of the fin 103, and may have, for example... Figure 11A The facet 1103 is shown. Dopant can be implanted into the epitaxial source / drain region 1101 and / or fin 103. For example, when structure 100 is used to fabricate an n-type metal-oxide-semiconductor fin field-effect transistor, n-type impurities can be implanted, and the n-type impurities may include phosphorus or arsenic, etc. For fabricating a p-type metal-oxide-semiconductor fin field-effect transistor, p-type impurities can be implanted, and the p-type impurities may include boron or gallium, etc. After impurity implantation, an annealing step can be performed to activate the p-type or n-type impurities. The source / drain region may have a diameter between approximately 10⁻⁶ and 10⁻⁶. 19 cm -3 To about 10 21 cm -3The impurity concentration between them. In some embodiments, during in-situ doping epitaxial growth, impurities can be introduced into the source / drain region 1101. In some embodiments, in order to remove the damage on the surface of the source / drain region 1101, an oxidation process can be performed. During the oxidation process, the damaged part can react with oxygen to form an oxide layer. Then, the oxide layer can be removed by an etching method such as wet etching.

[0128] Figure 11D FIG. shows an exemplary embodiment in which the source / drain region 1101B is formed in the source / drain recess region 1010, and the source / drain recess region 1010 is adjacent to Figure 10A the region 1011 shown in. Similarly, Figure 11E FIG. shows that the source / drain region 1101 is formed in the recess region 1040 (the recess region 1040 is shown in Figure 10D ).

[0129] After the step of depositing the source / drain region 1101, as shown in Figure 12A an interlayer dielectric (ILD) layer 1201 can be formed over the source / drain region 1101. In various embodiments, the interlayer dielectric layer 1201 can be adjacent to Figure 12A the top layer 601 shown in. The interlayer dielectric layer 1201 can be formed of a dielectric material such as an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), a phospho-silicate glass (PSG), a boro-silicate glass (BSG), a boron-doped PSG (BPSG), or an undoped silicate glass (USG), etc. The film layer 1201 can be deposited by any suitable method such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, or atomic layer deposition. The height of the void 1221 in the interlayer dielectric layer 1201 can be between 1 nm and 500 nm, but smaller or larger heights can be used. Then, the interlayer dielectric layer 1201 can be planarized by chemical mechanical polishing. In some embodiments, a liner 1203 such as silicon nitride can be formed over the surfaces of the source / drain region 1101 and a part of the interlayer dielectric layer 1201.

[0130] After the step of forming the interlayer dielectric layer 1201, the top layer 601 can be removed to form a void 1221 as shown in Figure 12B or a void 1235 as shown in Figure 12C . When removing the top layer 601, as shown in Figure 5AThe insulating layer 501 shown can serve as an etching stop layer. The top layer 601 can be etched using any known method such as wet etching, dry (plasma) etching, and / or other processes. For example, a dry etching process can use chlorine-containing gases, fluorine-containing gases, other etching gases, or combinations thereof. Wet etching solutions may include NH4OH, HF (hydrofluoric acid) or diluted HF, deionized water, tetramethylammonium hydroxide, other suitable wet etching solutions, or combinations thereof. Alternatively, as... Figure 12C As shown, a planarization process such as chemical mechanical polishing can be used to remove the top layer 601 and part of the interlayer dielectric layer 1201 to form a void 1235 and make the top surface of the interlayer dielectric layer 1201 flush with the top surface of the film layer 221B and the top surface of the filling region 401. Figure 12C The void 1235 shown corresponds to the area where the material has been removed. The removal of the top layer 601 forms a partial interlayer dielectric layer 1201. Figure 12C The structure shown.

[0131] 13A shows the filled semiconductor structure 1200 along... Figure 12A The image shows a G-view of plane 1250, where the top layer 601 and part of the interlayer dielectric layer 1201 have been removed. Figure 13A A cross-sectional view of the filled region 401 is shown. The filled region 401 has a filling material 412, voids 1235 after material removal, a membrane layer 221B, and Figure 1A The isolation zone 104 shown in the image. Figure 13B The G-view shows a filled semiconductor structure 1200 with a filled region 401, which includes an insulating layer 411 adjacent to the filled material 412 and is shown for the first time in the image. Figure 2A The membrane layer 221B in the middle.

[0132] After the step of removing the top layer 601, the filler material forming the fill area 401 can be removed. Removing the fill area 401 may include multiple steps. Figure 14A and Figure 14B The first step is shown, removing from structure 1200 as previously shown. Figure 13A and Figure 13B The film layer 221B is used to form the notch 1420. In a subsequent step, the filler material forming the filled area 401 can be removed by etching to form a shape such as... Figure 15A The partially exposed or re-exposed fin etched area 134 shown is defined as follows: the term "exposed" or "re-exposed" refers to the state of the fin etched area 134 before the formation of the filling area 401. The phrases "partially exposed" or "partially re-exposed" refer to the state achieved by etching a portion of the structure 400 and removing... Figure 13AThe filled region 401 shown modifies the fin etched region 134. Region 134 exposes the channel regions of individual epitaxial fins. Each channel region is disposed between adjacent pairs of epitaxial source / drain regions 1101. In an exemplary embodiment, as shown... Figure 13A As shown, when etching filler material 412 from region 401, as Figure 15B As shown, the insulating layer 310B deposited on the insulating layer 310A can serve as an etch stop layer. In various embodiments, one or more etching processes can be selectively used to remove the fill region 401. The etching process may include suitable wet etching, dry (plasma) etching, and / or other processes. The etching process may depend on the material used to form the fill region 401. For example, for SiGe fill material 412, a dry etching process can be used, and the dry etching process may include chlorine-containing gas, fluorine-containing gas, other etching gases, or combinations thereof. During dry etching, anisotropic etching can be performed using reactive ion etching with SF6 / O2 plasma, neutron beam etching, or deep cryogenic RIE. In some embodiments, when the fill region 401 comprises multiple fill materials (such as... Figure 4B When using filler materials 412 and 411 as shown, both wet and dry etching can be used. For example, wet etching can be used for insulating filler material 411. The wet etching solution may include NH4OH, HF (hydrofluoric acid) or diluted HF, deionized water, tetramethylammonium hydroxide, other suitable wet etching solutions, or combinations thereof. The dry etching described above can then be performed after wet etching.

[0133] After the step of removing filler material 412 from region 401, deposition can be performed as follows: Figure 16 and Figure 17 The gate dielectric layer 106 is shown. The gate dielectric layer 106 may be deposited in the fin recess 134 adjacent to the fin 103. For example, Figure 16 The diagram shows a gate dielectric layer 106 compliantly deposited on the etched regions 134 adjacent to the top surface 1601 and sidewall surfaces 1602 of the epitaxial fin 103 and the top surface 1607 of the isolation region 104. According to some embodiments, the gate dielectric layer 106 may be formed of silicon oxide, silicon nitride, or a multilayer thereof. In some embodiments, the gate dielectric layer 106 may be formed of a dielectric material with a high dielectric constant. For example, the film 106 may include metal oxides or silicides of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. Methods for forming the film 106 may include molecular beam deposition, atomic layer deposition, or plasma-enhanced chemical vapor deposition, etc.

[0134] In some embodiments, the gate dielectric layer 106 may include a structure having multiple sublayers. For example, the film layer 106 may include a first layer adjacent to the fin 103. In one exemplary embodiment, such as Figure 17 As shown, the interface sublayer 1701 may be adjacent to the fin 103. The interface sublayer 1701 may include a dielectric material such as a silicon oxide layer (SiO2) or silicon oxynitride and / or another suitable dielectric, and may be formed using chemical oxidation, thermal oxidation, atomic layer deposition, chemical vapor deposition, etc. In one exemplary embodiment, the interface sublayer 1701 is followed by a dielectric sublayer 1702, which is formed of a high-dielectric-constant dielectric material such as HfO2, Al2O3, La2O3, TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, combinations thereof, or other suitable materials. The dielectric sublayer 1702 may be formed using atomic layer deposition and / or other suitable methods. Following the dielectric secondary layer 1702 is a barrier secondary layer 1703, which protects the dielectric secondary layer 1702 from metal impurities generated during the deposition of the metal-containing gate structure 108. In various embodiments, the barrier secondary layer 1703 may include a metal element. For example, the barrier secondary layer 1703 may include tantalum nitride, titanium nitride, or niobium nitride. In an exemplary embodiment, the barrier secondary layer 1703 is formed using atomic layer deposition, physical vapor deposition (PVD), chemical vapor deposition, or other suitable methods, and the barrier secondary layer 1703 may have approximately [missing information - likely a number of elements]. The thickness can be between several nanometers. The thickness and material of the barrier sublayer 1703 can be selected to reduce or prevent the diffusion of metal used to form the gate structure 108 to the dielectric sublayer 1702 and the interface sublayer 1701. In various embodiments of this disclosure, another sublayer can also be used to form the gate dielectric layer 106. For example, the dielectric sublayer 1702 formed of a high-dielectric-constant dielectric material may include multiple sublayers of dielectric materials with different high-dielectric-constant properties. Similarly, the barrier sublayer 1703 may include a plurality of sublayers, which may be made of metal nitride and metal oxide materials such as tantalum nitride, titanium nitride, tantalum oxide, and titanium oxide. Other oxide or nitride materials can be deposited using various known methods.

[0135] After the step of forming the gate dielectric layer 106, as follows Figure 17 and Figure 18 As shown, a gate structure 108 can be deposited. Figure 17A metal layer 1704 is shown to be deposited on the gate dielectric layer 106. The metal layer 1704 may be formed of a metal having a selected work function. The work function of the metal layer 1704 may be p-type or n-type. Indicative metals of p-type work function include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, other suitable p-type work function materials, or combinations thereof. These metals can be used to form p-type metal-oxide-semiconductor fin field-effect transistors. Indicative metals of n-type work function include Ti, Ag, TaAl, TaAlC, TaAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. These metals can be used to form n-type metal-oxide-semiconductor fin field-effect transistors. The metal layer 1704 may include multiple film layers and may be deposited using chemical vapor deposition, physical vapor deposition, and / or another suitable process.

[0136] After depositing the metal layer 1704, the remaining space can be used to deposit other materials such as... Figure 17 The metal gate electrode material forming region 1711 shown is used to complete the gate structure 108. Region 1711 may include aluminum, tungsten, cobalt, copper, and / or other suitable materials. Region 1711 may be formed using chemical vapor deposition, physical vapor deposition, plating, and / or other suitable processes. A chemical mechanical polishing process may be performed to remove excess material to planarize the top surface of the gate structure 108 and complete the formation of the gate structure 108.

[0137] In various embodiments, such as Figure 18 The top conductive layer 1801 shown may be formed on the gate structure 108. The top conductive layer 1801 protects the gate structure 108 from various subsequent processes, such as etching or annealing. The top conductive layer 1801 may include materials such as tungsten. In various embodiments, an insulating layer 1802 (also referred to as a self-aligned layer) may be deposited on the top conductive layer 1801. The insulating layer 1802 prevents electrical connections from forming between the source / drain and the gate, and the insulating layer 1802 may include a low dielectric constant material (e.g., a material with a dielectric constant less than 15). In some embodiments, the film layer 1802 may include SiN, SiO2, HfO2, ZnO, and / or ZrN, etc.

[0138] Figure 1AThe semiconductor structure 100 shown can be used to fabricate semiconductor devices such as fin field-effect transistors. For fabricating fin field-effect transistor devices, the structure may further include source / drain contacts that contact the source / drain regions 1101. The source / drain contacts may include a conductive material (e.g., a metal such as tungsten, polysilicon, or a metal-containing material). In various embodiments, an interlayer dielectric layer may be deposited over the source / drain regions. For example, Figure 19 A structure 1900 is shown, including an interlayer dielectric layer 1901 deposited over a source / drain region 1101 formed on a fin 103. Structure 1900 may include a spacer layer 1904 deposited between the gate structure 108 and the source / drain region 1101. In various embodiments, for example, the spacer layer 1904 may include multiple dielectric layers. The spacer 1904 may be formed of silicon oxide, hafnium oxide, or silicon nitride, etc. Furthermore, structure 1900 may include an interlayer dielectric layer 1902 deposited over the spacer layer 1904. The upper surfaces of the interlayer dielectric layers 1901 and 1902 may be planarized. In some embodiments, a liner material located at the interface between the source / drain 1101 and the interlayer dielectric layer 1901 may be used to protect the source / drain contacts. For example, the liner material may be titanium nitride. In some embodiments, a silicide layer (not shown) may be formed on the source / drain region 1101.

[0139] In various embodiments, such as Figure 20 As shown, a process 2000 can be provided to form various of the said semiconductor structures. In step 2001 of process 2000, fins can be formed on semiconductor structure 102 (e.g., ...). Figure 1A As shown in the figure. In step 2002, as can be deposited Figure 2B The isolation zone shown, and in step 2003, as Figure 4A or Figure 4B As an example, the area between the fins can be filled. In step 2004, a structure such as... Figure 5A The insulating layer 501 shown, and in step 2005, can be... Figure 6A A top layer 601 is deposited on a portion of the surface 503 shown. In step 2006, a structure as shown can be formed. Figure 7A The source / drain etch region 710 shown is partially etched in step 2007, as shown. Figure 8A The filling area 401 shown. In step 2008, it can be... Figure 9A An insulating layer 901 is deposited in the front and rear trenches 825 shown, and in step 2009, it can be... Figure 11A Source / drain regions 1101 are formed in the source / drain etched region 710 shown. In step 2010, the source / drain region 1101 can be formed... Figure 12AAn interlayer dielectric layer is formed over the source / drain region 1101 shown, and in step 2011, it can be removed as follows: Figure 12B and Figure 12C The top layer 601 is shown. In step 2012, the filler material forming the filled area 401 can be removed, and in step 2013, a layer such as... Figure 16 and Figure 17 The gate dielectric layer 106 is shown. In step 2014, a process such as... Figure 17 and Figure 18 The gate structure 108 shown is illustrated.

[0140] The disclosed embodiments include a method for designing and / or manufacturing a circuit, the circuit including one or more devices designed and manufactured based on the various structures described herein (e.g., including one or more devices manufactured using the semiconductor structures described herein). In this context, Figure 21 This is an exemplary flowchart illustrating the fabrication of circuitry 2126 according to one embodiment. Initially, a user may use device design system 2110 to generate device design 2112 for a semiconductor device, which includes the semiconductor structure 100 described herein. Device design 2112 may include code that device fabrication system 2114 may use to generate a set of physical devices 2116 including the semiconductor structure 100 according to the features defined in device design 2112. Similarly, device design 2112 (e.g., components that can be used in a circuit) may be provided to circuit design system 2120, from which a user may generate circuit design 2122 (e.g., by connecting one or more inputs and outputs to various devices included in the circuit). Circuit design 2122 may include code that may include devices designed as described above. In any case, circuit design 2122 and / or one or more physical devices 2116 may be provided to circuit fabrication system 2124, which may generate physical circuitry 2126 based on circuit design 2122. The physical circuit 2126 may include one or more devices 2116, and the devices 2116 include the semiconductor structure 100 as described above.

[0141] The disclosed embodiments provide a device design system 2110 and / or a device manufacturing system 2114 for designing a semiconductor device 2116 including the semiconductor structure 100 described herein. In this case, systems 2110 and 2114 may include computing devices specifically programmed to execute the design and / or manufacturing methods of the semiconductor device 2116 including the semiconductor structure 100. Similarly, various embodiments provide a circuit design system 2120 and / or a circuit manufacturing system 2124 for designing a circuit 2126 including at least one device 2116, where the device 2116 includes the semiconductor structure 100 described herein. In this case, systems 2120 and 2124 may include computing devices specifically programmed to execute the circuit 2126 including at least one semiconductor device 1016, where the semiconductor device 1016 includes the semiconductor structure 100 described herein.

[0142] In some cases, the disclosed embodiments may include a computer program installed on at least one computer-readable medium, which, when executed, enables a computer system to implement methods for designing and / or manufacturing a semiconductor device including the semiconductor structure 100 described herein. For example, the computer program may enable a device design system 2110 to generate the device design 2112 described herein. In this case, the computer-readable medium includes program code that, when executed by the computer system, implements some or all of the processes described herein. It should be understood that the term "computer-readable medium" includes one or more of the substantial expressions of any form known or subsequently developed, from which a stored copy of program code can be understood, reproduced, or communicated by a computing device.

[0143] In some cases, the disclosed embodiments may include a method of providing a copy of program code that, when executed by a computer system, implements some or all of the processes described herein. In this case, the computer system may process the copy of the program code to generate or transmit (for reception at different second locations) a set of data signals having one or more of these characteristic sets, and / or modify the program code by encoding a copy of the program code in this set of data signals. Similarly, various embodiments provide methods of obtaining a copy of program code that implements some or all of the processes described herein, including a computer system receiving the set of data signals described herein and translating the set of data signals into a copy of a computer program installed on at least one computer-readable medium. In any case, this set of data signals may be transmitted / received using any form of communication link.

[0144] In some cases, the disclosed embodiments may include a method for generating a device design system 2110 and / or a device manufacturing system 2114 for manufacturing a semiconductor device including the semiconductor structure 100 described herein. In this case, a computer system may be obtained (e.g., manufactured, maintained, made usable, etc.), and one or more components for performing the process described herein may be obtained (e.g., manufactured, purchased, used, modified, etc.) and deployed to the computer system. In this case, the deployment steps may include one or more of the following: (1) installing code on the computing device; (2) adding one or more computing and / or input / output devices to the computer system; and / or (3) merging and / or modifying the computer system to enable it to perform the process described herein, etc.

[0145] The exemplary methods and techniques described herein can be used to manufacture integrated circuit chips. Manufacturers may distribute the manufactured integrated circuit chips in raw wafer form (i.e., a single wafer having multiple unpackaged chips) or in packaged form, such as bare dies. In the packaged form, the chips are mounted in a single-chip package (e.g., a plastic carrier with leads attached to a motherboard) or in a multi-chip package (e.g., a ceramic carrier with surface-mount or embedded interconnects, or both). The chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices, which are part of (a) a semi-finished product such as a motherboard or (b) a final product. The final product can be any product including integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with many components, such as displays, keyboards or other input devices, and / or central processing units; these are not limiting examples. Unless otherwise described or otherwise stated herein, “deposition” may include any currently known or subsequently developed techniques suitable for use with the material to be deposited, including chemical vapor deposition, low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, semi-atmosphere CVD (SACVD), high-density plasma chemical vapor deposition, rapid thermal CVD (RTCVD), ultra-high vacuum chemical vapor deposition, limited reaction processing CVD (LRPCVD), metal-organic chemical vapor deposition, sputtering deposition, ion beam deposition, electron beam deposition, laser-assisted deposition, thermal oxidation, thermal nitridation, spin-on methods, physical vapor deposition, atomic layer deposition, chemical oxidation, molecular beam epitaxy, electroplating, or evaporation, but is not limited thereto.

[0146] Unless otherwise described or otherwise stated herein, “etching” may include, but is not limited to, any techniques currently known or subsequently developed that are suitable for removing material, including dry etching (e.g., plasma etching, plasmaless gas etching, sputtering etching, ion milling, reactive ion etching) or wet etching (e.g., abrasive formulations that dissolve or grind away a portion of a structure with an acid, alkali, or solvent).

[0147] The exemplary methods and structures described herein are used to fabricate semiconductor structures with metal gates. This semiconductor structure can be used to form fin field-effect transistors and similar devices. In various embodiments, fins are first fabricated on a semiconductor substrate to form the semiconductor structure. The fins can be fabricated by etching the semiconductor substrate, epitaxial growth, or a combination of both. In various embodiments, multiple fins are formed on the semiconductor substrate. In various embodiments, a filler material is epitaxially grown in the regions between the fins. In some embodiments, the filler material may include SiGe. After the filler material is epitaxially grown, a top layer can be deposited on the filled semiconductor structure, and source and drain notches can be formed. Then, source and drain regions can be deposited in the source and drain notches. In various embodiments, after removing the top layer, the filler material between the fins can be removed. After removing the filler material, a gate structure can be deposited in the regions between the fins. In various embodiments, the gate structure includes dielectric and metal layers. In various embodiments, an insulating layer separates the gate structure from the source and drain regions in the regions between the fins.

[0148] Consistent with the disclosed embodiments, a method for manufacturing a semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate comprising fins separated by fin etch regions. The method for manufacturing the semiconductor structure may include filling the fin etch regions with a first material to form a filled semiconductor structure; forming a top layer over a first portion of the filled semiconductor structure; and etching source and drain etch regions from a second portion of the filled semiconductor structure. Furthermore, the method for manufacturing the semiconductor structure may include laterally etching a portion of the first material from the front and rear sidewalls of the first portion exposed by the source and drain etch regions to form front and rear sidewall trenches; depositing a second material into the front and rear sidewall trenches; forming a source region in the source etch region and a drain region in the drain etch region. Furthermore, the method for forming the semiconductor structure may include removing the top layer to expose the top surface of the first portion; removing the first filling material and partially re-exposing the fin etch regions; depositing a gate dielectric layer conforming to the surface of the partially re-exposed fin etch regions; and depositing a conductive material into the remaining portion of the fin etch regions.

[0149] Consistent with another disclosed embodiment, a method for manufacturing a semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate comprising fins separated by fin etch regions. The method for manufacturing the semiconductor structure may include depositing a first filler material to form a compliant layer on the surface of the fin etch regions; depositing a second filler material to form a filled semiconductor structure; forming a top layer over a first portion of the filled semiconductor structure; and etching source etch regions and drain etch regions from a second portion of the filled semiconductor structure. Furthermore, the method for manufacturing the semiconductor structure may include laterally etching a portion of the first filler material from the front and rear sidewalls of the first portion exposed by the source and drain etch regions to form front and rear sidewall trenches; depositing a second material into the front and rear sidewall trenches; forming a source region in the source etch region; and forming a drain region in the drain etch region. Furthermore, the method of manufacturing the semiconductor structure may include removing the top layer to expose the top surface of the first portion; removing the first and second filler materials and partially re-exposing the fin etched region; depositing a gate dielectric layer conforming to the surface of the partially re-exposed fin etched region; and depositing a conductive material into the remaining portion of the fin etched region.

[0150] Consistent with another disclosed embodiment, the semiconductor structure includes a fin region extending from a semiconductor substrate, the fin region comprising at least a pair of fins. The pair of fins is separated by a fill region filled with a first material, wherein the first material has a higher etch rate than the material used to form the at least one pair of fins. The first material is epitaxially grown to form the fill region, and the fin region includes a first set of surfaces and a second set of surfaces. The semiconductor structure also includes a source region and a drain region, the source region being adjacent to the first set of surfaces of the fin region, and the drain region being adjacent to the second set of surfaces of the fin region.

[0151] The accompanying drawings and this specification illustrate and describe various embodiments and their parts and components. Those skilled in the art to which this disclosure pertains will understand that any specific terminology used in the specification is for convenience only, and therefore the various embodiments should not be limited to the specific processes identified by such terminology. Thus, the embodiments described herein are intended to be illustrative rather than restrictive, and the scope of the various embodiments should be determined with reference to the claims.

[0152] The foregoing outlines components of several embodiments to facilitate a better understanding of the views expressed in the embodiments of this disclosure by those skilled in the art. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of this disclosure to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the concept and scope of this disclosure, and that various changes, substitutions, and replacements can be made without departing from the concept and scope of this disclosure.

Claims

1. A method for forming a semiconductor structure, the semiconductor structure comprising a plurality of fins separated by a fin etch region, the method comprising: The fin recessed area is filled with a first material to form a filled semiconductor structure; A top layer is formed on a first portion of the filled semiconductor structure; A source etch region and a drain etch region are etched from a second portion of the filled semiconductor structure; A portion of the first material is laterally etched from the front and rear sidewalls of the first portion exposed from the source and drain etched regions to form a front and rear sidewall trench. A second material is deposited into the trenches of the front and rear sidewalls; A source region is formed in the source etched region, and a drain region is formed in the drain etched region. Remove the top layer to expose the top surface of the first section; Remove the first material and partially re-expose the fin's etched area; A gate dielectric layer is deposited conforming to a surface of the partially re-exposed fin recessed region; and A conductive material is deposited into a remaining portion of the fin's recessed area.

2. The method for forming a semiconductor structure as claimed in claim 1 further includes depositing a protective mask on a top surface of the fin before filling the fin etched area with the first material.

3. The method for forming a semiconductor structure as claimed in claim 1, wherein the step of filling the fin etched region with the first material includes epitaxial growth of the first material.

4. The method for forming a semiconductor structure as described in claim 1, wherein the conductive material is a metal.

5. The method for forming a semiconductor structure as claimed in claim 1, wherein the second material comprises a dielectric material.

6. The method for forming a semiconductor structure as claimed in claim 1, wherein the second material comprises a dielectric material with a high dielectric constant.

7. The method for forming a semiconductor structure as claimed in claim 1 further includes a chemical mechanical planarization step prior to the step of forming the top layer.

8. The method for forming a semiconductor structure as claimed in claim 1, wherein the top layer comprises polycrystalline silicon.

9. The method for forming a semiconductor structure as claimed in claim 1, further comprising depositing an oxide material into the fin etched region and partially filling the fin etched region before filling the fin etched region with the first material.

10. The method of forming a semiconductor structure as claimed in claim 9, wherein the step of etching the source etch region and the drain etch region from the second portion of the filled semiconductor structure includes etching the second portion to at least the depth exposing the oxide material.

11. The method for forming a semiconductor structure as claimed in claim 1, wherein the step of forming the source region and the drain region comprises epitaxially growing a silicon-containing semiconductor material.

12. The method for forming a semiconductor structure as claimed in claim 1, wherein the second material comprises a dielectric material.

13. The method of forming a semiconductor structure as claimed in claim 1, wherein a thickness of the second material is selected to prevent conductivity between the conductive material and the source region and between the conductive material and the drain region.

14. The method for forming a semiconductor structure as claimed in claim 1, further comprising depositing a self-aligned layer on a top surface of the conductive material.

15. The method for forming a semiconductor structure as claimed in claim 1, wherein the step of etching the source etch region and the drain etch region includes performing reactive ion etching.

16. A method for forming a semiconductor structure, the semiconductor structure comprising a plurality of fins separated by a fin etch region, the method comprising: An insulating material is deposited to form a conforming layer on a surface of the fin recessed area; Deposit a filler material to form a filled semiconductor structure; A top layer is formed on a first portion of the filled semiconductor structure; A source etch region and a drain etch region are etched from a second portion of the filled semiconductor structure; A portion of the filling material is laterally etched from the front and rear sidewalls of the first portion exposed from the source and drain etched areas to form a front and rear sidewall trench. A second material is deposited into the trenches of the front and rear sidewalls; A source region is formed in the source etched region, and a drain region is formed in the drain etched region. Remove the top layer to expose the top surface of the first section; Remove the filler material and partially re-expose the fin etched area; A gate dielectric layer is deposited that conforms to a surface of the partially re-exposed fin recessed region; as well as A conductive material is deposited into a remaining portion of the fin's recessed area.

17. The method of forming a semiconductor structure as claimed in claim 16, further comprising depositing a protective mask on a top surface of the fin before filling the fin recessed area with the insulating material and the filling material.

18. The method for forming a semiconductor structure as claimed in claim 16, wherein the filling material comprises an oxide material.

19. The method for forming a semiconductor structure as claimed in claim 16, wherein the step of etching the source etch region and the drain etch region includes performing reactive ion etching.

20. A semiconductor structure for forming a fin-shaped field-effect transistor device, the semiconductor structure comprising: A fin region extending from a semiconductor substrate, the fin region including at least a pair of fins, wherein the pair of fins is separated by a filling region filled with a first material having a higher etch rate than a material used to form the at least one pair of fins, the first material being epitaxially grown to form the filling region, the fin region including a first set of surfaces and a second set of surfaces; and A source electrode region and a drain electrode region, the source electrode region being adjacent to the first set of surfaces of the fin region, and the drain electrode region being adjacent to the second set of surfaces of the fin region.

21. The semiconductor structure of claim 20, wherein the first material comprises SiGe.

22. The semiconductor structure of claim 20 further includes an insulating material located within the fin region, and the insulating material having a thickness greater than or equal to 1 nm and less than or equal to 100 nm.

23. The semiconductor structure of claim 22, wherein the insulating material has high etch selectivity compared to the first material.

24. The semiconductor structure of claim 20, further comprising a first insulating layer and a second insulating layer, wherein the first insulating layer is substantially parallel to the second insulating layer, and wherein the first insulating layer is in contact with the first set of surfaces, and the second insulating layer is in contact with the second set of surfaces.

25. The semiconductor structure of claim 24, wherein the first insulating layer is formed of a plurality of dielectric sublayers, the dielectric sublayers comprising two or more of SiO, LaO, AlO, AlN, AlON, ZrO, HfO, SiN, ZnO, ZrN, TiO, TaO, ZrAlO, YO, TaCN, ZrSi, HfSi, SiOCN, SiOC, or SiCN.

26. The semiconductor structure of claim 25, wherein the second insulating layer comprises the dielectric sublayer arranged as in the first insulating layer.

27. The semiconductor structure of claim 20 further includes an etch stop layer in contact with the filled region, and the etch stop layer includes at least one of SiN, SiO2, HFO2, ZnO or ZrN, wherein the etch stop layer has a thickness greater than or equal to 1 nm and less than or equal to 100 nm.

28. The semiconductor structure of claim 27, further comprising a top layer contacting the etch stop layer, and the top layer comprising at least a first sub-layer and a second sub-layer, wherein: The first top-secondary layer was formed by etching using a wet etching liquid, and The second top layer was formed by etching using plasma dry etching.

29. A semiconductor structure comprising: A plurality of semiconductor fins are formed of a material having a first etch rate, the semiconductor fins being separated from each other by an epitaxially grown filler material having a second etch rate different from the first etch rate; A source region is located adjacent to a first set of surfaces of the semiconductor fin; as well as A drain region is adjacent to a second set of surfaces of the semiconductor fin, the first set of surfaces and the second set of surfaces being located on opposite sides of the semiconductor fin.

30. The semiconductor structure of claim 29, wherein the filling material comprises SiGe.

31. The semiconductor structure of claim 29 further includes an insulating material separating the semiconductor fins from the filler material, wherein the insulating material has a thickness greater than or equal to 1 nm and less than or equal to 100 nm.

32. The semiconductor structure of claim 31, wherein the insulating material has high etch selectivity compared to the filling material.

33. The semiconductor structure of claim 29 further includes a first insulating layer and a second insulating layer, wherein the first insulating layer is substantially parallel to the second insulating layer, and wherein the first insulating layer is in contact with the first set of surfaces, and the second insulating layer is in contact with the second set of surfaces.

34. The semiconductor structure of claim 33, wherein the first insulating layer is formed of a plurality of dielectric sublayers, the dielectric sublayers comprising two or more of SiO, LaO, AlO, AlN, AlON, ZrO, HfO, SiN, ZnO, ZrN, TiO, TaO, ZrAlO, YO, TaCN, ZrSi, HfSi, SiOCN, SiOC, or SiCN.

35. The semiconductor structure of claim 34, wherein the second insulating layer comprises the dielectric sublayer arranged as in the first insulating layer.

36. The semiconductor structure of claim 29 further includes an etch stop layer in contact with the filler material, and the etch stop layer includes at least one of SiN, SiO2, HFO2, ZnO or ZrN, wherein the etch stop layer has a thickness greater than or equal to 1 nm and less than or equal to 100 nm.

37. The semiconductor structure of claim 36, further comprising a top layer contacting the etch stop layer, and the top layer comprising at least a first sub-layer and a second sub-layer, wherein: The first top-secondary layer was formed by etching using a wet etching liquid, and The second top layer was formed by etching using plasma dry etching.

38. A semiconductor structure comprising: A fin region extends from a semiconductor substrate, the fin region including at least a pair of fins, wherein the pair of fins is separated by a filling region filled with a first material having a higher etch rate than the material used to form the at least a pair of fins, the first material being epitaxially grown to form the filling region, the fin region including a first set of surfaces and a second set of surfaces. A source region and a drain region, the source region being adjacent to the first set of surfaces of the fin region, and the drain region being adjacent to the second set of surfaces of the fin region; and A first insulating layer and a second insulating layer, the first insulating layer being substantially parallel to the second insulating layer, wherein the first insulating layer is in contact with the first set of surfaces, and the second insulating layer is in contact with the second set of surfaces.

39. The semiconductor structure of claim 38, wherein: The first insulating layer is formed of a plurality of dielectric sublayers, wherein the dielectric sublayers include two or more of the following: SiO, LaO, AlO, AlN, AlON, ZrO, HfO, SiN, ZnO, ZrN, TiO, TaO, ZrAlO, YO, TaCN, ZrSi, HfSi, SiOCN, SiOC, or SiCN; and The second insulating layer includes the dielectric sublayer arranged as in the first insulating layer.

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