Semiconductor memory device and method of manufacturing the same

Abstract

A method of manufacturing a semiconductor memory device includes forming bit line structures extending in a first horizontal direction on a substrate and insulating spacer structures covering opposite sidewalls of each bit line structure; forming an initial buried contact material layer and a molding layer to fill lower and upper portions, respectively, of a space between a pair of insulating spacer structures; patterning the molding layer and the initial buried contact material layer into molding patterns spaced apart from each other in the first horizontal direction and buried contacts spaced apart from each other in the first horizontal direction; forming insulating fences between the molding patterns spaced apart from each other and between the buried contacts spaced apart from each other; removing the molding patterns to expose the buried contacts; and forming landing pads on the exposed buried contacts, each landing pad connected to a corresponding one of the exposed buried contacts.

Description

TECHNICAL FIELD

[0001] The present inventive concept relates to a semiconductor memory device and a method of fabricating the same, and more particularly, to a semiconductor memory device including insulating fences between contact structures and a method of fabricating the same. BACKGROUND

[0002] According to rapid development of the electronic industry and user demands, electronic devices have become more compact and lightweight. Accordingly, a high degree of integration is required for semiconductor memory devices used in the electronic devices, and design rules for configurations of the semiconductor memory devices are reduced. In order to secure electrical reliability of contact structures connected between an active region and a capacitor, a highly scaled-down semiconductor memory device is required. SUMMARY

[0003] The present inventive concept provides a semiconductor memory device including contact structures having improved electrical reliability and a method of fabricating the same.

[0004] According to an example embodiment of the present inventive concept, a method of fabricating a semiconductor memory device includes forming a plurality of bit line structures extending in parallel to each other in a first horizontal direction on a substrate and a plurality of insulating spacer structures covering opposite sidewalls of each of the plurality of bit line structures; forming an initial buried contact material layer and a molding layer to fill a lower portion of a space between a pair of the insulating spacer structures facing each other across the space and an upper portion of the space, respectively, the pair of the insulating spacer structures facing each other across the space; patterning the molding layer and the initial buried contact material layer into a plurality of molding patterns spaced apart from each other in the first horizontal direction and a plurality of buried contacts spaced apart from each other in the first horizontal direction, respectively; forming a plurality of insulating fences between the plurality of molding patterns spaced apart from each other and between the plurality of buried contacts spaced apart from each other; removing the plurality of molding patterns to expose the plurality of buried contacts; and forming a plurality of landing pads on the exposed plurality of buried contacts, each of the plurality of landing pads connected to a corresponding one of the exposed plurality of buried contacts.

[0005] According to an example embodiment of the present application, a method of manufacturing a semiconductor memory device includes: forming a plurality of bit line structures, a plurality of first insulating spacer structures each covering a first sidewall of a corresponding one of the plurality of bit line structures, and a plurality of second insulating spacer structures each covering a plurality of second sidewalls of the corresponding one of the plurality of bit line structures opposite the first sidewall; forming an initial buried contact material layer and a molding layer on the substrate, wherein the initial buried contact material layer and the molding layer are formed in a first space between one of the plurality of first insulating spacer structures and one of the plurality of second insulating spacer structures adjacent to the one of the plurality of first insulating spacer structures in a first horizontal direction, wherein the initial buried contact material layer fills a lower portion of the first space and the molding layer fills an upper portion of the first space; and patterning the molding layer and the initial buried contact material layer into a plurality of molding patterns spaced apart from each other in a second horizontal direction different from the first horizontal direction and a plurality of buried contacts spaced apart from each other in the second horizontal direction; forming a plurality of insulating fences between the plurality of buried contacts and the plurality of molding patterns, a first insulating fence of the plurality of insulating fences having a lower portion and an upper portion, the lower portion of the first insulating fence being disposed between a pair of buried contacts spaced apart from each other in the second horizontal direction among the plurality of buried contacts and having a first width in the second horizontal direction, the upper portion of the first insulating fence being disposed between a pair of molding patterns spaced apart from each other in the second horizontal direction among the plurality of molding patterns and having a second width different from the first width in the second horizontal direction.

[0006] According to an example embodiment of the present application, a method of manufacturing a semiconductor memory device includes: preparing a substrate having a plurality of active regions defined by a device isolation layer; forming a plurality of word line trenches crossing the plurality of active regions and extending in parallel to each other in a first horizontal direction and a plurality of gate dielectric layers and a plurality of word lines filling the plurality of word line trenches; forming a plurality of bit line structures on the substrate and a plurality of insulating spacer structures covering opposite sidewalls of each bit line structure, each bit line structure including a bit line and an insulating cap line covering the bit line, the plurality of bit line structures extending in parallel to each other in a second horizontal direction crossing the first horizontal direction; forming a first initial buried contact material layer to fill a first space between a pair of insulating spacer structures among the plurality of insulating spacer structures, the pair of insulating spacer structures facing each other across the first space; removing an upper portion of the first initial buried contact material layer to form a second initial buried contact material layer and a second space between the pair of insulating spacer structures; forming a molding layer to fill the second space; forming a plurality of molding patterns and a plurality of buried contacts by patterning the molding layer and the second initial buried contact material layer, respectively; forming a plurality of landing pads on the plurality of buried contacts after removing the plurality of molding patterns; and forming a plurality of capacitors on the plurality of landing pads. The plurality of molding patterns are separated from each other, and the plurality of buried contacts are separated from each other. Each of the plurality of buried contacts is connected to a corresponding active region among the plurality of active regions. Each of the plurality of landing pads is connected to a corresponding one among the plurality of buried contacts. Each of the plurality of capacitors includes a bottom electrode connected to a corresponding landing pad among the plurality of landing pads.

[0007] According to an exemplary embodiment of the present invention, a semiconductor memory device includes: a substrate having a plurality of active regions defined by a device isolation layer; a plurality of bit line structures extending parallel to each other in a first horizontal direction and spaced apart from each other in a second horizontal direction different from the first horizontal direction, each of the plurality of bit line structures including a bit line and an insulating cap line stacked on the bit line; a plurality of first insulating spacer structures covering a first sidewall of the plurality of bit line structures; a plurality of second insulating spacer structures covering a second sidewall of the plurality of bit line structures; and a plurality of insulating fences disposed in one of the plurality of first insulating spacer structures and in one of the plurality of second insulating spacer structures in the second horizontal direction, adjacent to the plurality of first insulating spacer structures. The first insulating spacer structure is located in a first space between adjacent second insulating spacer structures and spaced apart from each other in a first horizontal direction; a plurality of buried contacts are disposed in the first space and spaced apart from each other in the first horizontal direction, each of the plurality of buried contacts filling the lower portion of the first space and connected to a corresponding one of the plurality of active regions, wherein each of the plurality of buried contacts and each of the plurality of insulating fences are arranged alternately in the first horizontal direction; and a plurality of landing pads are spaced apart from each other in the first horizontal direction, each of the plurality of landing pads connected to a corresponding one of the plurality of buried contacts, each of the plurality of landing pads filling the upper portion of the first space and extending to the top of a corresponding one of the plurality of bit line structures. Each of the plurality of insulating fences extends from between corresponding pairs of buried contacts to between corresponding pairs of landing pads. A first width of each of the plurality of insulating fences in the lower portion between corresponding pairs of buried contacts is different from a second width of each of the plurality of insulating fences in the upper portion between corresponding pairs of landing pads. The first width and the second width are measured in the first horizontal direction. Attached Figure Description

[0008] The embodiments of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 This is a schematic planar layout of the main components of a semiconductor memory device according to an exemplary embodiment of the present invention;

[0010] Figures 2 to 13 These are cross-sectional views sequentially illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present invention, wherein... Figure 13 The main components of a semiconductor memory device according to an exemplary embodiment of the present invention are shown;

[0011] Figures 14 to 16These are cross-sectional views sequentially illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present invention, wherein... Figure 16 The main components of a semiconductor memory device according to an exemplary embodiment of the present invention are shown;

[0012] Figures 17 to 19 These are cross-sectional views sequentially illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present invention, wherein... Figure 19 The main components of a semiconductor memory device according to an exemplary embodiment of the present invention are shown;

[0013] Figures 20 to 22 These are cross-sectional views sequentially illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present invention, wherein... Figure 22 The main components of a semiconductor memory device according to an exemplary embodiment of the present invention are shown;

[0014] Figure 23 This is a cross-sectional view of the main components of a semiconductor memory device according to an exemplary embodiment of the present invention; and

[0015] Figure 24 This is a cross-sectional view of the main components of a semiconductor memory device according to an exemplary embodiment of the present invention. Detailed Implementation

[0016] Figure 1 This is a schematic planar layout of a semiconductor memory device 10 according to an exemplary embodiment of the present invention.

[0017] Reference Figure 1 The semiconductor memory device 10 may include a plurality of active regions ACT. In some embodiments, the plurality of active regions ACT may have a major axis in a diagonal direction relative to a first horizontal direction (X direction) and a second horizontal direction (Y direction).

[0018] Multiple word lines WL can extend parallel to each other across the multiple active regions ACT in a first horizontal direction (X direction). Multiple bit lines BL can extend parallel to each other in a second horizontal direction (Y direction) intersecting the first horizontal direction (X direction) along the multiple word lines WL.

[0019] The multiple bit lines BL can be connected to the multiple active regions ACT via direct contact DC.

[0020] In some embodiments, a plurality of buried contacts BC may be formed between two adjacent bit lines BL. In some embodiments, the plurality of buried contacts BC may be arranged in rows in a first horizontal direction (X direction) and a second horizontal direction (Y direction), respectively.

[0021] Multiple landing pads LP can be formed on the multiple buried contacts BC. The multiple landing pads LP can at least partially overlap with the multiple buried contacts BC. In some embodiments, the multiple landing pads LP can extend to the top of either of two adjacent bit lines BL. For example, each landing pad LP can be positioned between two adjacent corresponding bit lines, overlapping one of the two corresponding bit lines.

[0022] Multiple memory nodes (SNs) can be formed on the multiple landing pads (LPs). The multiple memory nodes (SNs) can be formed on the multiple bit lines (BLs). Each of the multiple memory nodes (SNs) can be the bottom electrode of each of a plurality of capacitors. The memory nodes (SNs) can be connected to the active region (ACT) via the landing pads (LPs) and buried contacts (BCs).

[0023] Figures 2 to 24 Each of them is shown along Figure 1 The cross-sectional views corresponding to the cross-sectional views taken by lines A-A', B-B', and C-C' in the diagram.

[0024] Figures 2 to 13 This is a cross-sectional view showing a method for manufacturing a semiconductor memory device 10 according to an embodiment of the present invention. Figure 13 The main components of a semiconductor memory device 1 according to an exemplary embodiment of the present invention are shown. The semiconductor memory device 1 may correspond to... Figure 1 10. Semiconductor memory device.

[0025] Reference Figure 2 Device isolation trenches 116T can be formed in the substrate 110, and device isolation layers 116 can be formed to fill the device isolation trenches 116T. Multiple active regions 118 can be defined in the substrate 110 through the device isolation layers 116. The active regions 118 can have a relatively long island shape with a short axis and a long axis, like... Figure 1 The active region ACT shown is the same.

[0026] Substrate 110 may include silicon (Si), such as crystalline Si, polycrystalline Si, or amorphous Si. Alternatively, substrate 110 may include at least one compound semiconductor of a semiconductor element, such as silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). Alternatively, substrate 110 may have a silicon-on-insulator (SOI) structure. For example, substrate 110 may include a buried oxide (BOX) layer. Substrate 110 may include conductive regions, such as impurity-doped wells or impurity-doped structures.

[0027] The component isolation layer 116 may comprise a material containing at least one of, for example, a silicon oxide layer, a silicon nitride layer, and a silicon oxide nitride layer. The component isolation layer 116 may comprise a single layer containing one insulating layer, a double layer containing two insulating layers, or a multilayer comprising a combination of at least three insulating layers. For example, the component isolation layer 116 may comprise a double or multilayer of oxide and nitride layers. However, according to the technical concept of the present invention, the configuration of the component isolation layer 116 is not limited thereto.

[0028] A plurality of word line trenches 120T may be formed in the substrate 110. The plurality of word line trenches 120T may extend parallel to each other in a first horizontal direction (X direction) and may be linear, wherein each of the plurality of word line trenches 120T is arranged to intersect the active region 118 and the plurality of word line trenches 120T have substantially equal spacing in a second horizontal direction (Y direction). As shown in the cross-sectional view along line B-B', a step may be formed on the bottom surface of each of the plurality of word line trenches 120T. In some embodiments, in forming the plurality of word line trenches 120T, the element isolation layer 116 and the substrate 110 may be etched by separate etching processes, such that the etching depth of the element isolation layer 116 differs from the etching depth of the substrate 110. In some embodiments, the plurality of word line trenches 120T can be formed by etching the element isolation layer 116 together with the substrate 110. However, due to the difference in etching rates between the element isolation layer 116 and the substrate 110, the etching depth of the element isolation layer 116 may be different from the etching depth of the substrate 110, and steps may be formed on the bottom surface of each of the plurality of word line trenches 120T.

[0029] After cleaning the resulting product in which the plurality of word line trenches 120T have been formed, a plurality of gate dielectric layers 122, a plurality of word lines 120, and a plurality of buried insulating layers 124 can be sequentially formed in the plurality of word line trenches 120T. The plurality of word lines 120 can constitute Figure 1 The multiple word lines WL shown.

[0030] The plurality of word lines 120 can fill the lower portion of the plurality of word line grooves 120T, and the plurality of buried insulating layers 124 can cover the plurality of word lines 120 and fill the upper portion of the plurality of word line grooves 120T. Therefore, the plurality of word lines 120 can extend parallel to each other in a first horizontal direction (X direction) and can have a linear shape in which each of the plurality of word lines 120 is arranged to intersect the active region 118 and the plurality of word lines 120 have substantially equal spacing between them in a second horizontal direction (Y direction). Similarly, the plurality of buried insulating layers 124 can extend parallel to each other in the first horizontal direction (X direction) and can have a linear shape in which each of the plurality of buried insulating layers 124 is arranged to intersect the active region 118 and the plurality of buried insulating layers 124 have substantially equal spacing between them in the second horizontal direction (Y direction).

[0031] In some embodiments, the plurality of word lines 120 may include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, or combinations thereof. In some embodiments, each of the plurality of word lines 120 may include a core layer and a barrier layer between the core layer and the gate dielectric layer 122. For example, the core layer may include a metallic material such as W or a conductive metal nitride such as WN, TiSiN, and WSiN, and the barrier layer may include a metallic material such as Ti and Ta or a conductive metal nitride such as TiN and TaN.

[0032] The gate dielectric layer 122 may include at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxide nitride layer, an oxide / nitride / oxide (ONO) layer, and a high dielectric layer having a higher dielectric constant than the silicon oxide layer. For example, the gate dielectric layer 122 may have a dielectric constant in the range of about 10 to about 25. In some embodiments, the gate dielectric layer 122 may include at least one of hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO). For example, the gate dielectric layer 122 may include HfO2, Al2O3, HfAlO3, Ta2O3, or TiO2.

[0033] The top surfaces of the plurality of buried insulating layers 124 may be at substantially the same level as the top surface of the substrate 110. The buried insulating layers 124 may include a material layer selected from silicon oxide layers, silicon nitride layers, silicon oxide nitride layers, and combinations thereof.

[0034] The top surface of each of the plurality of word lines 120 may be at a lower level than the top surface of the substrate 110. The bottom surface of the plurality of word lines 120 may have an uneven shape, and the plurality of active regions 118 may include saddle-shaped fin field-effect transistors (saddle-shaped FinFETs).

[0035] In this specification, "level" can refer to the height in the vertical direction (Z direction) relative to the main surface of substrate 110. In other words, a position at the same level or a constant level can mean that the position is at the same height or a constant height in the vertical direction (Z direction) relative to the main surface (e.g., the upper surface) of substrate 110, while a position at a lower / higher level can mean that the position is at a smaller / larger height in the vertical direction (Z direction) relative to the main surface (e.g., the upper surface) of substrate 110.

[0036] In some embodiments, after the plurality of word lines 120 are formed, impurity ions can be implanted into portions on both sides of each of the plurality of word lines 120 in the active regions 118 of the substrate 110, thereby forming source and drain regions within the plurality of active regions 118. In some other embodiments, the impurity ion implantation process for forming the source and drain regions can be performed prior to the formation of the plurality of word lines 120.

[0037] Reference Figure 3 This can form insulating layer patterns (112 and 114) covering the element isolation layer 116, the plurality of active regions 118, and the plurality of buried insulating layers 124. For example, the insulating layer patterns (112 and 114) may include silicon oxide layers, silicon nitride layers, silicon oxide nitride layers, or combinations thereof.

[0038] In some embodiments, the insulating layer patterns (112 and 114) can be formed by stacking multiple insulating layers including the first insulating layer pattern 112 and the second insulating layer pattern 114. For example, the second insulating layer pattern 114 may have a dielectric constant that is greater than that of the first insulating layer pattern 112.

[0039] In some embodiments, the first insulating layer pattern 112 may include a silicon oxide layer, and the second insulating layer pattern 114 may include a silicon nitride layer.

[0040] In some embodiments, the first insulating layer pattern 112 may include a non-metallic dielectric layer, and the second insulating layer pattern 114 may include a metallic dielectric layer. For example, the first insulating layer pattern 112 may include a silicon oxide layer, a silicon nitride layer, a silicon nitride layer, or a combination thereof. For example, the second insulating layer pattern 114 may include at least one of hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium nitride (HfON), hafnium silicon nitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium nitride (ZrON), zirconium silicon nitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO).

[0041] Next, a direct contact hole 134H can be formed that penetrates the first insulating layer pattern 112 and the second insulating layer pattern 114. The direct contact hole 134H can be formed to expose the source region in the active region 118. In some embodiments, the direct contact hole 134H can extend into the active region 118, that is, into the source region.

[0042] Reference Figure 4 A direct contact conductive layer can be formed, filling the direct contact hole 134H and covering the first insulating layer pattern 112 and the second insulating layer pattern 114. The direct contact conductive layer may include silicon (Si), germanium (Ge), tungsten (W), tungsten nitride (WN), cobalt (Co), nickel (Ni), aluminum (Al), molybdenum (Mo), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), copper (Cu), or combinations thereof. In some embodiments, the direct contact conductive layer may include an epitaxial silicon layer. In some embodiments, the direct contact conductive layer may include doped polycrystalline silicon.

[0043] Next, a metal-based conductive layer covering the first insulating layer pattern 112, the second insulating layer pattern 114, and the conductive layer that directly contacts the bit line structure 140, as well as an insulating capping layer, can be formed sequentially.

[0044] In some embodiments, the metal-based conductive layer may have a stacked structure including a first metal-based conductive layer and a second metal-based conductive layer. The metal-based conductive layer may have a dual-layer conductive layer stacked structure; however, this is just an example, and the inventive concept is not limited thereto. For example, the metal-based conductive layer may be a single layer, or it may have a stacked structure of three or more layers.

[0045] In some embodiments, the first metal-based conductive layer may include titanium nitride (TiN) or Ti-Si-N (TSN), and the second metal-based conductive layer may include W or tungsten silicide (WSi). x In some embodiments, the first metal-based conductive layer may serve as a diffusion barrier layer. In some embodiments, the insulating capping layer may include a silicon nitride layer.

[0046] By etching a first metal-based conductive layer, a second metal-based conductive layer, and an insulating capping layer, multiple bit lines 147, including linear first metal-based conductive patterns 145 and second metal-based conductive patterns 146, and multiple insulating capping lines 148 can be formed. A bit line 147 and an insulating capping line 148 covering the bit line 147 can constitute a bit line structure 140.

[0047] In some embodiments, the bit line structure 140 may further include a conductive semiconductor pattern 132 between the second insulating layer pattern 114 and the first metal base conductive pattern 145. The conductive semiconductor pattern 132 may, for example, comprise doped polysilicon. In some embodiments, the conductive semiconductor pattern 132 may be omitted or not formed.

[0048] Each of the plurality of bit line structures 140, including the plurality of bit lines 147 and the plurality of insulating cover lines 148, can extend parallel to each other and parallel to the main surface of the substrate 110 in a second horizontal direction (Y direction). The plurality of bit lines 147 can constitute Figure 1 The multiple bit lines BL shown.

[0049] In the etching process that forms the plurality of bit lines 147, a plurality of direct contact conductive patterns 134 can be formed by collectively removing portions of the direct contact conductive layer that do not perpendicularly overlap with the bit lines 147. In this case, the first insulating layer pattern 112 and the second insulating layer pattern 114 can be used as etch stop layers in the etching process that forms the plurality of bit lines 147 and the plurality of direct contact conductive patterns 134. The plurality of direct contact conductive patterns 134 can constitute Figure 1 The plurality of direct contact DCs are shown. The plurality of bit lines 147 can be electrically connected to the plurality of active regions 118 via the plurality of direct contact conductive patterns 134.

[0050] In some embodiments, the conductive semiconductor pattern 132 and the direct contact conductive pattern 134 can be formed together by the direct contact conductive layer during an etching process. For example, in the portion of the direct contact conductive layer that perpendicularly overlaps with the bit line 147, the conductive semiconductor pattern 132 may be a portion that does not perpendicularly overlap with the direct contact hole 134H and is on the first insulating layer pattern 112 and the second insulating layer pattern 114, and the direct contact conductive pattern 134 may be a portion that perpendicularly overlaps with the direct contact hole 134H and contacts the active region 118. Unless the context otherwise indicates, the term "contact" as used herein refers to directional connection (i.e., touching).

[0051] Two sidewalls of each of the plurality of bit line structures 140 may be covered by insulating spacer structures 150. Each of the plurality of insulating spacer structures 150 may include a first insulating spacer 152, a second insulating spacer 154, and a third insulating spacer 156. The second insulating spacer 154 may include a material having a dielectric constant lower than that of the first insulating spacer 152 and the third insulating spacer 156. In some embodiments, the first insulating spacer 152 and the third insulating spacer 156 may include nitride layers, and the second insulating spacer 154 may include an oxide layer. In some embodiments, the first insulating spacer 152 and the third insulating spacer 156 may include nitride layers, and the second insulating spacer 154 may include a material having etch selectivity relative to the materials of the first insulating spacer 152 and the third insulating spacer 156. For example, when the first insulating spacer 152 and the third insulating spacer 156 include nitride layers, the second insulating spacer 154 may include an oxide layer, but may be removed in a subsequent process and replaced with an air spacer. The term "air," as discussed here, can refer to the atmosphere or other gases that may be present during the manufacturing process.

[0052] Multiple buried contact holes 170H may be formed between the multiple bit lines 147. The multiple buried contact holes 170H may have an internal space defined by an insulating spacer structure 150 covering the sidewalls of each of the two adjacent bit lines 147 and an active region 118.

[0053] The plurality of buried contact holes 170H can be formed by using the plurality of insulating cap lines 148 and insulating spacer structures 150 covering the two sidewalls of each of the plurality of bit line structures 140 as an etching mask to remove portions of the first insulating layer pattern 112 and portions of the second insulating layer pattern 114. After performing a first anisotropic etching process using the plurality of insulating cap lines 148 and insulating spacer structures 150 covering the two sidewalls of each of the plurality of bit line structures 140 as an etching mask to remove portions of the first insulating layer pattern 112 and portions of the second insulating layer pattern 114, and performing an isotropic etching process to further remove portions of the active region 118, the plurality of buried contact holes 170H can be formed to have an enlarged space defined by the active region 118.

[0054] Reference Figure 5 An initial buried contact material layer 170p can be formed to fill the interior of the plurality of buried contact holes 170H. For example, the initial buried contact material layer 170p may include polysilicon. After forming a conductive material layer that fills the plurality of buried contact holes 170H and covers the plurality of bit line structures 140, the initial buried contact material layer 170p can be formed by performing a planarization process that removes a portion of the conductive material layer to expose the plurality of insulating cover lines 148. In some embodiments, the planarization process of removing a portion of the conductive material layer may be omitted, in which case the uppermost level of the initial buried contact material layer 170p may be higher than the uppermost level of the plurality of insulating cover lines 148.

[0055] Reference Figure 6 By removing the upper portion of the initial buried contact material layer 170p so that the level of the top surface of the initial buried contact material layer 170p is lower than the level of the uppermost end of the plurality of insulating cover lines 148, the initial buried contact material layer 170p can fill the lower portion of the buried contact hole 170H. In some embodiments, the upper portion of the initial buried contact material layer 170p can be partially removed so that the level of the top surface of the initial buried contact material layer 170p is not lower than the level of the top surface of the bit line 147. However, the embodiments are not limited to this.

[0056] In some implementations, refer to Figure 5 and Figure 6 The described process can be performed in situ, not sequentially. For example, after forming a conductive material layer that fills the plurality of buried contact holes 170H and covers the plurality of bit line structures 140 and removing the upper part of the conductive material layer, an initial buried contact material layer 170p can be formed that fills the lower part of the space between the plurality of insulating spacer structures 150 that cover the sidewalls of each of the plurality of bit line structures 140.

[0057] Reference Figure 7 It can form a fill due to the reference. Figure 6 The molded layer 175 describes the space created by the removal of a portion of the initial buried contact material layer 170p. The lower portion of each of the plurality of buried contact holes 170H can be filled by the initial buried contact material layer 170p, and the upper portion of each of the plurality of buried contact holes 170H can be filled by the molded layer 175. In other words, the lower portion of the space between the plurality of insulating spacer structures 150 covering the two sidewalls of each of the plurality of bit line structures 140 can be filled by the initial buried contact material layer 170p, and the upper portion of this space can be filled by the molded layer 175.

[0058] In some embodiments, the top surface of the molded layer 175 may be substantially the same level as the uppermost edge of the plurality of insulating cover lines 148. For example, the top surface of the molded layer 175 and the top surfaces of the plurality of insulating cover lines 148 may be coplanar.

[0059] The molding layer 175 may include a material that is etch-selective relative to the insulating cover line 148, the insulating spacer structure 150, and the initial buried contact material layer 170p. For example, when the insulating cover line 148 and the insulating spacer structure 150 comprise nitride layers and the initial buried contact material layer 170p comprises polysilicon, the molding layer 175 may comprise an oxide layer, but the implementation is not limited thereto.

[0060] Reference Figure 8 Multiple mask patterns MK can be formed on the molding layer 175. The multiple mask patterns MK can extend parallel to each other in a first horizontal direction (X direction). The multiple mask patterns MK can be positioned to partially overlap with the multiple word lines 120 in the vertical direction (Z direction). In other words, the space between a pair of adjacent mask patterns MK can overlap with one of the multiple word lines 120 in the vertical direction (Z direction).

[0061] Reference Figure 8 and Figure 9 By using the plurality of mask patterns MK as etching masks to remove a portion of the molding layer 175 and a portion of the initial buried contact material layer 170p, a plurality of enclosure holes 180H can be formed, such that the buried insulating layer 124 is exposed on the bottom surface of each of the plurality of enclosure holes 180H. In some embodiments, the plurality of enclosure holes 180H may be arranged in rows in a first horizontal direction (X direction) and a second horizontal direction (Y direction), respectively.

[0062] The initial buried contact material layer 170p can be divided into a plurality of buried contacts 170 through the plurality of enclosure holes 180H. In some embodiments, the plurality of buried contacts 170 can be arranged in rows in a first horizontal direction (X direction) and a second horizontal direction (Y direction), respectively. Each of the plurality of buried contacts 170 can be arranged in a vertical direction perpendicular to the substrate 110 ( Figure 9 Extending from the active region 118 in the Z direction (within the region). The plurality of buried contacts 170 can constitute Figure 1 The multiple buried contacts BC shown.

[0063] Similarly, when forming the plurality of buried contacts 170, the molding layer 175 can be divided into a plurality of molding patterns 175P through the plurality of enclosure holes 180H. In some embodiments, the plurality of molding patterns 175P can be arranged in rows in a first horizontal direction (X direction) and a second horizontal direction (Y direction), respectively. Each of the plurality of molding patterns 175P can be arranged in a vertical direction perpendicular to the substrate 110 ( Figure 9 It extends from the buried contact 170 in the Z direction.

[0064] In the process of forming the plurality of fence holes 180H, the plurality of insulating cover lines 148 and the plurality of insulating spacer structures 150 together with the plurality of mask patterns MK can be used as etching masks.

[0065] Although not shown separately, in some embodiments, the upper portions of the plurality of insulating cover lines 148 and / or the upper portions of the plurality of insulating spacer structures 150 may be removed during the formation of the plurality of enclosure holes 180H. In some other embodiments, when the upper portions of the plurality of insulating cover lines 148 and / or the upper portions of the plurality of insulating spacer structures 150 are removed during the formation of the plurality of enclosure holes 180H, the uppermost level of the second insulating spacer 154 may be lower than the uppermost levels of the first insulating spacer 152 and the third insulating spacer 156.

[0066] Furthermore, although not shown or described separately, the upper portions of the plurality of insulating cover lines 148 and / or the upper portions of the plurality of insulating spacer structures 150 may be further removed in subsequent processes, but the level of the tops of the plurality of insulating cover lines 148 and the level of the tops of the plurality of insulating spacer structures 150 may be maintained above the level of the tops of the plurality of bit lines 147.

[0067] In some embodiments, the plurality of enclosure holes 180H can be formed by sequentially performing a first etching process and a second etching process, in which the initial buried contact material layer 170p is exposed by removing part of the molding layer 175 using the plurality of mask patterns MK as an etching mask, and in the second etching process, the exposed portion of the initial buried contact material layer 170p is removed.

[0068] In some embodiments, the plurality of fence holes 180H can be formed by an etching process in which a portion of the molding layer 175 and a portion of the initial buried contact material layer 170p are removed in situ using the plurality of mask patterns MK as etching masks.

[0069] Reference Figure 10 Multiple insulating fences 180 can be formed to fill the plurality of fence holes 180H. The plurality of insulating fences 180 may include, for example, a nitride layer. After forming a fence material layer that fills the plurality of fence holes 180H and covers the top surface of the molded pattern 175P, the plurality of insulating fences 180 can be formed by removing the portion of the fence material layer covering the top surface of the molded pattern 175P.

[0070] The plurality of buried contacts 170 may be located within the space defined by the plurality of insulating spacer structures 150 covering the sidewalls of the plurality of bit line structures 140 and by the plurality of insulating fences 180. In other words, the plurality of buried contacts 170 and the plurality of insulating fences 180 may be alternately arranged in a second horizontal direction (Y direction) within the space between a pair of insulating spacer structures 150 facing each other among the plurality of insulating spacer structures 150 covering the sidewalls of the plurality of bit line structures 140. For example, each of the plurality of buried contacts 170 may be located within the space defined by two adjacent insulating spacer structures 150 (e.g., Figure 10 The cross section A-A') and the two adjacent insulating fences 180 (e.g. Figure 10 Within the space defined by the cross section C-C', the two adjacent insulating spacer structures 150 face each other across this space. For example, the plurality of buried contacts 170 can be spaced apart from each other in a first horizontal direction (X direction) by the plurality of insulating spacer structures 150, and can be spaced apart from each other in a second horizontal direction (Y direction) by the plurality of insulating fences 180.

[0071] Refer to together Figure 10 and Figure 11 Multiple pad holes 190H can be formed by removing the molding pattern 175P. The multiple buried contacts 170 can be exposed on the bottom surface of the multiple pad holes 190H.

[0072] ReferenceFigure 12 A plurality of landing pads 190 can be formed, filling the plurality of landing pad holes 190H and extending over the plurality of bit lines 147. The plurality of landing pads 190 can be on the plurality of buried contacts 170 and can extend over the plurality of bit lines 147. The plurality of landing pads 190 can be on the plurality of buried contacts 170, and each of the plurality of buried contacts 170 can be electrically connected to a corresponding one of the plurality of landing pads 190. The plurality of landing pads 190 can be connected to the active region 118 via the plurality of buried contacts 170. The plurality of landing pads 190 can constitute... Figure 1 The plurality of landing pads LP shown.

[0073] A buried contact 170 and a landing pad 190 on the buried contact 170 together can be referred to as a contact structure. The buried contact 170 constituting the contact structure can be between two adjacent bit line structures 140, and the landing pad 190 can be disposed on the buried contact 170 and extend from the buried contact 170 to one bit line structure 140 in the space between the two adjacent bit line structures 140. In other words, the landing pad 190 can be electrically connected to the buried contact 170 and can be formed to extend from the buried contact 170 to the top of one bit line structure 140 in the space between the two adjacent bit line structures 140, such that the landing pad 190 overlaps perpendicularly with one bit line structure 140.

[0074] In one example embodiment, a pad-laying material layer may be formed to fill the plurality of pad-laying holes 190H, covering the plurality of insulating cover lines 148 and the plurality of insulating fences 180. A portion of the upper surface of the pad-laying material layer may be recessed to form a recessed portion 190R, thereby forming the plurality of pads 190. The recessed portion 190R may divide the pad-laying material layer into the plurality of pads 190, each pad 190 being connected to one of the plurality of buried contacts 170. The plurality of pads 190 may be spaced apart from each other, with the recessed portion 190R therebetween. In the recessed portion 190R, the top ends of the insulating spacer structure 150, the top ends of the insulating cover lines 148, and the top ends of the insulating fences 180 may be exposed. In some embodiments, during the formation process of the recessed portion 190R, the upper portions of the plurality of insulating spacer structures 150, the upper portions of the plurality of insulating cover lines 148, and the upper portions of the plurality of insulating fences 180 may be removed.

[0075] In some embodiments, a metal silicide layer may be formed on the plurality of buried contacts 170 prior to the formation of the plurality of landing pads 190. The metal silicide layer may be between the plurality of buried contacts 170 and the plurality of landing pads 190. The metal silicide layer may include, but is not limited to, cobalt silicide (CoSi), nickel silicide (NiSi), or manganese silicide (MnSi).

[0076] In some embodiments, the plurality of pads 190 may include a conductive barrier layer and a conductive pad material layer on the conductive barrier layer. For example, the conductive barrier layer may include a metal, a conductive metal nitride, or a combination thereof. In some embodiments, the conductive barrier layer may have a Ti / TiN stacked structure. For example, the conductive pad material layer may include a metal. In some embodiments, the conductive pad material layer may include W.

[0077] Reference Figure 13 ,exist Figure 12 Following the steps shown, a plurality of capacitor structures 200 can be formed by sequentially forming a plurality of bottom electrodes 210, a capacitor dielectric layer 220, and a top electrode 230 on the plurality of landing pads 190. Each of the plurality of bottom electrodes 210 can be electrically connected to a corresponding one of the plurality of landing pads 190. The capacitor dielectric layer 220 can conformally cover the plurality of bottom electrodes 210. The top electrode 230 can cover the capacitor dielectric layer 220. The top electrode 230 can face the bottom electrode 210, with the capacitor dielectric layer 220 therebetween. Each of the capacitor dielectric layer 220 and the top electrode 230 can be integrally formed to cover the plurality of bottom electrodes 210 together in a specific area (e.g., in a unit block). The plurality of bottom electrodes 210 can be configured as Figure 1 The plurality of storage nodes SN shown.

[0078] Each of the plurality of bottom electrodes 210 may have a cylindrical shape with a closed end, but is not limited thereto. In some embodiments, each of the plurality of bottom electrodes 210 may have a cylindrical shape, that is, its interior is filled with a cylindrical shape having a circular horizontal cross-section. In some embodiments, the plurality of bottom electrodes 210 may have a honeycomb zigzag shape relative to a first horizontal direction (X direction) or a second horizontal direction (Y direction). In some other embodiments, the plurality of bottom electrodes 210 may be arranged in a linear matrix in the first horizontal direction (X direction) and the second horizontal direction (Y direction), respectively. The plurality of bottom electrodes 210 may include, for example, impurity-doped silicon, metals such as tungsten and copper, or conductive metal compounds such as titanium nitride. Although not shown separately, the semiconductor memory device 1 may also include at least one support pattern in contact with the sidewalls of the plurality of bottom electrodes 210.

[0079] The capacitor dielectric layer 220 may include, for example, TaO, TaAlO, TaON, AlO, AlSiO, HfO, HfSiO, ZrO, ZrSiO, TiO, TiAlO, (Ba,Sr)TiO (BST), SrTiO (STO), BaTiO (BTO), Pb(Zr,Ti)O (PZT), (Pb,La)(Zr,Ti)O, Ba(Zr,Ti)O, Sr(Zr,Ti)O, or combinations thereof.

[0080] The top electrode 230 may include, for example, doped silicon, Ru, RuO, Pt, PtO, Ir, IrO, SrRuO (SRO), (Ba,Sr)RuO (BSRO), CaRuO (CRO), BaRuO, La(Sr,Co)O, Ti, TiN, W, WN, Ta, TaN, TiAlN, TiSiN, TaAlN, TaSiN, or combinations thereof.

[0081] Before forming the plurality of capacitor structures 200, an insulating structure 195 may be formed to fill the recessed portion 190R. In some embodiments, the insulating structure 195 may include an interlayer insulating layer and an etch stop layer. For example, the interlayer insulating layer may include an oxide layer, and the etch stop layer may include a nitride layer. Figure 13 The top surface of the insulating structure 195 and the bottom surface of the bottom electrode 210 are shown to be at the same level, but the implementation is not limited to this. For example, the level of the top surface of the insulating structure 195 may be higher than the level of the bottom surface of the bottom electrode 210, and the bottom electrode 210 may extend toward the substrate 110 into the insulating structure 195.

[0082] Semiconductor memory device 1 may include a substrate 110 having the plurality of active regions 118. The plurality of gate dielectric layers 122, the plurality of word lines 120, and the plurality of buried insulating layers 124 may be sequentially formed within the plurality of word line trenches 120T formed in the substrate 110. A device isolation layer 116 may define the plurality of active regions 118. The plurality of insulating layer patterns (112 and 114) may be formed to cover the plurality of buried insulating layers 124. The plurality of landing pads 190 may be formed to fill the upper portion of a first space defined by the plurality of insulating spacer structures 150 covering the sidewalls of the plurality of bit line structures 140 and the upper portion of a second space between the plurality of insulating fences 180. The plurality of buried contacts 170 may fill the lower portion of the first space and the lower portion of the second space. Each of the plurality of buried contacts 170 may be connected to a corresponding one of the plurality of active regions 118. Each of the plurality of landing pads 190 may extend to the top of a corresponding one of the plurality of bit line structures 140. The plurality of capacitor structures 200 may be formed to include the plurality of bottom electrodes 210, capacitor dielectric layers 220, and top electrodes 230. Each bottom electrode 210 may be connected to a corresponding one of the plurality of landing pads 190.

[0083] The plurality of insulating barriers 180 may be disposed in the space between a pair of insulating spacer structures 150 facing each other, which cover the sidewalls of the plurality of bit line structures 140, and may be spaced apart from each other in a second horizontal direction (Y direction). Each of the plurality of insulating barriers 180 may extend in the vertical direction (Z direction) from the space between the plurality of buried contacts 170 to the space between the plurality of landing pads 190.

[0084] When the initial burial contact material layer is formed ( Figure 5 When the plurality of insulating fences 180 are first formed by patterning using an etching process prior to 170p, it may be difficult to form the plurality of buried contact holes 170H. Therefore, the distribution of electrical connection characteristics between the plurality of buried contacts 170 and the plurality of active regions 118 will increase in the semiconductor memory device. In addition, since large losses may occur in the upper part of the plurality of insulating cover lines 148 and the upper part of the plurality of insulating spacer structures 150, the volume of the second insulating spacer 154, which includes a material with a relatively low dielectric constant, will decrease, or the air spacer formed by removing the second insulating spacer 154 will decrease. Therefore, the parasitic capacitance between the plurality of bit lines 147 will increase.

[0085] However, since the plurality of insulating fences 180 are formed after the plurality of buried contacts 170 are formed in the semiconductor memory device 1 according to various embodiments, the reliability of the electrical connection between the plurality of buried contacts 170 and the plurality of active regions 118 can be improved, and thus the wiring of electrical characteristics in the semiconductor memory device 10 can be reduced. Furthermore, since the plurality of insulating fences 180 are formed by an inlay method of filling the plurality of fence holes 180H rather than by an etching process, losses in the upper portions of the plurality of insulating cover lines 148 and the upper portions of the plurality of insulating spacer structures 150 can be reduced, thus preventing the increase of parasitic capacitance between the plurality of bit lines 147.

[0086] When the plurality of insulating fences 180 are first formed and then the upper part of the initial buried contact material layer 170p is removed to form the plurality of buried contacts 170, defects in the etched profile of the spaces for the plurality of insulating fences 180 (i.e., the plurality of fence holes 180H) may occur during the process of forming the spaces for the plurality of insulating fences 180 by performing an etching process on the initial buried contact material layer 170p.

[0087] However, in the semiconductor memory device 10 conceived according to the present invention, after removing the upper portion of the initial buried contact material layer 170p and forming a molding layer 175 to fill the space caused by the removal of the upper portion of the initial buried contact material layer 170p, the space for the plurality of insulating fences 180 can be formed by performing an etching process on the molding layer 175 and the initial buried contact material layer 170p. For example, when the molding layer 175 includes an oxide layer and the initial buried contact material layer 170p includes polysilicon, since the etching process is first performed on the molding layer 175 including the oxide layer, the etching profile of the space for the insulating fences 180 (i.e., the plurality of fence holes 180H) can provide a better profile for subsequent processes that fill the space with conductive material, thus improving the reliability of the electrical connection between the plurality of capacitor structures 200 and the plurality of active regions 118 via the plurality of buried contacts 170 and the plurality of landing pads 190 between the plurality of insulating fences 180.

[0088] Figures 14 to 16 This is a cross-sectional view showing a method for manufacturing a semiconductor memory device 2 according to an embodiment of the present invention. Figure 14 It is shown in the reference Figure 6 A cross-sectional view of the operation following the operation, with references omitted. Figure 14 and Figure 15 The given reference Figures 2 to 12 The given description is repetitive, and the same reference numerals may denote the same parts. Figure 16The main components of a semiconductor memory device 2 according to an exemplary embodiment of the present invention are shown. The semiconductor memory device 2 may correspond to... Figure 1 10. Semiconductor memory device.

[0089] Refer to together Figure 6 and Figure 14 The upper portion of the plurality of insulating spacer structures 150 above the top surface of the initial buried contact material layer 170p can be removed, such that the upper portion of the plurality of insulating cover lines 148 protrudes from the top surface of the plurality of initial buried contact material layers 170p.

[0090] Reference Figure 15 Multiple extended capping layers 158 can be formed, covering the surfaces of the multiple insulating capping lines 148 that protrude beyond the top surfaces of the multiple initial buried contact material layers 170p. A bit line 147, an insulating capping line 148 covering the bit line 147, and an extended capping layer 158 covering the surface of the insulating capping line 148 can constitute a bit line structure 140a. In one example embodiment, the multiple extended capping layers 158 may comprise the same material as the multiple insulating capping lines 148 (such as nitrides), or may be formed of the same material as the multiple insulating capping lines 148 (such as nitrides).

[0091] The extended capping layer 158 may extend toward the top surface of the initial buried contact material layer 170p. For example, the extended capping layer 158 may cover the top surface of the second insulating spacer 154 on top of the plurality of insulating spacer structures 150. In some embodiments, the second insulating spacer 154 is removed, and then the extended capping layer 158 is formed to cover the top surfaces of the first insulating spacer 152 and the third insulating spacer 156, thereby forming an air space defined by the first insulating spacer 152, the third insulating spacer 156, and the extended capping layer 158. The second insulating spacer 154 may be replaced with an air spacer.

[0092] In the extended capping layer 158, the width of the portion covering the top surface of the insulating cover wire 148 can be greater than the width of the portion covering the side surface of the insulating cover wire 148 that protrudes toward the top surface of the initial buried contact material layer 170p. Through the extended capping layer 158, the top of the bit wire structure 140a can have a relatively large area.

[0093] Reference Figure 16 ,exist Figure 15 After the steps shown, you can execute the reference. Figures 7 to 13 The process described is used to form semiconductor memory devices 2.

[0094] The semiconductor memory device 2 may include a substrate 110 having the plurality of active regions 118. The plurality of gate dielectric layers 122, the plurality of word lines 120, and the plurality of buried insulating layers 124 may be sequentially formed within the plurality of word line trenches 120T formed in the substrate 110. A device isolation layer 116 may be formed to define the plurality of active regions 118. The plurality of insulating layer patterns (112 and 114) may be formed to cover the plurality of buried insulating layers 124. The plurality of bit line structures 140a may be formed on the plurality of insulating layer patterns (112 and 114). The plurality of landing pads 190 may be formed to fill the upper portion of a first space defined by the plurality of insulating spacer structures 150 covering the sidewalls of the plurality of bit line structures 140a and the upper portion of a second space between the plurality of insulating fences 180. The plurality of buried contacts 170 may fill the lower portion of the first space and the lower portion of the second space. Each of the plurality of buried contacts 170 can be connected to a corresponding one of the plurality of active regions 118. Each of the plurality of landing pads 190 can extend to the top of a corresponding one of the plurality of bit line structures 140. The plurality of capacitor structures 200 may include a plurality of bottom electrodes 210, a capacitor dielectric layer 220, and a top electrode 230. Each of the plurality of bottom electrodes 210 can be connected to a corresponding one of the plurality of landing pads 190. The plurality of landing pads 190 can cover at least a portion of the top surface of the plurality of extended capping layers 158 of the bit line structure 140a.

[0095] Figures 17 to 19 This is a cross-sectional view showing a method for manufacturing a semiconductor memory device 3 according to an embodiment of the present invention. Figure 17 It is shown in the reference Figure 8 A cross-sectional view of the operation following the operation, with references omitted. Figure 17 and Figure 18 The given reference Figures 2 to 12 The given descriptions are repetitive, and the same reference numerals may denote the same parts. Figure 19 The main components of a semiconductor memory device 3 according to an exemplary embodiment of the present invention are shown. The semiconductor memory device 3 may correspond to... Figure 1 10. Semiconductor memory device.

[0096] Refer to together Figure 8 and Figure 17By using the plurality of mask patterns MK as etching masks to remove a portion of the molding layer 175 and a portion of the initial buried contact material layer 170p, a plurality of fence holes 180Ha can be formed, such that the buried insulating layer 124 is exposed on the bottom surface of each of the plurality of fence holes 180Ha. In some embodiments, the plurality of fence holes 180Ha may be arranged in rows in a first horizontal direction (X direction) and a second horizontal direction (Y direction), respectively.

[0097] The initial buried contact material layer 170p can be divided into multiple buried contacts 170 through the multiple fence holes 180Ha.

[0098] During the formation of the plurality of enclosure holes 180Ha, due to the difference in etching characteristics between the molding layer 175 and the initial buried contact material layer 170p, the second width W2 (which is the upper width of each of the plurality of enclosure holes 180Ha in the second horizontal direction (Y direction) between a pair of molding patterns 175P) can be greater than the first width W1 (which is the lower width of each of the plurality of enclosure holes 180Ha in the second horizontal direction (Y direction) between a pair of buried contacts 170). In other words, among the plurality of enclosure holes 180Ha, the first width W1 (which is the width of the lower portion in the second horizontal direction (Y direction)) can be smaller than the second width W2 (which is the width of the upper portion in the second horizontal direction (Y direction)). In some embodiments, the first width W1 can be about 1 nm to about 5 nm smaller than the second width W2.

[0099] The width of each of the plurality of enclosure holes 180Ha in the first horizontal direction (X direction) can be defined by the width between a pair of insulating spacer structures 150 facing each other, and can increase as it moves away from the substrate 110 in the vertical direction (Z direction) perpendicular to the substrate 110.

[0100] In some implementations, during the formation Figure 9 After the plurality of fence holes 180H shown, a portion of the molded pattern 175P can be further removed to form Figure 17 The plurality of fence holes 180Ha shown.

[0101] Reference Figure 18 Multiple insulating fences 180a can be formed to fill the plurality of fence holes 180Ha. The plurality of insulating fences 180a may include, for example, a nitride layer. After forming a fence material layer that fills the plurality of fence holes 180Ha and covers the top surface of the molded pattern 175P, the plurality of insulating fences 180a can be formed by removing the portion of the fence material layer covering the top surface of the molded pattern 175P.

[0102] The plurality of buried contacts 170 may be located within a space defined by the plurality of insulating spacer structures 150 covering the sidewalls of the plurality of bit line structures 140 and by the plurality of insulating fences 180a. For example, each of the plurality of buried contacts 170 may be positioned within two adjacent insulating spacer structures 150 (e.g., Figure 18 The cross section A-A') and the two adjacent insulating fences 180a (e.g. Figure 18 Within the space defined by the cross section C-C', the two adjacent insulating spacer structures 150 face each other across this space. For example, the plurality of buried contacts 170 can be spaced apart from each other in a first horizontal direction (X direction) by the plurality of insulating spacer structures 150, and can be spaced apart from each other in a second horizontal direction (Y direction) by the plurality of insulating fences 180a.

[0103] Reference Figure 19 Semiconductor memory device 3 can be controlled by... Figure 18 The resulting structure is executed by reference. Figures 11 to 13 The process described is used to form it.

[0104] The semiconductor memory device 3 may include a substrate 110 having the plurality of active regions 118. The plurality of gate dielectric layers 122, the plurality of word lines 120, and the plurality of buried insulating layers 124 may be sequentially formed within the plurality of word line trenches 120T formed in the substrate 110. A device isolation layer 116 may be formed to define the plurality of active regions 118. The plurality of insulating layer patterns (112 and 114) may be formed to cover the plurality of buried insulating layers 124. The plurality of landing pads 190 may be formed to fill the upper portion of a first space defined by the plurality of insulating spacer structures 150 covering the sidewalls of the plurality of bit line structures 140 and the upper portion of a second space between the plurality of insulating fences 180a. The plurality of buried contacts 170 may fill the lower portion of the first space and the lower portion of the second space. Each of the plurality of buried contacts 170 may be connected to a corresponding one of the plurality of active regions 118. Each of the plurality of landing pads 190 may extend to the top of a corresponding one of the plurality of bit line structures 140. The plurality of capacitor structures 200 may be formed to include the plurality of bottom electrodes 210, a capacitor dielectric layer 220, and a top electrode 230. Each of the plurality of bottom electrodes 210 may be connected to a corresponding one of the plurality of landing pads 190.

[0105] Since the plurality of insulating fences 180a fill the plurality of fence holes 180Ha, the first width W1 (which is the width of the lower portion of each of the plurality of insulating fences 180a in the second horizontal direction (Y direction) between a pair of buried contacts 170) can be smaller than the second width W2 (which is the width of the upper portion of each of the plurality of insulating fences 180a in the second horizontal direction (Y direction) between a pair of landing pads 190). The upper and lower portions of the plurality of insulating fences 180a can be portions further away from the substrate 110 and closer to the substrate 110 in the vertical direction (Z direction) in the region overlapping with the plurality of buried contacts 170 and the plurality of landing pads 190, respectively. In other words, among the plurality of insulating fences 180a, the first width W1 (which is the width of the lower portion in the second horizontal direction (Y direction)) can be smaller than the second width W2 (which is the width of the upper portion in the second horizontal direction (Y direction)).

[0106] The width of each of the plurality of enclosure holes 180Ha in the first horizontal direction (X direction) can be defined by the width between a pair of insulating spacer structures 150 facing each other, and can increase as it moves away from the substrate 110 in the vertical direction (Z direction) perpendicular to the substrate 110.

[0107] In the semiconductor memory device 3, the upper portion of each of the plurality of insulating fences 180a has a second width W2 in the second horizontal direction (Y direction) that is greater than the lower portion of each of the plurality of insulating fences 180a has a first width W1 in the second horizontal direction (Y direction). Therefore, the plurality of buried contacts 170 between the lower portions of the plurality of insulating fences 180a can have a relatively large horizontal width in the second horizontal direction (Y direction). Consequently, the specific resistance of the plurality of buried contacts 170 can have a relatively small value, and the reliability of the electrical connection between the plurality of buried contacts 170 and the plurality of active regions 118 can be improved.

[0108] Figures 20 to 22 This is a cross-sectional view showing a method for manufacturing a semiconductor memory device 4 according to an embodiment of the present invention. Figure 20 It is shown in the reference Figure 8 A cross-sectional view of the operation following the operation, with references omitted. Figure 20 and Figure 21 The given reference Figures 2 to 12 The given description may be repeated, and the reference numerals may denote the same parts. Figure 22 The main components of a semiconductor memory device 4 according to an exemplary embodiment of the present invention are shown. The semiconductor memory device 4 may correspond to... Figure 1 10. Semiconductor memory device.

[0109] Refer to together Figure 8 and Figure 20 By using the plurality of mask patterns MK as etching masks to remove a portion of the molding layer 175 and a portion of the initial buried contact material layer 170p, a plurality of fencing holes 180Hb can be formed, exposing the buried insulating layer 124 to its bottom surface. In some embodiments, the plurality of fencing holes 180Hb can be arranged in a first horizontal direction (X direction) and a second horizontal direction (Y direction), respectively. In an example embodiment, by performing an etching process using the plurality of mask patterns MK as etching masks, the molding layer 175 and the initial buried contact material layer 170p can be patterned to form a plurality of molded patterns 175P and the plurality of buried contacts 170 that are spaced apart from each other.

[0110] The initial buried contact material layer 170p can be divided into multiple buried contacts 170 through the multiple fence holes 180Hb.

[0111] During the formation of the plurality of enclosure holes 180Hb, due to the difference in etching characteristics between the molding layer 175 and the initial buried contact material layer 170p, the second width W2a (which is the upper width of each of the plurality of enclosure holes 180Hb in the second horizontal direction (Y direction) between a pair of molding patterns 175P) can be smaller than the first width W1a (which is the lower width of each of the plurality of enclosure holes 180Hb in the second horizontal direction (Y direction) between a pair of buried contacts 170). In other words, in the plurality of enclosure holes 180Hb, the second width W2a (which is the upper width in the second horizontal direction (Y direction)) can be smaller than the first width W1a (which is the lower width in the second horizontal direction (Y direction)). In some embodiments, the first width W1a can be approximately 1 nm to approximately 5 nm larger than the second width W2a.

[0112] The width of each of the plurality of enclosure holes 180Hb in the first horizontal direction (X direction) can be defined by the width between a pair of insulating spacer structures 150 facing each other, and can increase as it moves away from the substrate 110 in the vertical direction (Z direction) perpendicular to the substrate 110.

[0113] In some implementations, during the formation Figure 9 After the plurality of fence holes 180H shown, a portion of the burial contact 170 can be further removed to form Figure 20 The plurality of fence holes 180Hb shown.

[0114] Reference Figure 21Multiple insulating fences 180b can be formed to fill the plurality of fence holes 180Hb. The plurality of insulating fences 180b may include, for example, a nitride layer. After forming a fence material layer that fills the plurality of fence holes 180Hb and covers the top surface of the molded pattern 175P, the plurality of insulating fences 180b can be formed by removing the portion of the fence material layer that covers the top surface of the molded pattern 175P.

[0115] The plurality of buried contacts 170 may be located within a space defined by the plurality of insulating spacer structures 150 covering the sidewalls of the plurality of bit line structures 140 and by the plurality of insulating fences 180b. For example, each of the plurality of buried contacts 170 may be positioned within two adjacent insulating spacer structures 150 (e.g., Figure 21 The cross section A-A') and the two adjacent insulating fences 180b (e.g. Figure 21 Within the space defined by the cross section C-C', the two adjacent insulating spacer structures 150 face each other across this space. For example, the plurality of buried contacts 170 can be spaced apart from each other in a first horizontal direction (X direction) by the plurality of insulating spacer structures 150 and can be spaced apart from each other in a second horizontal direction (Y direction) by the plurality of insulating fences 180b.

[0116] Each of the plurality of insulating fences 180b may include an air gap 180AR. In some embodiments, the air gap 180AR may be located within the lower portion of each of the plurality of insulating fences 180b. The lower portion of each of the plurality of insulating fences 180b may be its portion between a pair of burial contacts 170.

[0117] Reference Figure 22 This can be achieved by executing the reference. Figures 11 to 13 The process described is used to form semiconductor memory devices 4.

[0118] The semiconductor memory device 4 may include a substrate 110 having the plurality of active regions 118. The plurality of gate dielectric layers 122, the plurality of word lines 120, and the plurality of buried insulating layers 124 may be sequentially formed within the plurality of word line trenches 120T formed in the substrate 110. A device isolation layer 116 may define the plurality of active regions 118. The plurality of insulating layer patterns (112 and 114) may be formed to cover the plurality of buried insulating layers 124. The plurality of landing pads 190 may be formed to fill the upper portion of a first space defined by the plurality of insulating spacer structures 150 covering the sidewalls of the plurality of bit line structures 140 and the upper portion of a second space between the plurality of insulating fences 180b. The plurality of buried contacts 170 may fill the lower portion of the first space and the lower portion of the second space. Each of the plurality of buried contacts 170 may be connected to a corresponding one of the plurality of active regions 118. Each of the plurality of landing pads 190 may extend to the top of a corresponding one of the plurality of bit line structures 140. The plurality of capacitor structures 200 may be formed to include the plurality of bottom electrodes 210, a capacitor dielectric layer 220, and a top electrode 230. The plurality of bottom electrodes 210 may be connected to the plurality of landing pads 190.

[0119] Since the plurality of insulating fences 180b fill the plurality of fence holes 180Hb, the first width W1a (which is the width of the lower portion of each of the plurality of insulating fences 180b between a pair of buried contacts 170 in the second horizontal direction (Y direction)) can be greater than the second width W2a (which is the width of the upper portion of each of the plurality of insulating fences 180b between a pair of landing pads 190 in the second horizontal direction (Y direction). The upper and lower portions of the plurality of insulating fences 180b can be portions away from the substrate 110 and portions towards the substrate 110 in the vertical direction (Z direction) of the regions overlapping with the plurality of buried contacts 170 and the plurality of landing pads 190, respectively. In other words, among the plurality of insulating fences 180b, the first width W1a (which is the width of the lower portion in the second horizontal direction (Y direction)) can be greater than the second width W2a (which is the width of the upper portion in the second horizontal direction (Y direction)).

[0120] The width of each of the plurality of enclosure holes 180Hb in the first horizontal direction (X direction) can be defined by the width between a pair of insulating spacer structures 150 facing each other, and can increase as it moves away from the substrate 110 in the vertical direction (Z direction) perpendicular to the substrate 110.

[0121] In the semiconductor memory device 4, the second width W2a of the upper portion of each of the plurality of insulating fences 180b in the second horizontal direction (Y direction) can be smaller than the first width W1a of the lower portion of each of the plurality of insulating fences 180b in the second horizontal direction (Y direction). Therefore, the plurality of landing pads 190 between the upper portions of each of the plurality of insulating fences 180a can have a relatively large width in the second horizontal direction (Y direction). Consequently, the resistivity of the plurality of landing pads 190 can have a relatively small value, and the reliability of the electrical connection between the plurality of buried contacts 170 and the plurality of capacitor structures 200 can be improved.

[0122] Furthermore, since the semiconductor memory device 4 includes an air gap 180AR in each of the plurality of insulating fences 180b, the parasitic capacitance of the space between a pair of buried contacts 170 having one of the plurality of insulating fences 180b therebetween can be reduced.

[0123] Figure 23 This is a cross-sectional view of the main components of a semiconductor memory device 5 according to an exemplary embodiment of the present invention. The semiconductor memory device 5 may correspond to... Figure 1 10. Semiconductor memory device.

[0124] Reference Figure 23The semiconductor memory device 5 may include a substrate 110 having the plurality of active regions 118. The plurality of gate dielectric layers 122, the plurality of word lines 120, and the plurality of buried insulating layers 124 may be sequentially formed within the plurality of word line trenches 120T formed in the substrate 110. A device isolation layer 116 may define the plurality of active regions 118. The plurality of insulating layer patterns (112 and 114) may be formed to cover the plurality of buried insulating layers 124. The plurality of bit line structures 140a may be formed on the plurality of insulating layer patterns (112 and 114). The plurality of landing pads 190 may be formed to fill the upper portion of a first space defined by the plurality of insulating spacer structures 150 covering the sidewalls of the plurality of bit line structures 140a and the upper portion of a second space between the plurality of insulating fences 180a. The plurality of buried contacts 170 may fill the lower portion of the first space and the lower portion of the second space. Each of the plurality of buried contacts 170 can be connected to a corresponding one of the plurality of active regions 118. Each of the plurality of landing pads 190 can extend to the top of a corresponding one of the plurality of bit line structures 140. The plurality of capacitor structures 200 can be formed to include the plurality of bottom electrodes 210, capacitor dielectric layers 220, and top electrodes 230. Each of the plurality of bottom electrodes 210 can be connected to a corresponding one of the plurality of landing pads 190. The plurality of landing pads 190 can cover at least a portion of the top surface of the plurality of extended capping layers 158 of the bit line structure 140a.

[0125] Semiconductor memory device 5 may include multiple insulating barriers 180a, instead of Figure 16 The semiconductor memory device 2 shown has the plurality of insulating barriers 180. Therefore, in the semiconductor memory device 5, the second width W2 of the upper portion of each of the plurality of insulating barriers 180a in the second horizontal direction (Y direction) can be greater than the first width W1 of the lower portion of each of the plurality of insulating barriers 180a in the second horizontal direction (Y direction). Therefore, each of the plurality of buried contacts 170 between the lower portions of the plurality of insulating barriers 180a can have a relatively large width in the second horizontal direction (Y direction). Therefore, the specific resistance of the plurality of buried contacts 170 can have a relatively small value, and the reliability of the electrical connection between the plurality of buried contacts 170 and the plurality of active regions 118 can be improved.

[0126] Figure 24 This is a cross-sectional view of the main components of a semiconductor memory device 6 according to an exemplary embodiment of the present invention. The semiconductor memory device 6 may correspond to... Figure 1 10. Semiconductor memory device.

[0127] Reference Figure 24The semiconductor memory device 6 may include a substrate 110 having the plurality of active regions 118. The plurality of gate dielectric layers 122, the plurality of word lines 120, and the plurality of buried insulating layers 124 may be sequentially formed within the plurality of word line trenches 120T formed in the substrate 110. A device isolation layer 116 may be formed to define the plurality of active regions 118. The plurality of insulating layer patterns (112 and 114) may be formed to cover the plurality of buried insulating layers 124. The plurality of bit line structures 140a may be formed on the plurality of insulating layer patterns (112 and 114). The plurality of landing pads 190 may be formed to fill the upper portion of a first space defined by the plurality of insulating spacer structures 150 covering the sidewalls of the plurality of bit line structures 140a and the upper portion of a second space between the plurality of insulating fences 180b. The plurality of buried contacts 170 may fill the lower portion of the first space and the lower portion of the second space. Each of the plurality of buried contacts 170 can be connected to a corresponding one of the plurality of active regions 118. Each of the plurality of landing pads 190 can extend to the top of a corresponding one of the plurality of bit line structures 140. The plurality of capacitor structures 200 can be formed to include the plurality of bottom electrodes 210, capacitor dielectric layers 220, and top electrodes 230. Each of the plurality of bottom electrodes 210 can be connected to a corresponding one of the plurality of landing pads 190. The plurality of landing pads 190 can cover at least a portion of the top surface of the plurality of extended capping layers 158 of the bit line structure 140a.

[0128] Semiconductor memory device 6 may include multiple insulating fences 180b, instead of Figure 16 The semiconductor memory device 2 shown has the plurality of insulating barriers 180. Therefore, in the semiconductor memory device 6, since the second width W2a of the upper portion of each of the plurality of insulating barriers 180b in the second horizontal direction (Y direction) can be smaller than the first width W1a of the lower portion of each of the plurality of insulating barriers 180b in the second horizontal direction (Y direction), each of the plurality of landing pads 190 between the upper portions of each of the plurality of insulating barriers 180a can have a relatively large width in the second horizontal direction (Y direction). Therefore, the resistivity of the plurality of landing pads 190 can have a relatively small value, and the reliability of the electrical connection between the plurality of buried contacts 170 and the plurality of capacitor structures 200 can be improved.

[0129] Furthermore, since the semiconductor memory device 6 includes an air gap 180AR in each of the plurality of insulating fences 180b, the parasitic capacitance in the space between a pair of buried contacts 170 (i.e., each of the plurality of insulating fences 180b) can be reduced.

[0130] Although the inventive concept has been specifically shown and described with reference to exemplary embodiments thereof, the inventive concept is not limited to the exemplary embodiments, and various changes and modifications may be made by those skilled in the art without departing from the spirit and scope of the inventive concept.

[0131] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the following claims.

[0132] This application claims the benefit of Korean Patent Application No. 10-2019-0092003, filed on July 29, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A method of fabricating a semiconductor memory device, the method comprising: forming a plurality of bit line structures extending in a first horizontal direction parallel to one another on a substrate and a plurality of insulating spacer structures covering opposite sidewalls of each of the plurality of bit line structures; forming an initial buried contact material layer and a molding layer to fill a lower portion of a space between a pair of the plurality of insulating spacer structures facing each other across the space and an upper portion of the space, respectively; patterning the molding layer and the initial buried contact material layer into a plurality of molding patterns spaced apart from one another in the first horizontal direction and a plurality of buried contacts spaced apart from one another in the first horizontal direction, respectively; forming a plurality of insulating fences between the plurality of molding patterns spaced apart from one another and between the plurality of buried contacts spaced apart from one another; removing the plurality of molding patterns to expose the plurality of buried contacts; and forming a plurality of landing pads on the exposed plurality of buried contacts, each of the plurality of landing pads connected to a corresponding one of the exposed plurality of buried contacts.

2. The method of claim 1, further comprising: removing an upper portion of the plurality of insulating spacer structures above a top surface of the initial buried contact material layer in the lower portion of the space after the forming of the initial buried contact material layer in the lower portion of the space and before the forming of the molding layer in the upper portion of the space.

3. The method of claim 2, wherein each of the plurality of bit line structures comprises a bit line and an insulating cap line covering the bit line, and the removing of the upper portion of the plurality of insulating spacer structures exposes an upper portion of the insulating cap line of each of the plurality of bit line structures, the method further comprising: forming an extended cap layer covering the exposed upper portion of the insulating cap line and protruding toward the top surface of the initial buried contact material layer after the removing of the upper portion of the plurality of insulating spacer structures and before the forming of the molding layer.

4. The method of claim 3, wherein each of the plurality of landing pads is formed to cover at least a portion of the extended cap layer.

5. The method of claim 1, wherein the removing of the plurality of molding patterns forms a plurality of spaces, and each of the plurality of landing pads is formed to fill a corresponding one of the plurality of spaces and to extend to a corresponding one of the plurality of bit line structures.

6. The method of claim 1, wherein each of the plurality of insulating fences is formed to have an upper portion having a first width in the first horizontal direction and a lower portion having a second width in the first horizontal direction different from the first width, the upper portion of each of the plurality of insulating fences is disposed between two adjacent landing pads of the plurality of landing pads, and the lower portion of each of the plurality of insulating fences is disposed between two adjacent buried contacts of the plurality of buried contacts.

7. The method of claim 1, wherein ​ each of the plurality of insulative fences is formed to have an upper portion having a first width in the first horizontal direction and a lower portion having a second width in the first horizontal direction that is less than the first width, the upper portion of each of the plurality of insulative fences is disposed between two adjacent landing pads of the plurality of landing pads, and the lower portion of each of the plurality of insulative fences is disposed between two adjacent buried contacts of the plurality of buried contacts.

8. The method of claim 1, wherein each of the plurality of insulative fences is formed to have an upper portion having a first width in the first horizontal direction and a lower portion having a second width in the first horizontal direction that is greater than the first width, the upper portion of each of the plurality of insulative fences is disposed between two adjacent landing pads of the plurality of landing pads, and the lower portion of each of the plurality of insulative fences is disposed between two adjacent buried contacts of the plurality of buried contacts.

9. The method of claim 8, wherein each of the plurality of insulative fences is formed to include an air gap within a lower portion thereof, and the air gap is disposed between two adjacent buried contacts of the plurality of buried contacts.

10. The method of claim 1, wherein each of the plurality of insulative fences is formed to have a width that increases as it moves away from the substrate in a direction perpendicular to a major surface of the substrate, and the increasing width is measured in a second horizontal direction that is different from the first horizontal direction.

11. A method of fabricating a semiconductor memory device, the method comprising: forming a plurality of bit line structures, a plurality of first insulative spacer structures, and a plurality of second insulative spacer structures on a substrate, each of the plurality of first insulative spacer structures covering a first sidewall of a corresponding one of the plurality of bit line structures, each of the plurality of second insulative spacer structures covering a second sidewall of the corresponding one of the plurality of bit line structures that is opposite the first sidewall; forming an initial buried contact material layer and a molding layer on the substrate, wherein the initial buried contact material layer and the molding layer are formed in a first space between one of the plurality of first insulative spacer structures and one of the plurality of second insulative spacer structures that is adjacent to the one of the plurality of first insulative spacer structures in a first horizontal direction, wherein the initial buried contact material layer fills a lower portion of the first space and the molding layer fills an upper portion of the first space; and patterning the molding layer and the initial buried contact material layer into a plurality of molding patterns that are spaced apart from one another in a second horizontal direction that is different from the first horizontal direction and a plurality of buried contacts that are spaced apart from one another in the second horizontal direction. a plurality of insulative fences are formed between the plurality of buried contacts and between the plurality of molded patterns, a first insulative fence of the plurality of insulative fences has a lower portion and an upper portion, the lower portion of the first insulative fence is disposed between a pair of buried contacts of the plurality of buried contacts that are spaced apart from each other in the second horizontal direction and has a first width in the second horizontal direction, and the upper portion of the first insulative fence is disposed between a pair of molded patterns of the plurality of molded patterns that are spaced apart from each other in the second horizontal direction and has a second width in the second horizontal direction that is different from the first width.

12. The method of claim 11, further comprising: removing the plurality of molded patterns to expose the plurality of buried contacts; and forming a plurality of landing pads to fill second spaces formed by removing the plurality of molded patterns.

13. The method of claim 11, wherein the second width of the upper portion of the first insulative fence is greater than the first width of the lower portion of the first insulative fence.

14. The method of claim 11, further comprising: forming an air gap in the first insulative fence, wherein the second width of the upper portion of the first insulative fence is less than the first width of the lower portion of the first insulative fence.

15. A method of manufacturing a semiconductor memory device, the method comprising: preparing a substrate having a plurality of active regions defined by an element isolation layer; forming a plurality of word line trenches crossing the plurality of active regions and extending parallel to each other in a first horizontal direction, and forming a plurality of gate dielectric layers and a plurality of word lines to fill the plurality of word line trenches; forming a plurality of bit line structures on the substrate and a plurality of insulative spacer structures covering opposite sidewalls of each of the plurality of bit line structures, each of the bit line structures including a bit line and an insulative cap line covering the bit line, the plurality of bit line structures extending parallel to each other in a second horizontal direction crossing the first horizontal direction; forming a first initial buried contact material layer to fill a first space between a pair of insulative spacer structures of the plurality of insulative spacer structures facing each other across the first space; removing an upper portion of the first initial buried contact material layer to form a second initial buried contact material layer and a second space between the pair of insulative spacer structures; forming a molding layer to fill the second space; forming a plurality of molded patterns and a plurality of buried contacts by patterning the molding layer and the second initial buried contact material layer, respectively, wherein the plurality of molded patterns are separated from each other and the plurality of buried contacts are separated from each other, and wherein each of the plurality of buried contacts is connected to a corresponding active region of the plurality of active regions; forming a plurality of landing pads on the plurality of buried contacts after removing the plurality of molded patterns, wherein each of the plurality of landing pads is connected to a corresponding one of the plurality of buried contacts; and forming a plurality of capacitors on the plurality of landing pads, wherein each of the plurality of capacitors includes a bottom electrode connected to a corresponding one of the plurality of landing pads.

16. The method of claim 15, further comprising: removing an upper portion of each of the plurality of insulative spacer structures to expose an upper portion of the insulative cap line of each of the plurality of bit line structures, and forming an extended cap layer including an upper portion covering the exposed upper portion of the insulative cap line and a bottom portion protruding toward a top surface of the second initial buried contact material layer, wherein the removing of the upper portion of each of the plurality of insulative spacer structures and the forming of the extended cap layer are performed after the removing of the upper portion of the first initial buried contact material layer and before the forming of the molding layer.

17. The method of claim 16, wherein the extended cap layer is formed to include a first portion having a first thickness and a second portion having a second thickness smaller than the first thickness, the first portion being closer to a top end of the insulative cap line than the second portion.

18. The method of claim 17, wherein each of the plurality of landing pads is formed to extend to a top surface of the extended cap layer.

19. The method of claim 15, wherein each of the plurality of buried contacts and a corresponding one of the plurality of molding patterns connected thereto has a first width and a second width different from the first width, respectively.

20. The method of claim 19, wherein wherein the second width is 1 nm to 5 nm smaller than the first width.

21. A semiconductor memory device, comprising: a substrate having a plurality of active regions defined by element isolation layers; a plurality of bit line structures extending parallel to each other in a first horizontal direction on the substrate and spaced apart from each other in a second horizontal direction different from the first horizontal direction, each of the plurality of bit line structures including a bit line and an insulative cap line stacked on the bit line; a plurality of first insulative spacer structures covering first sidewalls of the plurality of bit line structures; a plurality of second insulative spacer structures covering second sidewalls of the plurality of bit line structures; a plurality of insulative fences disposed in a first space between one of the plurality of first insulative spacer structures and one of the plurality of second insulative spacer structures adjacent to the one of the plurality of first insulative spacer structures in the second horizontal direction and spaced apart from each other in the first horizontal direction; a plurality of buried contacts disposed in the first space and spaced apart from each other in the first horizontal direction, each of the plurality of buried contacts filling a lower portion of the first space and connected to a corresponding one of the plurality of active regions, wherein each of the plurality of buried contacts and each of the plurality of insulative fences are arranged alternately in the first horizontal direction; and a plurality of landing pads disposed in the first space and spaced apart from each other in the first horizontal direction, each of the plurality of landing pads connected to a corresponding one of the plurality of buried contacts. a plurality of landing pads spaced apart from one another in the first horizontal direction, each of the plurality of landing pads connected to a corresponding one of the plurality of buried contacts, each of the plurality of landing pads filling an upper portion of the first space and extending to a top portion of a corresponding one of the plurality of bit line structures, wherein each of the plurality of insulative fences extends from between a corresponding pair of buried contacts among the plurality of buried contacts to between a corresponding pair of landing pads among the plurality of landing pads, wherein a first width of each of the plurality of insulative fences at a lower portion between the corresponding pair of buried contacts is different from a second width of each of the plurality of insulative fences at an upper portion between the corresponding pair of landing pads, and wherein the first width and the second width are measured in the first horizontal direction.

22. The semiconductor memory device of claim 21, wherein the second width of each of the plurality of insulative fences is greater than the first width of each of the plurality of insulative fences.

23. The semiconductor memory device of claim 21, wherein the first width of each of the plurality of insulative fences is greater than the second width of each of the plurality of insulative fences.

24. The semiconductor memory device of claim 23, wherein each of the plurality of insulative fences includes an air gap therein, the air gap disposed between two adjacent buried contacts of the plurality of buried contacts.

25. The semiconductor memory device of claim 21, wherein the first width and the second width of each of the plurality of insulative fences differ by 1 nm to 5 nm.

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