Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device includes a first stack structure including a plurality of first insulating patterns and a plurality of first semiconductor patterns alternately stacked on a substrate, the first stack structure extending in a first direction parallel to an upper surface of the substrate; a first conductive pattern located on one side surface of the first stack structure, the first conductive pattern extending in a second direction crossing the upper surface of the substrate; and a first ferroelectric layer located between the first stack structure and the first conductive pattern, the first ferroelectric layer extending in the second direction, wherein each of the first semiconductor patterns includes a first impurity region, a first channel region, and a second impurity region sequentially arranged along the first direction.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0092960 filed on July 31, 2019, in the Korean Intellectual Property Office, and all the benefits accruing therefrom, the contents of which are incorporated herein in their entirety. TECHNICAL FIELD

[0002] The present disclosure relates to a semiconductor device, and more particularly, to a semiconductor device including a ferroelectric. BACKGROUND

[0003] To meet the demand for excellent performance and low price of a semiconductor device, higher integration of the semiconductor device is required. In the case of a two-dimensional or planar semiconductor device, since the integration thereof is mainly determined by the area occupied by a unit cell, the integration is greatly affected by the level of fine pattern forming technology.

[0004] However, recently, as the design rule of a semiconductor device is rapidly reduced, there is a limitation in forming a fine pattern due to resolution limitation of a process for forming a pattern required to implement the semiconductor device. Accordingly, a three-dimensional semiconductor device in which cells are arranged in three dimensions has been proposed. SUMMARY

[0005] At least one embodiment relates to a semiconductor device having improved performance and integration by implementing a ferroelectric field effect transistor arranged in three dimensions.

[0006] However, example embodiments are not limited to the example embodiments set forth herein. The above and other aspects of the example embodiments will become more apparent by referring to the following detailed description when considered in conjunction with the accompanying drawings.

[0007] According to an aspect of the present inventive concept, there is provided an example embodiment of a semiconductor device including: a first stack structure including a plurality of first insulating patterns and a plurality of first semiconductor patterns alternately stacked on a substrate, the first stack structure extending in a first direction, each of the plurality of first semiconductor patterns including a first impurity region, a first channel region, and a second impurity region arranged in order along the first direction, the first direction being parallel to an upper surface of the substrate; a first conductive pattern on a first side surface of the first stack structure, the first conductive pattern extending in a second direction, the second direction crossing the upper surface of the substrate; and a first ferroelectric layer between the first stack structure and the first conductive pattern, the first ferroelectric layer extending in the second direction.

[0008] According to an aspect of the present inventive concept, there is provided an example embodiment of a semiconductor device including: a first semiconductor pattern on a substrate, the first semiconductor pattern including a first impurity region, a first channel region, and a second impurity region sequentially arranged in a first direction, the first direction being parallel to an upper surface of the substrate; a first gate electrode on a first side surface of the first channel region and a second gate electrode on a second side surface of the first channel region, the first gate electrode and the second gate electrode respectively extending in a second direction, the second direction being transverse to the upper surface of the substrate; a first ferroelectric layer between the first channel region and the first gate electrode, the first ferroelectric layer extending in the second direction; and a second ferroelectric layer between the first channel region and the second gate electrode, the second ferroelectric layer extending in the second direction.

[0009] According to an aspect of the present inventive concept, there is provided an example embodiment of a semiconductor device including: a first stack structure including a plurality of first insulating patterns and a plurality of first semiconductor patterns alternately stacked on a substrate, the first stack structure extending in a first direction, each of the plurality of first semiconductor patterns including a first impurity region, a channel region, and a second impurity region sequentially arranged along the first direction, the first direction being parallel to an upper surface of the substrate; a plurality of first wiring patterns respectively connected to first ends of the plurality of first semiconductor patterns, the plurality of first wiring patterns extending in a second direction parallel to the upper surface of the substrate and transverse to the first direction; a second wiring pattern connected to second ends of the plurality of first semiconductor patterns; a first gate electrode on a first side surface of the first stack structure between the plurality of first wiring patterns and the second wiring pattern, the first gate electrode extending in a third direction transverse to the upper surface of the substrate; and a first ferroelectric layer between the first stack structure and the first gate electrode, the first ferroelectric layer extending in the third direction along first side surfaces of the channel regions of the plurality of first semiconductor patterns. BRIEF DESCRIPTION OF DRAWINGS

[0010] The above and other aspects and features of the present disclosure will become more apparent from the following detailed description, taken in conjunction with the accompanying drawings, which illustrate

[0011] Figure 1 is a circuit diagram illustrating a semiconductor device according to an example embodiment.

[0012] Figure 2 is a schematic perspective view illustrating a semiconductor device according to an example embodiment.

[0013] Figure 3 is a cross-sectional view taken along line A-A of Figure 2 .

[0014] Figure 4 is a cross-sectional view taken along lineFigure 2 The sectional view taken by line BB.

[0015] Figure 5 This is a circuit diagram illustrating a semiconductor device according to an example embodiment.

[0016] Figure 6 This is a schematic perspective view illustrating a semiconductor device according to an example embodiment.

[0017] Figure 7 It is along Figure 6 The sectional view taken by the CC line.

[0018] Figure 8 This is a circuit diagram illustrating a semiconductor device according to an example embodiment.

[0019] Figure 9 This is a schematic perspective view illustrating a semiconductor device according to an example embodiment.

[0020] Figure 10 It is along Figure 9 The sectional view taken by line DD.

[0021] Figure 11 This is a schematic perspective view illustrating a semiconductor device according to an example embodiment.

[0022] Figure 12 It is along Figure 11 The sectional view taken by the line EE.

[0023] Figure 13 This is a schematic perspective view illustrating a semiconductor device according to an example embodiment.

[0024] Figures 14 to 17 It is along Figure 13 Various sectional views captured by the FF line.

[0025] Figure 18 This is a schematic perspective view illustrating a semiconductor device according to an example embodiment.

[0026] Figure 19 and Figure 20 It is along Figure 18 Various sectional views taken from the line GG.

[0027] Figure 21 This is a schematic perspective view illustrating a semiconductor device according to an example embodiment.

[0028] Figure 22 This is a schematic perspective view illustrating a semiconductor device according to an embodiment. Detailed Implementation

[0029] Although the terms "first", "second", "third", and the like can be used herein to describe various elements, components, regions, and / or sections, these elements, components, regions, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, or section from another element, component, region, or section. Thus, a first element, component, region, layer, or section discussed below could be termed a second element, component, region, layer, or section without departing from the scope of the present disclosure.

[0030] When an element is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element or one or more other elements can be interposed therebetween. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intermediate elements interposed therebetween.

[0031] Hereinafter, a semiconductor device according to example embodiments of the present inventive concept will be described with reference to Figures 1 to 22

[0032] Figure 1 is a circuit diagram illustrating a semiconductor device according to an example embodiment. Figure 2 is a schematic perspective view illustrating a semiconductor device according to an example embodiment. Figure 3 is a cross-sectional view taken along line A-A of Figure 2 Figure 4 is a cross-sectional view taken along line B-B of Figure 2 In order to simplify the description, the illustration of the interlayer insulating layer 180 is omitted in Figure 2

[0033] With reference to Figure 1 , a semiconductor device according to some embodiments can include a plurality of bit lines BL, a plurality of word lines WL, and a plurality of cell transistors CT.

[0034] The plurality of bit lines BL can be arranged two-dimensionally. For example, the plurality of bit lines BL can be arranged on the same topological plane, can be spaced apart from each other, and can extend side by side. The plurality of cell transistors CT can be connected in parallel to each bit line BL. Although two cell transistors CT are shown to be connected to one bit line BL, this is merely an example embodiment, and a bit line BL can have one cell transistor CT connected thereto or three or more cell transistors CT.

[0035] ​​​A plurality of word lines WL can be arranged two-dimensionally. For example, the plurality of word lines WL can be arranged on the same topological plane, can be spaced apart from each other, and can extend side by side. A plurality of cell transistors CT can be connected in parallel to each word line WL. Although four cell transistors CT are shown to be connected to one word line WL, this is merely an example embodiment, and a word line WL can have one cell transistor CT or three or more cell transistors CT connected thereto. In some embodiments, each word line WL can extend in a direction crossing each bit line BL.

[0036] Each cell transistor CT can be connected to one word line WL and one bit line BL. A gate of each cell transistor CT can be connected to the word line WL. In addition, a source of each cell transistor CT can be connected to the bit line BL.

[0037] A drain of each cell transistor CT can be connected to a wiring line CL. In some embodiments, one wiring line CL can correspond to one word line WL. For example, as shown, a plurality of cell transistors CT sharing one word line WL can share one wiring line CL. In some embodiments, each wiring line CL can extend in a direction crossing each bit line BL.

[0038] Referring to Figures 2 to 4 The semiconductor device described above with reference to Figure 1 The semiconductor device according to some embodiments can include a substrate 100, a first stack structure SS1, a second stack structure SS2, a first wiring structure CS1, a first conductive pattern 170, a second conductive pattern 270, a first ferroelectric layer 160, a second ferroelectric layer 260, and an interlayer insulating layer 180.

[0039] The substrate 100 can include, for example, a semiconductor substrate such as a silicon substrate, a germanium substrate, or a silicon germanium substrate. Alternatively, the substrate 100 can include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0040] The first stack structure SS1 and the second stack structure SS2 can be formed on the substrate 100. Each of the first stack structure SS1 and the second stack structure SS2 can extend in a first direction X parallel to an upper surface of the substrate 100. In addition, the first stack structure SS1 and the second stack structure SS2 can extend in parallel to each other. For example, the first stack structure SS1 and the second stack structure SS2 can be arranged along a second direction Y parallel to the upper surface of the substrate 100 and crossing the first direction X.

[0041] In some embodiments, the first stack structure SS1 and the second stack structure SS2 can be formed at the same level. The term "the same level" as used herein means formed by the same manufacturing process.

[0042] Each of the first stack structure SS1 and the second stack structure SS2 can include a plurality of semiconductor patterns arranged vertically. For example, the first stack structure SS1 can include a plurality of first semiconductor patterns 120 arranged along a third direction Z crossing an upper surface of the substrate 100. Also, for example, the second stack structure SS2 can include a plurality of second semiconductor patterns 220 arranged along the third direction Z.

[0043] In some embodiments, the first stack structure SS1 can include a plurality of first insulating patterns 110 and a plurality of first semiconductor patterns 120 alternately stacked on the substrate 100. That is, the plurality of first semiconductor patterns 120 can be spaced apart from each other by the first insulating patterns 110. Example embodiments can include, for example, two to eight alternating stacks, but are not limited thereto. Also, in some embodiments, the second stack structure SS2 can include a plurality of second insulating patterns 210 and a plurality of second semiconductor patterns 220 alternately stacked on the substrate 100. That is, the plurality of second semiconductor patterns 220 can be spaced apart from each other by the second insulating patterns 210.

[0044] The plurality of first insulating patterns 110 and the plurality of second insulating patterns 210 can include an insulating material. For example, the plurality of first insulating patterns 110 and the plurality of second insulating patterns 210 can include, but are not limited to, silicon oxide.

[0045] Each of the first semiconductor patterns 120 and each of the second semiconductor patterns 220 can extend in the first direction X. Each of the first semiconductor patterns 120 and each of the second semiconductor patterns 220 can have, for example, a linear shape, a bar shape, or a column shape extending in the first direction X, but the present disclosure is not limited thereto.

[0046] Each of the first semiconductor patterns 120 and each of the second semiconductor patterns 220 can include an elemental semiconductor material (e.g., silicon (Si) or germanium (Ge)), a compound semiconductor (e.g., a group IV-IV compound semiconductor or a group III-V compound semiconductor), and / or a combination thereof.

[0047] Each first semiconductor pattern 120 can include a first impurity region 124, a first channel region 122, and a second impurity region 126 sequentially arranged along the first direction X. For example, the first channel region 122 can be disposed between the first impurity region 124 and the second impurity region 126. The first channel region 122 can correspond to a channel of a unit transistor CT described above with reference to FIG. 1. Figure 1 Each second semiconductor pattern 220 can include a third impurity region 224, a second channel region 222, and a fourth impurity region 226 sequentially arranged along the first direction X. For example, the second channel region 222 can be disposed between the third impurity region 224 and the fourth impurity region 226. The second channel region 222 can correspond to a channel of a unit transistor CT described above with reference to FIG. 1.

[0048] The first impurity region 124 and the second impurity region 126 can be regions in which impurities are doped in the first semiconductor pattern 120. For example, the first impurity region 124 and the second impurity region 126 can include n-type impurities or p-type impurities. Accordingly, the first impurity region 124 and the second impurity region 126 can correspond to the source and the drain of another unit transistor CT described above with reference to FIG. 1. Figure 1 The source and the drain of one unit transistor CT described above.

[0049] Although Figure 2 and Figure 4 Although it is shown that the bottom surface of the first impurity region 124 and the bottom surface of the second impurity region 126 have the same height as that of the bottom surface of the first channel region 122, one of ordinary skill in the art will recognize that example embodiments are not limited thereto. For example, the bottom surface of the first impurity region 124 and the bottom surface of the second impurity region 126 can be formed higher than the bottom surface of the first channel region 122.

[0050] Each of the second semiconductor patterns 220 can include a third impurity region 224, a second channel region 222, and a fourth impurity region 226 sequentially arranged along the first direction X. For example, the second channel region 222 can be interposed between the third impurity region 224 and the fourth impurity region 226. The second channel region 222 can correspond to the channel of another unit transistor CT described above with reference to FIG. 1. Figure 1 The channel of another unit transistor CT described above.

[0051] The third impurity region 224 and the fourth impurity region 226 can be regions in which impurities are doped in the second semiconductor pattern 220. For example, the third impurity region 224 and the fourth impurity region 226 can include n-type impurities or p-type impurities. Accordingly, the third impurity region 224 and the fourth impurity region 226 can correspond to the source and the drain of another unit transistor CT described above with reference to FIG. 1. Figure 1 The source and the drain of another unit transistor CT described above.

[0052] The first wiring structure CS1 can be formed on the base 100. The first wiring structure CS1 can be connected to one end of the first stack structure SS1. In some embodiments, the first wiring structure CS1 can extend in the second direction Y to be connected to one end of the first stack structure SS1 and one end of the second stack structure SS2.

[0053] The first wiring structure CS1 can include a plurality of wiring patterns arranged vertically. For example, the first wiring structure CS1 can include a plurality of first wiring patterns 145 arranged along a third direction Z.

[0054] In some embodiments, the first wiring structure CS1 can include a plurality of third insulating patterns 140 and a plurality of first wiring patterns 145 alternately stacked on the base 100. That is, the plurality of first wiring patterns 145 can be spaced apart from each other by the third insulating patterns 140.

[0055] The plurality of third insulating patterns 140 can include an insulating material. For example, the plurality of third insulating patterns 140 can include silicon oxide and / or germanium oxide, but the present disclosure is not limited thereto. In an example embodiment, the plurality of third insulating patterns 140 can be formed at the same level as the plurality of first and second insulating patterns 110 and 210.

[0056] Each first wiring pattern 145 can extend in the second direction Y. Each first wiring pattern 145 can be connected to one end of each first semiconductor pattern 120 and one end of each second semiconductor pattern 220. For example, each first wiring pattern 145 can be connected to the first impurity region 124 and the third impurity region 224. Each first wiring pattern 145 can correspond to each bit line BL described above with reference to FIG. 1. Figure 1

[0057] Although Figure 2 and Figure 4 It is shown that a bottom surface of each first wiring pattern 145 has the same height as that of the bottom surface of the first semiconductor pattern 120, but those skilled in the art will appreciate that example embodiments are not limited thereto. For example, the bottom surface of the first wiring pattern 145 can be formed higher than the bottom surface of the first semiconductor pattern 120 or can be formed lower than the bottom surface of the first semiconductor pattern 120, as long as the first wiring pattern 145 is connected to the first impurity region 124.

[0058] The plurality of first wiring patterns 145 can include an electrically conductive material. For example, the plurality of first wiring patterns 145 can include at least one selected from the group consisting of a doped semiconductor material (doped silicon, doped germanium, etc.), a conductive metal nitride (titanium nitride, tantalum nitride, etc.), a metal (tungsten, titanium, tantalum, etc.), a metal-semiconductor compound (tungsten silicide, cobalt silicide, titanium silicide, etc.), and combinations thereof, although the present disclosure is not limited thereto.

[0059] In some embodiments, the silicide layers 130 and 230 can be interposed between the first semiconductor patterns 120 and the first wiring patterns 145 and between the second semiconductor patterns 220 and the first wiring patterns 145. For example, as Figure 2 and Figure 4 ​As illustrated in FIG. 1, the first silicide layer 132 can be formed between the first impurity region 124 and the first wiring pattern 145 to connect the first impurity region 124 and the first wiring pattern 145. The silicide layers 130 and 230 can be used to reduce contact resistance between the first semiconductor pattern 120 and the first wiring pattern 145 and contact resistance between the second semiconductor pattern 220 and the first wiring pattern 145.

[0060] The silicide layers 130 and 230 can include a metal semiconductor compound. For example, the silicide layers 130 and 230 can include at least one selected from the group consisting of tungsten silicide, cobalt silicide, titanium silicide, nickel silicide, platinum silicide, tantalum silicide, and combinations thereof, but example embodiments are not limited thereto.

[0061] The first conductive pattern 170 can be formed on a first side surface of the first stack structure SS1. The first conductive pattern 170 and the first stack structure SS1 can be arranged along the second direction Y. The first conductive pattern 170 can extend in the third direction Z. For example, as illustrated in FIG. 1, the first conductive pattern 170 can extend along side surfaces of the plurality of first insulating patterns 110 and side surfaces of the plurality of first semiconductor patterns 120. The first conductive pattern 170 can have, for example, a linear shape, a bar shape, or a column shape extending in the third direction Z, but is not limited thereto. Figure 3

[0062] The first conductive pattern 170 can cross the first channel region 122 of each of the first semiconductor patterns 120. For example, the first conductive pattern 170 can extend along a side surface of the first channel region 122 of each of the first semiconductor patterns 120.

[0063] The first conductive pattern 170 can correspond to one word line WL described above with reference to Figure 1 That is, the first conductive pattern 170 can be a gate electrode of a unit transistor including the first semiconductor pattern 120. For example, when the unit transistor including the first semiconductor pattern 120 is turned on, a first gate voltage V1 can be applied to the first conductive pattern 170.

[0064] The second conductive pattern 270 can be formed on one side surface of the second stack structure SS2. The second conductive pattern 270 and the second stack structure SS2 can be arranged along the second direction Y. The second conductive pattern 270 can extend in the third direction Z. For example, as illustrated in FIG. 2, the second conductive pattern 270 can extend along side surfaces of the plurality of second insulating patterns 210 and side surfaces of the plurality of second semiconductor patterns 220. The second conductive pattern 270 can have, for example, a linear shape, a bar shape, or a column shape extending in the third direction Z, but is not limited thereto. Figure 3

[0065] ​​The second conductive pattern 270 can cross the second channel region 222 of each of the second semiconductor patterns 220. For example, the second conductive pattern 270 can extend along a side surface of the second channel region 222 of each of the second semiconductor patterns 220.

[0066] The second conductive pattern 270 can correspond to another word line WL described above with reference to Figure 1 That is, the second conductive pattern 270 can be a gate electrode of a unit transistor including the second semiconductor pattern 220. For example, when the unit transistor including the second semiconductor pattern 220 is turned on, a second gate voltage V2 can be applied to the second conductive pattern 270. The second gate voltage V2 can be the same as or can be different from the first gate voltage V1.

[0067] In some embodiments, the first conductive pattern 170 and the second conductive pattern 270 can be stacked on each other in the second direction Y. For example, in a plan view, the first conductive pattern 170 and the second conductive pattern 270 can be arranged in a row along the second direction Y.

[0068] The first conductive pattern 170 and the second conductive pattern 270 can include a conductive material. The conductive material of the first conductive pattern 170 and the second conductive pattern 270 can be the same conductive material as that of the first wiring pattern 145, or can be a different conductive material. For example, the first conductive pattern 170 and the second conductive pattern 270 can include at least one selected from the group consisting of a doped semiconductor material, a conductive metal nitride, a metal, a metal semiconductor compound, and a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the first conductive pattern 170 and the second conductive pattern 270 can be formed at the same level.

[0069] The first ferroelectric layer 160 can be disposed between the first stack structure SS1 and the first conductive pattern 170. That is, the first ferroelectric layer 160 can be formed on one side surface of the first stack structure SS1. The first ferroelectric layer 160 can extend along the third direction Z. For example, as shown in FIG. 1B, the first ferroelectric layer 160 can extend along the side surfaces of the plurality of first insulating patterns 110 and the side surfaces of the plurality of first semiconductor patterns 120. Figure 3

[0070] The second ferroelectric layer 260 can be disposed between the second stack structure SS2 and the second conductive pattern 270. That is, the second ferroelectric layer 260 can be formed on one side surface of the second stack structure SS2. The second ferroelectric layer 260 can extend along the third direction Z. For example, as shown in FIG. 1D, the second ferroelectric layer 260 can extend along the side surfaces of the plurality of second insulating patterns 210 and the side surfaces of the plurality of second semiconductor patterns 220. Figure 3 ​​

[0071] In some embodiments, the first ferroelectric layer 160 and the second ferroelectric layer 260 may be stacked on top of each other in the second direction Y. For example, in a plan view, the first ferroelectric layer 160 and the second ferroelectric layer 260 may be arranged in a row along the second direction Y.

[0072] In some embodiments, a portion of the first ferroelectric layer 160 may be disposed between the substrate 100 and the first conductive pattern 170, and a portion of the second ferroelectric layer 260 may be disposed between the substrate 100 and the second conductive pattern 270. For example, as Figure 2 and Figure 3 As shown, the first ferroelectric layer 160 may extend along the upper surface of the substrate 100 and the side surface of the first stacked structure SS1, and the second ferroelectric layer 260 may extend along the upper surface of the substrate 100 and the side surface of the second stacked structure SS2.

[0073] Additionally, in some embodiments, such as Figure 2 As shown, the width of the first ferroelectric layer 160 may be the same as the width of the first conductive pattern 170, and the width of the second ferroelectric layer 260 may be equal to the width of the second conductive pattern 270. As used herein, the term "width" refers to the width in the first direction X. Furthermore, the term "same" as used herein means not only identical but also includes minor differences that may occur due to process allowances, etc.

[0074] The shapes of the first ferroelectric layer 160 and the second ferroelectric layer 260 can be attributed to the characteristics of the process used to form the first ferroelectric layer 160 and the second ferroelectric layer 260. For example, the ferroelectric layer can be formed to conformally extend along the substrate 100, the first stacked structure SS1, and the second stacked structure SS2. Subsequently, a conductive layer can be formed on the ferroelectric layer. Then, by patterning the conductive layer and the ferroelectric layer, a first conductive pattern 170 extending in the third direction Z and the first ferroelectric layer 160 can be formed on the side surface of the first stacked structure SS1. In addition, a second conductive pattern 270 extending in the third direction Z and the second ferroelectric layer 260 can be formed on the side surface of the second stacked structure SS2.

[0075] Each of the first ferroelectric layer 160 and the second ferroelectric layer 260 may include a ferroelectric material. For example, the first ferroelectric layer 160 and the second ferroelectric layer 260 may include ferroelectrics such as barium titanate (BaTiO3), lead zirconate titanate (PbZrTiO3, PZT), strontium bismuth tantalate (SrBi2Ta2O9, SBT), bismuth ferrite (BiFeO3, BFO), and hafnium oxide (HfO2), but this disclosure is not limited thereto. In some embodiments, the first ferroelectric layer 160 and the second ferroelectric layer 260 may be formed at the same level.

[0076] In some embodiments, the other end of the first stack structure SS1 can be connected to the second wiring pattern 155. For example, the first stack structure SS1 can be disposed between the first wiring structure CS1 and the second wiring pattern 155 to be connected to the first wiring structure CS1 and the second wiring pattern 155.

[0077] The second wiring pattern 155 can extend in the third direction Z to be connected to the other end of each of the first semiconductor patterns 120. For example, the second wiring pattern 155 can be connected to the second impurity region 126. The second wiring pattern 155 can correspond to one wire CL described above with reference to FIG. 1. Figure 1

[0078] In some embodiments, the other end of the second stack structure SS2 can be connected to the third wiring pattern 255. For example, the second stack structure SS2 can be disposed between the first wiring structure CS1 and the third wiring pattern 255 to be connected to the first wiring structure CS1 and the third wiring pattern 255.

[0079] The third wiring pattern 255 can extend in the third direction Z to be connected to the other end of each of the second semiconductor patterns 220. For example, the third wiring pattern 255 can be connected to the fourth impurity region 226. The third wiring pattern 255 can correspond to another wire CL described above with reference to FIG. 1. Figure 1

[0080] The second wiring pattern 155 and the third wiring pattern 255 can include an electrically conductive material. For example, the second wiring pattern 155 and the third wiring pattern 255 can include at least one selected from the group consisting of a doped semiconductor material, an electrically conductive metal nitride, a metal, a metal semiconductor compound, and combinations thereof, but the present disclosure is not limited thereto. In some embodiments, the second wiring pattern 155 and the third wiring pattern 255 can be formed at the same level.

[0081] In some embodiments, the silicide layers 130 and 230 can be disposed between the first semiconductor patterns 120 and the second wiring pattern 155 and between the second semiconductor patterns 220 and the third wiring pattern 255. For example, as shown in FIG. 2, the second silicide layer 134 can be formed between the second impurity region 126 and the second wiring pattern 155 to connect the second impurity region 126 to the second wiring pattern 155. Figure 4 The silicide layers 130 and 230 can be used to reduce contact resistance between the first semiconductor patterns 120 and the second wiring pattern 155 and contact resistance between the second semiconductor patterns 220 and the third wiring pattern 255.

[0082] ​​The interlayer insulating layer 180 can be formed on the substrate 100. Also, the interlayer insulating layer 180 can be formed to cover the first stack structure SS1, the second stack structure SS2, the first wiring structure CS1, the first conductive pattern 170, the first ferroelectric layer 160, the second conductive pattern 270, and the second ferroelectric layer 260.

[0083] The interlayer insulating layer 180 can include an insulating material. For example, the interlayer insulating layer 180 can include at least one of silicon oxide, silicon oxynitride, silicon nitride, and a low-k material having a dielectric constant lower than that of silicon oxide, but is not limited thereto.

[0084] Recently, as the design rule of a semiconductor device rapidly decreases, there is a limitation in forming a fine pattern due to a resolution limit of a process for forming a pattern required to implement the semiconductor device.

[0085] However, the semiconductor device according to some embodiments can implement a ferroelectric field effect transistor (FeFET) arranged in three dimensions, thereby improving integration and performance.

[0086] Figure 5 is a circuit diagram illustrating a semiconductor device according to some embodiments. Figure 6 is a schematic perspective view illustrating a semiconductor device according to some embodiments. Figure 7 is a cross-sectional view taken along line C-C of Figure 6 For simplicity of description, descriptions repeated with reference to the description of Figures 1 to 4 will be briefly given or omitted.

[0087] Referring to Figure 5 , in the semiconductor device according to some embodiments, one wire CL can correspond to one bit line BL.

[0088] For example, as illustrated, a plurality of cell transistors CT sharing one bit line BL can share one wire CL. In some embodiments, each wire CL can extend in a direction crossing each word line WL.

[0089] Referring to Figure 6 and Figure 7 , the semiconductor device described above with reference to Figure 5 may be disposed on the substrate 100. Specifically, in the semiconductor device according to some embodiments, the other end of the first stack structure SS1 can be connected to the second wiring structure CS2.

[0090] A second wiring structure CS2 can be formed on the base 100. The second wiring structure CS2 can be connected to the other end of the first stack structure SS1. In some embodiments, the second wiring structure CS2 can extend in the second direction Y to be connected to the other end of the first stack structure SS1 and the other end of the second stack structure SS2.

[0091] The second wiring structure CS2 can include a plurality of wiring patterns arranged vertically. For example, the second wiring structure CS2 can include a plurality of second wiring patterns 155 arranged along the third direction Z.

[0092] In some embodiments, the second wiring structure CS2 can include a plurality of fourth insulating patterns 150 and a plurality of second wiring patterns 155 alternately stacked on the base 100. That is, the plurality of second wiring patterns 155 can be spaced apart from each other by the fourth insulating patterns 150.

[0093] The plurality of fourth insulating patterns 150 can include an insulating material. For example, the plurality of fourth insulating patterns 150 can include silicon oxide, but are not limited thereto.

[0094] Each second wiring pattern 155 can extend in the second direction Y. Each second wiring pattern 155 can be connected to the other end of each first semiconductor pattern 120 and the other end of each second semiconductor pattern 220. For example, each second wiring pattern 155 can be connected to the second impurity region 126 and the fourth impurity region 226. Each second wiring pattern 155 can correspond to each wiring line CL described above with reference to Figure 5 FIG. 1.

[0095] Although Figure 7 Although it is illustrated that the bottom surface of each second wiring pattern 155 has the same height as that of the bottom surface of the first semiconductor pattern 120, one of ordinary skill in the art will recognize that example embodiments are not limited thereto. For example, the bottom surface of the second wiring pattern 155 can be formed higher than the bottom surface of the first semiconductor pattern 120 or can be formed lower than the bottom surface of the first semiconductor pattern 120, as long as the second wiring pattern 155 is connected to the second impurity region 126.

[0096] Figure 8 FIG. 1 is a circuit diagram illustrating a semiconductor device according to some embodiments. Figure 9 FIG. 1 is a circuit diagram illustrating a semiconductor device according to some embodiments. Figure 10 is a cross-sectional view taken along line D-D of FIG. 1. For simplicity of description, descriptions that are briefly given or omitted with reference to the descriptions of FIGS. 1 through 4 will not be given or described. Figure 9 is a circuit diagram illustrating a semiconductor device according to some embodiments. Figures 1 to 4 FIG. 1 is a circuit diagram illustrating a semiconductor device according to some embodiments.

[0097] FIG. 1 is a circuit diagram illustrating a semiconductor device according to some embodiments. Figure 8In the semiconductor device according to some embodiments, each of the cell transistors CT can be connected to an information storage element DS.

[0098] For example, the drain of each of the cell transistors CT can be connected to the information storage element DS. The information storage element DS can be, for example, a capacitor. The information storage element DS can be controlled by each of the cell transistors CT to store data.

[0099] Referring to Figure 9 and Figure 10 the semiconductor device described above with reference to Figure 8 may be provided on the substrate 100. Specifically, in the semiconductor device according to some embodiments, the other end of the first stack structure SS1 can be connected to the first capacitor structure 190.

[0100] For example, the first stack structure SS1 can be interposed between the first wiring structure CS1 and the first capacitor structure 190 to be connected to the first wiring structure CS1 and the first capacitor structure 190.

[0101] The first capacitor structure 190 can include a first electrode 192, a capacitor dielectric layer 194, and a second electrode 196. The first capacitor structure 190 can store electric charges in the capacitor dielectric layer 194 using a potential difference generated between the first electrode 192 and the second electrode 196.

[0102] The first electrode 192 can be connected to the second impurity region 126 of each of the first semiconductor patterns 120. In some embodiments, a second silicide layer 134 can be interposed between the second impurity region 126 and the first electrode 192. For example, the first electrode 192 can have a cylindrical shape, but is not limited thereto.

[0103] The capacitor dielectric layer 194 can be formed on the first electrode 192. For example, the capacitor dielectric layer 194 can extend along the contour of the first electrode 192.

[0104] The second electrode 196 can be formed on the capacitor dielectric layer 194. The second electrode 196 can be spaced apart from the first electrode 192 by the capacitor dielectric layer 194. That is, the capacitor dielectric layer 194 can be interposed between the first electrode 192 and the second electrode 196.

[0105] The first electrode 192 and the second electrode 196 can include, for example, a conductive material, but are not limited to doped polysilicon, a metal, a metal-semiconductor compound, a metal nitride, and / or a combination thereof. In addition, the capacitor dielectric layer 194 can include, for example, silicon oxide or a high-k material having a dielectric constant higher than that of silicon oxide, but is not limited thereto.

[0106] In some embodiments, the other end of the second stack structure SS2 can be connected to the second capacitor structure 290. For example, the second stack structure SS2 can be disposed between the first wiring structure CS1 and the second capacitor structure 290 to be connected to the first wiring structure CS1 and the second capacitor structure 290.

[0107] Since the second capacitor structure 290 can be similar to the first capacitor structure 190, detailed descriptions thereof will be omitted below.

[0108] Figure 11 is a schematic perspective view illustrating a semiconductor device according to some embodiments. Figure 12 is a cross-sectional view taken along line E-E of Figure 11 For simplicity of description, descriptions that are briefly given or omitted will be repeated with reference to the descriptions of Figures 1 to 4

[0109] With reference to Figure 11 and Figure 12 , the semiconductor device according to some embodiments can further include a third conductive pattern 175.

[0110] The third conductive pattern 175 can be formed on the other side surface of the first stack structure SS1. The third conductive pattern 175 and the first stack structure SS1 can be arranged along the second direction Y. That is, the first stack structure SS1 can be disposed between the first conductive pattern 170 and the third conductive pattern 175.

[0111] The third conductive pattern 175 can extend in the third direction Z. For example, the third conductive pattern 175 can extend along the side surfaces of the plurality of first insulating patterns 110 and the side surfaces of the plurality of first semiconductor patterns 120. The third conductive pattern 175 can have, for example, a linear shape, a bar shape, or a column shape extending in the third direction Z, but is not limited thereto.

[0112] The third conductive pattern 175 can cross the first channel region 122 of each of the first semiconductor patterns 120. For example, the third conductive pattern 175 can extend along the side surface of the first channel region 122 of each of the first semiconductor patterns 120.

[0113] The semiconductor device according to some embodiments can further include a fourth conductive pattern 275.

[0114] The fourth conductive pattern 275 can be formed on the other side surface of the second stack structure SS2. The fourth conductive pattern 275 and the second stack structure SS2 can be arranged along the second direction Y. That is, the second stack structure SS2 can be disposed between the second conductive pattern 270 and the fourth conductive pattern 275.

[0115] ​The fourth conductive pattern 275 can extend in the third direction Z. For example, the fourth conductive pattern 275 can extend along side surfaces of the plurality of second insulating patterns 210 and side surfaces of the plurality of second semiconductor patterns 220. The fourth conductive pattern 275 can have, for example, a linear shape, a bar shape, or a column shape extending in the third direction Z, but is not limited thereto.

[0116] The fourth conductive pattern 275 can cross the second channel region 222 of each of the second semiconductor patterns 220. For example, the fourth conductive pattern 275 can extend along a side surface of the second channel region 222 of each of the second semiconductor patterns 220.

[0117] In some embodiments, the first to fourth conductive patterns 170, 270, 175, and 275 can be stacked on each other in the second direction Y. For example, in a plan view, the first to fourth conductive patterns 170, 270, 175, and 275 can be arranged in a row along the second direction Y.

[0118] The third and fourth conductive patterns 175 and 275 can include a conductive material. For example, the third and fourth conductive patterns 175 and 275 can include at least one selected from the group consisting of a doped semiconductor material, a conductive metal nitride, a metal, a metal semiconductor compound, and a combination thereof, but the disclosure is not limited thereto. In some embodiments, the first to fourth conductive patterns 170, 270, 175, and 275 can be formed at the same level.

[0119] In some embodiments, the third conductive pattern 175 can be in contact with a side surface of the first channel region 122 of each of the first semiconductor patterns 120, and the fourth conductive pattern 275 can be in contact with a side surface of the second channel region 222 of each of the second semiconductor patterns 220. Accordingly, the third conductive pattern 175 can be electrically connected to each of the first semiconductor patterns 120, and the fourth conductive pattern 275 can be electrically connected to each of the second semiconductor patterns 220. The third conductive pattern 175 can serve as a body contact of a unit transistor including the first semiconductor pattern 120, and the fourth conductive pattern 275 can serve as a body contact of a unit transistor including the second semiconductor pattern 220. For example, a floating body effect can not occur in the first and second semiconductor patterns 120 and 220.

[0120] Figure 13 FIG. 1 is a schematic perspective view illustrating a semiconductor device according to some embodiments. Figures 14 to 17 is a cross-sectional view taken along a line F-F of Figure 13 for simplicity of description, descriptions repeated with reference to the descriptions of Figures 1 to 4 , Figure 11 and Figure 12 will be briefly given or omitted.

[0121] Referring to Figure 13 and Figure 14 According to some embodiments, the semiconductor device can further include a third ferroelectric layer 165.

[0122] The third ferroelectric layer 165 can be disposed between the first stack structure SS1 and a third conductive pattern 175. That is, the third ferroelectric layer 165 can be formed on the other side surface of the first stack structure SS1. The third ferroelectric layer 165 can extend along the third direction Z. For example, the third ferroelectric layer 165 can extend along the side surfaces of the plurality of first insulating patterns 110 and the side surfaces of the plurality of first semiconductor patterns 120.

[0123] According to some embodiments, the semiconductor device can further include a fourth ferroelectric layer 265.

[0124] The fourth ferroelectric layer 265 can be disposed between the second stack structure SS2 and a fourth conductive pattern 275. That is, the fourth ferroelectric layer 265 can be formed on the other side surface of the second stack structure SS2. The fourth ferroelectric layer 265 can extend along the third direction Z. For example, the fourth ferroelectric layer 265 can extend along the side surfaces of the plurality of second insulating patterns 210 and the side surfaces of the plurality of second semiconductor patterns 220.

[0125] Since the shape of the third ferroelectric layer 165 and the shape of the fourth ferroelectric layer 265 can be similar to the shape of the first ferroelectric layer 160 and the shape of the second ferroelectric layer 260, detailed descriptions thereof will be omitted below.

[0126] In some embodiments, the first to fourth ferroelectric layers 160, 260, 165, and 265 can be stacked on each other in the second direction Y. For example, in a plan view, the first to fourth ferroelectric layers 160, 260, 165, and 265 can be arranged in a row along the second direction Y.

[0127] Each of the third ferroelectric layer 165 and the fourth ferroelectric layer 265 can include a ferroelectric material. For example, the third ferroelectric layer 165 and the fourth ferroelectric layer 265 can include a ferroelectric such as barium titanate (BaTiO3), lead zirconate titanate (PbZrTiO3, PZT), strontium bismuth tantalate (SrBi2Ta2O9, SBT), bismuth ferrite (BiFeO3, BFO), and hafnium oxide (HfO2), but the present disclosure is not limited thereto. In some embodiments, the first to fourth ferroelectric layers 160, 260, 165, and 265 can be formed at the same level.

[0128] In some embodiments, the first conductive pattern 170 and the third conductive pattern 175 can be gate electrodes of a unit transistor including the first semiconductor pattern 120. For example, when the unit transistor including the first semiconductor pattern 120 is turned on, a first gate voltage V1 can be applied to the first conductive pattern 170 and the third conductive pattern 175.

[0129] In some embodiments, the second conductive pattern 270 and the fourth conductive pattern 275 can be gate electrodes of a unit transistor including the second semiconductor pattern 220. For example, when the unit transistor including the second semiconductor pattern 220 is turned on, a second gate voltage V2 can be applied to the second conductive pattern 270 and the fourth conductive pattern 275.

[0130] Accordingly, the semiconductor device according to some embodiments can implement a multi-gate transistor to improve a current control capability.

[0131] Referring to Figure 13 and Figure 15 In the semiconductor device according to some embodiments, different gate voltages can be applied to the first conductive pattern 170 and the third conductive pattern 175.

[0132] For example, when the unit transistor including the first semiconductor pattern 120 is turned on, a first gate voltage V1 can be applied to the first conductive pattern 170. In this case, a third gate voltage V3 different from the first gate voltage V1 can be applied to the third conductive pattern 175.

[0133] Further, in the semiconductor device according to some embodiments, different gate voltages can be applied to the second conductive pattern 270 and the fourth conductive pattern 275.

[0134] For example, when the unit transistor including the second semiconductor pattern 220 is turned on, a second gate voltage V2 can be applied to the second conductive pattern 270, and a fourth gate voltage V4 different from the second gate voltage V2 can be applied to the fourth conductive pattern 275.

[0135] Threshold voltage V th may vary according to a voltage applied to a gate electrode. That is, the threshold voltage of the unit transistor including the first semiconductor pattern 120 can be adjusted according to the first gate voltage V1 and the third gate voltage V3. Further, the threshold voltage of the unit transistor including the second semiconductor pattern 220 can be adjusted according to the second gate voltage V2 and the fourth gate voltage V4.

[0136] Referring to Figure 13 and Figure 16 In the semiconductor device according to some embodiments, the first ferroelectric layer 160 and the third ferroelectric layer 165 can include different materials.

[0137] For example, the first ferroelectric layer 160 can include a first ferroelectric material, and the third ferroelectric layer 165 can include a third ferroelectric material different from the first ferroelectric material.

[0138] In the semiconductor device according to some embodiments, the second ferroelectric layer 260 and the fourth ferroelectric layer 265 can include different materials.

[0139] For example, the second ferroelectric layer 260 can include a second ferroelectric material, and the fourth ferroelectric layer 265 can include a fourth ferroelectric material different from the second ferroelectric material.

[0140] The threshold voltage of the FeFET can vary depending on the type of the ferroelectric layer included in the ferroelectric field effect transistor. That is, the threshold voltage of the unit transistor including the first semiconductor pattern 120 can be adjusted depending on the materials included in the first ferroelectric layer 160 and the third ferroelectric layer 165. Also, the threshold voltage of the unit transistor including the second semiconductor pattern 220 can be adjusted depending on the materials included in the second ferroelectric layer 260 and the fourth ferroelectric layer 265.

[0141] Referring to Figure 13 and Figure 17 In the semiconductor device according to some embodiments, the first ferroelectric layer 160 and the third ferroelectric layer 165 can have different thicknesses.

[0142] For example, the first ferroelectric layer 160 can have a first thickness TH1, and the third ferroelectric layer 165 can have a third thickness TH3 different from the first thickness TH1. Although it is shown that the third thickness TH3 is greater than the first thickness TH1, those skilled in the art will recognize that example embodiments are not limited thereto. For example, the third thickness TH3 can be less than the first thickness TH1.

[0143] In the semiconductor device according to some embodiments, the second ferroelectric layer 260 and the fourth ferroelectric layer 265 can have different thicknesses.

[0144] For example, the second ferroelectric layer 260 can have a second thickness TH2, and the fourth ferroelectric layer 265 can have a fourth thickness TH4 different from the second thickness TH2. Although it is shown that the fourth thickness TH4 is greater than the second thickness TH2, those skilled in the art will recognize that example embodiments are not limited thereto. For example, the fourth thickness TH4 can be less than the second thickness TH2.

[0145] The threshold voltage of the FeFET can vary according to the thickness of the ferroelectric layer included in the ferroelectric field effect transistor. That is, the threshold voltage of the unit transistor including the first semiconductor pattern 120 can be adjusted according to the thickness of the first ferroelectric layer 160 and the thickness of the third ferroelectric layer 165. In addition, the threshold voltage of the unit transistor including the second semiconductor pattern 220 can be adjusted according to the thickness of the second ferroelectric layer 260 and the thickness of the fourth ferroelectric layer 265.

[0146] Figure 18 is a schematic perspective view illustrating a semiconductor device according to some embodiments. Figure 19 and Figure 20 are various cross-sectional views taken along lines G-G of Figure 18 For simplicity of description, descriptions that are repeated with reference to the descriptions of Figures 1 to 4 and Figures 13 to 17 will be briefly given or omitted.

[0147] With reference to Figure 18 and Figure 19 , the semiconductor device according to some embodiments can further include first to fourth gate dielectric layers 162, 262, 167, and 267.

[0148] The first gate dielectric layer 162 can be disposed between the first stack structure SS1 and the first ferroelectric layer 160. The second gate dielectric layer 262 can be disposed between the second stack structure SS2 and the second ferroelectric layer 260. The first gate dielectric layer 162 and the second gate dielectric layer 262 can extend along the third direction Z. For example, the first gate dielectric layer 162 can extend along the side surfaces of the plurality of first insulating patterns 110 and the side surfaces of the plurality of first semiconductor patterns 120. Also, for example, the second gate dielectric layer 262 can extend along the side surfaces of the plurality of second insulating patterns 210 and the side surfaces of the plurality of second semiconductor patterns 220.

[0149] The third gate dielectric layer 167 can be disposed between the first stack structure SS1 and the third ferroelectric layer 165. The fourth gate dielectric layer 267 can be disposed between the second stack structure SS2 and the fourth ferroelectric layer 265. The third gate dielectric layer 167 and the fourth gate dielectric layer 267 can extend along the third direction Z. For example, the third gate dielectric layer 167 can extend along the side surfaces of the plurality of first insulating patterns 110 and the side surfaces of the plurality of first semiconductor patterns 120, and the fourth gate dielectric layer 267 can extend along the side surfaces of the plurality of second insulating patterns 210 and the side surfaces of the plurality of second semiconductor patterns 220.

[0150] In some embodiments, the first to fourth gate dielectric layers 162, 262, 167, and 267 can be stacked on top of each other in the second direction Y. For example, in a plan view, the first to fourth gate dielectric layers 162, 262, 167, and 267 can be arranged in a row along the second direction Y.

[0151] In some embodiments, a portion of the first gate dielectric layer 162 can be disposed between the substrate 100 and the first ferroelectric layer 160, and a portion of the second gate dielectric layer 262 can be disposed between the substrate 100 and the second ferroelectric layer 260. For example, the first ferroelectric layer 160 can extend along the contour of the first gate dielectric layer 162, and the second ferroelectric layer 260 can extend along the contour of the second gate dielectric layer 262.

[0152] Further, in some embodiments, a portion of the third gate dielectric layer 167 can be disposed between the substrate 100 and the third ferroelectric layer 165, and a portion of the fourth gate dielectric layer 267 can be disposed between the substrate 100 and the fourth ferroelectric layer 265. For example, the third ferroelectric layer 165 can extend along the contour of the third gate dielectric layer 167, and the fourth ferroelectric layer 265 can extend along the contour of the fourth gate dielectric layer 267.

[0153] In some embodiments, the width of the first gate dielectric layer 162 can be the same as the width of the first ferroelectric layer 160, and the width of the second gate dielectric layer 262 can be the same as the width of the second ferroelectric layer 260. Further, in some embodiments, the width of the third gate dielectric layer 167 can be the same as the width of the third ferroelectric layer 165, and the width of the fourth gate dielectric layer 267 can be the same as the width of the fourth ferroelectric layer 265. The term "width" as used herein refers to the width in the first direction X.

[0154] The first to fourth gate dielectric layers 162, 262, 167, and 267 can include, for example, at least one of silicon oxide, silicon oxynitride, silicon nitride, and a high-k material having a dielectric constant higher than that of silicon oxide, but the present disclosure is not limited thereto. Alternatively, for example, the first to fourth gate dielectric layers 162, 262, 167, and 267 can include a ferroelectric.

[0155] Referring to Figure 18 and Figure 20 In the semiconductor device according to some embodiments, the interlayer insulating layer 180 can be multi-layered. For example, the interlayer insulating layer 180 can include a first insulating layer 182 and a second insulating layer 184.

[0156] In some embodiments, the first insulating layer 182 can extend conformally along the upper surface of the substrate 100, the side surface of the first stack structure SS1, and the side surface of the second stack structure SS2. The second insulating layer 184 can be formed on the first insulating layer 182. In some embodiments, the second insulating layer 184 can be a fill insulating layer that fills spaces in the first insulating layer 182.

[0157] The first insulating layer 182 and the second insulating layer 184 can include the same material or can include different materials.

[0158] Figure 21 is a schematic perspective view illustrating a semiconductor device according to some embodiments. For simplifying the description, the description that is repetitive with the description with reference to Figures 1 to 4 and Figures 13 to 17 will be briefly given or omitted.

[0159] With reference to Figure 21 , in the semiconductor device according to some embodiments, the other end of the first stack structure SS1 and the other end of the second stack structure SS2 can be connected to the second wiring structure CS2.

[0160] Since the second wiring structure CS2 is substantially the same as the second wiring structure CS2 described above with reference to Figure 6 and Figure 7 , detailed description thereof will be omitted below.

[0161] Figure 22 is a schematic perspective view illustrating a semiconductor device according to some embodiments. For simplifying the description, the description that is repetitive with the description with reference to Figures 1 to 4 and Figures 13 to 17 will be briefly given or omitted.

[0162] With reference to Figure 22 , in the semiconductor device according to some embodiments, the other end of the first stack structure SS1 can be connected to the first capacitor structure 190, and the other end of the second stack structure SS2 can be connected to the second capacitor structure 290.

[0163] Since the first capacitor structure 190 and the second capacitor structure 290 are substantially the same as described above with reference to Figure 9 and Figure 10 , detailed description thereof will be omitted.

[0164] While the present concepts have been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details can be made therein without departing from the spirit and scope of the present concepts as defined by the appended claims. Therefore, it is desired to be understood that the present embodiments are to be considered only as illustrative and not restrictive, and that reference will be made to the appended claims to indicate the scope of the invention.

Claims

1. A semiconductor device comprising: a first stack structure including a plurality of first insulating patterns and a plurality of first semiconductor patterns alternately stacked on a base, the first stack structure extending in a first direction, each of the plurality of first semiconductor patterns including a first impurity region, a first channel region, and a second impurity region arranged in order along the first direction, the first direction being parallel to an upper surface of the base; a first conductive pattern on a first side surface of the first stack structure, the first conductive pattern extending in a second direction, the second direction intersecting the upper surface of the base; and a first ferroelectric layer between the first stack structure and the first conductive pattern, the first ferroelectric layer extending in the second direction, wherein a portion of the first ferroelectric layer is interposed between the base and the first conductive pattern. The first ferroelectric layer extends along a first side surface of the first channel region of the plurality of first semiconductor patterns.

2. The semiconductor device according to claim 1, wherein A width of the first conductive pattern in the first direction and a width of the first ferroelectric layer in the first direction are equal to each other.

3. The semiconductor device according to claim 1, wherein 4. The semiconductor device according to claim 1, further comprising a second conductive pattern on a second side surface of the first stack structure, the second conductive pattern extending in the second direction.

5. The semiconductor device according to claim 4, further comprising a second ferroelectric layer between the first stack structure and the second conductive pattern, the second ferroelectric layer extending in the second direction. The second conductive pattern is in contact with the first channel region of the plurality of first semiconductor patterns.

6. The semiconductor device according to claim 4, wherein 7. The semiconductor device according to claim 1, further comprising a gate dielectric layer between the first stack structure and the first ferroelectric layer, the gate dielectric layer extending in the second direction. a first wiring structure including a plurality of second insulating patterns and a plurality of first wiring patterns alternately stacked on the base, the first wiring structure extending in a third direction parallel to the upper surface of the base and intersecting the first direction, 8. The semiconductor device according to claim 1, further comprising: wherein each of the plurality of first wiring patterns is connected to the first impurity region of each of the plurality of first semiconductor patterns.

9. The semiconductor device according to claim 8, further comprising a capacitor structure connected to the second impurity region of the plurality of first semiconductor patterns.

10. A semiconductor device comprising: a first semiconductor pattern on a base, the first semiconductor pattern including a first impurity region, a first channel region, and a second impurity region arranged in order in a first direction, the first direction being parallel to an upper surface of the base; a first gate electrode on a first side surface of the first channel region and a second gate electrode on a second side surface of the first channel region, the first gate electrode and the second gate electrode extending in a second direction, the second direction intersecting the upper surface of the base; a first ferroelectric layer between the first channel region and the first gate electrode, the first ferroelectric layer extending in the second direction; and a second ferroelectric layer between the first channel region and the second gate electrode, the second ferroelectric layer extending in the second direction, wherein a portion of the first ferroelectric layer is interposed between the base and the first conductive pattern. ​ wherein a portion of the first ferroelectric layer is disposed between the substrate and the first gate electrode, and a portion of the second ferroelectric layer is disposed between the substrate and the second gate electrode.

11. The semiconductor device according to claim 10, wherein The first gate electrode is configured to be applied with a first gate voltage, and the second gate electrode is configured to be applied with a second gate voltage different from the first gate voltage.

12. The semiconductor device according to claim 10, wherein The first ferroelectric layer includes a first ferroelectric material, and the second ferroelectric layer includes a second ferroelectric material different from the first ferroelectric material.

13. The semiconductor device according to claim 10, wherein The first ferroelectric layer has a first thickness, and the second ferroelectric layer has a second thickness different from the first thickness.

14. The semiconductor device according to claim 10, further comprising: a second semiconductor pattern on the substrate, the second semiconductor pattern including a third impurity region, a second channel region, and a fourth impurity region arranged sequentially along a first direction; a third gate electrode on a first side surface of the second channel region and a fourth gate electrode on a second side surface of the second channel region, the third gate electrode and the fourth gate electrode extending in a second direction; a third ferroelectric layer between the second channel region and the third gate electrode, the third ferroelectric layer extending in the second direction; and a fourth ferroelectric layer between the second channel region and the fourth gate electrode, the fourth ferroelectric layer extending in the second direction. The first to fourth gate electrodes are stacked on each other in a third direction parallel to the upper surface of the substrate and intersecting the first direction.

15. The semiconductor device according to claim 14, wherein 16. A semiconductor device comprising: a first stacked structure including a plurality of first insulating patterns and a plurality of first semiconductor patterns alternately stacked on a substrate, the first stacked structure extending in a first direction, each of the plurality of first semiconductor patterns including a first impurity region, a channel region, and a second impurity region arranged sequentially along the first direction, the first direction being parallel to an upper surface of the substrate; a plurality of first wiring patterns connected to first ends of the plurality of first semiconductor patterns, respectively, the plurality of first wiring patterns extending in a second direction parallel to the upper surface of the substrate and intersecting the first direction; a second wiring pattern connected to second ends of the plurality of first semiconductor patterns; a first gate electrode on a first side surface of the first stacked structure between the plurality of first wiring patterns and the second wiring pattern, the first gate electrode extending in a third direction intersecting the upper surface of the substrate; and a first ferroelectric layer between the first stacked structure and the first gate electrode, the first ferroelectric layer extending in the third direction along first side surfaces of the channel regions of the plurality of first semiconductor patterns, wherein a portion of the first ferroelectric layer is disposed between the substrate and the first gate electrode.

17. The semiconductor device according to claim 16, further comprising: a first silicide layer connecting the first impurity regions of the plurality of first semiconductor patterns to the plurality of first wiring patterns; and a second silicide layer connecting the second impurity regions of the plurality of first semiconductor patterns to the second wiring pattern.

18. The semiconductor device according to claim 16, further comprising: ​ ​ ​ a second stack structure including a plurality of second insulating patterns and a plurality of second semiconductor patterns alternately stacked on a base, the second stack structure being spaced apart from the first stack structure in a second direction and extending in a first direction; a second gate electrode on a first side surface of the second stack structure, the second gate electrode extending in a third direction; and a second ferroelectric layer between the second stack structure and the second gate electrode, the second ferroelectric layer extending in the third direction. each of the plurality of first wiring patterns is connected to a first end of each of the plurality of first semiconductor patterns and a first end of each of the plurality of second semiconductor patterns.

19. The semiconductor device according to claim 18, wherein a second wiring pattern extending in the third direction and connected to a second end of each of the plurality of first semiconductor patterns.

20. The semiconductor device according to claim 19, wherein a second stack structure including a plurality of second insulating patterns and a plurality of second semiconductor patterns alternately stacked on a base, the second stack structure being spaced apart from the first stack structure in a second direction and extending in a first direction; a second gate electrode on a first side surface of the second stack structure, the second gate electrode extending in a third direction; and a second ferroelectric layer between the second stack structure and the second gate electrode, the second ferroelectric layer extending in the third direction. each of the plurality of first wiring patterns is connected to a first end of each of the plurality of first semiconductor patterns and a first end of each of the plurality of second semiconductor patterns. a second wiring pattern extending in the third direction and connected to a second end of each of the plurality of first semiconductor patterns.

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