Semiconductor device and method of manufacturing the same

Abstract

Embodiments of the present disclosure relate to a semiconductor device and a manufacturing method thereof. A first amorphous film containing hafnium, oxygen, and a first element is formed, and a plurality of crystal grains containing a second element different from any of the hafnium, the oxygen, and the first element is formed on the first amorphous film. An insulating film containing a third element different from any of the hafnium and the second element is formed over the plurality of crystal grains and the first amorphous film, thereby forming the plurality of crystal grains containing the second element and the third element. A second amorphous film containing the same material as that of the first amorphous film is formed on the plurality of crystal grains and the first amorphous film. The first amorphous film and the second amorphous film are crystallized by performing a heat treatment, to form an orthorhombic first ferroelectric film and an orthorhombic second ferroelectric film, respectively.

Description

[0001] Cross-references to related applications

[0002] The disclosure of Japanese Patent Application No. 2019-136577, filed on July 25, 2019 (including the specification, drawings and abstract), is incorporated herein by reference in its entirety. Background Technology

[0003] The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device, and more particularly, to a technique for a semiconductor device and a method for manufacturing the semiconductor device, the semiconductor device being used as a memory device using a ferroelectric film.

[0004] In recent years, ferroelectric memory cells using ferroelectric layers have been developed as semiconductor memory devices that operate at low voltages. Ferroelectric memory cells are non-volatile memory cells that change the write and erase states of information by controlling the polarization direction of the ferroelectric layer.

[0005] The disclosed technologies are listed below.

[0006] [Patent Document 1] U.S. Patent Application Publication No. 2015 / 0340372

[0007] Patent document 1 discloses a non-volatile memory cell composed of a transistor, which has a ferroelectric layer made of ferroelectric crystal material below the gate electrode. Summary of the Invention

[0008] In ferroelectric memory cells using HfO2 films constituting the ferroelectric layer, the crystalline phase of the HfO2 film must be orthorhombic. However, the orthorhombic phase is metastable, and if an amorphous HfO2 film is formed on a semiconductor substrate during semiconductor device fabrication, and then heat-treated at a high temperature of, for example, approximately 700 to 1000 °C for crystallization, the crystalline phase of the HfO2 film becomes monoclinic, and thus the HfO2 film becomes paraelectric rather than ferroelectric. In ferroelectric memory cells, the threshold voltage is controlled by applying positive and negative voltages to the gate electrode and controlling the inversion of polarization domains in the ferroelectric layer. Therefore, the grain size and crystal orientation of the ferroelectric layer change, causing an increase in the variation of the threshold voltage relative to the gate voltage. Therefore, it is necessary to align the grain size and crystal orientation of the ferroelectric layer to improve the performance of the semiconductor device.

[0009] In this regard, forming aluminum (Al) grains within the ferroelectric layer could be considered to suppress variations in grain size and crystal orientation. However, simply forming grains may still cause changes in polarization characteristics when operations are performed between ferroelectric memory cells.

[0010] In addition, in ferroelectric memory cells equipped with ferroelectric layers, the heat resistance of the ferroelectric layers is very low, and when the semiconductor device is exposed to high temperatures during the manufacturing process, the crystallization of the ferroelectric layers becomes unstable, which may reduce the reliability of the semiconductor device.

[0011] Other objects and novel features will become clear from the description and accompanying drawings in this specification.

[0012] Typical embodiments of the embodiments disclosed in this application will be briefly described below.

[0013] A method for manufacturing a semiconductor device according to an embodiment includes the following steps: (a) forming a first amorphous film comprising hafnium, oxygen, and a first element; (b) forming a plurality of first grains comprising a second element different from any one of hafnium, oxygen, and the first element on the first amorphous film; (c) after (b), forming an insulating film comprising a third element different from any one of hafnium, oxygen, the first element, and the second element on the first amorphous film; (d) forming a second amorphous film comprising hafnium, oxygen, and the first element on the insulating film; (e) forming a first metal film on the second amorphous film; and (f) after (e), performing a heat treatment to crystallize the first amorphous film to form an orthorhombic first ferroelectric film and to crystallize the second amorphous film to form an orthorhombic second ferroelectric film.

[0014] According to one embodiment, the performance of a semiconductor device can be improved. Attached Figure Description

[0015] Figure 1 A planar layout diagram of a semiconductor chip as a semiconductor device according to the first embodiment is shown;

[0016] Figure 2 A cross-sectional view of the semiconductor device related to the first embodiment is shown;

[0017] Figure 3 A table is shown, illustrating examples of conditions for applying voltage to each portion of a selected memory cell during "write," "erase," and "read" operations.

[0018] Figure 4 This is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment;

[0019] Figure 5 It shows the continuation Figure 4 Cross-sectional view of the subsequent semiconductor device manufacturing process;

[0020] Figure 6 It shows the continuation Figure 5 Cross-sectional view of the subsequent semiconductor device manufacturing process;

[0021] Figure 7It shows the continuation Figure 6 Cross-sectional view of the subsequent semiconductor device manufacturing process;

[0022] Figure 8 It shows the continuation Figure 7 Cross-sectional view of the subsequent semiconductor device manufacturing process;

[0023] Figure 9 It shows the continuation Figure 8 Cross-sectional view of the subsequent semiconductor device manufacturing process;

[0024] Figure 10 It shows the continuation Figure 9 Cross-sectional view of the subsequent semiconductor device manufacturing process;

[0025] Figure 11 It shows the continuation Figure 10 Cross-sectional view of the subsequent semiconductor device manufacturing process;

[0026] Figure 12 It shows the continuation Figure 11 Cross-sectional view of the subsequent semiconductor device manufacturing process;

[0027] Figure 13 It shows the continuation Figure 12 Cross-sectional view of the subsequent semiconductor device manufacturing process;

[0028] Figure 14 It shows the continuation Figure 13 Cross-sectional view of the subsequent semiconductor device manufacturing process;

[0029] Figure 15 It shows the continuation Figure 14 Cross-sectional view of the subsequent semiconductor device manufacturing process;

[0030] Figure 16 It shows the continuation Figure 15 Cross-sectional view of the subsequent semiconductor device manufacturing process;

[0031] Figure 17 It shows the continuation Figure 16 Cross-sectional view of the subsequent semiconductor device manufacturing process;

[0032] Figure 18 This is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment;

[0033] Figure 19 It shows the continuation Figure 18 Cross-sectional view of the subsequent semiconductor device manufacturing process;

[0034] Figure 20 An enlarged cross-sectional view of the main parts of the first embodiment is shown; and

[0035] Figure 21 This is a cross-sectional view showing the manufacturing process of a semiconductor device as an example of comparison. Detailed Implementation

[0036] In the following embodiments, for convenience, they are described in multiple sections or embodiments when necessary, unless otherwise stated, and they are not unrelated to each other, one of which relates to some or all of other modified examples, detailed descriptions, supplementary descriptions, etc. Furthermore, in the following embodiments, except in specific cases or where it is obviously limited to a particular number in principle, the number of elements, etc. (including counts, values, quantities, ranges, etc.) is not limited to the stated number, and may be equal to or greater than the stated number, or may be less than or equal to the stated number.

[0037] Furthermore, in the following embodiments, except where specifically specified or deemed obviously necessary in principle, constituent elements (including element steps, etc.) are not required. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of constituent elements, etc., it is assumed that the shape, etc., is approximately similar to or analogous to the shape, etc., except where specifically specified or deemed obvious in principle. The same considerations also apply to the numerical values ​​and ranges above.

[0038] In the following description, embodiments will be illustrated with reference to the accompanying drawings. Throughout the drawings used to explain the embodiments, components with the same function are denoted by the same reference numerals, and repeated descriptions are omitted. In the following embodiments, unless specifically necessary, descriptions of identical or similar parts will generally not be repeated.

[0039] In the accompanying drawings used in the embodiments, the shading lines may be omitted to make the drawings easier to understand.

[0040] (First Embodiment)

[0041] Referring to the accompanying drawings, a semiconductor device having ferroelectric memory cells, which in this embodiment are non-volatile memory cells, will be described. First, referring to... Figure 1 Describes the planar layout configuration of a semiconductor chip CHP as a semiconductor device, in which a system including ferroelectric memory cells is formed. For example... Figure 1 As shown, the semiconductor chip CHP has a ferroelectric memory circuit C1 and a CPU (Central Processing Unit) circuit C2. The semiconductor chip CHP further includes a RAM (Random Access Memory) circuit C3, an analog circuit C4, and an I / O (Input / Output) circuit C5.

[0042] The ferroelectric memory circuit C1 has a circuit capable of electrically rewriting the stored information, and as a semiconductor element, it is a region in which multiple ferroelectric memory cells are formed as non-volatile memory cells.

[0043] CPU circuit C2 has logic circuitry for driving at a voltage of approximately 1.5V. CPU circuit C2 has a low voltage tolerance and, as a semiconductor element, it is a region in which MISFETs (metal-insulator-semiconductor field-effect transistors) with low voltage tolerance and fast operation are formed.

[0044] RAM circuit C3 has SRAM (Static RAM) and, as a semiconductor element, it is a region in which a low-voltage-tolerant MISFET with a configuration substantially the same as that of CPU circuit C2 is formed.

[0045] Analog circuit C4 contains analog circuitry and, as a semiconductor element, is the region in which capacitor elements, resistor elements, bipolar transistors, etc., are formed. Within analog circuit C4, a high-voltage MISFET is formed, which has a higher withstand voltage than a low-voltage MISFET and is driven by a voltage of approximately 6V.

[0046] I / O circuit C5 has input / output circuitry and, as a semiconductor element, it is the region in which a high-voltage-tolerant MISFET, essentially the same as that in analog circuit C4, is formed.

[0047] <Structure of Semiconductor Devices>

[0048] In the following text, reference will be made to Figure 2 The structure of the semiconductor device according to this embodiment is described. In this embodiment, as an example of the structure of the semiconductor device, a ferroelectric memory cell MC formed in a ferroelectric memory circuit C1 and a low-voltage-tolerant MISFET 1Q formed in a CPU circuit C2 will be described.

[0049] like Figure 2 As shown, the semiconductor device of this embodiment includes a region MR in which a ferroelectric memory cell MC is formed and a region LR in which a low-voltage-tolerant MISFET 1Q is formed.

[0050] The semiconductor substrate (semiconductor wafer) SB comprises, for example, p-type single-crystal silicon (Si) having a resistivity of about 1-10 Ωcm. A p-type well region PW1 is formed in the semiconductor substrate SB in region MR, and a p-type well region PW2 is formed in the semiconductor substrate SB in region LR. Multiple device isolation portions STIs are formed in well regions PW1 and PW2. The device isolation portions STIs are formed by embedding an insulating film (such as a silicon oxide film) in trenches formed in the semiconductor substrate SB.

[0051] First, the structure of the ferroelectric memory cell MC in region MR will be described. In this embodiment, as an example, a memory cell with a ferroelectric layer FEL applied to a transistor structure, referred to as MFIS (metal ferroelectric insulator semiconductor), is used as the ferroelectric memory cell MC. The ferroelectric memory cell MC is formed by sequentially forming a ferroelectric layer FEL, a gate electrode G1, and a transistor on a semiconductor substrate SB, the transistor including a source region and a drain region formed on the semiconductor substrate SB.

[0052] In region MR, an insulating film IF1 is formed on the semiconductor substrate SB, including the well region PW1. The insulating film IF1 comprises, for example, a silicon oxide film or a silicon oxynitride film, and has a thickness of, for example, 1 nm to 3 nm. The insulating film IF1 is formed to stabilize the interface between the semiconductor substrate SB and the ferroelectric layer FEL, which will be described later. Alternatively, the insulating film IF1 is formed to prevent electrons from entering the ferroelectric layer FEL from the semiconductor substrate SB during operation of the ferroelectric memory cell MC when a voltage is applied to the gate electrode G1. Therefore, if one or more of these objectives can be achieved, the insulating film IF1 may not be provided.

[0053] A ferroelectric layer FEL is formed on an insulating film IF1. The ferroelectric layer FEL has ferroelectric films FE1 and FE2 stacked in the longitudinal direction. The ferroelectric layer FEL further includes a plurality of grains GR formed between the ferroelectric films FE1 and FE2 and an insulating film IF2. The insulating film IF2 is a film formed between the ferroelectric films FE1 and FE2, and each of the plurality of grains GR is partially or completely covered by the insulating film IF2. The longitudinal direction (vertical direction) used herein is the direction perpendicular to the upper surface (main surface) of the semiconductor substrate SB. Therefore, by sandwiching the insulating film IF2 in the middle, the ferroelectric layer FEL of this embodiment is divided into at least two layers. For clarity, the shaded line of the insulating film IF2 is shown in the figure. Figure 2 The Chinese text and the accompanying drawings used for illustration are omitted.

[0054] Ferroelectric films FE1 and FE2 each comprise a metal oxide film, for example, a high-dielectric-constant film with a dielectric constant higher than that of silicon nitride. The thickness of each ferroelectric film FE1 and FE2 is, for example, 5 nm. The thickness of the insulating film IF2 is 2 nm or less. Here, the thickness of the insulating film IF2 is, for example, 2 nm. In this case, the thickness of the ferroelectric layer FEL is, for example, 12 nm.

[0055] Furthermore, in each of the ferroelectric films FE1 and FE2, dielectric polarization is generated when an electric field is applied, and each is a material that retains polarization even when the electric field is removed; that is, an insulating film composed of ferroelectric materials. In other words, polarization is preserved in ferroelectric films FE1 and FE2 even without an applied electric field. Ferroelectrics are materials that can align electric dipoles even in the absence of an external electric field and whose orientation can be changed by an electric field.

[0056] Then, each of the ferroelectric films FE1 and FE2 must be an orthorhombic crystal. In other words, a film mainly composed of crystals other than orthorhombic crystals is a paraelectric film. In the ferroelectric memory cell MC, it is important to achieve the following: increase the remanent polarization of the ferroelectric layer FEL, improve the performance as a ferroelectric material, and reduce the driving power of the ferroelectric memory cell MC. To this end, it is necessary to form the crystals constituting the ferroelectric films FE1 and FE2 as orthorhombic crystals as possible. The grain size of each of the ferroelectric films FE1 and FE2 is, for example, 5 to 50 nm.

[0057] In this embodiment, each of the ferroelectric films FE1 and FE2 is, for example, an insulating film containing hafnium (Hf) and oxygen (O) in addition to hafnium. Besides hafnium, each of the ferroelectric films FE1 and FE2 also includes, for example, zirconium (Zr) as a first element. Instead of zirconium, the first element may be silicon (Si), yttrium (Y), lanthanum (La), or yb.

[0058] Each of the ferroelectric films FE1 and FE2 includes, for example, hafnium oxide (HfO2). When the first element is zirconium, each of the ferroelectric films FE1 and FE2 includes, for example, zirconium-containing HfO2, i.e., HfZrO. When the first element is silicon, each of the ferroelectric films FE1 and FE2 includes, for example, silicon-containing HfO2, i.e., HfSiO.

[0059] Multiple grains GR are formed between ferroelectric films FE1 and FE2 as part of a ferroelectric layer FEL. As described below, the multiple grains GR are used as nuclei during the fabrication process of the ferroelectric layer FEL to create orthorhombic nanostructures of ferroelectric films FE1 and FE2. Therefore, each of the multiple grains GR is separate from the others. In other words, the multiple grains GR are formed discontinuously, rather than as a continuously formed layer like ferroelectric films FE1 and FE2. If each grain of the multiple grains GR were formed as a film in which multiple grains are connected to each other, the multiple grains GR serving as nuclei would deteriorate.

[0060] The multiple grains GR include a second element that is different from any of hafnium, oxygen, and the first element. The second element is, for example, aluminum (Al). Instead of aluminum, the second element can be carbon (C), nitrogen (N), fluorine (F), or titanium (Ti). Furthermore, as one of the key features of this embodiment, the second element constituting each grain of the multiple grains GR is bonded to a third element. The third element is different from both hafnium and the second element. The third element is also contained within the insulating film IF2. It is also conceivable to bond the second element to oxygen.

[0061] The insulating film IF2 comprises, for example, a SiO2 film, i.e., a silicon oxide film. In this case, the third element is silicon. That is, for example, each grain in the plurality of grains GR comprises Al-Si as a compound of aluminum and silicon. That is, each grain in the plurality of grains GR is an Al-Si cluster. Specifically, each grain in the plurality of grains GR comprises, for example, AlxSiyOz. In this embodiment, each grain in the plurality of grains GR is formed, for example, by an aggregate of 2 to 4 atoms. The third element may be germanium (Ge) instead of silicon.

[0062] The insulating film IF2 covers all or part of the surface of each of the multiple grains GR and is in contact with the multiple grains GR. The insulating film IF2 is a film continuously arranged across the multiple grains GR that are separated from each other.

[0063] Multiple grains of GR do not diffuse throughout the ferroelectric films FE1 and FE2, but remain near the interface between them. Therefore, the peak concentration of these multiple grains of GR in the ferroelectric layer FEL near the interface between FE1 and FE2 is higher than that near the lower surface of FE1 and near the upper surface of FE2. In other words, the peak concentrations of the second and third elements in the ferroelectric layer FEL are between FE1 and FE2. That is, the concentrations of the second and third elements in FE1 on the opposite side of FE2 (the semiconductor substrate SB side) are smaller than those on the FE2 side. Similarly, the concentrations of the second and third elements in FE2 on the opposite side of FE1 (the metal film MF1 side, described later) are smaller than those on the FE1 side.

[0064] The proportion of the first element in the ferroelectric layer FEL is 30% to 50%, and the combined proportion of the second and third elements is 5% or less. That is, the proportion of each of the second and third elements in the ferroelectric layer FEL is less than the proportion of the first element. The proportion of hafnium dioxide (HfO2) in the ferroelectric layer FEL is, for example, about 50% to 70%.

[0065] Therefore, multiple grains GR exist near the interface between ferroelectric films FE1 and FE2. Thus, each of ferroelectric films FE1 and FE2 is readily formed as an orthorhombic crystal with a highly uniform grain size. Therefore, when the ferroelectric layer FEL is applied to the ferroelectric memory cell MC, the problem of increased threshold voltage variation due to polarization reversal of the ferroelectric layer FEL can be suppressed. Therefore, the problem of reduced rewrite durability and / or reduced retention characteristics of the ferroelectric memory cell MC can be suppressed. In other words, the technology according to this embodiment can improve the performance of semiconductor devices.

[0066] A metal film MF1 is formed on the ferroelectric layer FEL. The metal film MF1 is a conductive film, including, for example, a titanium nitride film, a tantalum nitride film, or a tungsten film. The thickness of the metal film MF1 is, for example, 10 nm to 20 nm. The metal film MF1 is a capping film configured to provide stress to the ferroelectric films FE1 and FE2 during the fabrication process of the ferroelectric layer FEL to control the crystal orientation of each of the ferroelectric films FE1 and FE2. Therefore, after the formation of the ferroelectric layer FEL, if each of the ferroelectric films FE1 and FE2 can exist as an orthorhombic crystal, the metal film MF1 can be removed. However, if the metal film MF1 is removed, the crystal orientation of each of the ferroelectric films FE1 and FE2 may change, so it is more preferable to retain the metal film MF1. When the metal film MF1 is retained, the metal film MF1 is used as part of the gate electrode together with the gate electrode G1, which will be described later. The crystal orientation of each of the ferroelectric films FE1 and FE2 is a (001) orientation.

[0067] A gate electrode G1 is formed on a metal film MF1. The gate electrode G1 is a conductive film comprising, for example, a polycrystalline silicon film in which n-type impurities are introduced. Instead of a polycrystalline silicon film, a metal film such as a titanium nitride film, an aluminum film, or a tungsten film, or a stacked film in which two or more of these films are suitably stacked, can be used as the material for forming the gate electrode G1.

[0068] Sidewall spacers SW are formed on the side surface of the gate electrode G1. The sidewall spacers SW may include, for example, a stacked film of silicon oxide film and silicon nitride film.

[0069] An extension region EX1, serving as a low-concentration n-type impurity region, is formed in a well region PW1 below the sidewall spacer SW at a predetermined depth from the upper surface of the semiconductor substrate SB. Furthermore, a diffusion region D1, serving as an n-type impurity region with a higher concentration than the extension region EX1, is formed at a location in the well region PW1 that matches the sidewall spacer SW. The diffusion region D1 is formed at a predetermined depth from the upper surface of the semiconductor substrate SB. Relative to the semiconductor substrate SB located directly below the gate electrode G1, the diffusion region D1 is formed at a location far from the extension region EX1.

[0070] Each of the extended region EX1 and the diffusion region D1 is formed in pairs to sandwich the semiconductor substrate SB directly below the gate electrode G1. One side of the paired extended region EX1 and one side of the paired diffusion region D1 are connected to each other to form the source region of the ferroelectric memory cell MC. The other side of the paired extended region EX1 and the other side of the paired diffusion region D1 are connected to each other to form the drain region of the ferroelectric memory cell MC.

[0071] A silicide layer SI, comprising, for example, cobalt silicide (CoSi2), nickel silicide (NiSi), or nickel platinum silicide (NiPtSi), is formed on the gate electrode G1 and the diffusion region D1. The formation of the silicide layer SI is primarily to reduce the contact resistance with the plug PG, which will be described later.

[0072] Next, the structure of the MISFET 1Q with low withstand voltage in region LR will be described.

[0073] In region LR, a gate insulating film GF is formed on a semiconductor substrate SB, including the well region PW2. The gate insulating film GF is, for example, a silicon oxide film, and has a thickness of, for example, 1 nm to 4 nm.

[0074] A gate electrode G2 is formed on the gate insulating film GF. The gate electrode G2 is a conductive film including, for example, a polycrystalline silicon film in which n-type impurities are introduced. Instead of a polycrystalline silicon film, a metal film such as a titanium nitride film, an aluminum film, or a tungsten film, or a stacked film in which two or more of these films are suitably stacked, can be used as the material for forming the gate electrode G2.

[0075] Sidewall spacers SW are formed on the side of the gate electrode G2. The sidewall spacers SW may include, for example, a stacked film of silicon oxide film and silicon nitride film.

[0076] In the well region PW2 below the sidewall spacer SW, an extension region EX2, serving as a low-concentration n-type impurity region, is formed. At the location of the well region PW2, which matches the sidewall spacer SW, a diffusion region D2, also serving as an n-type impurity region, is formed with a higher concentration than the extension region EX2. The extension region EX2 and the diffusion region D2 each constitute a portion of the source region and drain region of the MISFET 1Q, respectively. The extension region EX2 and the diffusion region D2 have the same structure as the extension region EX1 and the diffusion region D1, respectively.

[0077] The impurity concentration in the extended region EX1 of region MR is substantially the same as the impurity concentration in the extended region EX2 of region LR. The impurity concentration in the diffusion region D1 of region MR is substantially the same as the impurity concentration in the diffusion region D2 of region LR.

[0078] A silicide layer SI, comprising, for example, cobalt silicide (CoSi2), nickel silicide (NiSi), or nickel platinum silicide (NiPtSi), is formed on the gate electrode G2 and the diffusion region D2. The formation of the silicide layer SI is primarily to reduce the contact resistance with the plug PG, which will be described later.

[0079] An interlayer insulating film IL1 is formed on the ferroelectric memory cell MC formed in region MR and on the MISFET 1Q formed in region LR. The interlayer insulating film IL1 is, for example, a silicon oxide film. Multiple contact holes are formed in the interlayer insulating film IL1, extending from its upper surface to its lower surface, and multiple plugs PG are formed in these contact holes. The plugs PG include a barrier metal film, which may include, for example, a titanium film, a titanium nitride film, or a stacked film thereof, and a conductive film primarily formed of tungsten. However, in… Figure 2 In the diagram, the barrier metal film and the main conductive film are not distinguished from each other, and a plug PG comprising both the barrier metal film and the main conductive film is shown. The plug PG is electrically connected to the diffusion region D1 or the diffusion region D2 through the silicide layer SI. Although not shown, a plug PG electrically connected to the gate electrodes G1 and G2 is also present in the interlayer insulating film IL1.

[0080] Furthermore, although not shown in the figure, multiple interconnects are formed on the interlayer insulating film IL1 and the plug PG. For example, an interlayer insulating film is formed on the interlayer insulating film IL1, and trenches for interconnection are formed in the interlayer insulating film. Then, a conductive film mainly formed of, for example, copper is embedded in the trenches for interconnection, thereby forming the first layer of interconnection connected to the plug PG.

[0081] <Operation of Ferroelectric Memory Cell MC>

[0082] Next, we will refer to Figure 3 Describe an operational example of a ferroelectric memory cell (MC).

[0083] Figure 3 This is an example table showing the voltage applied to each portion of a selected memory cell in the ferroelectric memory cell MC during "write," "erase," and "read" operations. Figure 3 The table describes the voltage Vd applied to the drain region (one side of the diffusion region D1), the voltage Vg applied to the gate electrode G1, the voltage Vs applied to the source region (the other side of the diffusion region D1), and the voltage Vs applied to the source region during each "write," "erase," and "read" operation. Figure 2 The voltage Vb of the well region PW1 in the ferroelectric memory cell MC shown. Note that in Figure 3 The table shows preferred examples of applied voltage conditions, but is not limited to these, and various changes can be made as needed.

[0084] In this embodiment, the case where the polarization of the ferroelectric layer FEL changes upward and the threshold voltage of the ferroelectric memory cell MC becomes relatively high is defined as "writing". Then, the case where the polarization of the ferroelectric layer FEL changes downward and the threshold voltage of the ferroelectric memory cell MC becomes relatively low is defined as "erasing".

[0085] The write operation is performed by applying a negative voltage to the gate electrode G1. That is, for example, by applying a negative voltage to the gate electrode G1. Figure 3 The voltage shown in the "Write" column is applied to each portion of the selected memory cell to be written. The polarization of the ferroelectric layer FEL accordingly becomes upward, and the threshold voltage of the ferroelectric memory cell MC increases, thus putting the ferroelectric layer FEL into a write state.

[0086] The erase operation is performed by applying a positive voltage to the gate electrode G1. That is, for example, as shown in the image. Figure 3 The voltage shown in the "Erase" column is applied to each portion of the selected memory cell to be erased. The polarization of the ferroelectric layer FEL accordingly turns downward, and the threshold voltage of the ferroelectric memory cell MC decreases, thus the ferroelectric layer FEL enters the erase state.

[0087] In read operations, for example, ... Figure 3 The voltage shown in the "Read" column is applied to each portion of the selected memory cell to be read. The write and erase states can be determined by setting the voltage Vg to be applied to the gate electrode G1 to a value between the threshold voltage of the ferroelectric layer FEL in the write state and the threshold voltage of the ferroelectric layer FEL in the erase state.

[0088] Semiconductor device manufacturing processes

[0089] The following will refer to Figures 4 to 17 This embodiment describes a method for manufacturing a semiconductor device. Figures 4 to 17 Each figure in the diagram is a cross-sectional view showing the region MR in which the ferroelectric memory cell MC is formed and the region LR in which the low-voltage-tolerant MISFET 1Q is formed.

[0090] First, such as Figure 4 As shown, a semiconductor substrate SB comprising, for example, single-crystal silicon with introduced p-type impurities is prepared. Next, trenches are formed on the upper surface of the semiconductor substrate SB using photolithography and etching processes. Subsequently, an insulating film, such as a silicon oxide film, is formed to fill the trenches. Afterward, the insulating film outside the trenches is removed by a CMP (chemical mechanical polishing) method, thereby forming a device isolation portion STI, which includes the insulating film remaining in the trenches.

[0091] Next, impurities are introduced into the semiconductor substrate SB using photolithography and ion implantation to form a p-type well region PW1 in region MR and a p-type well region PW2 in region LR.

[0092] Next, as Figure 5 As shown, a semiconductor substrate SB comprising a well region PW1 in region MR and a well region PW2 in region LR is thermally processed in an atmosphere including, for example, oxygen. Consequently, a gate insulating film GF comprising, for example, silicon oxide is formed on the semiconductor substrate SB in regions MR and LR. The thickness of the gate insulating film GF is, for example, 1 nm to 3 nm. Subsequently, a resist pattern RP1 having an opening in region MR and covering region LR is formed. Next, an etching process is performed using the resist pattern RP1 as a mask, in which the gate insulating film GF in region LR is retained, and the gate insulating film GF in region MR is removed.

[0093] Next, as Figure 6 As shown, the resist pattern RP1 is removed by, for example, an ashing process. Then, a heat treatment is performed on the semiconductor substrate SB in an atmosphere including, for example, oxygen. As a result, an insulating film IF1, including, for example, a silicon oxide film or a silicon oxynitride film, is formed on the semiconductor substrate SB in region MR. The thickness of the gate insulating film GF is, for example, 1 nm to 3 nm. At this time, the gate insulating film GF is formed in region LR, and the thickness of the gate insulating film GF is slightly increased by this thermal oxidation treatment.

[0094] Next, as Figure 7 As shown, an amorphous film (amorphous membrane) AM1 is formed on the insulating film IF1 in region MR and the gate insulating film GF in region LR by, for example, ALD (atomic layer deposition). The thickness of the amorphous film AM1 is, for example, 5 nm. In addition to hafnium, the amorphous film AM1 also contains hafnium (Hf) and oxygen (O). In addition to hafnium, the amorphous film AM1 also contains, for example, zirconium (Zr) as the first element. Instead of zirconium, the first element can be any of silicon (Si), yttrium (Y), lanthanum (La), or (Yb).

[0095] Next, as Figure 8 As shown, multiple grains GR1 are formed on the amorphous film AM1. In this embodiment, multiple grains GR1 are formed on the amorphous film AM1 in region MR and region LR by sputtering. Figure 8In the diagram, each grain in the plurality of grains GR1 is represented by an unshaded white circle. Each grain in the plurality of grains GR1 is spaced apart from each other. In other words, the plurality of grains GR1 are not formed continuously like the amorphous film AM1, but are formed discontinuously. That is, the plurality of grains GR1 do not cover the entire upper surface of the amorphous film AM1, but are dispersed on the amorphous film AM1. Therefore, a portion of the amorphous film AM1 is covered by the plurality of grains GR1, and another portion of the amorphous film AM1 is exposed from the plurality of grains GR1. In addition, although a portion of the plurality of grains GR1 is deposited on the upper surface of the amorphous film AM1, there are also a plurality of grains GR1 introduced into the amorphous film AM1 near the upper surface. Therefore, in the process of crystallizing the amorphous film AM1, which will be described later, the plurality of grains GR1 can be used as crystal nuclei.

[0096] Multiple grains GR1 contain a second element other than hafnium, oxygen, and the first element. The second element is, for example, aluminum (Al). Instead of aluminum, the second element can be carbon (C), nitrogen (N), fluorine (F), or titanium (Ti). Note that in this embodiment, the case where the second element is aluminum is described as an example.

[0097] Multiple grains GR1 can be formed using CVD (chemical vapor deposition) instead of sputtering, but as mentioned above, it is preferable to form multiple grains GR1 that are separated from each other. Therefore, it is preferred to form multiple grains GR1 by sputtering. This is because, according to sputtering, multiple grains GR1 can be formed relatively easily and uniformly in a controlled manner. The areal density of the multiple grains GR1 relative to the upper surface of the amorphous film AM1 is 1 × 10⁻⁶. 13 / cm 2 Up to 1×10 15 / cm 2 Within a certain range. Therefore, multiple grains of GR1 are uniformly added to the upper surface of the amorphous film AM1. Furthermore, by setting the areal density of the multiple grains of GR1 to 1×10 13 / cm 2 Up to 1×10 15 / cm 2 Within a certain range, the grain radius of multiple GR1 grains can be precisely controlled, for example, in the range of 0.1 nm to 1 nm.

[0098] To prevent excessive diffusion of multiple GR1 grains into the amorphous film AM1, the sputtering method is preferably performed within a temperature range of 1°C to 150°C. Here, the process of forming multiple GR1 grains by the above sputtering method is performed, for example, at room temperature (25°C).

[0099] As mentioned above, the second element constituting multiple GR1 grains can be any element other than aluminum. Note that when the second element is other than aluminum, multiple GR1 grains can be formed using ion implantation instead of sputtering. When using ion implantation, the dose for multiple GR1 grains is approximately 1 × 10⁻⁶. 13 / cm 2 Up to 1×10 15 / cm 2 Within the range.

[0100] Next, as Figure 9 As shown, an insulating film IF2 is formed (deposited) on a semiconductor substrate SB using, for example, the ALD method. The insulating film IF2 includes a third element other than either hafnium or the second element. The insulating film IF2 includes, for example, a SiO2 film, i.e., a silicon oxide film, and in this case, the third element is silicon (Si).

[0101] Therefore, the upper surface of the amorphous film AM1 is covered by the insulating film IF2. Furthermore, during the formation of the insulating film IF2, the second and third elements constituting the plurality of grains GR1 react to form a plurality of grains GR, which are nanostructures formed by compounds in which the second and third elements are bonded. Here, each of the plurality of grains GR includes, for example, Al-Si, which is a compound of aluminum and silicon. That is, each grain of the plurality of grains GR is an Al-Si cluster. Specifically, each grain of the plurality of grains GR contains, for example, AlxSiyOz. In this embodiment, each grain of the plurality of grains GR is formed by, for example, an aggregate of 2 to 4 atoms. The third element may be germanium (Ge) instead of silicon. Figure 9 In the image, each grain in the multiple grains GR that form an Al-Si cluster is indicated by a black circle.

[0102] The insulating film IF2 covers all or part of the surface of each of the multiple grains GR and is in contact with the multiple grains GR. The insulating film IF2 is a film continuously arranged across the multiple grains GR that are separate from each other.

[0103] Here, the deposition process for forming the insulating film IF2 is performed using the ALD method at 100°C or higher. Specifically, the deposition process is performed at 300°C. In the deposition process, 1 to 4 deposition cycles are performed, where one deposition cycle is defined as sequentially providing water (H2O) and silicon tetrachloride (SiCl4) to the ALD apparatus. That is, an insulating film IF2 containing, for example, silicon oxide is formed by one or more depositions using the ALD method. As mentioned above, the number of deposition cycles is preferably 1 to 4, but from the perspective of improving reliability, a number of cycles of 2 is most preferred. The thickness of the insulating film IF2 is 1 nm or less. The thickness of the insulating film IF2 is, for example, 1 nm.

[0104] Although the ALD method for forming insulating film IF2 has been described, the insulating film IF2 can be formed by low-energy DC magnetron sputtering instead of the ALD method.

[0105] Next, as Figure 10 As shown, in regions MR and LR, an amorphous film (amorphous membrane) AM2 is formed on an insulating film IF2, multiple grains GR, and an amorphous film AM1 using, for example, an ALD method. Through this process, the multiple grains GR are covered by the amorphous film AM2. The thickness of the amorphous film AM2 is, for example, 5 nm. The amorphous film AM2 contains the same material as the amorphous film AM1, i.e., hafnium (Hf) and oxygen (O) in addition to hafnium. Besides hafnium, the amorphous film AM2 also includes, for example, zirconium (Zr) as a first element. Instead of zirconium, the first element can be silicon (Si), yttrium (Y), lanthanum (La), or ybium (Yb).

[0106] Next, as Figure 11 As shown, in regions MR and LR, a metal film MF1 comprising, for example, titanium nitride, tantalum nitride, or tungsten is formed on the amorphous film AM2. The metal film MF1 can be formed by, for example, CVD or sputtering. The thickness of the metal film MF1 is, for example, 10 nm to 20 nm. The metal film MF1 is primarily provided as a cover film for applying stress to both the amorphous film AM1 and the amorphous film AM2.

[0107] Next, as Figure 12 As shown, heat treatment is performed in regions MR and LR at, for example, 600 to 900 °C, while a metal film MF1 is formed on the amorphous film AM2. Therefore, by crystallizing the amorphous film AM1 and the amorphous film AM2, orthorhombic ferroelectric films FE1 and FE2 are formed, respectively. Specifically, it is desirable to perform the heat treatment at approximately 700 °C.

[0108] Heat treatment can be performed at temperatures below 600°C using the RTA (Rapid Thermal Annealing) method; however, it is preferable, for example, to use microwaves with a frequency of 1 GHz to 10 GHz as electromagnetic waves to perform heat treatment, and more preferably, to use microwaves with a frequency of 2.45 GHz. Heat treatment using microwaves enables crystallization to be carried out at lower temperatures (e.g., below 400°C).

[0109] In microwave heat treatment, microwaves are irradiated so that the oscillation direction of the electric field is 90 degrees (perpendicular) relative to the upper surface of the metal film MF1 or the upper surface of the semiconductor substrate SB. Electromagnetic waves such as microwaves have the following characteristics: because energy is absorbed in the polarizing crystal, ferroelectric films FE1 and FE2, which are polarizing crystals, are easily formed. Therefore, as described above, heat treatment for crystallization can be easily performed at low temperatures of 400°C or lower.

[0110] The second and third elements in the crystalline ferroelectric layer FEL exhibit peaks between ferroelectric films FE1 and FE2. Specifically, the concentrations of the second and third elements in ferroelectric film FE1 are lower on the opposite side of ferroelectric film FE2 compared to their concentrations on the FE2 side. Furthermore, the concentrations of the second and third elements in ferroelectric film FE2 are lower on the opposite side of ferroelectric film FE1 compared to their concentrations on the FE1 side. This distribution of the second and third elements is attributed to their bonding during the heat treatment required for crystallization.

[0111] For example, if a heat treatment for crystallization is performed at a temperature greater than 900°C, such as 1000°C or less, the crystal phases of ferroelectric films FE1 and FE2 tend to be monoclinic. When the crystal phases of ferroelectric films FE1 and FE2 become monoclinic, they become paraelectric films instead of ferroelectric films, and the ferroelectric memory cells to be formed later become ineffective. As in this embodiment, by performing heat treatment at a temperature of 900°C or less, ferroelectric films FE1 and FE2 can be easily formed into orthorhombic crystals.

[0112] Furthermore, in this crystallization process, the orientations of the ferroelectric films FE1 and FE2 are controlled by stress from the metal film MF1. That is, when the amorphous film AM1 and the amorphous film AM2 are crystallized into ferroelectric films FE1 and FE2, the metal film MF1 has the function of making the corresponding crystal phase orientations of the ferroelectric films FE1 and FE2 orthorhombic.

[0113] In this embodiment, a plurality of grains GR and an insulating film IF2 covering the plurality of grains GR are formed between the amorphous film AM1 and the amorphous film AM2. The plurality of grains GR covered by the insulating film IF2 are used as crystal nuclei in the crystallization process.

[0114] In the following description, as an example of the crystallization process, the case where the second and third elements constituting the multiple grains GR are aluminum and silicon, respectively, will be described. Amorphous films AM1 and AM2 are crystallized using multiple Al-Si grains (which are multiple grains GR) as nuclei, and are therefore ferroelectric films FE1 and FE2. Here, the radius of the grain size of the multiple grains GR is precisely controlled within, for example, a range of 0.1 nm to 1 nm. That is, since the grain size of each of the ferroelectric films FE1 and FE2 is aligned according to the grain size of the multiple grains GR containing aluminum, silicon, and oxygen, the uniformity of the grain size in the ferroelectric layer FEL is improved.

[0115] Therefore, in the ferroelectric layer FEL, the uniformity of the grain size is improved, and the crystal orientation is aligned with the orthorhombic crystal with the (001) orientation. When the ferroelectric layer is applied to a ferroelectric memory cell, the film quality of the ferroelectric layer may deteriorate due to polarization reversal. In this case, the threshold voltage variation may increase with changes in the grain size and crystal orientation of the ferroelectric layer. Conversely, since this embodiment improves the uniformity of the grain size and aligns the crystal orientation with the orthorhombic crystal, such changes in the grain size and crystal orientation of the ferroelectric layer FEL can be suppressed. Therefore, the problems of reduced rewrite durability and reduced retention characteristics of the ferroelectric memory cell MC can be suppressed. In other words, the technology of this embodiment can improve the performance of semiconductor devices.

[0116] Next, as Figure 13 As shown, a resist pattern RP2 is formed having an opening in region LR and covering region MR. Next, an etching process is performed using the resist pattern RP2 as a mask. In this way, the metal film MF1 and the ferroelectric layer FEL formed in region LR are removed, leaving the metal film MF1 and the ferroelectric layer FEL formed in region MR.

[0117] Next, as Figure 14 As shown, the resist pattern RP2 is removed by, for example, an ashing process. Then, a conductive film FG comprising polycrystalline silicon with introduced n-type impurities is formed on the metal film MF1 in region MR and on the gate insulating film GF in region LR by, for example, CVD.

[0118] As described above, as long as the ferroelectric layer FEL can be sufficiently maintained as an orthorhombic crystal, the metal film MF1 can be removed before the conductive film FG is formed.

[0119] Next, as Figure 15 As shown, the conductive film FG in regions MR and LR is patterned using photolithography and etching processes. Therefore, a gate electrode G1 is formed in region MR, and a gate electrode G2 is formed in region LR. Subsequently, an etching process is performed to remove the metal film MF1, the ferroelectric layer FEL, and the insulating film IF1 in region MR that are not covered by the gate electrode G1. Furthermore, an etching process is performed to remove the gate insulating film GF in region LR that is not covered by the gate electrode G2.

[0120] In this embodiment, the metal film MF1 is used as part of the gate electrode because, in this example, the metal film MF1 is retained below the gate electrode G1 (below the conductive film FG).

[0121] Next, as Figure 16As shown, using photolithography and ion implantation, an extension region EX1, serving as an n-type impurity region, is formed in the well region PW1 at a location matching the gate electrode G1 in the region MR. Similarly, an extension region EX2, also serving as an n-type impurity region, is formed in the well region PW2 at a location matching the gate electrode G2 in the region LR. Extension region EX1 constitutes part of the source region or drain region of the ferroelectric memory cell MC. Extension region EX2 constitutes part of the source region or drain region of the MISFET 1Q.

[0122] Next, as Figure 17 As shown, for example, a silicon oxide film and a silicon nitride film are sequentially formed by, for example, CVD to cover gate electrode G1 and gate electrode G2. Then, the silicon nitride film is processed by an anisotropic etching process. Afterwards, the silicon oxide film formed on the upper surfaces of gate electrode G1 and gate electrode G2 is removed. Therefore, sidewall spacers SW comprising a stack of silicon oxide and silicon nitride films are formed on the side surfaces of gate electrode G1 and gate electrode G2.

[0123] Next, n-type impurities are introduced into the semiconductor substrate using photolithography and ion implantation. Therefore, in region MR, a diffusion region D1, serving as an n-type impurity region, is formed at a location in well region PW1 that matches the sidewall spacer SW. Impurities are introduced in region LR, and in region LR, a diffusion region D2, also serving as an n-type impurity region, is formed at a location in well region PW2 that matches the sidewall spacer SW.

[0124] In region MR, diffusion region D1 has a higher impurity concentration than extension region EX1, and is connected to extension region EX1, forming part of the source region or part of the drain region of ferroelectric memory cell MC.

[0125] In region LR, diffusion region D2 has a higher impurity concentration than extension region EX2, is connected to extension region EX2, and forms part of the source or drain region of MISFET 1Q.

[0126] Next, a low-resistance silicide layer SI is formed on the upper surface of each of the diffusion regions D1, D2, gate electrode G1, and gate electrode G2 using self-aligned silicide technology.

[0127] Specifically, the silicide layer SI can be formed as follows: First, a metal film for forming the silicide layer SI is formed to cover regions MR and LR. The metal film contains, for example, cobalt, nickel, or a nickel-platinum alloy. Next, the semiconductor substrate SB is subjected to a first heat treatment at approximately 300 to 400°C, and then the unreacted metal film is removed. Afterward, a second heat treatment is performed at approximately 500 to 700°C. Therefore, the materials included in diffusion regions D1, D2, gate electrode G1, and gate electrode G2 react with the metal film. Thus, the silicide layer SI is formed on the upper surface of each of diffusion regions D1, D2, gate electrode G1, and gate electrode G2. The silicide layer SI contains cobalt silicide (CoSi2), nickel silicide (NiSi), or nickel-platinum silicide (NiPtSi).

[0128] Alternatively, the material constituting the gate electrode G1 can be replaced with a metal film such as a titanium nitride film, an aluminum film, or a tungsten film, or a stacked film of two or more of these metal films appropriately stacked therein. In this case, in Figure 17 After the process, the polysilicon film used as the gate electrode G1 material can be replaced with a metal film or a stacked film by using a so-called post-gate process.

[0129] As described above, a ferroelectric memory cell MC with an MFIS structure is formed in region MR, and a MISFET 1Q is formed in region LR. That is, the semiconductor device of this embodiment is basically completed.

[0130] Subsequently, it is obtained through the following process. Figure 2 The structure shown.

[0131] First, an interlayer insulating film IL1 comprising, for example, silicon oxide is formed by, for example, CVD to cover the ferroelectric memory cell MC formed in region MR and the MISFET 1Q formed in region LR. Next, multiple contact holes are formed in the interlayer insulating film IL1 using photolithography and etching processes. Then, a barrier metal film, including, for example, a titanium film, a titanium nitride film, or a stack thereof, is formed in the multiple contact holes. Subsequently, a conductive film mainly formed of tungsten is formed on the barrier metal film. Next, an embolization PG is formed in the contact holes by removing the barrier metal film and the conductive film outside the contact holes, for example, by CMP. The embolization PG is electrically connected to diffusion region D1 or diffusion region D2 through a silicide layer SI. Although not shown in the figure, an embolization PG electrically connected to gate electrode G1 and gate electrode G2 is also present.

[0132] <Comparison Example with This Embodiment>

[0133] Figure 21 A cross-sectional view of a comparative example studied by the inventors during the manufacturing process of a semiconductor device is shown. Figure 21This is shown in relation to the embodiment. Figure 12 The corresponding cross-sectional view during the manufacturing process. That is, Figure 21 The following state is shown: a heat treatment for crystallization is provided relative to the amorphous film used as the ferroelectric layer FEL, and a ferroelectric film FE4 is formed.

[0134] In the comparative example, similar to this embodiment, a ferroelectric memory cell with a ferroelectric layer FEL is formed. Here, the ferroelectric layer FEL in the comparative example comprises a single layer of ferroelectric film FE4, unlike the stacked film comprising ferroelectric films FE1 and FE2 in this embodiment, and does not have multiple grains GR. The ferroelectric film FE4 contains hafnium (Hf), oxygen (O), and zirconium (Zr) as the first elements.

[0135] For example, in the case of hafnium oxide (HfO2) films, an amorphous film is deposited by methods such as ALD, followed by heat treatment at a temperature above 900°C, thereby changing the crystalline phase of the HfO2 film to monoclinic. Therefore, the HfO2 film becomes paraelectric rather than ferroelectric. Here, by adding a first element containing zirconium (Zr) to the HfO2 film, it is easy to form the ferroelectric film FE4 as an orthorhombic crystal. Furthermore, by forming a metallic film MF1 containing titanium nitride or the like on the amorphous film, the orientation of the ferroelectric film FE4 can be easily controlled.

[0136] In ferroelectric memory cells, the threshold voltage is controlled by applying positive and negative voltages to the gate electrode, thereby controlling the inversion of polarization domains in the ferroelectric layer (FEL). Therefore, the variation in the threshold voltage within a ferroelectric memory cell largely depends on changes in the grain size and crystal orientation of the ferroelectric film FE4. As the number of rewrites of the ferroelectric memory cell (MC) increases, the film quality in the FEL deteriorates. Therefore, the magnitude of changes in grain size and crystal orientation significantly influences the change in threshold voltage.

[0137] According to the inventors' research, it has been found that variations in the grain size and crystal orientation of the ferroelectric film FE4 cannot be sufficiently suppressed in the ferroelectric memory cell of the comparative example. Therefore, in the comparative example, the threshold voltage variation increases with the number of rewrites of the ferroelectric memory cell MC. Furthermore, in the ferroelectric memory cell of the comparative example, the threshold voltage distribution in the write state and the threshold voltage distribution in the erase state overlap, thus narrowing the memory window. That is, in the case of the comparative example, there is a problem of easy occurrence of accidental writing and accidental erasure.

[0138] Therefore, the inventors have investigated using a stacked structure comprising two amorphous films during the formation of the ferroelectric layer, and further provided multiple grains containing a second element (e.g., aluminum) between the amorphous films. However, the grains do not contain the aforementioned third element. By providing multiple grains, variations in the grain size and crystal orientation of the ferroelectric layer can be suppressed. However, if only multiple grains are formed, the polarization characteristics between the ferroelectric memory cells may change during operation.

[0139] Conversely, in this embodiment, when forming the ferroelectric layer FEL, a stacked structure of amorphous films AM1 and AM2 is adopted. Furthermore, multiple grains GR, each containing a second element and a third element, are disposed between amorphous films AM1 and AM2. The radius of each grain size of the multiple grains GR is precisely controlled within, for example, a range of 0.1 nm to 1 nm. Then, while forming a metal film MF1 on amorphous film AM2, heat treatment for crystallization is performed on amorphous films AM1, AM2, and the multiple grains GR, so that the grain sizes of each of the ferroelectric films FE1 and FE2 are aligned according to the grain sizes of the multiple grains GR.

[0140] Therefore, the uniformity of grain size in the ferroelectric layer FEL is improved compared to the case where multiple aluminum grains without a third element are formed between amorphous films AM1 and AM2. Thus, by improving the uniformity of grain size in the ferroelectric layer FEL, the crystal orientation can be aligned with the orthorhombic crystal with a (001) orientation. That is, it improves the reliability of the ferroelectric layer FEL.

[0141] Here, Figure 20 An enlarged cross-sectional view of the main part of the ferroelectric memory cell, which is the semiconductor device of this embodiment, is shown. Figure 20 A stacked film comprising insulating films IF1 and IF2, multiple grains GR, ferroelectric films FE1 and FE2, and a metal film MF1 constituting a ferroelectric memory cell is shown. When the ferroelectric memory cell is operated and the ferroelectric layer FEL is polarized, the polarization within the ferroelectric layer FEL begins with each of the multiple grains GR that serve as nuclei, and in a planar view, begins with the region DP that overlaps with the multiple grains GR. This is because the dielectric constant of the multiple grains GR is higher than the dielectric constant of the portion in which the multiple grains GR are not present. Subsequently, the polarized region in the ferroelectric layer FEL extends laterally from the region DP, which extends longitudinally between the ferroelectric films FE1 and FE2.

[0142] In this embodiment, an insulating film IF2 is formed between adjacent grains GR. This insulating film IF2 comprises a material (containing a third element) with a dielectric constant lower than any one of the plurality of grains GR, the ferroelectric film FE1, and the ferroelectric film FE2. Therefore, the difference in dielectric constant between region R1, where the plurality of grains GR are present, and region R2, where the plurality of grains GR are absent, is greater than the difference in dielectric constant when the insulating film IF2 is not formed. That is, the dielectric constant of region R1, which includes the ferroelectric film FE1, the insulating film IF2, the grains GR, and the ferroelectric film FE2 stacked in the longitudinal direction, is higher than the dielectric constant of region R2, which includes the ferroelectric film FE1, the insulating film IF2, and the ferroelectric material FE2 stacked in the longitudinal direction. Therefore, when operating the ferroelectric memory cell, polarization is easily initiated from region R1 (DP), which includes each of the plurality of grains GR.

[0143] That is, compared to the case where the insulating film IF2 is absent, the formation density of the polarization initiation portion is more uniform. Therefore, the occurrence of threshold voltage variations in ferroelectric memory cells can be suppressed. The rewrite resistance of ferroelectric memory cells can be improved, and the degradation of retention characteristics can be suppressed.

[0144] An insulating film IF2 is formed to reduce the dielectric constant of the region R2 between multiple adjacent grains GR. Therefore, it is sufficient for the multiple grains GR forming the Al-Si cluster to serve as nuclei for crystal growth, and for an insulating film IF2 to be formed between the multiple adjacent grains GR. That is, each grain in the multiple grains GR may not be covered by the insulating film IF2.

[0145] Here, the areal density of multiple grains GR1 and multiple grains GR is set to 1×10. 13 / cm 2 Up to 1×10 15 / cm 2 Therefore, the grain size of each of the ferroelectric films FE1 and FE2 is aligned, for example, in the range of 5 nm to 50 nm. Thus, by suppressing changes in the polarization characteristics of the ferroelectric layer FEL, changes in the threshold voltage of the ferroelectric memory cell MC can be suppressed.

[0146] Therefore, in this embodiment, the distribution of the threshold voltage in the write state and the distribution of the threshold voltage in the erase state are prevented from overlapping. That is, the memory window is expanded. In other words, accidental writing or erasing can be prevented when using ferroelectric memory cells.

[0147] Furthermore, in ferroelectric memory cells equipped with ferroelectric layers, the heat resistance of the ferroelectric layers is very low. Therefore, the crystallization of the semiconductor device becomes unstable at high temperatures during the manufacturing process, resulting in a decrease in the reliability of the semiconductor device. Conversely, in this embodiment, by providing multiple grains GR, the uniformity of the grain size is improved, and it is easier to align the crystal orientation with the orthorhombic crystal with the (001) orientation. That is, when the ferroelectric films FE1 and FE2 are at high temperatures due to heat treatment, the threshold temperature at which the crystal phase of these films may become monoclinic can be increased. In other words, it increases the heat resistance of the ferroelectric layer FEL of the semiconductor device during and after the manufacturing process. To this end, in this embodiment, the upper limit of the heat treatment performed to crystallize the amorphous films AM1 and AM2 can be increased not only to about 700°C, but also, for example, to 900°C. As a result, stable crystallization in the heat treatment process can be achieved. Therefore, the reliability and yield of the semiconductor device are improved.

[0148] In this embodiment, when a ferroelectric layer FEL comprising ferroelectric films FE1 and FE2 and multiple grains GR is applied to a ferroelectric memory cell MC, as described above, the increase in threshold voltage variation can be suppressed. Therefore, the problems of reduced rewrite durability and reduced retention of the ferroelectric memory cell MC can be suppressed. In other words, the technology of this embodiment can improve the performance of semiconductor devices.

[0149] (Second Embodiment)

[0150] The following will refer to Figure 18 and 19 The semiconductor device of the second embodiment is described. In the following description, the differences from the first embodiment will be mainly explained.

[0151] In the first embodiment, a ferroelectric memory cell MC with an MFIS structure is illustrated, while in the second embodiment, a memory cell with a structure called MFMIS (metal ferroelectric metal insulator semiconductor) is illustrated, wherein a ferroelectric layer FEL is applied to a transistor structure as a ferroelectric memory cell MC.

[0152] In the semiconductor device manufacturing process of this embodiment, firstly, the process is performed in accordance with reference to... Figures 4 to 6 The same process described.

[0153] Next, as Figure 18 As shown, a metal film MF2 is formed on the insulating film IF1 in region MR and on the gate insulating film GF in region LR. Subsequently, it is compared with a reference... Figure 7In the same manner as described, an amorphous film AM1 is formed on a metal film MF2 in regions MR and LR. The metal film MF2 comprises the same material as the metal film MF1 and can be formed by the same manufacturing method as the metal film MF1. Subsequently, the process is performed in accordance with the reference... Figures 8 to 12 The same process described. Figure 18 The structure shown is obtained accordingly.

[0154] Next, as Figure 19 As shown, execution and reference Figures 13 to 17 and Figure 2 The same process described. Therefore, Figure 19 The semiconductor device of the illustrated embodiment is essentially complete.

[0155] Metal film MF2 has the same function as metal film MF1. That is, when amorphous films AM1 and AM2 are crystallized, metal film MF2 has the function of orthorhombic orientation of the crystal phase of each of ferroelectric films FE1 and FE2. Therefore, the orientation of each of ferroelectric films FE1 and FE2 is controlled not only by the stress from metal film MF1, but also by the stress from metal film MF2.

[0156] Therefore, in this embodiment, compared to the first embodiment, the stress used to control the crystal phase of each of the ferroelectric films FE1 and FE2 is higher. Thus, it is possible to ensure to a greater extent that the ferroelectric films FE1 and FE2 are orthorhombic crystals.

[0157] Although the invention made by the inventors of this application has been specifically described based on embodiments, the invention is not limited to the above embodiments and various modifications can be made without departing from its spirit.

[0158] For example, the ferroelectric layer of the first embodiment may have an MFM structure and may also be applied to a capacitor-type memory formed between interconnects. The stacked films of the MFM structure include, for example, a titanium nitride (TiN) film, an HfZrO film (ferroelectric layer), and a titanium nitride (TiN) film formed sequentially on an interlayer insulating film in the interconnect layer.

[0159] Regarding the use of virtually any plural and / or singular terms in this document, those skilled in the art may appropriately convert plural to singular and / or singular to plural depending on the context and / or application. For clarity, various singular / plural substitutions may be explicitly described herein.

Claims

1. A method for manufacturing a semiconductor device, comprising: (a) Forming a first amorphous film containing hafnium, oxygen and a first element; (b) A plurality of first grains are formed on the first amorphous film, the plurality of first grains comprising a second element different from hafnium, oxygen and any of the first elements; (c) After (b), an insulating film is formed on the first amorphous film, the insulating film containing a third element different from any one of hafnium, oxygen, the first element and the second element; (d) A second amorphous film comprising hafnium, oxygen and the first element is formed on the insulating film; (e) Forming a first metal film on the second amorphous film; as well as (f) After (e), a heat treatment is performed to crystallize the first amorphous film to form an orthorhombic first ferroelectric film, and to crystallize the second amorphous film to form an orthorhombic second ferroelectric film.

2. The method according to claim 1, wherein In (b), the plurality of first grains are formed separately from each other; and In (f), the plurality of first grains serve as nuclei for the first ferroelectric film and the second ferroelectric film.

3. The method according to claim 2, wherein In (c), by forming the insulating film, the plurality of first grains react with the third element to form a plurality of second grains comprising the second element and the third element; and In (f), the plurality of second grains serve as crystal nuclei.

4. The method according to claim 2, wherein In (f), the orientation of each of the first ferroelectric film and the second ferroelectric film is controlled by stress from the first metal film.

5. The method according to claim 1, wherein (b) is performed using the sputtering method.

6. The method according to claim 5, wherein In (c), the insulating film is formed by depositing the insulating film by the ALD method at a temperature of 100°C or higher for 1 to 4 cycles.

7. The method according to claim 1, wherein The second element is aluminum.

8. The method according to claim 1, wherein In (b), the areal density of the plurality of first grains relative to the upper surface of the first amorphous film is 1 × 10⁻⁶. 13 / cm 2 Up to 1×10 15 / cm 2 Within the range.

9. The method according to claim 1, wherein In (f), microwaves are used to perform the heat treatment, and the electric field of the microwaves vibrates in the longitudinal direction relative to the upper surface of the first metal film.

Images