Semiconductor device

Abstract

A semiconductor device is provided, including: a substrate having a conductive region and an insulating region; a gate electrode including sub-gate electrodes spaced apart from each other and stacked in a first direction perpendicular to an upper surface of the substrate and extending in a second direction perpendicular to the first direction, and a gate connector connecting the sub-gate electrodes disposed on the same level; a channel structure penetrating the gate electrode and extending in the conductive region of the substrate; and a first dummy channel structure penetrating the gate electrode and extending in the insulating region of the substrate, and disposed adjacent to at least one side of the gate connector in a third direction perpendicular to the first and second directions.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of priority to Korean Patent Application No. 10-2019-0094345, filed on August 2, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] An exemplary embodiment of the present invention relates to a semiconductor device. Background Technology

[0004] There is a demand for semiconductor devices that offer reduced size and high capacity for processing large volumes of data. Therefore, to meet these requirements, the integration density of semiconductor elements included in semiconductor devices has been increased. As one method to increase the integration density of semiconductor devices, a semiconductor device with a vertical transistor structure instead of the typical planar transistor structure has been proposed. Summary of the Invention

[0005] An exemplary embodiment of the present invention provides a semiconductor device with improved reliability.

[0006] According to an exemplary embodiment of the present invention, a semiconductor device includes: a substrate having a first region and a second region; gate electrodes spaced apart from each other and stacked in the first region in a first direction perpendicular to an upper surface of the substrate, extending for different lengths in the second region in a second direction perpendicular to the first direction, and including at least one ground select gate electrode, a memory cell gate electrode, and at least one string select gate electrode stacked sequentially from the substrate; a first separation region penetrating the gate electrodes and extending in the second direction in the first and second regions, and spaced apart from each other in a third direction perpendicular to the first and second directions; a second separation region penetrating the gate electrodes and extending between the first separation regions in a second direction, and spaced apart from each other in the second region in the second direction; a lower separation region penetrating the at least one ground select gate electrode between the second separation regions, and separating the at least one ground select gate electrode together with the second separation region; a substrate insulating layer disposed in the second region in the substrate between the first and second separation regions; a channel structure penetrating the gate electrodes and extending perpendicular to the substrate in the first region; and a first pseudo-channel structure penetrating the gate electrodes and the substrate insulating layer, and extending perpendicular to the substrate on the outside of the lower separation region in a third direction.

[0007] According to an exemplary embodiment of the present invention, a semiconductor device includes: a substrate having a conductive region and an insulating region; a gate electrode including sub-gate electrodes and a gate connector, the sub-gate electrodes being spaced apart from each other and stacked in a first direction perpendicular to an upper surface of the substrate and extending in a second direction perpendicular to the first direction, the gate connector connecting the sub-gate electrodes disposed at the same level; a channel structure penetrating the gate electrode and extending in the conductive region of the substrate; and a first pseudo-channel structure penetrating the gate electrode and extending in the insulating region of the substrate, and being configured to be adjacent to at least one side of the gate connector in a third direction perpendicular to the first and second directions.

[0008] According to an exemplary embodiment of the present invention, a semiconductor device includes: a substrate having a first region and a second region; gate electrodes spaced apart from each other and stacked in the first region in a first direction perpendicular to an upper surface of the substrate, and extending for different lengths in a second direction perpendicular to the first direction, and providing pad regions in the second region; penetration separation regions penetrating the gate electrodes and extending in the first and second regions in a second direction, and spaced apart from each other in the second region in the second direction; a lower separation region penetrating at least one gate electrode including a lowermost gate electrode between the penetration separation regions; a substrate insulating layer disposed in a portion of the substrate in the second region; a channel structure penetrating the gate electrodes and extending perpendicular to the substrate in the first region; and a pseudo-channel structure penetrating at least some portions of the gate electrodes and the substrate insulating layer, extending perpendicular to the substrate in the second region, and including a first pseudo-channel structure disposed around the lower separation region adjacent to the lower separation region and a second pseudo-channel structure disposed in a regular pattern in the pad regions of the gate electrodes. Attached Figure Description

[0009] The above and other aspects, features and advantages of the present invention will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is a block diagram illustrating an exemplary embodiment of a semiconductor device according to a concept of the present invention;

[0011] Figure 2 This is an equivalent circuit diagram illustrating a cell array of a semiconductor device according to an exemplary embodiment of the present invention;

[0012] Figures 3A to 3C This is a plan view illustrating an exemplary embodiment of a semiconductor device according to a concept of the present invention;

[0013] Figures 4A to 4C This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor device according to a concept of the present invention;

[0014] Figures 5A to 6BThese are plan views and cross-sectional views illustrating exemplary embodiments of a semiconductor device according to the present invention;

[0015] Figure 7A and Figure 7B This is a plan view illustrating an exemplary embodiment of a semiconductor device according to a concept of the present invention;

[0016] Figure 8 This is a plan view illustrating an exemplary embodiment of a semiconductor device according to a concept of the present invention;

[0017] Figure 9 This is a plan view illustrating an exemplary embodiment of a semiconductor device according to a concept of the present invention;

[0018] Figure 10A and Figure 10B This is a plan view illustrating an exemplary embodiment of a semiconductor device according to a concept of the present invention;

[0019] Figure 11 This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor device according to the present invention; and

[0020] Figures 12A to 16B These are plan views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention. Detailed Implementation

[0021] Hereinafter, embodiments of the inventive concept will be described with reference to the accompanying drawings. In the drawings, for clarity, the sizes and relative sizes of layers and regions may be enlarged. The same numbers always refer to the same elements. Although different drawings illustrate variations of exemplary embodiments, these drawings are not necessarily intended to be incompatible with each other. Rather, as will be seen from the context of the detailed description below, certain features depicted and described in different drawings may be combined with other features from other drawings to produce various embodiments when the drawings and their description are considered as a whole.

[0022] Figure 1 This is a block diagram illustrating a semiconductor device according to an example embodiment.

[0023] Reference Figure 1 The semiconductor device 10 may include a memory cell array 20 and peripheral circuitry 30. Peripheral circuitry 30 may include a row decoder 32, a page buffer 34, an input and output (I / O) buffer 35, control logic 36, and a voltage generator 37. Control logic 36 can transmit address ADDR to the row decoder 32, and I / O buffer 35 can exchange data "DATA" with external devices.

[0024] Figure 2 This is an equivalent circuit diagram illustrating a cell array of a semiconductor device according to an example embodiment.

[0025] Reference Figure 2 The memory cell array 20 may include multiple memory cell strings S, each comprising a memory cell MC connected in series with each other, and a ground selection transistor GST and a string selection transistor SST1 and SST2 connected in series to both ends of the memory cell MC. The multiple memory cell strings S may be connected in parallel with bit lines BL0 to BL2 respectively. The multiple memory cell strings S may be connected together to a common source line CSL. Therefore, the multiple memory cell strings S can be arranged between multiple bit lines BL0 to BL2 and a single common source line CSL. In an example embodiment, the multiple common source lines CSL can be arranged in two dimensions.

[0026] The memory cell array 20 may further include: a ground select line GSL connected to the ground select transistor GST of each memory cell string S; and multiple word lines WL0...WLn-1, WLn connected to the memory cells MC of the memory cell string S. Additionally, a pseudo-word line DWL may be positioned below the string select line SSL1 (e.g., string select lines SSL1_1, SSL1_2, and SSL1_3) and may be connected to the memory cell MC directly below the string select transistor SST1 in the memory cell string S. In some embodiments, the memory cell MC directly below the string select transistor SST1 in a given memory cell string S may be a pseudo-memory cell.

[0027] Figures 3A to 3C This is a plan view illustrating a semiconductor device according to an example embodiment. Figure 3B It shows Figure 3A The area "R" shown, and Figure 3C Only a single memory gate electrode 130M in region "R" is shown. Figure 3A and Figure 3B For ease of explanation, only the main components of the semiconductor device 100 are shown in the diagram.

[0028] Figures 4A to 4C This is a cross-sectional view showing a semiconductor device according to an example embodiment. Figure 4A , Figure 4B and Figure 4C They show the following along Figure 3A The cross sections taken from lines I-I', II-II', and III-III'.

[0029] Reference Figures 3A to 4CThe semiconductor device 100 may include: a substrate 101 having a first region A and a second region B; a substrate insulating layer 110 disposed in the second region B within the substrate 101; a gate electrode 130 stacked on the substrate 101; a channel structure CH and a pseudo-channel structure DCH penetrating the gate electrode 130; a first separation region MS1 ​​and second separation regions MS2a and MS2b penetrating the gate electrode 130; an upper separation region SS penetrating a portion of the uppermost portion of the gate electrode 130; and a lower separation region GS penetrating a portion of at least one gate electrode 130 disposed in the lowermost portion. The channel structure CH may include a channel layer 140, a gate dielectric layer 145, a channel insulating layer 150, and a channel pad 155. The semiconductor device 100 may also include an interlayer insulating layer 120 alternately stacked on the substrate 101 with the gate electrode 130, and a cell region insulating layer 190 on the interlayer insulating layer 120 and the gate electrode 130.

[0030] In the first region A of the substrate 101, the gate electrodes 130 can be stacked vertically, and a channel structure CH can be formed therein. The first region A can correspond to Figure 1 The memory cell array 20 is shown. In the second region B, the gate electrode 130 can extend to different lengths and a pseudo-channel structure DCH can be configured. Figure 1 As shown, the second region B can electrically connect the memory cell array 20 to the peripheral circuitry 30. The second region B can be disposed on at least one end of the first region A in at least one direction (e.g., the x-direction). For example, the second region B can be configured to be adjacent to the first region A in at least one direction.

[0031] Substrate 101 may have an upper surface extending in both the x and y directions. For example, substrate 101 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, a group IV semiconductor may include silicon, germanium, or silicon-germanium. Substrate 101 may be configured as a bulk wafer or an epitaxial layer.

[0032] The substrate insulating layer 110 can be disposed in the second region B of the substrate 101. For example... Figure 3A and Figure 3BAs shown, the substrate insulating layer 110 may be disposed between the first separation region MS1, the second intermediate separation region MS2a, the lower separation region GS, and the second auxiliary separation region MS2b. The substrate insulating layer 110 may not extend along the x-direction to the spacing region between the second intermediate separation regions MS2a. The substrate insulating layer 110 may extend along the x-direction to a portion of the spacing region between the second auxiliary separation regions MS2b (e.g., the spacing region between the adjacent second auxiliary separation regions MS2b closest to the first region A), and the substrate insulating layer 110 may not extend to other spacing regions. Alternatively, in the example embodiment, the substrate insulating layer 110 may extend along the x-direction to all spacing regions between the second auxiliary separation regions MS2b.

[0033] For example, the substrate insulating layer 110 can be formed using a shallow trench isolation (STI) process. The substrate insulating layer 110 can extend from the upper surface of the substrate 101 to a specific depth within the substrate 101. The substrate insulating layer 110 can be formed of an insulating material and can include, for example, oxides, nitrides, or combinations thereof. The substrate insulating layer 110 can also be described as being included within an insulating region of the substrate 101, and in this case, the substrate 101 can include an insulating region corresponding to the substrate insulating layer 110 and a conductive region formed through a semiconductor region.

[0034] Gate electrodes 130 may be spaced apart from each other and stacked vertically on a first region A, and may extend from the first region A to a second region B at different lengths. Gate electrodes 130 may include: a ground select gate electrode 130G, which is included in the gate of a ground select transistor GST; a memory cell gate electrode 130M, which is included in a plurality of memory cells MC; and a string select gate electrode 130S, which is included in the gates of string select transistors SST1 and SST2. The number of memory cell gate electrodes 130M included in the memory cells MC can be determined according to the capacity of the semiconductor device 100. In an example embodiment, the number of string select gate electrodes 130S of string select transistors SST1 and SST2 may be one or two, and the number of ground select gate electrodes 130G of the ground select transistor GST may be one or two. Each of the string select gate electrodes 130S and the ground select gate electrodes 130G may have the same or different structure as the memory cell gate electrode 130M of the memory cells MC. One or more of the gate electrodes 130 (e.g., memory cell gate electrodes 130M adjacent to ground select gate electrode 130G and / or memory cell gate electrodes 130M adjacent to string select gate electrode 130S) can be configured as dummy gate electrodes.

[0035] like Figure 3A and Figure 3CAs shown, the gate electrode 130 can be divided in the y-direction by a first separation region MS1 ​​extending in the x-direction. The gate electrode 130 between a pair of first separation regions MS1 can form a single memory block, but the range of examples of memory blocks is not limited thereto. A portion of the gate electrode 130 (e.g., the memory cell gate electrode 130M) can be formed as a single layer within a single memory block. For example, as... Figure 3C As shown, each of the gate electrodes 130M in the memory cell may include four sub-gate electrodes 130M_S1, 130M_S2, 130M_S3, and 130M_S4 extending longitudinally in the x-direction. These four sub-gate electrodes 130M_S1, 130M_S2, 130M_S3, and 130M_S4 can be interconnected via gate connectors GC and can be configured as a single layer. The gate connectors GC are located along the x-direction in the space between the second separation regions MS2a and MS2b. The gate connectors GC may refer to the region of the gate electrode 130 where the gate electrodes 130 are horizontally connected at the same level. The string select gate electrode 130S can be divided into four sub-gate electrodes by a first separation region MS1 ​​and a pair of second separation regions MS2a and MS2b between the first separation regions MS1. For example, the four sub-gate electrodes of the string select gate electrode 130S may not be interconnected via gate connectors GC in the space between the second separation regions MS2a and MS2b. The ground selection gate electrode 130G may include sub-gate electrodes that are connected to each other by gate connectors GC between some portions of the second separation regions MS2a and MS2b, and may be divided into two sub-gate electrodes by the lower separation region GS between the second intermediate separation regions MS2a.

[0036] like Figure 4C As shown, the gate electrode 130 can extend longitudinally to varying lengths in the x-direction and can form a stepped portion in the form of a staircase in the second region B of the substrate 101, and can provide a pad area in which the gate electrode 130 in the lower part is exposed upwards. For example, the pad area of ​​the gate electrode 130 can be a portion of the gate electrode 130 that does not overlap with one or more other gate electrodes 130 disposed above the gate electrode 130 in the z-direction. In the example embodiment, the gate electrode 130 can also form a stepped portion in the y-direction. Each gate electrode 130 can be connected to a contact plug (not shown) in its pad area, thus the gate electrode 130 can be connected to the wiring structure in the upper part. In the pad area, the gate electrode 130 can have a region in which the thickness of the gate electrode 130 increases to stably connect to the contact plug, but the example embodiment is not limited to this.

[0037] The gate electrode 130 may include a metallic material, such as tungsten (W). In an example embodiment, the gate electrode 130 may include polycrystalline silicon or a metal silicide material. In an example embodiment, the gate electrode 130 may also include a diffusion barrier, and the diffusion barrier may include tungsten nitride (WN), tantalum nitride (TaN), titanium carbide (TiN), or a combination thereof.

[0038] Interlayer insulating layers 120 may be disposed between gate electrodes 130. Interlayer insulating layers 120 may also be spaced apart from each other in a direction perpendicular to the upper surface of substrate 101, and similar to gate electrodes 130, may extend longitudinally in the x-direction. Interlayer insulating layers 120 may comprise insulating materials such as silicon oxide or silicon nitride.

[0039] The first separation region MS1 ​​and the second separation regions MS2a and MS2b may extend longitudinally in the x-direction within the first region A and the second region B. The first separation region MS1 ​​and the second separation regions MS2a and MS2b may be arranged parallel to each other. The first separation region MS1 ​​and the second separation regions MS2a and MS2b may form a specific pattern in the y-direction, and the second separation regions MS2a and MS2b may be linearly spaced apart from each other in the x-direction. The first separation region MS1 ​​and the second separation regions MS2a and MS2b may be configured to penetrate the penetration separation regions of all gate electrodes 130 stacked on the substrate 101 and may be connected to the substrate 101. For example, the lower surface of each of the first separation region MS1 ​​and the second separation regions MS2a and MS2b may contact the upper surface of the substrate 101.

[0040] The second separation regions MS2a and MS2b may include a second intermediate separation region MS2a disposed between a pair of first separation regions MS1 and a second auxiliary separation region MS2b disposed between the first separation region MS1 ​​and the second intermediate separation region MS2a. The second intermediate separation region MS2a may be disposed across the first region A and the second region B, and the second auxiliary separation region MS2b may be disposed only in the second region B. The second intermediate separation regions MS2a may extend from the first region A to a portion of the second region B as a single region, and may be spaced apart from each other in the second region B, and may extend again as a single region. For example, each second intermediate separation region MS2a may include two segments extending longitudinally in the x-direction and adjacent to each other, and the short sidewall of the first segment (e.g., the segment extending longitudinally from the first region A to a portion of the second region B) may face the short sidewall of the second segment of the second separation region MS2a (e.g., the segment extending longitudinally in the second region B). The second auxiliary separation regions MS2b may be linearly separated from each other by a certain distance, and multiple second auxiliary separation regions MS2b may be provided. For example, each of the second auxiliary separation regions MS2b may include multiple segments extending longitudinally in the x-direction and adjacent to each other. In some embodiments, the first segment of the second auxiliary separation region MS2b (e.g., the segment closest to the first region A) may have a first short sidewall facing the first region A and a second short sidewall facing the first short sidewall of the adjacent second segment of the second auxiliary separation region MS2b. The second segment of the second auxiliary separation region MS2b may include a first short sidewall facing the first segment and a second short sidewall facing the first short sidewall of the adjacent third segment of the second auxiliary separation region MS2b. The remaining segments of the second auxiliary separation region MS2b may be arranged similarly. The arrangement order and number of the first separation region MS1 ​​and the second separation regions MS2a and MS2b are not limited to... Figure 3A The example shown. For instance, in the example embodiment, the second separation regions MS2a and MS2b may be configured as four or more columns in the y-direction between a pair of first separation regions MS1.

[0041] like Figure 4A and Figure 4B As shown, the first separation region MS1 ​​and the second separation regions MS2a and MS2b may include a separation layer 107. The separation layer 107 may consist only of insulating material, or it may include both insulating and conductive materials. In an example embodiment, when the separation layer 107 includes a conductive layer spaced apart from the gate electrode 130 by an insulating layer, the first separation region MS1 ​​may include a reference layer. Figure 2The described common-source line CSL, and the second separation regions MS2a and MS2b may include a pseudo-common-source line. In this case, the pseudo-common-source line may be in a floating state, in which the pseudo-common-source line is not connected to the element for driving the semiconductor device 100 and / or no electrical signal is applied. In an example embodiment, when the separation layer 107 consists only of an insulating layer, the common-source line CSL may be disposed in the substrate 101, or may be disposed on the substrate 101 to contact the upper surface of the substrate 101.

[0042] The upper separation region SS can extend longitudinally in the x-direction between the first separation region MS1 ​​and the second intermediate separation region MS2a in the first region A. The upper separation region SS can be arranged side by side with the second auxiliary separation region MS2b. The upper separation region SS can penetrate some portions of the gate electrode 130, including the string selection gate electrode 130S. The string selection gate electrode 130S separated by the upper separation region SS can form different string selection lines SSL1_1, SSL1_2, SSL1_3, SSL2_1, SSL2_2, and SSL2_3 (see...). Figure 2 In some embodiments, the upper separation region SS may also penetrate the uppermost of the memory cell gate electrodes 130M. In this embodiment, the uppermost of the memory cell gate electrodes 130M separated by the upper separation region SS may be a dummy gate electrode.

[0043] The upper separation region SS may include the upper insulating layer 103. For example... Figure 4B As shown, the upper insulating layer 103 can separate the three gate electrodes 130 (e.g., the uppermost of the two string select gate electrodes 130S and the memory cell gate electrode 130M) from each other in the y-direction. In the example embodiment, the number of gate electrodes 130 separated from each other by the upper insulating layer 103 can vary.

[0044] The lower separation region GS can be positioned at the same level as the ground selection gate electrode 130G located at the lowest part. The lower separation region GS and the ground selection gate electrode 130G can have the same thickness. For example, the upper surfaces of the lower separation region GS and the ground selection gate electrode 130G can be coplanar, and the lower surfaces of the lower separation region GS and the ground selection gate electrode 130G can be coplanar. When referring to orientation, layout, position, shape, size, amount, or other measures, terms such as “same,” “equal,” “planar,” or “coplanar” as used herein do not necessarily mean exactly the same orientation, layout, position, shape, size, amount, or other measures, but are intended to cover substantially the same orientation, layout, position, shape, size, amount, or other measures, for example, that may vary due to acceptable variations in the manufacturing process. Unless the context or other description otherwise indicates, the term “substantially” may be used herein to emphasize this meaning. For example, items described as "substantially identical", "substantially equal", or "substantially planar" can be completely identical, equal, or planar, or can be completely identical, equal, or planar within an acceptable range of variation, for example, that would occur due to manufacturing processes.

[0045] The ground selection gate electrode 130G can be divided into two parts in the y-direction between a pair of first separation regions MS1. For example, the first part can be located between the first separation region MS1 ​​and the lower separation region GS, and the second part can be located between the lower separation region GS and the second separation region MS1. The lower separation region GS can connect the second intermediate separation regions MS2a to each other together with the spacer region between the second intermediate separation regions MS2a.

[0046] like Figure 4A As shown, the lower separation region GS may include a lower insulating layer 170. The lower insulating layer 170 may be formed of, for example, silicon oxide, and may be formed of the same material as the interlayer insulating layer 120. At least some portions of the interlayer insulating layer 120 and the gate electrode 130 above the lower separation region GS may have a recessed portion DP formed in the upper portion of the lower separation region GS towards the center of the lower separation region GS. In regions (e.g., in the z-direction) away from the lower separation region GS, the interlayer insulating layer 120 and the gate electrode 130 may include a recessed portion DP with a smooth curvature or may not include a recessed portion DP. For example, the interlayer insulating layer 120 and the gate electrode 130 closer to the lower separation region GS may have a larger recessed portion DP, while the interlayer insulating layer 120 and the gate electrode 130 further away from the lower separation region GS may have a smaller recessed portion DP or no recessed portion DP. In an example embodiment, depending on the process of forming the lower separation region GS, the recessed portion DP may not be formed, and the interlayer insulating layer 120 on the lower separation region GS may have a planar upper surface.

[0047] When viewed in a plan view, the channel structures CH can form rows and columns and can be spaced apart from each other on the first region A. The channel structures CH can be arranged in a lattice pattern or in a zigzag pattern in one direction. Each of the channel structures CH can be cylindrical and can have sloping side surfaces, and has a width that decreases toward the substrate 101 depending on the aspect ratio. In an example embodiment, the channel structure CH disposed on one end of the first region A adjacent to the second region B can be a pseudo-channel. The channel structure CH overlapping with the upper separation region SS can also be a pseudo-channel. In this case, each of the pseudo-channel DCH can have the same or similar structure as each of the channel structures CH and can be formed simultaneously with the channel structures CH by the same process, but may not have substantial functionality in the semiconductor device 100. For example, the pseudo-channel structure DCH is not functional for read or write operations (e.g., the pseudo-channel structure DCH may not be electrically connected to the bit line contacts, and therefore may not be connected to the bit lines).

[0048] Reference Figure 4C In the enlarged view, the channel layer 140 can be disposed in the channel structure CH. In the channel structure CH, the channel layer 140 can have an annular shape surrounding the channel insulating layer 150 disposed therein; however, in an example embodiment, without the channel insulating layer 150, the channel layer 140 can have a cylindrical or prismatic shape. The channel layer 140 can be connected to the epitaxial layer 105 disposed in the lower part of the channel structure CH. The channel layer 140 can include a semiconductor material such as polycrystalline silicon or monocrystalline silicon, and the semiconductor material can be an undoped material or a material including p-type or n-type impurities. The channel structure CH, linearly arranged in the y-direction, can be connected to different bit lines BL0 to BL2 (see [reference needed]) depending on the arrangement of the upper wiring structure connected to the channel pad 155. Figure 2 ).

[0049] The channel pad 155 may be disposed in the upper part of the channel layer 140 in the channel structure CH. The channel pad 155 may cover the upper surface of the channel insulating layer 150 and may be electrically connected to the channel layer 140. The channel pad 155 may include, for example, doped polysilicon.

[0050] A gate dielectric layer 145 may be disposed between the gate electrode 130 and the channel layer 140. Although not shown in detail, the gate dielectric layer 145 may include a tunneling layer, a charge storage layer, and a barrier layer stacked sequentially from the channel layer 140. The tunneling layer can tunnel charge to the charge storage layer. For example, the tunneling layer may include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or combinations thereof. The charge storage layer may be a charge trapping layer or a floating gate conductive layer. The barrier layer may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), a high-k dielectric material, or combinations thereof. In an example embodiment, at least a portion of the gate dielectric layer 145 may extend horizontally along the gate electrode 130.

[0051] The epitaxial layer 105 may be disposed on the substrate 101 at the lower end of the channel structure CH, and may be disposed on the side surface of at least one gate electrode 130. The epitaxial layer 105 may be disposed in a recessed region of the substrate 101. The height of the upper surface of the epitaxial layer 105 may be higher than the upper surface of the lowermost gate electrode 130, and may be lower than the lower surface of the gate electrode 130 above it (e.g., the gate electrode 130 is directly above the lowermost gate electrode 130), but the exemplary embodiments are not limited thereto. In the exemplary embodiments, the epitaxial layer 105 may not be provided, and in this case, the channel layer 140 may be directly connected to the substrate 101.

[0052] A pseudo-channel structure DCH can be disposed in the second region B, and each of the pseudo-channel structures DCH can have the same or similar structure as each of the channel structures CH, but the pseudo-channel structures DCH may not have substantial functionality in the semiconductor device 100. The pseudo-channel structures DCH can penetrate the substrate insulating layer 110 and can be connected to the substrate 101. For example, the pseudo-channel structures DCH can extend through the lower surface of the substrate insulating layer 110. The pseudo-channel structures DCH may include: a first pseudo-channel structure DCH1 disposed on the outer side of the lower separation region GS in the y direction; a second pseudo-channel structure DCH2 formed in rows and columns and disposed in a regular pattern in the pad area of ​​the gate electrode 130; and a third pseudo-channel structure DCH3 disposed along the x direction in at least a portion of the spacer region between the second auxiliary separation regions MS2b. As described above, the channel structures CH may also include pseudo-channel structures in the first region A.

[0053] The first pseudo-channel structure DCH1 can be disposed on both sides of the lower separation region GS in the y-direction. The first pseudo-channel structure DCH1 can be disposed between adjacent second pseudo-channel structures DCH2 in the x-direction. The maximum diameter (or width) of each of the first pseudo-channel structures DCH1 can be greater than the maximum diameter (or width) of each of the channel structures CH, the second pseudo-channel structures DCH2, and the third pseudo-channel structure DCH3. For example, the maximum diameter of the first pseudo-channel structure DCH1 can be a second width W2 greater than the first width W1 (which is the maximum diameter of each of the channel structures CH), and the second width W2 can be greater than the third width W3 (which is the maximum diameter of each of the third pseudo-channel structures DCH3). The second width W2 can also be greater than the maximum diameter of each of the second pseudo-channel structures DCH2. For example, the first width W1 can be in the range of approximately 50 nm to 150 nm, and the second width W2 can be in the range of approximately 120 nm to 220 nm. Each of the channel structure CH, the second pseudo-channel structure DCH2, and the third pseudo-channel structure DCH3 can have a circular or approximately circular shape, while each of the first pseudo-channel structures DCH1 can have a shape in which the width along the y-direction is greater than the width along the x-direction. For example, each of the first pseudo-channel structures DCH1 can be elliptical, elongated, rectangular, or oval.

[0054] The second pseudo-channel structure DCH2 can be arranged according to a pattern. When the smallest unit surrounded by the first separation region MS1 ​​and the second separation regions MS2a and MS2b in the pad area is called a unit pad area, the second pseudo-channel structure DCH2 can be set at the four corners of a single unit pad area, and four second pseudo-channel structures DCH2 can be repeatedly set in each unit pad area. The maximum diameter of each of the second pseudo-channel structures DCH2 can be smaller than the maximum diameter of each of the first pseudo-channel structures DCH1, and can be equal to or smaller than the maximum diameter of each of the third pseudo-channel structures DCH3.

[0055] The third pseudo-channel structure DCH3 can be linearly arranged together with the first pseudo-channel structure DCH1 in the y-direction, and can be arranged along the x-direction in the interval between the second auxiliary separation regions MS2b. In an example embodiment, the third pseudo-channel structure DCH3 can be linearly arranged together with the first pseudo-channel structure DCH1 only in the y-direction, and can be arranged in other intervals in the second auxiliary separation region MS2b without being arranged along the x-direction. In this case, as... Figure 3A As shown, the substrate insulating layer 110 may not extend into the other spacer regions. In the example embodiment, the third pseudo-channel structure DCH3 may be disposed along the x-direction in all spacer regions between the second auxiliary separation regions MS2b.

[0056] Since the pseudo-channel structure DCH penetrates the substrate insulating layer 110, the lower end of the pseudo-channel structure DCH can be positioned at a level lower than the lower end of the channel structure CH. Therefore, the height of the pseudo-channel structure DCH can be greater than the height of each of the channel structures CH. Furthermore, at least a portion of the side surface of each of the epitaxial layers 105 in the pseudo-channel structure DCH can be surrounded by the substrate insulating layer 110. For example, the upper surface of the epitaxial layer 105 of the pseudo-channel structure can be lower than the upper surface of the substrate insulating layer 110, and the lower surface of the epitaxial layer 105 of the pseudo-channel structure can be lower than the lower surface of the substrate insulating layer 110. When the diameter of each of the epitaxial layers 105 is relatively large, each of the epitaxial layers 105 in the pseudo-channel structure DCH can have a relatively low height or a relatively reduced thickness, depending on the diameters of the first pseudo-channel structure DCH1, the second pseudo-channel structure DCH2, and the third pseudo-channel structure DCH3. For example, each of the epitaxial layers 105 in the channel structure CH may have a first height H1, each of the epitaxial layers 105 in the first pseudo-channel structure DCH1 may have a second height H2, and each of the epitaxial layers 105 in the third pseudo-channel structure DCH3 may have a third height H3, wherein the third height H3 is the same as or lower than the first height H1 and higher than the second height H2.

[0057] The dummy channel structure DCH can be configured to support a stacked structure including the interlayer insulating layer 120 to prevent collapse during the manufacturing process of the semiconductor device 100. The region where the lower separation region GS is located may be susceptible to collapse that can occur during the manufacturing process of the semiconductor device 100. In an example embodiment, although the dummy channel structure DCH may not overlap with the lower separation region GS, collapse in the upper part of the lower separation region GS can be prevented by placing the dummy channel structure DCH on both sides of the lower separation region GS.

[0058] Furthermore, since there are fewer restrictions on the size of each of the first pseudo-channel structures DCH1 compared to a configuration where the first pseudo-channel structure DCH1 overlaps with the lower separation region GS, each of the first pseudo-channel structures DCH1 can have a relatively larger size, and defects such as misalignment can be prevented. In addition, since the first pseudo-channel structure DCH1 is spaced apart from the center of the recessed portion DP, defects caused by the structure of the recessed portion DP can be prevented. Furthermore, since the pseudo-channel structure DCH penetrates the substrate insulating layer 110, and the lower end of the pseudo-channel structure DCH can be positioned at a lower level than the channel structure CH, defects such as short circuits or leakage current between the epitaxial layer 105 and the gate electrode 130 can be prevented.

[0059] The cell region insulating layer 190 can be disposed on the stacked structure of the gate electrode 130 and can include insulating materials such as silicon oxide and silicon nitride.

[0060] Figures 5A to 6B These are plan views and cross-sectional views illustrating a semiconductor device according to an example embodiment. Figure 5A and Figure 6A It shows the corresponding Figure 3B The area shown, and Figure 5B and Figure 6B It shows the corresponding Figure 4A District of the district shown.

[0061] Reference Figure 5A and Figure 5B In semiconductor device 100a, the pseudo-channel structure DCHa may include only the first pseudo-channel structure DCH1 and the second pseudo-channel structure DCH2. Therefore, with Figures 3A to 4C Unlike the example embodiments described above, the pseudo-channel structure DCHa may not include the third pseudo-channel structure DCH3. In this case, in substrate 101, substrate insulating layer 110a may not extend into the region between the second intermediate separation regions MS2a that are adjacent to each other in the x-direction, and may not extend into the region between the second auxiliary separation regions MS2b that are adjacent to each other in the x-direction.

[0062] Reference Figure 6A and Figure 6B ,and Figures 3A to 4C Unlike the example embodiment shown, in semiconductor device 100b, substrate insulating layer 110b can extend to the region between second auxiliary separation regions MS2b that are adjacent to each other in the x-direction, and can also extend to the region between second intermediate separation regions MS2a that are adjacent to each other in the x-direction. Therefore, substrate insulating layer 110b can overlap with lower separation region GS in a plane or in the z-direction.

[0063] Figure 7A and Figure 7B This is a plan view illustrating a semiconductor device according to an example embodiment. Figure 7A and Figure 7B Showing the corresponding Figure 3B District of the district shown.

[0064] Reference Figure 7A ,and Figure 3BUnlike the example embodiment shown, in semiconductor device 100c, each of the second pseudo-channel structures DCH2 in the pseudo-channel structure DCHc can have an approximately oval rather than circular shape. The four second pseudo-channel structures DCH2 disposed in a single cell pad area can each be configured to be tilted in a direction toward the center of the cell pad area. Even in this case, the maximum diameter of each of the first pseudo-channel structures DCH1 can be larger than the maximum diameter of each of the second pseudo-channel structures DCH2. In the example embodiment, the shapes of the first pseudo-channel structure DCH1, the second pseudo-channel structure DCH2, and the third pseudo-channel structure DCH3 included in the pseudo-channel structure DCHc can be changed.

[0065] Reference Figure 7B ,and Figure 3B Unlike the example embodiments, in semiconductor device 100d, each of the first pseudo-channel structures DCH1 of the pseudo-channel structure DCHc can be configured to have an extended length. Each of the first pseudo-channel structures DCH1 can have an extended maximum diameter W4, such that the first pseudo-channel structure DCH1 can be adjacent to the extension lines in the y-direction of the two ends of the second separation regions MS2a and MS2b between the second auxiliary separation region MS2b and the second intermediate separation region MS2a. Therefore, in a single cell pad area, the first pseudo-channel structure DCH1 can overlap with each of the second pseudo-channel structures DCH2 in the x-direction. In the example embodiment, the size and shape of each of the first pseudo-channel structures DCH1 can vary within a range in which the first pseudo-channel structure DCH1 is spaced apart from the second pseudo-channel structure DCH2 on both sides.

[0066] Figure 8 This is a plan view illustrating a semiconductor device according to an example embodiment.

[0067] Reference Figure 8 In semiconductor device 100e, in Figure 8 To the right of the lower separation region GS, the second intermediate separation region MS2a may not extend as a single region, and may be spaced apart from each other in at least one region in the x-direction, and may be connected with... Figure 3A The example embodiments described herein employ a plurality of second intermediate separation regions MS2a. As the number of gate electrodes 130 in the semiconductor device 100e increases, the above configuration can enhance the ability to prevent collapse of the stacked structure, including the interlayer insulating layer 120, during the manufacturing process. Therefore, in order to separately select the gate electrodes 130G, a lower separation region GSa can also be disposed in a region in which the second intermediate separation regions MS2a are spaced apart from each other.

[0068] In an example embodiment, the first pseudo-channel structure DCH1 can be disposed on the outer side of the spacing region between the second intermediate separation regions MS2a in the higher region (e.g., the region closer to the first region A) of the stacked structure of the gate electrode 130, and may not be disposed on the outer side of the spacing between the second intermediate separation regions MS2a in the lower region (e.g., the region furthest from the first region A) of the stacked structure. Therefore, the first pseudo-channel structure DCH1 can be disposed only on both sides of the lower separation region GS adjacent to the first region A, and may not be disposed on both sides of other lower separation regions GSa. The above configuration can be based on the arrangement of the contact plug MCP, and will be referred to later. Figure 10A and Figure 10B The configuration will be described in more detail below.

[0069] Figure 9 This is a plan view illustrating a semiconductor device according to an example embodiment.

[0070] Reference Figure 9 In semiconductor device 100f, the arrangement of the second pseudo-channel structure DCH2 of pseudo-channel structure DCHf can be consistent with... Figure 3A The example shown is different. The second pseudo-channel structure DCH2 can be disposed along the end of the gate electrode 130. For example, the second pseudo-channel structure DCH2 can be disposed across the end of the gate electrode 130, thereby bridging the end of the gate electrode 130. Therefore, two second pseudo-channel structures DCH2 can be arithmetically located in a single cell pad area, instead of four second pseudo-channel structures DCH2 disposed in a single cell pad area. For example, each second pseudo-channel structure DCH2 can be configured such that the first half of the second pseudo-channel structure DCH2 is located in the first pad area, and the second half of the second pseudo-channel structure DCH2 is located in the second pad area. Even in this case, the first pseudo-channel structure DCH1 can be disposed on the outside of the lower separation region GS in the y direction. Therefore, in the example embodiment, with Figure 3A Compared to the example embodiment shown, each of the first pseudo-channel structures DCH1 can have an extended dimension in the x-direction.

[0071] Figure 10A and Figure 10B This is a plan view illustrating a semiconductor device according to an example embodiment.

[0072] Reference Figure 10A The semiconductor device 100g may further include a contact plug MCP disposed in the stepped portion (e.g., pad area) of the gate electrode 130. The contact plug MCP connects the gate electrode 130 to a wiring structure disposed in the upper portion and may be formed of a conductive material. Figure 10AAs shown, the contact plug MCP may not be located in the pad area (where the lower separation region GS is located) adjacent to the second intermediate separation region MS2a in the y-direction. For example, the contact plug MCP may be arranged in a regular pattern, and the contact plug MCP may not be located in the memory gate electrode 130M located in the uppermost portion surrounding the first pseudo-channel structure DCH1. Therefore, it can be ensured that the area containing the first pseudo-channel structure DCH1 is located. In this case, since the memory gate electrode 130M in the uppermost portion can form a single layer between the pair of first separation regions MS1, the memory gate electrode 130M can be electrically connected to the wiring structure through the contact plug MCP located in other pad areas.

[0073] Reference Figure 10B ,and Figure 10A Unlike the example embodiment shown, in the semiconductor device 100h, in the cell pad area adjacent to the region where the lower separation region GS is disposed in the y-direction, the contact plug MCP may be disposed in the cell pad area on one side, and the contact plug MCP may not be disposed in the cell pad area on the other side. Therefore, the first pseudo-channel structure DCH1 may not be disposed on the side of the cell pad area where the contact plug MCP is disposed, and may only be disposed on the other side of the cell pad area where the contact plug MCP is not disposed.

[0074] Figure 11 This is a cross-sectional view showing a semiconductor device according to an example embodiment.

[0075] Reference Figure 11 The semiconductor device 100i may include a memory cell region (CELL) and a peripheral circuit region (PERI). The memory cell region (CELL) may be disposed on the upper surface of the peripheral circuit region (PERI). Alternatively, in an example embodiment, the memory cell region (CELL) may be disposed on the lower surface of the peripheral circuit region (PERI).

[0076] The memory cell area (CELL) may include, for example, in Figures 3A to 4C The example embodiment shown includes a substrate 101, a substrate insulating layer 110, a gate electrode 130, a channel structure CH and a pseudo-channel structure DCH, a first separation region MS1, second separation regions MS2a and MS2b, and a lower separation region GS. The memory cell region CELL may also have a reference... Figures 5A to 10B One or more structures described in the above example embodiments.

[0077] The peripheral circuit area PERI may include a substrate 201, a circuit device 220 disposed on the substrate 201, a circuit contact plug 270, and wiring 280.

[0078] The substrate 201 may have an upper surface extending in both the x and y directions. The substrate 201 may include a device isolation layer, and an active region may be defined within the substrate 201. Source / drain regions 205, including impurities, may be disposed within a portion of the active region. For example, the substrate 201 may include a semiconductor material such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor.

[0079] The circuit device 220 may include a planar transistor. Each of the circuit devices 220 may include a circuit gate insulating layer 222, a spacer layer 224, and a circuit gate electrode 225. Source / drain regions 205 may be disposed on both sides of the circuit gate electrode 225 in the substrate 201.

[0080] A peripheral insulating layer 290 can be disposed on a circuit arrangement 220 on a substrate 201. A circuit contact plug 270 can penetrate the peripheral insulating layer 290 and can be connected to the source / drain region 205. Electrical signals can be applied to the circuit arrangement 220 through the circuit contact plug 270. In a region not shown, the circuit contact plug 270 can also be connected to the circuit gate electrode 225. Wiring 280 can be connected to the circuit contact plug 270 and can be configured as multiple layers. The gate electrode 130 of the memory cell region (CELL) can be connected to the circuit arrangement 220 of the peripheral circuit region (PERI) through a through-hole region penetrating the PERI and through-vias formed in the through-hole region.

[0081] In the semiconductor device 100i, a peripheral circuit region (PERI) can be fabricated, and a substrate 101 for a memory cell region (CELL) can be formed on top of the PERI, thereby fabricating the memory cell region (CELL). The size of the substrate 101 can be the same as or smaller than the size of the base substrate 201.

[0082] Figures 12A to 16B These are plan views and cross-sectional views illustrating a method of manufacturing a semiconductor device according to an example embodiment. Figures 12A to 16B The sectional view in the diagram shows the corresponding Figure 4A District of the district shown.

[0083] Reference Figure 12A and Figure 12B A substrate insulating layer 110 can be formed in the second region B of the substrate 101.

[0084] Trench regions can be formed by anisotropic etching of a portion of substrate 101. The width of each trench region can decrease downwards. For example, the width of each trench region can be narrower closer to the lower surface of substrate 101 and wider closer to the upper surface of substrate 101. The trench regions can be filled with an insulating material, and a planarization process can be performed along the upper surface of substrate 101 to form a substrate insulating layer 110. Through the planarization process, the upper surface of the substrate insulating layer 110 can be coplanar with the upper surface of substrate 101.

[0085] Except for the region where the first separation region MS1 ​​and the second separation regions MS2a and MS2b are provided, a substrate insulating layer 110 may be provided in the second region B of the substrate 101. In an example embodiment, when a device isolation layer defining an active region of the substrate 101 is formed in a region not shown in the figure, the substrate insulating layer 110 may be formed together with the device isolation layer in the same process.

[0086] Reference Figure 13A and Figure 13B The sacrificial layer 180 and the interlayer insulating layer 120 can be stacked alternately on the substrate 101. Some portions of the sacrificial layer 180 and the interlayer insulating layer 120 can be removed, so that the sacrificial layer 180 can extend to different lengths in the x direction, and can form a lower separation region GS and an upper separation region SS.

[0087] The gate electrode 130 can be used to replace the sacrificial layer 180 in subsequent processes. The sacrificial layer 180 can be formed of a material that has etch selectivity relative to the interlayer insulating layer 120. For example, the interlayer insulating layer 120 can be formed of at least one of silicon oxide and silicon nitride, and the sacrificial layer 180 can be formed of a material different from the material of the interlayer insulating layer 120, selected from silicon, silicon oxide, silicon carbide, and silicon nitride. In an example embodiment, the thickness of the interlayer insulating layer 120 can be non-uniform. For example, the lowermost interlayer insulating layer 120 can have a relatively thin thickness, and the uppermost interlayer insulating layer 120 can have a relatively thick thickness. The thickness of the sacrificial layer 180 and the interlayer insulating layer 120, as well as the number of layers of the sacrificial layer 180 and the interlayer insulating layer 120, can be varied.

[0088] In the second region B, photolithography and etching processes can be repeatedly performed on the sacrificial layer 180 to allow the upper sacrificial layer 180 to extend less than the lower sacrificial layer 180. Therefore, the sacrificial layer 180 can have a staircase shape. In an example embodiment, material for forming the sacrificial layers 180 can also be deposited in such a region that the ends of each of the sacrificial layers 180 can have increased thickness: in this region, the lower sacrificial layer 180 can be exposed by extending further than the sacrificial layer 180 in the upper region.

[0089] After forming the bottommost sacrificial layer 180, a patterning process and a process for depositing insulating material can be performed such that the lower separation region GS may include a lower insulating layer 170. The lower insulating layer 170 may be formed of a material having etch selectivity relative to the sacrificial layer 180. In an example embodiment, the lower separation region GS may be formed of the material of the interlayer insulating layer 120 by removing the sacrificial layer 180 from the lower separation region GS and forming an interlayer insulating layer 120 thereon. Where a planarization process is not performed on the interlayer insulating layer 120, the upper interlayer insulating layer 120 may have, for example, a patterning process and a deposition process of insulating material, such as a lower insulating layer 170. Figure 13B The recessed portion DP is shown. When a planarization process is performed on the interlayer insulation layer 120 in the upper part, the recessed portion DP may not be formed.

[0090] The upper separation region SS can extend longitudinally in the x-direction and can extend from a portion of the first region A to the second region B. The region where the upper separation region SS is formed can be exposed using a mask layer, and a specific number of sacrificial layers 180 and interlayer insulating layers 120 can be removed from the uppermost portion. For example... Figure 4B The upper separation region SS can extend further downward than the region where the string select gate electrode 130S is disposed. Insulating material can be deposited in the region where the sacrificial layer 180 and interlayer insulating layer 120 have been removed, and an upper insulating layer 103 can be formed. The upper insulating layer 103 can be formed of a material having etch selectivity relative to the sacrificial layer 180, and can be formed of, for example, the same material as the interlayer insulating layer 120.

[0091] A unit area insulation layer 190 can be formed in the upper part of a stacked structure that covers the sacrificial layer 180 and the interlayer insulation layer 120.

[0092] Reference Figure 14A and Figure 14B This can form a channel structure CH and a pseudo-channel structure DCH that are stacked structures that penetrate the sacrificial layer 180 and the interlayer insulating layer 120.

[0093] The channel structure CH and the pseudo-channel structure DCH can be formed by anisotropic etching of the sacrificial layer 180 and the interlayer insulating layer 120, and they can be formed as vias. Due to the height of the stacked structure, the sidewalls of the channel structure CH and the pseudo-channel structure DCH may not be perpendicular to the upper surface of the substrate 101. The channel structure CH can be formed in a first region A of the substrate 101, and the pseudo-channel structure DCH can be formed in a second region B. The pseudo-channel structure DCH can be configured to penetrate at least a portion of the substrate insulating layer 110. In an example embodiment, the channel structure CH and the pseudo-channel structure DCH can be configured to recess a portion of the substrate 101. Alternatively, in an example embodiment, the pseudo-channel structure DCH may not completely penetrate the substrate insulating layer 110 and may only extend into the substrate insulating layer 110, such that the pseudo-channel structure DCH does not contact the substrate 101.

[0094] An epitaxial layer 105, at least a portion of a gate dielectric layer 145, a channel layer 140, a channel insulating layer 150, and a channel pad 155 can be formed in the channel structure CH and the pseudo-channel structure DCH. When other pseudo-channel structures (not shown) are provided in the first region A together with the channel structure CH in addition to the pseudo-channel structure DCH, the pseudo-channel structure can be formed together with the channel structure CH in the current stage.

[0095] The epitaxial layer 105 can be formed using a selective epitaxial growth (SEG) process. The epitaxial layer 105 can be a single epitaxial layer or multiple epitaxial layers. The epitaxial layer 105 may include polycrystalline silicon, monocrystalline silicon, polycrystalline germanium, or monocrystalline germanium, which may or may not be doped with impurities. In a pseudo-channel structure (DCH), the upper end of the epitaxial layer 105 can be disposed in the substrate insulating layer 110, and at least a portion of the side surface of the epitaxial layer 105 can be surrounded by the substrate insulating layer 110. Therefore, in a pseudo-channel structure (DCH), the epitaxial layer 105 can be spaced apart from the sacrificial layer 180.

[0096] The gate dielectric layer 145 can be configured to have a uniform thickness using atomic layer deposition (ALD) or chemical vapor deposition (CVD). In this process, the entire portion of the gate dielectric layer 145 can be formed, or only a portion of the gate dielectric layer 145 can be formed, and a portion extending perpendicular to the substrate 101 can be formed together with the channel structure CH and the pseudo-channel structure DCH. A channel layer 140 can be formed on the gate dielectric layer 145 within the channel structure CH and the pseudo-channel structure DCH. A channel insulating layer 150 can fill the channel structure CH and the pseudo-channel structure DCH and can be formed of an insulating material. In an example embodiment, the internal region of the channel layer 140 can be filled with a conductive material instead of the channel insulating layer 150. The channel pads 155 can be formed of a conductive material such as polysilicon.

[0097] Reference Figure 15A and Figure 15B An opening OP can be formed in the stacked structure that penetrates the sacrificial layer 180 and the interlayer insulating layer 120, and the sacrificial layer 180 can be removed through the opening OP.

[0098] The opening OP can be formed by using photolithography to form a mask layer and an anisotropic etching stack structure. Before forming the opening OP, an additional cell region insulating layer 190 can be formed on the channel structure CH and the pseudo-channel structure DCH to protect the lower structure. The opening OP can be formed as a trench at the location corresponding to the first separation region MS1 ​​and the second separation regions MS2a and MS2b. Therefore, the opening OP can extend longitudinally in the x-direction. Some portions of the opening OP can extend along the entire area of ​​the first region A and the second region B, and other portions can extend only in the second region B. In this process, the substrate 101 can be exposed in the lower part of the opening OP.

[0099] For example, a wet etching process can be used to selectively remove the sacrificial layer 180 relative to the interlayer insulating layer 120. Therefore, side openings can be formed between the interlayer insulating layers 120, and these side openings can expose portions of the sidewalls of the gate dielectric layer 145 of the channel structure CH and the side surface of the lower insulating layer 170. In this process, the stability of the stacked structure of the interlayer insulating layers 120 is degraded after the removal of the sacrificial layer 180, but the regions where the openings OP are spaced apart from each other and the pseudo-channel structures DCH can stably support the stacked structure. Furthermore, each of the first pseudo-channel structures DCH1 disposed on the outer side of the lower separation region GS can have a relatively large size, such that it can also support the stacked structure of the interlayer insulating layers 120.

[0100] Reference Figure 16A and Figure 16B The gate electrode 130 can be formed by filling the area where the sacrificial layer 180 has been removed with a conductive material.

[0101] The gate electrode 130 may comprise a metal, polysilicon, or a metal silicide material. Openings (OPs) provide a pathway for the material used to form the gate electrode 130. The gate electrodes 130 may not be separated from each other and may be interconnected between openings (OPs) linearly spaced apart along the x-direction, thereby forming a gate connection. After the gate electrode 130 is formed, the material deposited in the openings (OPs) for forming the gate electrode 130 can be removed by an additional process.

[0102] Return to reference Figure 3A and Figure 4A A separation layer 107 can be formed in the opening OP.

[0103] The separation layer 107 may include an insulating material, and in the example embodiment, the separation layer 107 may also include a conductive material and an insulating material. Therefore, a first separation region MS1 ​​and second separation regions MS2a and MS2b can be formed, and the first separation region MS1 ​​and the second separation regions MS2a and MS2b can be formed in the same process and can have the same structure.

[0104] Upper wiring structures such as contact plugs and bit lines can be formed on the channel structure CH.

[0105] According to the foregoing example embodiments, by optimizing the arrangement of the pseudo-channel structure taking into account the arrangement of the substrate insulating layer and the lower separation region, a semiconductor device with improved reliability can be provided.

[0106] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and alterations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor device, comprising: A substrate having a first region and a second region; Gate electrodes, spaced apart from each other and stacked on the first region in a first direction perpendicular to the upper surface of the substrate, extending different lengths on the second region in a second direction perpendicular to the first direction, and including at least one ground selection gate electrode, a memory cell gate electrode and at least one string selection gate electrode stacked sequentially from the substrate. A first separation region, which penetrates the gate electrode and extends in the second direction in the first and second regions, and is spaced apart from each other in a third direction perpendicular to the first and second directions; The second intermediate separation region penetrates all of the gate electrodes and extends in the second direction between the first separation regions, and is spaced apart from each other in the second direction on the second region; The second auxiliary separation region penetrates all the gate electrodes and extends in the second direction between the first separation region and the second intermediate separation region, and is spaced apart from each other in the second direction in the second region, and the spacer region that separates the second auxiliary separation regions from each other is located between the first separation region and the second intermediate separation region. A lower separation region that penetrates the at least one ground selection gate electrode between the second intermediate separation regions and, together with the second intermediate separation region, separates the at least one ground selection gate electrode; A substrate insulating layer is disposed in the second region in the substrate between the first separation region and the second auxiliary separation region and between the second auxiliary separation region and the second intermediate separation region; A channel structure that penetrates the gate electrode and extends perpendicularly to the substrate in the first region; A first pseudo-channel structure penetrates the gate electrode and the substrate insulating layer, and extends perpendicularly to the substrate on the outer side of the lower separation region in the third direction; as well as A third pseudo-channel structure penetrates the gate electrode and the substrate insulating layer, and extends perpendicularly to the substrate in at least a portion of the spacer region between the second auxiliary separation regions.

2. The semiconductor device according to claim 1, wherein The first pseudo-channel structure has a first width in the second direction and a second width greater than the first width in the third direction.

3. The semiconductor device according to claim 2, wherein Each of the channel structures has a first maximum width, and the first maximum width is less than the second width of the first pseudo-channel structure.

4. The semiconductor device according to claim 3, wherein The first maximum width is in the range of 50 nm to 150 nm, and the second width is in the range of 120 nm to 220 nm.

5. The semiconductor device according to claim 1, wherein The substrate insulating layer is disposed between the lower separation region and the first separation region, between the second auxiliary separation region and the first separation region, and between the second auxiliary separation region and the second intermediate separation region, so as not to overlap with the lower separation region in the plane.

6. The semiconductor device according to claim 1, further comprising: A second pseudo-channel structure penetrates the gate electrode and the substrate insulating layer, and forms rows and columns in the second region. The first pseudo-channel structure is disposed between the second pseudo-channel structures that are adjacent to each other in the second direction.

7. The semiconductor device according to claim 6, wherein Each of the second pseudo-channel structures is different in size and shape from the first pseudo-channel structure.

8. The semiconductor device according to claim 6, wherein The first pseudo-channel structure is surrounded by four second pseudo-channel structures.

9. The semiconductor device according to claim 6, wherein The second pseudo-channel structure is disposed along the end of the gate electrode.

10. The semiconductor device according to claim 1, wherein The substrate insulating layer is disposed on the substrate in the lower part of the first spacer region, which is closest to the first region in the spacer region, and The third pseudo-channel structure extends perpendicularly to the substrate in the first spacer region.

11. The semiconductor device according to claim 1, wherein, The maximum diameter of the third pseudo-channel structure is smaller than the maximum diameter of the first pseudo-channel structure.

12. The semiconductor device according to claim 10, wherein The substrate insulating layer is spaced apart from the spacers other than the first spacer region so as not to overlap with the spacers other than the first spacer region.

13. The semiconductor device according to claim 1, wherein As the gate electrode in the lower region of the second region extends further than the gate electrode in the upper region, the gate electrode provides a pad area, and The semiconductor device further includes a contact plug connected to the gate electrode in the pad area.

14. The semiconductor device according to claim 13, wherein The first pseudo-channel structure is disposed on the first side of the lower separation region in the third direction, and one of the contact plugs is disposed on the second side of the lower separation region in the third direction.

15. A semiconductor device, comprising: A substrate having conductive and insulating regions; A gate electrode includes sub-gate electrodes and a gate connector, the sub-gate electrodes being spaced apart from each other and stacked in a first direction perpendicular to the upper surface of the substrate, and extending in a second direction perpendicular to the first direction, the gate connector connecting the sub-gate electrodes disposed at the same level; The lower separation region penetrates at least one gate electrode, including the lowermost gate electrode, of the gate electrodes; A first separation region, which penetrates all of the gate electrodes and extends in the second direction, and is spaced apart from each other in a third direction perpendicular to the first and second directions; The second separation region penetrates all of the gate electrodes and extends between the first separation regions in the second direction, and is spaced apart from each other in the second direction; A channel structure that penetrates the gate electrode and extends in the conductive region of the substrate; A first pseudo-channel structure penetrates the gate electrode and extends in an insulating region of the substrate, and is configured to be adjacent to at least one side of the gate connector in a third direction perpendicular to the first and second directions, and does not overlap with the lower separation region; as well as A substrate insulating layer is disposed in the substrate between the first separation region and the second separation region. The substrate insulating layer is disposed between the lower separation region and the first separation region, and between the second separation region and the first separation region, so as not to overlap with the lower separation region in the plane.

16. The semiconductor device according to claim 15, wherein Each of the channel structures has a first height in the first direction, and the first pseudo-channel structure has a second height greater than the first height.

17. A semiconductor device, comprising: A substrate having a first region and a second region; Gate electrodes, which are spaced apart from each other and stacked in the first region in a first direction perpendicular to the upper surface of the substrate, and extend to different lengths in a second direction perpendicular to the first direction, and provide pad areas in the second region; A penetration separation region that penetrates all of the gate electrodes and extends in the second direction in both the first and second regions, and is spaced apart from each other in the second direction in the second region, the penetration separation region comprising: A first separation region, which penetrates the gate electrode and extends in the second direction in the first and second regions, and is spaced apart from each other in a third direction perpendicular to the first and second directions; The second separation region penetrates all of the gate electrodes and extends in the second direction between the first separation regions, and is spaced apart from each other in the second direction on the second region; The lower separation region penetrates at least one gate electrode, including the lowermost gate electrode, between the second separation regions; A substrate insulating layer disposed in a portion of the substrate located between the first separation region and the second separation region in the second region; A channel structure that penetrates the gate electrode and extends perpendicularly to the substrate in the first region; and A pseudo-channel structure that penetrates at least a portion of the gate electrode and the substrate insulating layer, and extends perpendicularly to the substrate in the second region, and includes a first pseudo-channel structure disposed adjacent to and not overlapping with the lower separation region around the lower separation region, and a second pseudo-channel structure disposed in a regular pattern in the pad region of the gate electrode. The substrate insulating layer is disposed between the lower separation region and the first separation region, and between the second separation region and the first separation region, so as not to overlap with the lower separation region in the plane.

18. The semiconductor device according to claim 17, wherein The first pseudo-channel structure is disposed on each of the two sides of the lower separation region in a third direction perpendicular to the first direction and the second direction.

19. The semiconductor device according to claim 17, wherein Each of the channel structure and the pseudo-channel structure includes an epitaxial layer disposed therein at its lower portion, and The epitaxial layer of the channel structure has a first thickness, and the epitaxial layer of the pseudo-channel structure has a second thickness that is less than the first thickness.

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