OLED driving characteristic detection circuit and OLED display device including the same

Abstract

Provided are an organic light-emitting diode (OLED) driving characteristic detection circuit and an OLED display device including the same. The OLED driving characteristic detection circuit includes: a first current integrator that receives a first current via a first sensing channel and outputs a first sampled voltage based on the first current; a second current integrator that receives a second current via a second sensing channel and outputs a second sampled voltage based on the second current; and a sampling circuit that receives the first sampled voltage and the second sampled voltage, then stores and holds the first sampled voltage and the second sampled voltage, and removes common noise components contained in the first sampled voltage and the second sampled voltage.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0094737 filed on August 5, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety. Technical Field

[0003] The present disclosure relates to an organic light emitting diode (OLED) driving characteristic detection circuit and an OLED display device including the OLED driving characteristic detection circuit. More particularly, the present disclosure relates to an OLED driving characteristic detection circuit capable of sensing the electrical characteristics of a driving element and an OLED display device including the OLED driving characteristic detection circuit. Background Art

[0004] Active matrix type organic light emitting diode display devices include OLEDs that can emit light by themselves, and have many advantages such as fast response speed, excellent light emitting efficiency, high brightness, and a wide viewing angle.

[0005] In an organic light-emitting diode display device, multiple pixels, each including an OLED and a driving thin-film transistor (TFT), are arranged in a matrix. The brightness of the image displayed by the pixels is controlled according to the grayscale level of the video data. The driving TFT controls the driving current flowing through the OLED based on the voltage applied between the gate and source electrodes of the driving TFT. The amount of light emitted from the OLED is determined by the driving current, and the brightness of the image is determined by the amount of light emitted from the OLED.

[0006] When the drive TFT operates in the saturation region, the pixel current flowing between the drain and source of the drive TFT varies depending on the electrical characteristics of the drive TFT, such as threshold voltage and electron mobility. If the electrical characteristics vary between pixels due to various reasons such as process characteristics and time-varying characteristics, brightness deviations may occur between pixels even when the same data voltage is applied to the pixels. Unless such deviations are addressed, it may be difficult to achieve the desired image quality.

[0007] Conventional voltage-sensing-based compensation methods detect the electrical characteristics of the driving TFT using the voltage corresponding to the current rather than the current flowing through the driving TFT. This method converts and stores the current into a source voltage using a parasitic capacitor on the sensing line, which is then sensed. However, accurate sensing data may not be obtained because the parasitic capacitors are relatively large and the data varies depending on the load of the display panel.

[0008] To address the shortcomings of the conventional voltage sensing-based compensation method, a current sensing-based compensation method using a current integrator may be used, but it is still difficult to obtain accurate sensing data due to the offset of the current integrator and external noise that may affect the voltage. Summary of the Invention

[0009] Embodiments of the present disclosure provide an organic light emitting diode (OLED) driving characteristic detection circuit having improved operating characteristics.

[0010] Embodiments of the present disclosure also provide an OLED display device having improved operating characteristics.

[0011] However, the embodiments of the present disclosure are not limited to the embodiments described herein. The following and other embodiments of the present disclosure will become more apparent to those skilled in the art by referring to the detailed description of the present disclosure given below.

[0012] According to one aspect of the inventive concept, an organic light emitting diode driving characteristic detection circuit includes: a first current integrator configured to receive a first current via a first sensing channel and output a first sampled voltage based on the first current; a second current integrator configured to receive a second current via a second sensing channel and output a second sampled voltage based on the second current; and a sampling circuit configured to receive the first sampled voltage and the second sampled voltage, store and hold the first sampled voltage and the second sampled voltage, and remove a common noise component contained in the first sampled voltage and the second sampled voltage. The sampling circuit includes a first sampling capacitor, a second sampling capacitor, a third sampling capacitor, and a fourth sampling capacitor, wherein the first sampling capacitor and the second sampling capacitor are connected to an output terminal of the first current integrator and are configured to store and hold the first sampled voltage, and the third sampling capacitor and the fourth sampling capacitor are connected to an output terminal of the second current integrator and are configured to store and hold the second sampled voltage. The sampling circuit also includes a plurality of switches that selectively connect a first end of the first sampling capacitor, a first end of the second sampling capacitor, a first end of the third sampling capacitor, and a first end of the fourth sampling capacitor.

[0013] According to another aspect of the present inventive concept, an organic light emitting diode driving characteristic detection circuit includes: a first current integrator configured to receive a first current via a first sensing channel and output a first sampling voltage based on the first current; a second current integrator configured to receive a second current via a second sensing channel and output a second sampling voltage based on the second current; and a sampling circuit configured to receive the first sampling voltage and the second sampling voltage, then store and hold the first sampling voltage and the second sampling voltage, and remove a common noise component contained in the first sampling voltage and the second sampling voltage, the sampling circuit including: a first sampling capacitor configured to store the first sampling voltage; a first sampling switch connected between an output terminal of the first current integrator and the first sampling capacitor, the first sampling switch configured to be turned on during a first period to complete the storage of the first sampling voltage in the first sampling capacitor; a second sampling capacitor configured to store the first sampling voltage; and a second sampling switch configured to store the first sampling voltage in the first sampling capacitor. a container configured to store the first sampling voltage; a second sampling switch connected between the output terminal of the first current integrator and the second sampling capacitor, the second sampling switch configured to be turned on in a second period after the first period to complete the storage of the first sampling voltage in the second sampling capacitor; a third sampling capacitor configured to store the second sampling voltage; a third sampling switch connected between the output terminal of the second current integrator and the third sampling capacitor, the third sampling switch configured to be turned on in the first period to complete the storage of the second sampling voltage in the third sampling capacitor; a fourth sampling capacitor configured to store the second sampling voltage; and a fourth sampling switch connected between the output terminal of the second current integrator and the fourth sampling capacitor, the fourth sampling switch configured to be turned on in the second period to complete the storage of the second sampling voltage in the fourth sampling capacitor.

[0014] According to another aspect of the present inventive concept, an organic light emitting diode display device includes: a display panel having a plurality of pixels connected to data lines and sensing lines, each of the plurality of pixels including an organic light emitting diode (OLED) and a driving thin film transistor (TFT), the driving TFT being configured to control the amount of light emitted by the OLED; and a data driving circuit including a digital-to-analog converter (DAC), a plurality of sensing circuits, and an analog-to-digital converter (ADC), the DAC being configured to apply a data voltage for sensing to the data lines during a sensing operation, the plurality of sensing circuits being configured to sense current information of the pixels via a plurality of sensing channels connected to the sensing lines during the sensing operation, each of the sensing circuits including a first current integrator, a second current integrator, and a sampling circuit, the first current integrator being configured to receive a first current via a first sensing channel of the plurality of sensing channels and output a first sampling voltage, the second current integrator being configured to receive a first current via a first sensing channel of the plurality of sensing channels and output a first sampling voltage, and the second current integrator being configured to receive a first current via a first sensing channel of the plurality of sensing channels and output a first sampling voltage. A second sensing channel among the sensing channels receives a second current and outputs a second sampled voltage, and the sampling circuit is configured to receive, store, and hold the first sampled voltage and the second sampled voltage, and remove a common noise component contained in the first sampled voltage and the second sampled voltage. The sampling circuit includes a first sampling capacitor, a second sampling capacitor, a third sampling capacitor, a fourth sampling capacitor, and a plurality of switches. The first sampling capacitor and the second sampling capacitor are connected to the output terminal of the first current integrator and configured to store the first sampled voltage. The third sampling capacitor and the fourth sampling capacitor are connected to the output terminal of the second current integrator and configured to store the second sampled voltage. The plurality of switches selectively connect a first end of the first sampling capacitor, a first end of the second sampling capacitor, a first end of the third sampling capacitor, and a first end of the fourth sampling capacitor. The ACD is commonly connected to the sensing circuit.

[0015] Other features and embodiments will become apparent from the following detailed description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other embodiments and features of the present disclosure will become more apparent by describing in detail example embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0017] Figure 1 is a block diagram of an organic light emitting diode display device that performs compensation in a current sensing manner;

[0018] Figure 2A is a circuit diagram showing how a pixel to which a current sensing-based compensation method is applied is connected to a driver integrated circuit (IC);

[0019] Figure 2B It shows Figure 2A A graph of the output of the current integrator;

[0020] Figure 3A is a diagram showing how noise is generated in a current sensing-based compensation method;

[0021] Figure 3B It is shown in Figure 3A Graph showing the output of the current integrator when an error occurs due to noise;

[0022] Figure 4 is a block diagram of an OLED display device according to an example embodiment;

[0023] Figure 5 According to an example embodiment, Figure 4 A pixel array and a sensing circuit formed in a display panel;

[0024] Figure 6 is a circuit diagram of an OLED display device including an OLED driving characteristic detection circuit according to an example embodiment;

[0025] Figure 7 is a flowchart illustrating a sensing operation of an OLED display device according to an example embodiment;

[0026] Figures 8A to 8D is a circuit diagram showing how to remove noise that may be generated in the process of sensing current according to an embodiment;

[0027] Figure 9 is a timing diagram illustrating states of switches of an OLED driving characteristic detection circuit according to an example embodiment;

[0028] Figure 10 is a graph showing how noise can be removed by four capacitors according to an example embodiment;

[0029] Figure 11 is a circuit diagram illustrating how to remove noise that may be generated in the process of sensing current according to an example embodiment;

[0030] Figure 12 is a timing diagram illustrating states of switches of an OLED driving characteristic detection circuit according to an example embodiment. DETAILED DESCRIPTION

[0031] Although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts are not limited by these terms. These terms are only used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, the first element, component, region, layer, or part discussed below may be referred to as a second element, component, region, layer, or part without departing from the scope of this disclosure.

[0032] In the following, reference will be made to Figures 1 to 3B The structure of an organic light emitting diode ("OLED") display device and problems arising in conventional current sensing-based compensation methods are described.

[0033] Figure 1 FIG. 4 is a block diagram of an organic light emitting diode display device that performs compensation in a current sensing manner. Figure 2A is a circuit diagram showing how a pixel to which a current sensing-based compensation method is applied is connected to a driver integrated circuit (IC), Figure 2B It shows Figure 2A A graph of the output of the current integrator.

[0034] Reference Figure 1 , an OLED display device may include a display panel, a driver IC, and a timing controller. The driver IC may include a sensing block and senses current information input from the display panel. The sensing block includes a plurality of current integrators and integrates the current information input from the display panel. The pixels of the display panel are connected to the sensing lines, and the current integrators are connected to the sensing lines via sensing channels. The integral value (e.g., integral reference voltage value) obtained by the current integrator is input to an analog-to-digital converter (ADC) through sampling and holding. The ADC sends a digital code converted from the analog integral value to a digital sensing value to the timing controller. The timing controller derives compensation data for compensating for threshold voltage and mobility deviation from the digital sensing value, modulates image data for realizing an image using the compensation data, and sends the modulated image data to the driver IC. The modulated image data is converted into a data voltage for displaying an image by the driver IC, and the data voltage is applied to the display panel.

[0035] Reference Figure 2A , a pixel “Pixel” may include an OLED “OLED”, a driving transistor T_DRV, a storage capacitor C_ST, a first switching transistor T_SW1 and a second switching transistor T_SW2 .

[0036] The OLED "OLED" may include an anode connected to a driving transistor T_DRV, a cathode connected to an input terminal of a low potential driving voltage EVSS, and an organic compound layer between the anode and the cathode. The driving transistor T_DRV may be implemented as a thin film transistor (TFT). The driving transistor T_DRV may control the amount of current input to the OLED "OLED" according to the gate-source voltage of the driving transistor T_DRV. The driving transistor T_DRV may include a gate, a drain connected to an input terminal of a high potential driving voltage EVDD, and a source connected to the anode of the OLED "OLED". The storage capacitor C_ST may connect the gate and source of the driving transistor T_DRV. The first switching transistor T_SW1 may receive a data voltage from a digital-to-analog converter (DAC) "DAC" via a data pad PAD_Y and may apply the data voltage to the gate of the driving transistor T_DRV in response to a gate pulse VSCAN. The second switching transistor T_SW2 may switch the current flowing in the sensing line in response to the gate pulse VSCAN. When the pixel current Ipix flows in the sensing line in response to the first and second switching transistors T_SW1 and T_SW2 being turned on, a low potential driving voltage EVSS below a threshold level may be applied so that the OLED “OLED” does not affect the flow of the pixel current Ipix.

[0037] The current integrator ITG may include an amplifier AMP. The amplifier AMP may include an inverting input terminal (-), a non-inverting input terminal (+), and an output terminal. The inverting input terminal (-) may be connected to a sensing line of the pixel "Pixel" via a sensing pad PAD_S and receive a pixel current Ipix (e.g., a source-drain current of the driving transistor T_DRV). The non-inverting input terminal (+) may receive a reference voltage VREF. The current integrator ITG may further include an integration capacitor C_ITG and a reset switch SW_ITG, the integration capacitor C_ITG being connected between the inverting input terminal (-) and the output terminal of the amplifier AMP, and the reset switch SW_ITG being connected to both ends of the integration capacitor C_ITG.

[0038] The current integrator ITG is connected to an analog-to-digital converter (ADC) “ADC” via a sampling circuit (eg, a sample / hold circuit S / H) and a fully differential amplifier (FDA) “FDA”.

[0039] The sample / hold circuit S / H may include two sampling switches SW_S1 and SW_S2, sampling capacitors C_S1 and C_S2, and hold switches SW_H1 and SW_H2. The sampling switches SW1-S1 can sample the output voltage VS of the amplifier AMP, and the sampling switch SW_S2 can sample the initial voltage VINT. The sampling capacitor C_S1 can store the output voltage VS of the amplifier AMP applied thereto via the sampling switch SW_S1. The sampling capacitor C_S2 can store the initial voltage VINT applied thereto via the sampling switch SW_S2. The hold switches SW_H1 and SW_H2 can transfer the output voltage VS and the initial voltage VINT stored in the sampling capacitors C_S1 and C_S2, respectively, to the FDA "FDA." In addition, the sample / hold circuit S / H may include a switch SW_b and a switch SW_a, wherein the switch SW_b is used to apply the sampling reference voltage VCM to the sampling capacitors C_S1 and C_S2, and when the holding switches SW_H1 and / or SW_H2 are turned on, the sampling capacitors C_S1 and C_S2 can be connected by turning on the switch SW_a.

[0040] Reference Figure 2B , the driving characteristic sensing operation of the driving transistor T_DRV using the current integrator ITG includes a reset period Sensing period and transmission period

[0041] During the reset period In the MOSFET, since the reset switch SW_ITG is turned on, the amplifier AMP can be used as a unity gain buffer with a gain of 1.

[0042] During the reset period In the embodiment, the input terminals (+) and (-) and the output terminal of the amplifier AMP may all be initialized to the reference voltage VREF.

[0043] During the reset period In the reset period, a data voltage for sensing may be applied to the gate of the driving transistor T_DRV via a digital-to-analog converter (DAC) "DAC" of the driver IC "Driver IC", and as a result, a source-drain current (eg, pixel current Ipix) of the driving transistor T_DRV flows and may be stabilized. However, due to the During this period, the amplifier AMP continues to function as a unity-gain buffer, so the output voltage VS of the amplifier AMP can be maintained at the reference voltage VREF.

[0044] During the sensing period During the sensing period, since the reset switch SW_ITG is turned off, the amplifier AMP can be used as a current integrator and integrate the pixel current Ipix using the integration capacitor C_ITG. During the sensing period, the pixel current Ipix is ​​introduced into the inverting input terminal (-) of the amplifier AMP, so the potential difference between the two ends of the integration capacitor C_ITG (for example, the amount of current accumulated) increases with time. However, due to the characteristics of the amplifier AMP, the inverting input terminal (-) and the non-inverting input terminal (+) of the amplifier AMP can be short-circuited by a virtual ground, so that the potential difference between the inverting input terminal (-) and the non-inverting input terminal (+) of the amplifier AMP is zero. Therefore, no matter how the potential of the integration capacitor C_ITG increases, during the sensing period, the potential difference between the two ends of the integration capacitor C_ITG increases with time. During the sensing period, the potential of the inverting input terminal (-) of the amplifier AMP can be maintained at the reference voltage VREF. On the contrary, the potential of the output terminal of the amplifier AMP can be reduced according to the increase of the potential difference between the two ends of the integration capacitor C_ITG. During this period, the pixel current Ipix introduced through the sensing pad PAD_S can be converted into the output voltage VS by the integration capacitor C_ITG. As the pixel current Ipix increases, the falling slope of the output voltage VS of the amplifier AMP increases, and the output voltage VS can decrease.

[0045] During the sensing period Within, the sampling capacitor C_S1 may store the output voltage VS via the sampling switch SW_S1 , and the sampling capacitor C_S2 may store the initial voltage VINT via the sampling switch SW_S2 .

[0046] During the transmission period In the embodiment of the present invention, when the holding switches SW_H1 and SW_H2 are turned on, the output voltage VS stored in the sampling capacitor C_S1 can be input to the FDA "FDA" via the holding switch SW_H1, and the initial voltage VINT stored in the sampling capacitor C_S2 can be input to the FDA "FDA" via the holding switch SW_H2. Hereinafter, the difference between the output voltage V1 of the non-inverting output terminal of the FDA "FDA" and the output voltage V2 of the inverting output terminal of the FDA "FDA" can be input to the ADC "ADC".

[0047] The output voltage of the FDA "FDA" based on the difference ΔV between the output voltage VS and the initial voltage VINT may be converted into a digital sensing value by the ADC "ADC", and the digital sensing value may be transmitted to Figure 1The timing controller may derive a threshold voltage deviation ΔVth and a mobility deviation ΔK of the driving transistor T_DRV by applying the digital sensing value to a previously stored compensation algorithm, and may derive compensation data for compensating for the threshold voltage deviation ΔVth and the mobility deviation ΔK.

[0048] Figure 3A is a diagram showing how noise is generated in a current sensing-based compensation method, Figure 3B It is shown in Figure 3A The following diagram shows the output of the current integrator when an error occurs due to noise. Figures 2A to 3B Noise that may be generated when a sensing operation is performed according to a current sensing method to determine driving characteristics of the driving transistor T_DRV is described.

[0049] The sensing method using the current integrator ITG is more advantageous than the conventional voltage sensing method in terms of reducing the duration of sensing. However, since the sensing target (e.g., the pixel current Ipix or the source-drain current of the drive transistor T_DRV) can be very low, it may be susceptible to noise. In addition, noise may be generated in the current integrator ITG and the reset switch SW_ITG.

[0050] like Figure 3A As shown, during the sensing of the pixel current Ipix, problems may arise with the noise "noise(EVSS)" generated during the generation of the low-potential driving voltage EVSS and the noise "noise(VREF)" generated during the generation of the reference voltage VREF. In addition, during the initialization period, due to the coupling of the reset switch SW_ITG, noise "coupling(SW)" may be generated, and due to the offset of the current integrator ITG connected to the plurality of pixels and due to the offset of the reference voltage VREF, noises "offset(ITG)" and "offset(VREF)" may be generated.

[0051] like Figure 3B As shown, due to the above-mentioned noise, accurate sensing may not be performed. That is, due to the noise "coupling(SW)", "offset(ITG)", and "offset(VREF)" that may be generated during the initialization period, a voltage peak as shown in area P may be generated, and due to the noise "noise(EVSS)" and "noise(VREF)", the output voltage VS' may fluctuate (as shown in area Q), and thus accurate sensing may not be performed.

[0052] In the following, reference will be made to Figures 4 to 12An OLED driving characteristic detection circuit according to some embodiments of the present disclosure and an OLED display device including the OLED driving characteristic detection circuit according to some embodiments of the present disclosure are described.

[0053] Figure 4 is a block diagram of an OLED display device according to an embodiment of the present disclosure, Figure 5 The embodiment according to the present disclosure is shown in Figure 4 The pixel array and sensing circuit are formed in the display panel.

[0054] Reference Figure 4 and Figure 5 The OLED display device 10 may include a display panel 100 , a data driving circuit 200 , a gate driving circuit 300 , a timing controller 400 , and a memory 500 .

[0055] In the display panel 100 , a plurality of data lines 210 and a plurality of sensing lines 220 may intersect a plurality of gate lines 310 , and pixels P may be disposed at intersections between the data lines 210 / sensing lines 220 and the gate lines 310 and may be arranged in a matrix.

[0056] Each pixel P may be connected to one data line 210, one sensing line 220, and one gate line 310. Each pixel P may be electrically connected to one data line 210 in response to a gate pulse input thereto via one gate line 310 to receive a data voltage from the corresponding data line 210 and output a sensing signal via one sensing line 220.

[0057] Each pixel P may receive a high potential driving voltage EVDD and a low potential driving voltage EVSS from a power generator (not shown). Each pixel P may include an OLED "OLED", a driving transistor T_DRV, a first switch T_SW1 and a second switch T_SW2, and a storage capacitor C_ST. That is, the pixel P may have a Figure 2A The structure of the pixel "Pixel" is the same as that of the pixel "Pixel". The transistor of the pixel P can be implemented as a p-type or n-type transistor. In addition, the semiconductor layer of the transistor of the pixel P may include amorphous silicon, polysilicon or oxide.

[0058] The pixel P can be operated differently for display operation for displaying an image and sensing operation for obtaining a sensing value. The sensing operation can be performed within a predetermined time period before the display operation, or can be performed during a vertical blanking period during the display operation.

[0059] The display operation may include a first operation performed by the data driving circuit 200 and the gate driving circuit 300 under the control of the timing controller 400. The sensing operation may include a second operation performed by the data driving circuit 200 and the gate driving circuit 300 under the control of the timing controller 400. The operation of deriving compensation data for compensating for the deviation based on the sensing result data and the operation of modulating the digital video data RGB using the compensation data are performed by the timing controller 400.

[0060] The data driving circuit 200 may include at least one data driver IC “SDIC”. The data driver IC “SDIC” may include a plurality of DACs connected to the data lines 210 via sensing channels. A plurality of sensing circuits SU0 , SU1 , and SU2 connected to the sensing line 220 , and an ADC commonly connected to the sensing circuits SU0 , SU1 , and SU2 .

[0061] During a display operation, the DAC of the data driver IC “SDIC” may convert digital video data RGB into data voltages for displaying an image and provide the data voltages for displaying an image to the data lines 210 according to a data timing control signal DDC applied thereto from the timing controller 400 .

[0062] During a sensing operation, the DAC of the data driver IC "SDIC" can generate a data voltage for sensing based on a data timing control signal DDC applied thereto from the timing controller 400, and supply the data voltage for sensing to the data line 210. Here, the data voltage for sensing can include a grayscale data voltage for generating a pixel current Ipix (or the source-drain current of each drive transistor T_DRV) greater than zero, and a black data voltage for suppressing the generation of the pixel current Ipix. During a sensing operation, the data driver IC "SDIC" can alternately supply the grayscale data voltage and the black data voltage to the data line 210, so that the grayscale data voltage and the black data voltage can be alternately supplied to the channels, specifically, to the columns of pixels P connected to the channels. For example, if the grayscale data voltage is supplied to the first column of pixels connected to the first channel CH1, the black data voltage can be applied to the second column of pixels connected to the second channel CH2. In another example, if the black data voltage is supplied to the first column of pixels connected to the first channel CH1, the grayscale data voltage can be applied to the second column of pixels connected to the second channel CH2.

[0063] Each of the sensing circuits SU0, SU1, and SU2 of the data driver IC "SDIC" may include: a first current integrator CI1, which may be connected to one of the odd-numbered sensing channels (e.g., the first channel CH1, the third channel CH3, and the fifth channel CH5); a second current integrator CI2, which is connected to one of the even-numbered sensing channels (e.g., the second channel CH2, the fourth channel CH4, and the sixth channel CH6); and four sampling capacitors CS, which are connected between the output terminal of the first current integrator CI1 and the output terminal of the second current integrator CI2. Figure 6 Implemented as shown Figure 5 The ADC of the data driver IC "SDIC" can sequentially digitize the outputs of the sensing circuits SU0, SU1, and SU2 and send the digitized outputs to the timing controller 400. Figures 6 to 12 The operations of the sensing circuits SU0 , SU1 , and SU2 are described in detail.

[0064] During the display operation, the gate drive circuit 300 generates a gate pulse for displaying an image based on the gate control signal GDC, and sequentially provides the gate pulse for displaying the image to the gate lines 310 in a row-sequential manner (L#1, L#2...). During the sensing operation, the gate drive circuit 300 generates a gate pulse for sensing based on the gate control signal GDC, and sequentially provides the gate pulse for sensing to the gate lines 310 in a row-sequential manner (L#1, L#2...). The gate pulse for sensing may have a wider on-pulse portion than the gate pulse for displaying an image. The on-pulse portion of the gate pulse for sensing corresponds to the "one-line sensing on-time". Here, the term "single-line sensing on-time" refers to the scanning time required to simultaneously sense each row of pixels P (i.e., L#1, L#2...).

[0065] The timing controller 400 can generate a data timing control signal DDC for controlling the operation timing of the data driving circuit 200 and a gate control signal GDC for controlling the operation timing of the gate driving circuit 300 based on timing signals (e.g., a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a dot clock signal DCLK, and a data enable signal DE). The timing controller 400 can identify a display operation and a sensing operation based on predetermined reference signals (e.g., a driving power enable signal, a vertical synchronization signal Vsync, and a data enable signal DE), and generate a data timing control signal DDC and a gate control signal GDC suitable for each of the display operation and the sensing operation.

[0066] During the sensing operation, the timing controller 400 may transmit digital data corresponding to the data voltage for sensing to the data driving circuit 200. The digital data may include first digital data corresponding to the grayscale data voltage and second digital data corresponding to the black data voltage. During the sensing operation, the timing controller 400 may derive the threshold voltage deviation ΔVth and the mobility deviation ΔK of each driving transistor T_DRV by applying the digital sensing value SD received from the data driving circuit 200 to a previously stored compensation algorithm, and store compensation data for compensating the derived deviations in the memory 500.

[0067] During a display operation, the timing controller 400 may modulate the digital video data RGB with reference to the compensation data stored in the memory 500 and transmit the modulated digital video data to the data driving circuit 200 .

[0068] Figure 6 is a circuit diagram of an OLED display device including an OLED driving characteristic detection circuit according to an example embodiment.

[0069] Reference Figure 6 The OLED driving characteristic detection circuit may include a first current integrator ITG1, a second current integrator ITG2, a first sample / hold circuit S / H1, a second sample / hold circuit S / H2, and an FDA "FDA".

[0070] The first current integrator ITG1 may receive the first current Ia applied thereto via the first pad P1 and may generate a first integrated output voltage VS1. For example, the first pad P1 may be connected to Figure 5 The first current integrator ITG1 receives the source-drain current (e.g., pixel current Ipix1) of the driving transistor of the pixel connected to the first pad P1, but receives the first current Ia in which noise generated by the parasitic capacitor Cprs1 during the process of generating the low potential driving voltage EVSS is reflected. The first current Ia may be a current generated based on the grayscale data voltage. This operation may be a sensing operation for sensing the driving characteristics of the driving transistor of the pixel connected to the first pad P1.

[0071] The first current integrator ITG1 may include a first amplifier AMP1, a first integration capacitor C_ITG1, and a first integration switch SW_ITG1. The first amplifier AMP1, the first integration capacitor C_ITG1, and the first integration switch SW_ITG1 may respectively perform Figure 2AThat is, the voltage across the first integration capacitor C_ITG1 may be initialized by the first integration switch SW_ITG1, and the first amplifier AMP1 may perform integration based on the first current Ia to generate and output the first integrated output voltage VS1.

[0072] The second current integrator ITG2 can receive the second current Ib applied thereto via the second pad P2 and can generate a second integrated output voltage VS2. For example, the second pad P2 can be connected to Figure 5 The second current integrator ITG2 receives the source-drain current of the driving transistor of the pixel connected to the second pad P2 (i.e., pixel current Ipix2), but receives the second current Ib in which noise is reflected. The noise is generated under the influence of the parasitic capacitor Cprs2 in the process of generating the low potential driving voltage EVSS. The second current Ib may be a current generated based on the black data voltage.

[0073] The second amplifier AMP2, the second integrating capacitor C_ITG2, and the second integrating switch SW_ITG2 of the second current integrator ITG2 can respectively perform the same operations as the first amplifier AMP1, the first integrating capacitor C_ITG1, and the first integrating switch SW_ITG1. That is, the voltage across the second integrating capacitor C_ITG2 can be initialized by the second integrating switch SW_ITG2, and the second amplifier AMP2 can perform integration based on the second current Ib to generate and output the second integrated output voltage VS2.

[0074] The sampling circuit may include a first sampling / holding circuit S / H1 and a second sampling / holding circuit S / H2. The first sampling / holding circuit S / H1 may include a first sampling switch SW_SP1, a second sampling switch SW_SN1, a sampling transmission switch SW_ST, a first sampling capacitor C S 1. Second sampling capacitor C S 2. Two sampling reset switches SW_RST and two holding switches SW_H.

[0075] During the first sensing period, the first sampling switch SW_SP1 may be turned on to store the first integrated output voltage VS1 on the first sampling capacitor C S 1. The first sensing period may be an early sensing period.

[0076] In a second sensing period after the first sensing period, the second sampling switch SW_SN1 may be turned on to store the first integrated output voltage VS1 in the second sampling capacitor C S 2 in.

[0077] When the first integrated output voltage VS1 is stored in the first sampling capacitor C S 1 and the second sampling capacitor C S 2, the sampling reset switch SW_RST of the first sample / hold circuit S / H1 may be turned on to apply the sampling reference voltage VCM to the first sampling capacitor C S The second terminal of 1 and the second sampling capacitor C S 2. By fixing the sampling reference voltage VCM to the first sampling capacitor C S The second terminal of 1 and the second sampling capacitor C S 2, the first integrated output voltage VS1 can be stored in the first sampling capacitor C S 1 and the second sampling capacitor C S 2 in.

[0078] In the transmission period after the second sensing period, the first sampling switch SW_SP1 and the second sampling switch SW_SN1 and the sampling reset switch SW_RST of the first sample / hold circuit S / H1 may be turned off, and the sampling transmission switch SW_ST and the holding switch SW_H of the first sample / hold circuit S / H1 may be turned on. In response to the sampling transmission switch SW_ST being turned on, the first sampling capacitor C S 1 and the first terminal of the second sampling capacitor C S 2 and the first terminal of the third sampling capacitor C S 3 and the first terminal of the fourth sampling capacitor C S In addition, in response to the holding switch SW_H of the first sample / hold circuit S / H1 being turned on, the voltage stored in the first sampling capacitor C S The voltage in 1 can be applied to the inverting input terminal (-) of FDA "FDA" and stored in the second sampling capacitor C S The voltage in 2 can be applied to the non-inverting input terminal (+) of FDA "FDA".

[0079] The second sample / hold circuit S / H2 may include a third sampling switch SW_SP2, a fourth sampling switch SW_SN2, a sampling transmission switch SW_ST, a third sampling capacitor C S 3. The fourth sampling capacitor C S 4. Two sampling reset switches SW_RST and two holding switches SW_H.

[0080] During the first sensing period, the third sampling switch SW_SP2 may be turned on to store the second integrated output voltage VS2 on the third sampling capacitor C S3. In the second sensing period, the fourth sampling switch SW_SN2 may be turned on to store the second integrated output voltage VS2 in the fourth sampling capacitor C S 4 in.

[0081] The sampling reset switch SW_RST of the second sample / hold circuit S / H2 can be operated in the same manner as the sampling reset switch SW_RST of the first sample / hold circuit S / H1. That is, during the first sensing period and the second sensing period, the sampling reset switch SW_RST of the second sample / hold circuit S / H2 can be turned on to apply the sampling reference voltage VCM to the third sampling capacitor C S The second terminal of 3 and the fourth sampling capacitor C S The second end of 4.

[0082] During the transfer period, the third sampling switch SW_SP2 and the fourth sampling switch SW_SN2 and the sampling reset switch SW_RST of the second sample / hold circuit S / H2 may be turned off, and the sampling transfer switch SW_ST and the holding switch SW_H of the second sample / hold circuit S / H2 may be turned on. In response to the sampling transfer switch SW_ST of the second sample / hold circuit S / H2 being turned on, the first sampling capacitor C S 1 to the fourth sampling capacitor C S In addition, in response to the holding switch SW_H of the second sample / hold circuit S / H2 being turned on, the voltage stored in the third sampling capacitor C S The voltage in 3 can be applied to the non-inverting input terminal (+) of FDA "FDA", stored in the fourth sampling capacitor C S The voltage in 4 can be applied to the inverting input terminal (-) of FDA "FDA".

[0083] The FDA "FDA" may receive a sampled voltage from the first sample / hold circuit S / H1 and the second sample / hold circuit S / H2 via the inverting input terminal (-) and the non-inverting input terminal (+) of the FDA "FDA", and may output a non-inverting output voltage VOP and an inverting output voltage VON to the non-inverting input terminal (+) and the inverting input terminal (-) of the ADC "ADC", respectively. In some embodiments, the voltage transmitted to the ADC "ADC" may be a voltage corresponding to the difference between the non-inverting output voltage VOP and the inverting output voltage VON (i.e., the output voltage "VOP-VON"). Hereinafter, it will be assumed and described that the output voltage "VOP-VON" is input to the ADC "ADC".

[0084] The ADC "ADC" receives the output voltage "VOP-VON" from the FDA "FDA" and outputs a digital value SD obtained by analog-to-digital conversion of the output voltage "VOP-VON" to the timing controller 400. The timing controller 400 can generate compensation data based on the digital value SD, as described above with reference to FIG. Figure 4 described.

[0085] Figure 7 is a flowchart illustrating a sensing operation of an OLED display device according to example embodiments. Figures 8A to 8D is a circuit diagram illustrating how to remove noise that may be generated in the process of sensing current according to some embodiments. Figure 9 is a timing diagram illustrating states of switches of an OLED driving characteristic detection circuit according to an example embodiment. Figure 10 is a graph showing how noise can be removed by four capacitors according to an example embodiment. Figures 7 to 9 Describes how the OLED driving characteristic detection circuit according to some embodiments of the present disclosure senses the operating characteristics of the driving transistor. Figure 6 A detailed description of the described features or elements.

[0086] Reference Figures 7 to 9 In S100, the first integration capacitor C_ITG1 of the first current integrator ITG1 and the second integration capacitor C_ITG2 of the second current integrator ITG2 may be reset. That is, during the reset period from t1 to t2, the first integration switch SW_ITG1 and the second integration switch SW_ITG2 may be turned on, and a reset operation may be performed such that the voltage across the first integration capacitor C_ITG1 and the voltage across the second integration capacitor C_ITG2 become the same. In some embodiments, during the reset period from t1 to t2, the first sampling switch SW_SP1, the second sampling switch SW_SN1, the third sampling switch SW_SP2, and the fourth sampling switch SW_SN2, as well as the sampling reset switch SW_RST, may be turned on to track the output of the first current integrator ITG1 and the output of the second current integrator ITG2.

[0087] After the reset period from t1 to t2 , the first and second integration switches SW_ITG1 and SW_ITG2 may be turned off, and a sensing period from t3 to t5 may begin. Figure 9 It is shown that there is a delay between the reset period and the start of the sensing period, but the present disclosure is not limited thereto. That is, as an alternative, the end of the reset period and the start of the sensing period may coincide with each other.

[0088] In S200, the first integrated output voltage VS1 may be stored in the first sampling capacitor CS 1, the second integrated output voltage VS2 can be stored in the third sampling capacitor C S 3. That is, in the first sensing period from t3 to t4, the first sampling switch SW_SP1 and the third sampling switch SW_SP2 may be turned on, and as a result, the first integrated output voltage VS1 of the first current integrator ITG1 and the second integrated output voltage VS2 of the second current integrator ITG2 may be stored in the first sampling capacitor C S 1 and the third sampling capacitor C S 3. The first sampling capacitor C is stored in the first sensing period from t3 to t4. S The first integrated output voltage VS1 in FIG1 is defined as the first sampling voltage Va, which is stored in the third sampling capacitor C during the first sensing period. S The second integrated output voltage VS2 in FIG3 is defined as the third sampling voltage Vc.

[0089] During the sensing period from t3 to t5, the sampling reset switches SW_RST of the first and second sample / hold circuits S / H1 and S / H2 may be turned on to provide the sampling reference voltage VCM to the first ends of the first to fourth sampling capacitors CS1 to CS4.

[0090] In S300, the first integrated output voltage VS1 may be stored in the second sampling capacitor C S 2, the second integrated output voltage VS2 can be stored in the fourth sampling capacitor C S That is, in the second sensing period from t4 to t5, the second sampling switch SW_SN1 and the fourth sampling switch SW_SN2 may be turned on, and as a result, the first integrated output voltage VS1 and the second integrated output voltage VS2 may be stored in the second sampling capacitor C S 2 and the fourth sampling capacitor C S 4. The second sampling capacitor C is stored in the second sensing period from t4 to t5. S The first integrated output voltage VS1 in FIG. 2 is defined as the second sampling voltage Vb and is stored in the fourth sampling capacitor C during the second sensing period. S The second integrated output voltage VS2 in FIG4 is defined as the fourth sampling voltage Vd.

[0091] As already mentioned above Figure 3A and Figure 3BAs described, during the reset period from t1 to t2 and the sensing period from t3 to t5, noises "coupling(SW)", "offset(ITG)", "offset(VREF)", "noise(EVSS)", and "noise(VREF)" may be generated in the first current integrator ITG1 and the second current integrator ITG2. These noises may be collectively referred to as common noise components, and the first sampling voltage Va to the fourth sampling voltage Vd reflecting these noises may be respectively expressed by the following equations (1) to (4).

[0092] [Formula 1]

[0093]

[0094] [Formula 2]

[0095]

[0096] [Formula 3]

[0097]

[0098] [Formula 4]

[0099]

[0100] Here, noise(EVSS S1 ) represents the noise generated by the low potential driving voltage EVSS during the first sensing period from t3 to t4, noise(EVSS S2 ) represents the noise generated by the low potential driving voltage EVSS during the second sensing period from t4 to t5, noise(VREF S1 ) represents the noise generated by the reference voltage VREF during the first sensing period from t3 to t4, noise(VREF S2 ) represents noise generated by the reference voltage VREF during the second sensing period from t4 to t5, offset(ITG1) represents noise caused by an offset present in the first current integrator ITG1 during the sensing operation, offset(ITG2) represents noise caused by an offset present in the second current integrator ITG2 during the sensing operation, Ia(S1) represents a first current Ia introduced via the first pad P1 during the first sensing period from t3 to t4, Ia(S2) represents the first current Ia introduced via the first pad P1 during the second sensing period from t4 to t5, Ib(S1) represents a second current Ib introduced via the second pad P2 during the first sensing period from t3 to t4, and Ib(S2) represents the second current Ib introduced via the second pad P2 during the second sensing period from t4 to t5.

[0101] In S400, the first to fourth sampling capacitors C S 1 to C S 4, and transmits the output voltage "VOP-VON" to the ADC "ADC".

[0102] During the transmission period from t6 to t7, the transmission switch SW_ST and the holding switch SW_H are turned on, and the first sampling switch SW_SP1, the second sampling switch SW_SN1, the third sampling switch SW_SP2, the fourth sampling switch SW_SN2 and the sampling reset switch SW_RST are turned off. S 1 to the fourth sampling capacitor C S 4 are connected to each other, the first sampling capacitor C S 1 and the first terminal of the fourth sampling capacitor C S The first end of 4 is connected to the inverting input terminal (-) of FDA "FDA", and the second sampling capacitor C S 2 and the first terminal of the third sampling capacitor C S The first end of 3 is connected to the non-inverting input terminal (+) of FDA "FDA".

[0103] As a result, the output voltage "VOP-VON" of the FDA "FDA" can be expressed by the following equation (5).

[0104] [Formula 5]

[0105]

[0106] As described above, the pixel current Ipix2 is obtained by applying the black data voltage and is therefore negligibly low. As a result, the second current Ib can also be negligibly low. Therefore, the output voltage "VOP-VON" can also be expressed by the following equation (6).

[0107] [Formula 6]

[0108]

[0109] according to Figures 7 to 10In this embodiment, two sampling capacitors are provided to store the output voltages of the two current integrators, respectively, and the output voltage of the FDA can be generated by performing calculations on the sampled voltages stored in the sampling capacitors. Therefore, the noise "coupling(SW)", "offset(ITG)", and "offset(VREF)" that may be generated during the reset period, as well as the noise "noise(EVSS)" and "noise(VREF)" that may be generated during the sensing period, can be removed, thereby accurately performing sensing for detecting the driving characteristics of each driving transistor.

[0110] Figure 11 is a circuit diagram illustrating how to remove noise that may be generated in the process of sensing current according to an example embodiment of the present disclosure. Figure 12 1 is a timing diagram showing the state of the switch of the OLED driving characteristic detection circuit according to an example embodiment. Figures 7 to 10 A detailed description of the described features or elements.

[0111] Reference Figure 11 and Figure 12 The OLED driving characteristic detection circuit according to some embodiments of the present disclosure and the OLED display device according to some embodiments of the present disclosure can accurately detect the capacitance of the first integral capacitor C_ITG1 and the capacitance of the second integral capacitor C_ITG2 by applying the reference current IREF, and thus can perform a sensing operation for detecting the driving characteristics of each driving transistor based on the detection result.

[0112] The current integrator required for the sensing operation may include multiple current integrators connected to each pixel, and the capacitance of the integration capacitor included in each current integrator may be different. In addition, as the sensing operation continues, the capacitance of the first integration capacitor C_ITG1 and the capacitance of the second integration capacitor C_ITG2 may change due to external influences or internal noise. In this case, it is impossible to accurately detect the driving capability of each drive transistor.

[0113] Therefore, the sensing operation can be performed by applying an arbitrary fixed reference current IREF as the input of the first integration capacitor ITG1. In this case, as shown in the following equation (7), the capacitance of the first integration capacitor C_ITG1 (i.e., the integration capacitor C ITG1 ).

[0114] [Formula 7]

[0115]

[0116] When using the integrating capacitor C ITG1In case the sensing operation is performed, a more accurate first current Ia may be detected, and the timing controller 400 may appropriately generate, store, and apply compensation data by applying a compensation algorithm to the sensing value SD generated based on the first current Ia.

[0117] Although embodiments have been described above, it is not intended that these embodiments describe all possible forms of the inventive concept of the present disclosure. Rather, the terms used in the specification are descriptive rather than restrictive, and it should be understood that various changes may be made without departing from the spirit and scope of the inventive concept of the present disclosure. In addition, the features of the various embodiments may be combined to form other embodiments of the present disclosure.

Claims

1. An organic light emitting diode driving characteristic detection circuit, comprising: a first current integrator configured to receive a first current via a first sensing channel and output a first sample voltage based on the first current; a second current integrator configured to receive a second current via a second sensing channel and output a second sample voltage based on the second current; as well as a sampling circuit having a plurality of sampling capacitors including a first sampling capacitor, a second sampling capacitor, a third sampling capacitor, and a fourth sampling capacitor, The first sampling capacitor and the second sampling capacitor are connected to the output terminal of the first current integrator and are configured to store and hold the first sampling voltage, The third sampling capacitor and the fourth sampling capacitor are connected to the output terminal of the second current integrator and are configured to store and hold the second sampling voltage, and a plurality of switches that selectively connect a first end of the first sampling capacitor, a first end of the second sampling capacitor, a first end of the third sampling capacitor, and a first end of the fourth sampling capacitor, and The sampling circuit is configured to receive the first sampling voltage and the second sampling voltage, store and hold the first sampling voltage and the second sampling voltage, and remove a common noise component contained in the first sampling voltage and the second sampling voltage. The multiple switches include a first sampling transfer switch, a second sampling transfer switch, and a third sampling transfer switch. The first sampling transfer switch connects one end of the first sampling capacitor and one end of the second sampling capacitor; the second sampling transfer switch connects one end of the third sampling capacitor and one end of the fourth sampling capacitor; and the third sampling transfer switch connects the one end of the second sampling capacitor and the one end of the fourth sampling capacitor.

2. The organic light emitting diode driving characteristic detection circuit according to claim 1, wherein: The sampling circuit further includes: a first sampling switch connected between the output terminal of the first current integrator and the first sampling capacitor, a second sampling switch connected between the output terminal of the first current integrator and the second sampling capacitor, a third sampling switch connected between the output terminal of the second current integrator and the third sampling capacitor, and a fourth sampling switch connected between the output terminal of the second current integrator and the fourth sampling capacitor. The first sampling switch and the third sampling switch are configured to be turned off in a first period, and The second sampling switch and the fourth sampling switch are configured to be turned off in a second period different from the first period.

3. The organic light emitting diode driving characteristic detection circuit according to claim 2, wherein: After the first sampling switch, the second sampling switch, the third sampling switch, and the fourth sampling switch are turned off, the plurality of switches are turned on.

4. The organic light emitting diode driving characteristic detection circuit according to claim 2, further comprising: a differential amplifier configured to receive a first held voltage and a second held voltage from the sampling circuit and output an output voltage based on the first held voltage and the second held voltage; as well as The analog-to-digital converter is configured to output a digital sensing signal based on the output voltage.

5. The organic light emitting diode driving characteristic detection circuit according to claim 4, wherein: The differential amplifier comprises a fully differential amplifier, The output voltage is the difference between the non-inverting output voltage and the inverting output voltage of the differential amplifier, and The output voltage is input to the analog-to-digital converter.

6. The organic light emitting diode driving characteristic detection circuit according to claim 5, wherein: The first sampling capacitor and the fourth sampling capacitor are connected to the inverting input terminal of the differential amplifier, and The second sampling capacitor and the third sampling capacitor are connected to a non-inverting input terminal of the differential amplifier.

7. The organic light emitting diode driving characteristic detection circuit according to claim 6, further comprising: a first holding switch connected between the first sampling capacitor and the inverting input terminal of the differential amplifier; a second holding switch connected between the second sampling capacitor and the non-inverting input terminal of the differential amplifier; a third holding switch connected between the third sampling capacitor and the non-inverting input terminal of the differential amplifier; as well as a fourth holding switch connected between the fourth sampling capacitor and the non-inverting input terminal of the differential amplifier, The first holding switch, the second holding switch, the third holding switch, and the fourth holding switch are turned on in the same period.

8. The organic light emitting diode driving characteristic detection circuit according to claim 1, wherein: The sampling circuit further includes a plurality of reference switches, each of which is connected to the first to fourth sampling capacitors and configured to apply a sampling reference voltage to the first, second, third, and fourth sampling capacitors.

9. The organic light emitting diode driving characteristic detection circuit according to claim 1, wherein: The first current integrator and the second current integrator each include an amplifier, The amplifier includes a first input terminal, a second input terminal, an output terminal, an integrating capacitor, and an integrating switch, The first input terminal is connected to the first sensing channel or the second sensing channel, The integrating capacitor is connected between the first input terminal and the output terminal of the amplifier, and The integration switch is connected across the integration capacitor and is configured to reset the integration capacitor, The second input terminal is configured to receive an integrating reference voltage, and The output terminal is configured to output the first sampling voltage or the second sampling voltage.

10. An organic light emitting diode driving characteristic detection circuit, comprising: a first current integrator configured to receive a first current via a first sensing channel and output a first sample voltage based on the first current; a second current integrator configured to receive a second current via a second sensing channel and output a second sample voltage based on the second current; as well as a sampling circuit configured to receive the first sampling voltage and the second sampling voltage, store and hold the first sampling voltage and the second sampling voltage, and remove a common noise component contained in the first sampling voltage and the second sampling voltage; The sampling circuit includes a plurality of sampling capacitors, the plurality of sampling capacitors including a first sampling capacitor, a second sampling capacitor, a third sampling capacitor, a fourth sampling capacitor, and a plurality of switches, the plurality of switches selectively connecting a first end of the first sampling capacitor, a first end of the second sampling capacitor, a first end of the third sampling capacitor, and a first end of the fourth sampling capacitor. The first sampling capacitor is configured to store the first sampling voltage; a first sampling switch connected between the output terminal of the first current integrator and the first sampling capacitor, wherein the first sampling switch is configured to be turned off during a first period of time to complete storing the first sampled voltage in the first sampling capacitor; The second sampling capacitor is configured to store the first sampling voltage; a second sampling switch connected between the output terminal of the first current integrator and the second sampling capacitor, the second sampling switch being configured to be turned off in a second time period after the first time period to complete storing the first sampled voltage in the second sampling capacitor; The third sampling capacitor is configured to store the second sampling voltage; a third sampling switch connected between the output terminal of the second current integrator and the third sampling capacitor, wherein the third sampling switch is configured to be turned off during the first period to complete storing the second sampled voltage in the third sampling capacitor; The fourth sampling capacitor is configured to store the second sampling voltage; and a fourth sampling switch connected between the output terminal of the second current integrator and the fourth sampling capacitor, the fourth sampling switch being configured to be turned off during the second period to complete storing the second sampled voltage in the fourth sampling capacitor, and The multiple switches include a first sampling transfer switch, a second sampling transfer switch, and a third sampling transfer switch. The first sampling transfer switch connects one end of the first sampling capacitor and one end of the second sampling capacitor; the second sampling transfer switch connects one end of the third sampling capacitor and one end of the fourth sampling capacitor; and the third sampling transfer switch connects the one end of the second sampling capacitor and the one end of the fourth sampling capacitor.

11. The organic light emitting diode driving characteristic detection circuit according to claim 10, wherein: The first current integrator and the second current integrator each include an amplifier having a first input terminal, a second input terminal, an output terminal, an integrating capacitor, and an integrating switch. The first input terminal is connected to the first sensing channel or the second sensing channel, The second input terminal is configured to receive an integrating reference voltage, and The output terminal is configured to output the first sampling voltage or the second sampling voltage, The integrating capacitor is connected between the first input terminal and the output terminal of the amplifier, and The integration switch is connected across the integration capacitor and resets the integration capacitor. The integration switch is configured to be turned on and reset the integration capacitor before the first period, and remain turned off during the first period and the second period.

12. The organic light emitting diode driving characteristic detection circuit according to claim 10, wherein: The sampling circuit further includes a plurality of switches, the plurality of switches connecting a first end of the first sampling capacitor, a first end of the second sampling capacitor, a first end of the third sampling capacitor, and a first end of the fourth sampling capacitor, and The plurality of switches are configured to be turned on in a third period after the second period to connect the first sampling capacitor, the second sampling capacitor, the third sampling capacitor, and the fourth sampling capacitor.

13. The organic light emitting diode driving characteristic detection circuit according to claim 12, further comprising: a differential amplifier configured to receive a first held voltage via an inverting input terminal of the sampling circuit and a second held voltage via a non-inverting input terminal of the sampling circuit, and to output an output voltage based on the first held voltage and the second held voltage; as well as an analog-to-digital converter configured to receive the output voltage and output a digital sensing signal related to the output voltage, in, The first sampling capacitor and the fourth sampling capacitor are connected to the inverting input terminal of the differential amplifier, and The second sampling capacitor and the third sampling capacitor are connected to the non-inverting input terminal of the differential amplifier.

14. The organic light emitting diode driving characteristic detection circuit according to claim 13, further comprising: a first holding switch connected between the first sampling capacitor and the inverting input terminal of the differential amplifier; a second holding switch connected between the second sampling capacitor and the non-inverting input terminal of the differential amplifier; a third holding switch connected between the third sampling capacitor and the non-inverting input terminal of the differential amplifier; as well as a fourth holding switch connected between the fourth sampling capacitor and the inverting input terminal of the differential amplifier, The first holding switch, the second holding switch, the third holding switch, and the fourth holding switch are turned on in the third time period to connect the first sampling capacitor, the second sampling capacitor, the third sampling capacitor, and the fourth sampling capacitor to the inverting input terminal or the non-inverting input terminal of the differential amplifier.

15. The organic light emitting diode driving characteristic detection circuit according to claim 13, wherein: The differential amplifier comprises a fully differential amplifier, The output voltage is the difference between the non-inverting output voltage and the inverting output voltage of the differential amplifier, and The output voltage is input to the analog-to-digital converter.

16. The organic light emitting diode driving characteristic detection circuit according to claim 12, wherein: The sampling circuit further includes a plurality of reference switches connected to the first sampling capacitor, the second sampling capacitor, the third sampling capacitor, and the fourth sampling capacitor, the plurality of reference switches being configured to apply a sampling reference voltage to the first sampling capacitor, the second sampling capacitor, the third sampling capacitor, and the fourth sampling capacitor, and The plurality of reference switches are configured to be turned off during the third period.

17. An organic light emitting diode display device, comprising: a display panel having a plurality of pixels connected to data lines and sensing lines, the plurality of pixels including organic light emitting diodes and driving thin film transistors configured to control an amount of light emitted by the organic light emitting diodes; as well as A data driving circuit including a digital-to-analog converter, a plurality of sensing circuits and an analog-to-digital converter, The digital-to-analog converter is configured to apply a data voltage for sensing to the data line during a sensing operation, The plurality of sensing circuits are configured to sense current information of the pixels via a plurality of sensing channels connected to the sensing lines during the sensing operation, each of the sensing circuits comprising a first current integrator, a second current integrator, and a sampling circuit. The first current integrator is configured to receive a first current via a first sensing channel and output a first sampling voltage. The second current integrator is configured to receive a second current via a second sensing channel and output a second sampling voltage, and The sampling circuit is configured to receive, store, and hold the first sampling voltage and the second sampling voltage, and remove a common noise component contained in the first sampling voltage and the second sampling voltage. The sampling circuit includes a plurality of capacitors and a plurality of switches. The plurality of capacitors include a first sampling capacitor, a second sampling capacitor, a third sampling capacitor, and a fourth sampling capacitor. The first sampling capacitor and the second sampling capacitor are connected to the output terminal of the first current integrator and are configured to store the first sampling voltage. The third sampling capacitor and the fourth sampling capacitor are connected to the output terminal of the second current integrator and are configured to store the second sampling voltage. The plurality of switches connect a first end of the first sampling capacitor, a first end of the second sampling capacitor, a first end of the third sampling capacitor, and a first end of the fourth sampling capacitor. The plurality of switches include a first sampling transfer switch, a second sampling transfer switch, and a third sampling transfer switch, wherein the first sampling transfer switch connects one end of the first sampling capacitor and one end of the second sampling capacitor; the second sampling transfer switch connects one end of the third sampling capacitor and one end of the fourth sampling capacitor; the third sampling transfer switch connects the one end of the second sampling capacitor and the one end of the fourth sampling capacitor, and The analog-to-digital converters are commonly connected to the sensing circuit.

18. The organic light emitting diode display device according to claim 17, wherein: The sampling circuit further includes a first sampling switch, a second sampling switch, a third sampling switch and a fourth sampling switch. The first sampling switch is connected between the output terminal of the first current integrator and the first sampling capacitor, and the first sampling switch is configured to be turned off during a first period of time to complete the storage of the first sampling voltage in the first sampling capacitor. The second sampling switch is connected between the output terminal of the first current integrator and the second sampling capacitor, and the second sampling switch is configured to be turned off in a second time period after the first time period to complete the storage of the first sampled voltage in the second sampling capacitor. The third sampling switch is connected between the output terminal of the second current integrator and the third sampling capacitor, and the third sampling switch is configured to be turned off during the first period to complete the storage of the second sampling voltage in the third sampling capacitor. The fourth sampling switch is connected between the output terminal of the second current integrator and the fourth sampling capacitor, and the fourth sampling switch is configured to be turned off during the second period to complete the storage of the second sampling voltage in the fourth sampling capacitor, and The plurality of switches are configured to be turned on in a third period after the second period to connect the first sampling capacitor, the second sampling capacitor, the third sampling capacitor, and the fourth sampling capacitor.

19. The organic light emitting diode display device according to claim 17, wherein: The data voltage for sensing includes a first data voltage and a second data voltage, the first data voltage generates a pixel current greater than zero, and the second data voltage does not generate a pixel current. The driving thin film transistor of the first pixel is configured to generate the first current by applying the first data voltage, and the driving thin film transistor of the first pixel is connected to the first sensing channel. The driving thin film transistor of the second pixel is configured to generate the second current by applying the second data voltage, and the driving thin film transistor of the second pixel is connected to the second sensing channel. The sensing circuit is configured to sense a driving characteristic of the driving thin film transistor of the first pixel based on the first current and the second current.

20. The organic light emitting diode display device according to claim 17, wherein: The data voltage for sensing includes a first data voltage and a second data voltage, the first data voltage generates a pixel current greater than zero, and the second data voltage does not generate a pixel current. A driving thin film transistor of a first pixel and a driving thin film transistor of a second pixel are configured to receive the second data voltage during a first period, the driving thin film transistor of the first pixel is connected to the first sensing channel, and the driving thin film transistor of the second pixel is connected to the second sensing channel, the first current integrator is configured to receive a reference current as an input during the first period, and the sensing circuit is configured to determine a capacitance of an integration capacitor connected between an input terminal and the output terminal of the first current integrator based on the reference current and the second current during the first period, and The driving thin film transistor of the first pixel is configured to receive the first data voltage to generate the first current in a second time period after the first time period, the driving thin film transistor of the second pixel is configured to receive the second data voltage to generate the second current in the second time period, and the sensing circuit is configured to sense the driving characteristics of the driving thin film transistor of the first pixel based on the capacitance of the integration capacitor and based on the first current and the second current in the second time period.

Images