Metal Oxide Semiconductor (MOS) device

Abstract

Embodiments of the present disclosure relate to metal-oxide semiconductor (MOS) devices. The MOS device includes first, second, third, and fourth interconnections. The first interconnection (402) extends on a first track in a first direction. The first interconnection is configured in a metal layer. The second interconnection (404) extends on the first track in the first direction. The second interconnection is configured in the metal layer. The third interconnection (408) extends on a second track in the first direction. The third interconnection is configured in the metal layer. The second track is parallel to the first track. The third interconnection is coupled to the second interconnection. The second and third interconnections (404, 408) are configured to provide a first signal (Clk). The fourth interconnection (410) extends on the second track in the first direction. The fourth interconnection is configured in the metal layer. The fourth interconnection is coupled to the first interconnection. The first and fourth interconnections (402, 410) are configured to provide a second signal (Clk) different from the first signal.

Description

[0001] This application is a divisional application of a Chinese patent application with an application date of March 31, 2016, an application number of 201680029651.0, and an invention title of "Cross-Coupled Clock Signal Distribution Layout in Multi-Height Sequential Cells for Unidirectional M1".

[0002] Cross - Reference to Related Applications

[0003] This application claims the benefit of U.S. Patent Application No. 14 / 723,357, filed on May 27, 2015, entitled "CROSS-COUPLE IN MULTI-HEIGHT SEQUENTIAL CELLS FOR UNI-DIRECTIONAL M1", the entire content of which is hereby expressly incorporated by reference. TECHNICAL FIELD

[0004] The present disclosure generally relates to cross-coupled structures in multi-height sequential cells for unidirectional M1. BACKGROUND ART

[0005] As semiconductor devices are fabricated in smaller dimensions, manufacturers of semiconductor devices find it more difficult to integrate a larger number of devices on a single chip. In addition, modern processing technologies impose more restrictions on semiconductor device layout design, which may result in certain semiconductor layout designs consuming a large amount of area on metal-oxide-semiconductor (MOS) devices. Therefore, there is a need to improve semiconductor layout design to overcome such limitations. SUMMARY OF THE INVENTION

[0006] In one aspect of the present disclosure, a MOS device includes first, second, third, and fourth interconnections. The first interconnection extends on a first track in a first direction. The first interconnection is configured in a metal layer. The second interconnection extends on the first track in the first direction. The second interconnection is configured in the metal layer. The third interconnection extends on a second track in the first direction. The third interconnection is configured in the metal layer. The second track is parallel to the first track. The third interconnection is coupled to the second interconnection. The second and third interconnections are configured to provide a first signal. The fourth interconnection extends on the second track in the first direction. The fourth interconnection is configured in the metal layer. The fourth interconnection is coupled to the first interconnection. The first and fourth interconnections are configured to provide a second signal different from the first signal.

[0007] In one aspect of the present disclosure, in a MOS device, a first signal is propagated through a first interconnect that extends in a first direction on a first track. The first interconnect is configured in a metal layer. Additionally, a second signal is propagated through a second interconnect that extends in the first direction on the first track. The second interconnect is configured in the metal layer. The second signal is different from the first signal. Further, the first signal is propagated through a third interconnect that extends in the first direction on a second track. The third interconnect is configured in the metal layer. The second track is parallel to the first track. The third interconnect is coupled to the second interconnect. Moreover, the second signal is propagated through a fourth interconnect that extends in the first direction on the second track. The fourth interconnect is configured in the metal layer. The fourth interconnect is coupled to the first interconnect. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a diagram showing a multi-bit flip-flop disk.

[0009] Figure 2 is a diagram showing a single-bit flip-flop circuit.

[0010] Figure 3 is a top view of an exemplary layout of a MOS device.

[0011] Figure 4 is a top view of an exemplary layout of a MOS device in accordance with various aspects of the present disclosure.

[0012] Figure 5 is a top view of an exemplary layout of a MOS device in accordance with various aspects of the present disclosure.

[0013] Figure 6 is a flowchart of an exemplary method. DETAILED DESCRIPTION

[0014] The following detailed description presented in conjunction with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts. The apparatus and methods will be described in the following detailed description and may be illustrated in the drawings by various boxes, modules, components, circuits, steps, processes, algorithms, elements, etc.

[0015] Figure 1 is a diagram showing a multi-bit flip-flop disk 100. As Figure 1 shown, the multi-bit flip-flop disk 100 includes single-bit flip-flops 104, 106, 108, 110, 112, 114, 116, and 118. As Figure 1As further shown, each flip-flop in the multi-bit flip-flop disk 100 (which may be referred to as a sequential logic unit) includes a master latch and a slave latch. In one aspect, each master latch is configured to receive the input D of the flip-flop (e.g., D1 of flip-flop 104), and each slave latch is configured to provide the output Q of the flip-flop (e.g., Q1 of flip-flop 104). The multi-bit flip-flop disk 100 may be configured on a MOS device as an arrangement of eight single-row cells.

[0016] Figure 2 is a diagram showing a single-bit flip-flop circuit 200. In one aspect, Figure 2 the flip-flop circuit 200 represents a transistor-level implementation of a flip-flop (e.g., single-bit flip-flop 104) in the multi-bit flip-flop disk 100. As Figure 2 shown, the flip-flop circuit 200 includes a master latch and a slave latch. As Figure 2 shown, the master latch includes N-type transistors 206, 210, 216, and 218 and P-type transistors 204, 208, 212, 214. As Figure 2 further shown, the slave latch includes N-type transistors 222, 226, 232, and 234 and P-type transistors 220, 224, 228, and 230.

[0017] An exemplary operation of the single-bit flip-flop circuit 200 will now be discussed. The input value D may be provided to the input 202 of the master latch. When the clock signal (Clk) is logic "0", the transmission gate 203 (e.g., P-type transistor ("P1") 204 and N-type transistor ("N1") 206) will conduct, and allow the value D to appear at node PN1. When the clock signal transitions to logic "1", the value D will be latched at node PN1 (and the inverse of the value D will be latched at node PN2). When the clock signal is logic "1", the transmission gate 205 (e.g., P-type transistor 220 and N-type transistor 222) will conduct, and allow the inverse of the value D at PN2 to appear at node PN3, and allow the value D to appear at node PN4. When the clock signal (Clk) transitions from logic "1" to logic "0", the transmission gate 205 will disconnect, and the value D will be latched at node PN4. Then the value D is provided at the output Q 236.

[0018] Figure 3 is a top view of an exemplary layout of a MOS device 300. Referring to Figure 2 , the layout is an implementation of part 207 of the single-bit flip-flop circuit 200. It should be understood that Figure 3The figures herein are representations of various masks for features that can be used to fabricate the MOS device 300. For example, each mask can correspond to various features that will be configured in a particular layer (e.g., interconnects, vias, etc.) of the MOS device 300. Thus, for ease of illustration and understanding of the present disclosure, Figure 3 the figures herein simultaneously show multiple layers of the MOS device 300 in a superimposed manner.

[0019] As Figure 3 shown, the MOS device 300 includes P diffusion regions 362, 364, 366, 368 and N diffusion regions 346, 348, 370, 372 and 374. The MOS device 300 also includes gate interconnects 312, 314, 332, 334, 336 and 338. The gate interconnects can be configured in the POLY layer and can be referred to as POLY interconnects. In some process technologies, the gate interconnects can be formed of metal. However, in other process technologies, the gate interconnects can be entirely polysilicon or can be polysilicon with a metal top layer. In Figure 3 the configuration shown, the gate interconnects 312, 334 and 336 correspond to the respective pMOS transistors P1, P2 and P3. The gate interconnects 314, 338 and 332 correspond to the respective nMOS transistors N1, N2 and N3. The gate interconnects 312, 334, 336, 314, 338 and 332 extend in a second direction as shown in the upper right corner of Figure 3 the figure. In Figure 3 the exemplary configuration shown, the gate interconnects 312, 334, 336, 314, 338 and 332 are configured as transistor gates. For example, the gate interconnect 312 is configured as the transistor gate for the pMOS transistor P1, the gate interconnect 314 is configured as the transistor gate for the nMOS transistor N1, the gate interconnect 334 is configured as the transistor gate for the pMOS transistor P2, the gate interconnect 336 is configured as the transistor gate for the pMOS transistor P3, the gate interconnect 338 is configured as the transistor gate for the nMOS transistor N2, and the gate interconnect 332 is configured as the transistor gate for the nMOS transistor N3.

[0020] As Figure 3 shown, the MOS device 300 also includes M1 layer interconnects 301, 302, 304, 306, 308, 317 and 344 in the M1 layer. As Figure 3 shown, the M1 layer interconnects 301, 302, 304, 306, 308, 317 and 344 extend in a first direction. In one aspect, the M1 layer interconnects 301, 304 and 308 are formed using a first mask and are referred to as M1_A layer interconnects. In such an aspect, the M1 layer interconnects 302, 306, 317 and 344 are formed using a second mask and are referred to as M1_V layer interconnects. InFigure 3 In the configuration of, the M1 layer interconnect 302 is coupled to the gate interconnect 312 through a via (V0_MG) 316. In the aspects disclosed herein, the term V0_MG refers to a via formed using metal and coupling an interconnect in a metal layer to an interconnect in the POLY layer. The M1 layer interconnect 302 is also coupled to the gate interconnect 338 through a via (V0_MG) 322. The M1 layer interconnect 304 is coupled to the gate interconnect 336 through a via (V0_MG) 320. The M1 layer interconnect 308 is coupled to the gate interconnect 314 through a via (V0_MG) 318. The M1 layer interconnect 308 is also coupled to the gate interconnect 334 through a via (V0_MG) 340. Thus, in Figure 3 it should be understood that the vias (V0_MG) 316, 318, 320, 322, and 340 are located above the POLY layer and below the M1 layer.

[0021] As Figure 3 shown, the MOS device 300 further includes metal diffusion two (MD2) layer interconnects 313, 315, and 328 configured in the MD2 layer. As Figure 3 shown, the MD2 layer interconnects 313, 315, and 328 extend in a second direction. In one aspect, the MD2 layer is located below the M1 layer and above the POLY layer. As Figure 3 shown, the MD2 layer interconnect 313 is coupled to the source of the transistor P1 (e.g., the diffusion region 362) and the drain of the transistor N1 (e.g., the diffusion region 346). The MD2 layer interconnect 313 can be coupled to the drain of the transistor N1 (e.g., the diffusion region 346) through a metal diffusion one (MD1) layer interconnect (e.g., the MD1 layer interconnect 319). The MD1 layer has the same height as the POLY layer. As Figure 3Further shown, MD2 layer interconnect 315 is coupled to the drain of transistor P1 (e.g., diffusion region 364) and the source of transistor N1 (e.g., diffusion region 348). Since diffusion region 364 is also the drain of transistor P2, MD2 layer interconnect 315 couples the drains of transistors P1 and P2 to the source of transistor N1. MD2 layer interconnect 315 is also coupled to M1 layer interconnect 306 through via (V0_MD) 321. In the aspects disclosed herein, the term V0_MD refers to a via formed using metal and coupling an interconnect in an MD layer (e.g., MD2 layer) to an interconnect in a metal layer. MD2 layer interconnect 325 is coupled to M1 layer interconnect 306 through via (V0_MD) 323 and further coupled to the drain of transistor N2 (e.g., diffusion region 370). MD2 layer interconnect 328 is coupled to M1 layer interconnect 304 through via (V0_MD) 326 and is also coupled to gate interconnect 332 via a metal POLY (MP) layer interconnect 330 in the MP layer located above gate interconnect 332. The MP layer is at the same height as the MD2 layer. Thus, MD2 layer interconnect 328 and MP layer interconnect 330 are adjacent to each other to form a connection.

[0022] In Figure 3 aspects, gate interconnect 312 is electrically isolated from gate interconnect 314 by configuring a single gate interconnect and by applying a cut mask portion 310. The cut mask portion 310 is configured to cut the single gate interconnect to effectively form two electrically isolated gate interconnects. Additionally, M1 layer interconnect 317 is electrically isolated from M1 layer interconnect 344 by configuring a single M1 layer interconnect and by applying a cut mask portion 342. The cut mask portion 342 is configured to cut the single M1 layer interconnect to effectively form two electrically isolated M1 layer interconnects.

[0023] In Figure 3 an example configuration, an input value D (e.g., logic "1" or logic "0") can be provided to M1 layer interconnect 317. As Figure 3 shown, M1 layer interconnect 302 is configured to carry a clock signal (Clk), and M1 layer interconnect 308 is configured to carry the inverse of the clock signal Referring Figure 2 to, M1 layer interconnect 306 corresponds to node PN1, and M1 layer interconnect 304 corresponds to node PN2.

[0024] As Figure 3 shown, the area consumed on the MOS device can be represented in grid cells, such as grid cells 350, 352, 354, 356, 358, and 360. In Figure 3In an example configuration, each of the grid cells 350, 352, 354, 356, 358, and 360 indicates the required spacing between two adjacent gate interconnections. In one aspect, the grid cells 350, 352, 354, 356, 358, and 360 are substantially equal. Thus, in Figure 3 In an example configuration, the MOS device consumes six grid cells (e.g., grid cells 350, 352, 354, 356, 358, and 360). In the case of six grid cells, there are six gate interconnections within the cell. The six gate interconnections include gate interconnections 312 / 314, 334, 336, 338, 332, and two "half gate interconnections" (not shown) on each side of the cell.

[0025] Figure 4 is a top view of an exemplary layout of a MOS device 400 according to various aspects of the present disclosure. Similar to Figure 3 the layout diagram of Figure 4 the layout diagram of Figure 2 is an implementation of part 207 of the single-bit flip-flop circuit 200 of Figure 4 Thus, the layout diagram of Figure 3 performs the same function as the layout diagram of Figure 4 It should be understood that the diagrams in Figure 4 are representations of various masks that can be used to fabricate the features of the MOS device 400. For example, each mask can correspond to various features that will be configured in a specific layer (e.g., interconnect, via, etc.) of the MOS device 400. Thus, for ease of illustration and understanding of the present disclosure,

[0026] As Figure 4 shown, the MOS device 400 includes P-diffusion regions 446, 449, 451, and 453 and N-diffusion regions 438, 440, 455, and 457. The MOS device 400 also includes gate interconnections 414, 416, 418, 420, and 424. At the edges of the cell, the MOS device 400 includes half-width gate interconnections 422 and 426. As Figure 4 further shown, the gate interconnections 414 and 418 extend along track 492 in a second direction, and the gate interconnections 416 and 420 extend along track 494 in the second direction, where track 492 is parallel to track 494.

[0027] The gate interconnections can be configured in the POLY layer and can be referred to as POLY interconnections. In Figure 4In the configuration, gate interconnections 414 and 416 correspond to respective pMOS transistors P1 and P2. Gate interconnections 418 and 420 correspond to respective nMOS transistors N1 and N2. Gate interconnection 424 corresponds to pMOS transistor P3 and nMOS transistor N3. Gate interconnections 414, 416, 418, 420, 422, 424, and 426 extend along Figure 4 the second direction as shown in the upper right corner of Figure 4 In the exemplary configuration of

[0028] As Figure 4 shown, MOS device 400 further includes M1 layer interconnections 401, 404, 406, 408, 410, 412, and 473 configured in the M1 layer. As Figure 4 shown, M1 layer interconnections 401, 404, 406, 408, 410, 412, and 473 extend in the first direction. As Figure 4 further shown, M1 layer interconnection 404 extends along track 480 in the first direction, and M1 layer interconnection 410 extends along track 490 in the first direction, where track 480 is parallel to track 490.

[0029] In one aspect, M1 layer interconnections 401, 406, and 412 are formed using a first mask and are referred to as M1_A layer interconnections. In such an aspect, M1 layer interconnections 402, 404, 408, 410, and 473 are formed using a second mask and are referred to as M1_V layer interconnections. In Figure 4 the configuration, M1 layer interconnection 402 is coupled to gate interconnection 414 through via (V0_MG) 428. M1 layer interconnection 404 is coupled to gate interconnection 416 through via (V0_MG) 430. M1 layer interconnection 408 is coupled to gate interconnection 418 through via (V0_MG) 432. M1 layer interconnection 410 is coupled to gate interconnection 420 through via (V0_MG) 434. M1 layer interconnection 412 is coupled to gate interconnection 424 through via (V0_MG) 436. Thus, in Figure 4 it should be understood that vias (V0_MG) 428, 430, 432, 434, and 436 are located above the POLY layer and below the M1 layer.

[0030] As Figure 4 shown, the MOS device 400 further includes MD2 layer interconnects 443 and 471 configured in the MD2 layer. As Figure 4 shown, the MD2 layer interconnects 443 and 471 extend in the second direction. In one aspect, the MD2 layer is located below the M1 layer and above the POLY layer. As Figure 4 shown, the MD2 layer interconnect 443 is coupled to the source of transistor P1 (e.g., diffusion region 446) and the drain of transistor N1 (e.g., diffusion region 438). The MD2 layer interconnect 443 may be coupled to the drain of transistor N1 (e.g., diffusion region 438) through an MD1 layer interconnect (e.g., MD1 layer interconnect 475). As Figure 4 Further shown, the MD2 layer interconnect 471 is coupled to the drain of transistor P1 (e.g., diffusion region 449) and the source of transistor N1 (e.g., diffusion region 440). Since the diffusion region 449 is also the drain of transistor P2, the MD2 layer interconnect 471 is also coupled to the drain of transistor P2 (e.g., diffusion region 449). Since the diffusion region 440 is also the drain of transistor N2, the MD2 layer interconnect 471 is also coupled to the drain of transistor N2 (e.g., diffusion region 440). The MD2 layer interconnect 471 is further coupled to the M1 layer interconnect 406 through a via (V0_MD) 476. The MD2 layer interconnect 443 is coupled to the M1 layer interconnect 473 through a via (V0_MD) 445. Referring again to the diffusion regions 453, 451, 457, and 455, the diffusion region 453 is the source of transistor P3, the diffusion region 451 is the drain of transistor P3 and the source of transistor P2, the diffusion region 457 is the source of transistor N3, and the diffusion region 455 is the drain of transistor N3 and the source of transistor N2.

[0031] In Figure 4 this aspect, the gate interconnect 414 is electrically isolated from the gate interconnect 418 by configuring a single gate interconnect and applying a cut mask portion 442. Additionally, the gate interconnect 416 is electrically isolated from the gate interconnect 420 by configuring a single gate interconnect and applying a cut mask portion 442. The cut mask portion 442 extending in the first direction is configured to cut the corresponding gate interconnects extending in the second direction so as to effectively form a plurality of electrically isolated gate interconnects. Additionally, the M1 layer interconnect 402 is electrically isolated from the M1 layer interconnect 404 by configuring a single M1 layer interconnect and applying a cut mask portion 444. The M1 layer interconnect 408 is electrically isolated from the M1 layer interconnect 410 by configuring a single M1 layer interconnect 410 and applying a cut mask portion 444. The cut mask portion 444 extending in the second direction is configured to cut the corresponding M1 layer interconnects extending in the first direction so as to effectively form a plurality of electrically isolated M1 layer interconnects.

[0032] In Figure 4 an example configuration, an input value D (e.g., a logic "1" or a logic "0") can be provided to the M1 layer interconnect 473. As Figure 4 shown, the M1 layer interconnects 402 and 410 are configured to carry a clock signal (Clk), and the M1 layer interconnects 404 and 408 are configured to carry the inverse of the clock signal with reference to Figure 2 , the M1 layer interconnect 406 corresponds to the node PN1, and the M1 layer interconnect 412 corresponds to the node PN2.

[0033] As Figure 4 shown, the area consumed on the MOS device can be represented in grid cells, such as grid cells 448, 450, 452, and 454. In Figure 4 an example configuration, each of the grid cells 448, 450, 452, and 454 indicates the spacing required between two adjacent gate interconnects. In one aspect, the grid cells 448, 450, 452, and 454 are substantially equal. Additionally, Figure 4 each of the four grid cells 448, 450, 452, and 454 in Figure 3 can be substantially equal to each of the six grid cells 350, 352, 354, 356, 358, and 360 in Figure 4 . In the case of the four grid cells, there are four gate interconnects within the cell. The four gate interconnects include the gate interconnects 414 / 418, 416 / 420, and 424, and two "half-width gate interconnects" 422 and 426 on each side of the cell. When the cell is next to an adjacent cell, the half-width gate interconnects 422 and 426 are adjacent to the adjacent half-width gate interconnects to form a normal-width gate interconnect (which can be utilized by the corresponding adjacent cell or can be a dummy / unused gate interconnect). Thus, since the MOS device 400 consumes the area of four grid cells (e.g., grid cells 448, 450, 452, and 454), the

[0034] Figure 5 is a top view of an exemplary layout of a MOS device 500 in accordance with various aspects of the present disclosure. The MOS device 500 includes M1 layer interconnects 502, 504, and 506, metal 2 (M2) layer interconnects 508, 510, 512, and 514, and a portion 490. It should be noted that Figure 5 the portion 490 in Figure 4 corresponds to the portion 490 shown in Figure 5As shown, the M1 layer interconnect 502 extends in a first direction along the track 503, and the M1 layer interconnect 504 extends in the first direction along the track 505. In one aspect, the M1 layer interconnect 502 can be configured to carry a clock signal (Clk), and the M1 layer interconnect 504 can be configured to carry the inverse of the clock signal

[0035] As Figure 5 shown, a first group of interconnects 508 and 512 configured in the M2 layer located above the M1 layer are respectively coupled to the M1 layer interconnects 402 and 410. The first group of interconnects 508 and 512 are respectively coupled to the M1 layer interconnects 402 and 410 using vias (V1) 516, 518, 524, and 526. As Figure 5 further shown, a second group of interconnects 510 and 514 configured in the M2 layer are respectively coupled to the M1 layer interconnects 408 and 404. The second group of interconnects 510 and 514 are respectively coupled to the M1 layer interconnects 408 and 404 using vias (V1) 520, 522, 528, and 530. In one aspect, referring Figure 1 to, the M1 layer interconnects 502 and 504 can be extended to provide the clock signal and the inverse of the clock signal to multiple single-row cells in the multi-bit flip-flop disk 100

[0036] Referring again Figure 1 , 4 and 5, the multi-bit flip-flop disk 100 includes multiple bit flip-flops 104, 106, 108, 110, 112, 114, 116, and 118. As Figure 5 shown, the clock Clk and the inverse clock can be respectively provided to each bit flip-flop through the M1 layer interconnects 503 and 505 and through the corresponding M2 layer interconnects 516, 524, 520, and 528. The M2 layer interconnects 516, 524, 520, and 528 can extend across the cells and across each bit flip-flop unit in the same column to provide the clock Clk and the inverse clock to the bit flip-flop unit For example, assuming that the MOS device 400 corresponds to the bit flip-flop unit 104, the M2 layer interconnects 516 and 524 can extend across the unit corresponding to the MOS device 400 / bit flip-flop unit 104 and across each unit corresponding to the bit flip-flop units 106, 108, and 110, so as to provide the clock Clk for each of the bit flip-flop units 104, 106, 108, and 110. In addition, the M2 layer interconnects 520 and 528 can extend across the unit corresponding to the MOS device 400 / bit flip-flop unit 104 and across each unit corresponding to the bit flip-flop units 106, 108, and 110, so as to provide the inverse clock to each of the bit flip-flop units 104, 106, 108, and 110 The M1 layer interconnects 502 and 504 are shown as being connected to the clock Clk and the inverse clock respectively However, the M1 layer interconnects 502 and 504 can be connected to the inverse clock and the clock Clk respectively. As Figure 4 and Figure 5 shown, the clock Clk and the inverse clock are cross-coupled because the couplings of the M1 layer interconnects 404 and 408 that are diagonally positioned with respect to each other across the M1 layer interconnects 402 and 410 are coupled together, and the couplings of the M1 layer interconnects 402 and 410 that are diagonally positioned with respect to each other across the M1 layer interconnects 404 and 408 are coupled together. Each of the M1 layer interconnects 503, 505, 402, 410, 404 and 408 is unidirectional and extends in the same direction (e.g., the first direction). The other M1 layer interconnects 401, 406, 412 and 473 are also unidirectional and extend in the same direction (e.g., the first direction).

[0037] Referring again to Figure 4 and 5 , the MOS device includes a first interconnect 402 that extends on a first track 480 in a first direction. The first interconnect 402 is configured in the M1 layer. The MOS device further includes a second interconnect 404 that extends on the first track 480 in the first direction. The second interconnect 404 is configured in the M1 layer. The MOS device further includes a third interconnect 408 that extends on a second track 490 in the first direction. The third interconnect 408 is configured in the M1 layer. The second track 490 is parallel to the first track 480. The MOS device further includes a fourth interconnect 410 that extends on the second track 490 in the first direction. The fourth interconnect 410 is configured in the M1 layer. The first interconnect 402 is coupled to the fourth interconnect 410, and the second interconnect 404 is coupled to the third interconnect 408.

[0038] In one configuration, the MOS device further includes a first gate interconnect 414 extending on a third track 492 in a second direction orthogonal to the first direction. The first gate interconnect is located in the POLY layer below the M1 layer. The MOS device further includes a second gate interconnect 418 extending on the third track 492 in the second direction. The second gate interconnect 418 is located in the POLY layer. The MOS device further includes a third gate interconnect 416 extending on a fourth track 494 in the second direction. The third gate interconnect 416 is located in the POLY layer. The fourth track 494 is parallel to the third track 492. The MOS device further includes a fourth gate interconnect 420 extending on the fourth track 494 in the second direction. The fourth gate interconnect 420 is located in the POLY layer. In one configuration, the first interconnect 402 is coupled to the first gate interconnect 414, the second interconnect 404 is coupled to the third gate interconnect 416, the third interconnect 408 is coupled to the second gate interconnect 418, and the fourth interconnect 410 is coupled to the fourth gate interconnect 420.

[0039] In one configuration, the MOS device further includes a fifth interconnect 502 extending on a third track 503. The third track 503 is parallel to the first track 480 and the second track 490. The MOS device further includes a sixth interconnect 504 extending on a fourth track 505. The fourth track 505 is parallel to the third track 503. The fifth interconnect 502 is coupled to the first interconnect 402 and the fourth interconnect 410, and the sixth interconnect 504 is coupled to the second interconnect 404 and the third interconnect 408. In one configuration, the fifth interconnect 502 is coupled to the first interconnect 402 and the fourth interconnect 410 through a first set of interconnects 508, 512 configured in the M2 layer and extending in a second direction orthogonal to the first direction. In such a configuration, the sixth interconnect 504 is coupled to the second interconnect 404 and the third interconnect 408 through a second set of interconnects 514, 510 configured in the M2 layer and extending in the second direction.

[0040] In one configuration, the MOS device further includes: a first pMOS transistor P1 including a first pMOS transistor gate, a first pMOS transistor source, and a first pMOS transistor drain; a second pMOS transistor P2 including a second pMOS transistor gate, a second pMOS transistor source, and a second pMOS transistor drain; a first nMOS transistor N1 including a first nMOS transistor gate, a first nMOS transistor source, and a first nMOS transistor drain; and a second nMOS transistor N2 including a second nMOS transistor gate, a second nMOS transistor source, and a second nMOS transistor drain. The first pMOS transistor gate 414 is coupled to the first interconnect 402, the second pMOS transistor gate 416 is coupled to the second interconnect 404, the first nMOS transistor gate 418 is coupled to the third interconnect 408, and the second nMOS transistor gate 420 is coupled to the fourth interconnect 410. In one configuration, the first pMOS transistor source 446 and the first nMOS transistor drain 438 are coupled together to an MD layer (e.g., MD2 layer) interconnect 443 that extends in a second direction orthogonal to the first direction. In one configuration, the MOS device further includes a fifth interconnect 473 that extends in the first direction on the M1 layer. The fifth interconnect 473 is coupled to the MD layer interconnect 443. The fifth interconnect 473 is configured to receive an input to the MOS device.

[0041] In one configuration, the first pMOS transistor drain 449 and the second pMOS transistor drain 449 are the same, and the first nMOS transistor source 440 and the second nMOS transistor drain 440 are the same. In one configuration, the first pMOS transistor drain and the second pMOS transistor drain 449 are coupled to the first nMOS transistor source and the second nMOS transistor drain 440 through an MD layer (e.g., MD2 layer) interconnect 471 that extends in a second direction orthogonal to the first direction. In one configuration, the MOS device further includes a fifth interconnect 412 (PN2) that extends in the first direction on the M1 layer. The fifth interconnect 412 is coupled to the MD layer interconnect 471. The fifth interconnect 412 is the output of the MOS device.

[0042] In one configuration, the MOS device further includes: a third pMOS transistor P3 including a third pMOS transistor gate, a third pMOS transistor source, and a third pMOS transistor drain; and a third nMOS transistor N3 including a third nMOS transistor gate, a third nMOS transistor source, and a third nMOS transistor drain. The third pMOS transistor gate 424 and the third nMOS transistor gate 424 are formed by the same gate interconnect 424 extending in a first direction. In one configuration, the third pMOS transistor drain 451 and the second pMOS transistor source 451 are the same, and the third nMOS transistor drain 455 and the second nMOS transistor source 455 are the same. In one configuration, the third pMOS transistor source 453 is configured to be coupled to a first voltage source (e.g., VDD), and the third nMOS transistor source 457 is configured to be coupled to a second voltage source (e.g., VSS, which may be ground).

[0043] As Figure 4 shown, the MOS device has a width of four grids. The first, second, third, and fourth interconnects 402, 404, 408, 410 are unidirectional interconnects. The first, second, third, and fourth interconnects 402, 404, 408, 410 are M1 layer interconnects.

[0044] Figure 6 is a flowchart 600 of an exemplary method. The exemplary method is a method of operating a MOS device. It should be understood that Figure 6 the operations shown in dashed lines are optional operations.

[0045] At 602, a first signal is propagated through a first interconnect extending in a first direction on a first track, and the first interconnect is configured in a metal layer. For example, referring to Figure 4 , the first interconnect may be the M1 layer interconnect 402, the first track may be the track 480, and the first signal may be the clock signal Clk.

[0046] At 604, a second signal is propagated through a second interconnect extending in a first direction on a first track. The second interconnect is configured in a metal layer. The second signal is different from the first signal. For example, referring to Figure 4 , the second interconnect may be the M1 layer interconnect 404, and the second signal may be the inverse clock signal.

[0047] At 606, the first signal is propagated through a third interconnect extending in a first direction on a second track. The third interconnect is configured in a metal layer. The second track is parallel to the first track. For example, referring to Figure 4 , the third interconnect may be the M1 layer interconnect 408, and the second track may be the track 490.

[0048] At 608, a second signal is propagated through a fourth interconnect extending in a first direction on a second track. The fourth interconnect is configured in a metal layer. For example, referring to Figure 4 , the fourth interconnect may be the M1 layer interconnect 410. In one aspect, the first interconnect is coupled to the fourth interconnect, and the second interconnect is coupled to the third interconnect.

[0049] At 610, a first signal is propagated through a first gate interconnect extending in a second direction orthogonal to the first direction on a third track. The first gate interconnect is located in a first layer below the metal layer. For example, referring to Figure 4 , the first gate interconnect may be the POLY layer interconnect 414, and the third track may be the track 492.

[0050] At 612, a second signal is propagated through a second gate interconnect extending in the second direction on the third track. The second gate interconnect is located in the first layer. For example, referring to Figure 4 , the second gate interconnect may be the POLY layer interconnect 418.

[0051] At 614, a second signal is propagated through a third gate interconnect extending in the second direction on a fourth track. The third gate interconnect is located in the first layer. The fourth track is parallel to the third track. For example, referring to Figure 4 , the third gate interconnect may be the POLY layer interconnect 416, and the fourth track may be the track 494.

[0052] At 616, a first signal is propagated through a fourth gate interconnect extending in the second direction on the fourth track. The fourth gate interconnect is located in the first layer. For example, referring to Figure 4 , the fourth gate interconnect may be the POLY layer interconnect 420. In one aspect, the first interconnect is coupled to the first gate interconnect, the second interconnect is coupled to the third gate interconnect, the third interconnect is coupled to the second gate interconnect, and the fourth interconnect is coupled to the fourth gate interconnect.

[0053] At 618, a first signal is propagated through a fifth interconnect extending on the third track. The third track is parallel to the first and second tracks. For example, the fifth interconnect may be the M1 layer interconnect 502, and the third track may be the track 503.

[0054] At 620, a second signal is propagated through a sixth interconnect extending on the fourth track. The fourth track is parallel to the third track. For example, the sixth interconnect may be the M1 layer interconnect 504, and the third track may be the track 505. In one aspect, the fifth interconnect is coupled to the first and fourth interconnects, and the sixth interconnect is coupled to the second and third interconnects. In one aspect, the fifth interconnect is coupled to the first and fourth interconnects through a first set of interconnects configured in a second metal layer (e.g., M2) and extending in the second direction. For example, referring toFigure 5 , the first set of interconnects can be the M2 layer interconnects 508 and 512. In such an aspect, the sixth interconnect is coupled to the second and third interconnects through a second set of interconnects configured in the second metal layer and extending in the second direction. For example, referring to Figure 5 , the second set of interconnects can be the M2 layer interconnects 510 and 514. In one aspect, the first, second, third, and fourth gate interconnects are configured in the POLY layer.

[0055] In one aspect, the MOS device includes a first means for propagating a first signal. The first means (e.g., the M1 layer interconnect 402) extends in a first direction on a first track (e.g., track 480). The first means is configured in a metal layer (e.g., M1). The MOS device further includes a second means (e.g., the M1 layer interconnect 404) for propagating a second signal. The second means extends in the first direction on the first track. The second means is configured in the metal layer. The MOS device further includes a third means (e.g., the M1 layer interconnect 408) for propagating the first signal. The third means extends in the first direction on a second track (e.g., track 490). The third means is configured in the metal layer. The second track is parallel to the first track. The MOS device further includes a fourth means for propagating the second signal. The fourth means (e.g., the M1 layer interconnect 410) extends in the first direction on the second track. The fourth means is configured in the metal layer. In one aspect, the first means is coupled to the fourth means, and the second means is coupled to the third means.

[0056] In one aspect, the MOS device further includes a fifth means for propagating the first signal. The fifth means (e.g., the gate interconnect 414) extends in a second direction orthogonal to the first direction on a third track (e.g., track 492). The fifth means is located in a first layer (e.g., the POLY layer) below the metal layer. The MOS device further includes a sixth means (e.g., the gate interconnect 418) for propagating the second signal. The sixth means extends in the second direction on the third track. The sixth means is located in the first layer. The MOS device further includes a seventh means (e.g., the gate interconnect 416) for propagating the second signal. The seventh means extends in the second direction on a fourth track (e.g., track 494). The seventh means is located in the first layer. The fourth track is parallel to the third track. The MOS device further includes an eighth means (e.g., the gate interconnect 420) for propagating the first signal. The eighth means extends in the second direction on the fourth track. The eighth means is located in the first layer. In one aspect, the first means is coupled to the fifth means, the second means is coupled to the seventh means, the third means is coupled to the sixth means, and the fourth means is coupled to the eighth means.

[0057] In one aspect, the MOS device further includes a fifth means for propagating a first signal. The fifth means (e.g., M1 layer interconnect 502) extends on a third track (e.g., track 503). The third track is parallel to the first and second tracks. The MOS device further includes a sixth means (e.g., M1 layer interconnect 504) for propagating a second signal. The sixth means extends on a fourth track (e.g., track 505). The fourth track is parallel to the third track. In one aspect, the fifth means is coupled to the first and fourth means (e.g., M1 layer interconnects 402 and 410), and the sixth means is coupled to the second and third means (e.g., M1 layer interconnects 404 and 408).

[0058] In one aspect, the fifth means is coupled to the first and fourth means by a first set of interconnects configured in a second metal layer (e.g., M2) and extending in a second direction, and the sixth means is coupled to the second and third means by a second set of interconnects configured in the second metal layer (e.g., M2) and extending in a second direction. In one aspect, the fifth, sixth, seventh, and eighth means are configured in the POLY layer. In one aspect, the fifth, sixth, seventh, and eighth means are gate interconnects. In one aspect, the first, second, third, and fourth means are unidirectional interconnects. Specifically, in one aspect, the first, second, third, and fourth means are unidirectional M1 layer interconnects.

[0059] It should be understood that the specific order or hierarchy of steps in the disclosed processes is an illustration of exemplary methods. It should be understood that based on design preferences, the specific order or hierarchy of steps in a process may be rearranged. Additionally, some steps may be combined or omitted. The appended method claims present the elements of various steps in a sample order and do not imply limitation to the specific order or hierarchy presented.

[0060] The foregoing description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects. Thus, the claims are not intended to be limited to the aspects shown herein, but are to be accorded the full scope consistent with the language of the claims, where the reference to an element in the singular is not intended to mean "one and only one" unless specifically so stated, but rather "one or more." The term "exemplary" as used herein means "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects. Unless specifically stated otherwise, the term "some" means one or more. Combinations such as "at least one of A, B, or C," "at least one of A, B, and C," and "any combination of A, B, C, or their combinations" include any combination of A, B, and / or C, and may include multiple A's, multiple B's, or multiple C's. Specifically, combinations such as "at least one of A, B, or C," "at least one of A, B, and C," and "any combination of A, B, C, or their combinations" can be only A, only B, only C, A and B, A and C, B and C, or A and B and C, where any such combination can include one or more members of A, B, or C. All structural and functional equivalents of the elements of the various aspects described throughout this disclosure that are known or later become known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be covered by the claims. Furthermore, nothing disclosed herein is dedicated to the public, whether or not such disclosure is expressly recited in the claims. No requirement is made that the elements of a claim be construed as means-plus-function unless the phrase "means for" is expressly recited with respect to the element.

Claims

1. A metal-oxide-semiconductor (MOS) device, comprising: A first interconnect extending in a first direction on a first track, the first interconnect being configured in a metal layer; A second interconnect extending in the first direction on the first track, the second interconnect being configured in the metal layer; A third interconnect extending in the first direction on a second track, the third interconnect being configured in the metal layer, the second track being parallel to the first track, the third interconnect being coupled to the second interconnect, the second interconnect and the third interconnect being configured to provide a first signal; And A fourth interconnect extending in the first direction on the second track, the fourth interconnect being configured in the metal layer, the fourth interconnect being coupled to the first interconnect, the first interconnect and the fourth interconnect being configured to provide a second signal different from the first signal, Wherein the first interconnect and the third interconnect extend in a second direction with a first equal length, wherein the second interconnect and the fourth interconnect extend in the second direction with a second equal length, and wherein the second direction is orthogonal to the first direction.

2. The MOS device according to claim 1, wherein the first interconnect and the second interconnect are adjacent to each other in the first direction, and the third interconnect and the fourth interconnect are adjacent to each other in the first direction.

3. The MOS device according to claim 1, wherein the first interconnect and the second interconnect are formed by configuring a first single metal layer and applying a cutting mask, and wherein the third interconnect and the fourth interconnect are formed by configuring a second single metal layer and applying the cutting mask.

4. The MOS device according to claim 1, further comprising: A fifth interconnect extending on a third track, the third track being parallel to the first track and the second track; And A sixth interconnect extending on a fourth track, the fourth track being parallel to the third track, Wherein the fifth interconnect is coupled to the first interconnect and the fourth interconnect, and wherein the sixth interconnect is coupled to the second interconnect and the third interconnect.

5. The MOS device according to claim 4, wherein the fifth interconnect is coupled to the first interconnect and the fourth interconnect through a first group of interconnects, the first group of interconnects being configured in a second metal layer and extending in the second direction, and wherein the sixth interconnect is coupled to the second interconnect and the third interconnect through a second group of interconnects, the second group of interconnects being configured in the second metal layer and extending in the second direction.

6. The MOS device according to claim 1, further comprising: A first pMOS transistor, comprising a first pMOS transistor gate, a first pMOS transistor source, and a first pMOS transistor drain; A second pMOS transistor, comprising a second pMOS transistor gate, a second pMOS transistor source, and a second pMOS transistor drain; The first nMOS transistor, comprising a first nMOS transistor gate, a first nMOS transistor source, and a first nMOS transistor drain; The second nMOS transistor, comprising a second nMOS transistor gate, a second nMOS transistor source, and a second nMOS transistor drain, wherein the first pMOS transistor gate is coupled to the first interconnect, the second pMOS transistor gate is coupled to the second interconnect, the first nMOS transistor gate is coupled to the third interconnect, and the second nMOS transistor gate is coupled to the fourth interconnect.

7. The MOS device according to claim 6, wherein the first pMOS transistor source and the first nMOS transistor drain are coupled together through a metal diffusion MD layer interconnect, and the metal diffusion layer interconnect extends in the second direction.

8. The MOS device according to claim 7, further comprising a fifth interconnect extending in the first direction on the metal layer, the fifth interconnect being coupled to the MD layer interconnect, and the fifth interconnect being configured to receive an input to the MOS device.

9. The MOS device according to claim 6, wherein the first pMOS transistor drain and the second pMOS transistor drain are the same, and the first nMOS transistor source and the second nMOS transistor drain are the same.

10. The MOS device according to claim 9, wherein the first pMOS transistor drain and the second pMOS transistor drain are coupled to the first nMOS transistor source and the second nMOS transistor drain through a metal diffusion MD layer interconnect, and the metal diffusion layer interconnect extends in the second direction.

11. The MOS device according to claim 10, further comprising a fifth interconnect extending in the first direction on the metal layer, the fifth interconnect being coupled to the MD layer interconnect, and the fifth interconnect being the output of the MOS device.

12. The MOS device according to claim 6, further comprising: A third pMOS transistor, comprising a third pMOS transistor gate, a third pMOS transistor source, and a third pMOS transistor drain; And A third nMOS transistor, comprising a third nMOS transistor gate, a third nMOS transistor source, and a third nMOS transistor drain, wherein the third pMOS transistor gate and the third nMOS transistor gate are formed by the same gate interconnect extending in the first direction.

13. The MOS device according to claim 12, wherein the third pMOS transistor drain and the second pMOS transistor source are the same, and the third nMOS transistor drain and the second nMOS transistor source are the same.

14. The MOS device according to claim 12, wherein the third pMOS transistor source is configured to be coupled to a first voltage source, and the third nMOS transistor source is configured to be coupled to a second voltage source.

15. The MOS device according to claim 1, wherein the MOS device has a width of four grids.

16. The MOS device according to claim 1, wherein the first interconnect, the second interconnect, the third interconnect, and the fourth interconnect are unidirectional interconnects.

17. The MOS device according to claim 16, wherein the first interconnect, the second interconnect, the third interconnect, and the fourth interconnect are metal-M1 layer interconnects.

18. The MOS device according to claim 1, wherein the second signal is the inverse of the first signal.

19. The MOS device according to claim 18, wherein the second signal is a clock signal, and the first signal is an inverse clock signal.

20. The MOS device according to claim 1, wherein the MOS device is a flip-flop circuit.

21. The MOS device according to claim 20, wherein the first signal is the clock signal of the flip-flop circuit, and the second signal is the inverse of the clock signal of the flip-flop circuit.

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