Display device and method for manufacturing the same

Abstract

A display device and a method of manufacturing the display device are provided. The display device includes pixels connected to scan lines and data lines intersecting the scan lines. Each of the pixels includes a light-emitting element and a first transistor configured to control a driving current supplied to the light-emitting element according to a data voltage applied from the data line. The first transistor includes a first active layer and a first oxide layer. The first active layer has an oxide semiconductor, and the first oxide layer is located on the first active layer and has a crystalline oxide containing tin (Sn).

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2019 - 0086441, filed with the Korean Intellectual Property Office on July 17, 2019, the content of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate to a display device including a thin - film transistor having an oxide layer and a method of manufacturing the display device. Background Art

[0004] With the development of multimedia technology, the importance of display devices has gradually increased. Accordingly, various types of display devices, such as organic light - emitting displays (OLEDs), liquid - crystal displays (LCDs), etc., have been used.

[0005] A display device is a device for displaying an image and includes a display panel such as an organic light - emitting display panel or a liquid - crystal display panel. Among them, the light - emitting display panel may include light - emitting elements. Examples of light - emitting diodes (LEDs) include organic light - emitting diodes (OLEDs) using organic materials as fluorescent materials and inorganic light - emitting diodes using inorganic materials as fluorescent materials.

[0006] A display device includes a display panel, a gate driving circuit, a data driving circuit, and a timing controller. The display panel includes data lines, gate lines, and pixels formed at the intersection regions of the data lines and the gate lines. When using a thin - film transistor as a switching element to supply a gate signal to the gate line, each of the pixels receives a data voltage from the data line. Each of the pixels emits light (e.g., light having a predetermined brightness) according to the data voltage.

[0007] Recently, display devices capable of displaying high - resolution images with ultra - high definition (UHD) have been proposed, and display devices capable of displaying high - resolution images with 8K ultra - high definition (8K UHD) are being developed. UHD refers to a resolution of 3840 × × 2160 pixels, and 8K UHD refers to a resolution of 7680 × × 4320 pixels.

[0008] In the case of a high - resolution display device, as the number of pixels increases, the driving current of each pixel decreases. As a result, the driving voltage range of the driving transistor of each pixel is reduced. Summary of the Invention

[0009] Aspects of the present disclosure provide a display device including a thin - film transistor, and the thin - film transistor further includes an oxide layer.

[0010] However, aspects of the present disclosure are not limited to those described herein. By referring to the detailed description of the present disclosure given below, the above and other aspects of the present disclosure will become apparent to those of ordinary skill in the art to which the present disclosure pertains, and may include other aspects not described herein.

[0011] Some embodiments relate to a display device that may include a driving transistor, wherein the driving transistor includes an active layer having an oxide semiconductor and an oxide layer having a crystalline oxide containing tin. The oxide layer may inject oxygen into the active layer to reduce the concentration of oxygen defect regions in the active layer. Accordingly, the driving transistor of the display device may have excellent device characteristics.

[0012] In addition, according to some embodiments, since the driving transistor includes an oxide layer having a crystalline oxide, the possibility of undercut phenomenon that may occur in the process of forming the gate electrode can be reduced or prevented. The possibility of defects that may be formed in the interlayer insulating layer formed on the gate electrode can be reduced or prevented, and the driving transistor of the display device can ensure excellent device reliability.

[0013] According to an embodiment of the present disclosure, a display device includes pixels connected to a scan line and a data line intersecting the scan line, each of the pixels including a light-emitting element and a first transistor configured to control a driving current supplied to the light-emitting element according to a data voltage applied from the data line, the first transistor including a first active layer and a first oxide layer, wherein the first active layer has an oxide semiconductor and the first oxide layer is located on the first active layer and has a crystalline oxide containing tin (Sn).

[0014] The first oxide layer may have a tin content in the range of about 1 at.% to about 100 at.% relative to the content of cations contained in the crystalline oxide.

[0015] The first oxide layer may include tin zinc oxide (TZO), tin gallium oxide (TGO), indium tin zinc oxide (ITZO), indium tin gallium oxide (ITGO), or indium tin zinc gallium oxide (ITZGO).

[0016] The first active layer may include indium tin oxide (ITO), indium tin gallium oxide (ITGO), indium gallium zinc oxide (IGZO), or indium gallium zinc tin oxide (IGZTO).

[0017] The first transistor may include a first gate insulating layer located on the first active layer and a first gate electrode located on the first gate insulating layer and overlapping the first active layer, and the first oxide layer may be located between the first gate electrode and the first gate insulating layer.

[0018] The oxygen concentration in the first active layer can be greater than the oxygen concentration in the first oxide layer.

[0019] The first active layer can include a first conductive region, a second conductive region, and a channel region located between the first conductive region and the second conductive region, and at least a part of the first oxide layer can overlap with the channel region of the first active layer.

[0020] The width of the first oxide layer can be greater than the width of the channel region of the first active layer.

[0021] The first transistor can further include an interlayer insulating layer located on the first gate electrode, a first source electrode in contact with the first conductive region via a first contact hole passing through the interlayer insulating layer, and a first drain electrode in contact with the second conductive region via a second contact hole passing through the interlayer insulating layer.

[0022] The first transistor can further include a first light-blocking layer located below the first active layer and a buffer layer located between the first active layer and the first light-blocking layer, wherein the first source electrode is in contact with the first light-blocking layer via a third contact hole passing through the interlayer insulating layer and the buffer layer.

[0023] At least one end of the first oxide layer can protrude outward beyond one end of the first gate electrode.

[0024] The width of the first oxide layer can be greater than the width of the first gate electrode.

[0025] At least a part of the upper surface of the first oxide layer can be in contact with the interlayer insulating layer on the first gate electrode.

[0026] One of the pixels can include a second transistor configured to apply a data voltage of a corresponding data line in a data line to the first transistor according to a scan signal applied to a corresponding scan line in a scan line, and the second transistor can include a second active layer having an oxide semiconductor, a second gate insulating layer located on the second active layer, and a second gate electrode located on the second gate insulating layer and overlapping with the second active layer.

[0027] The second transistor can further include a second oxide layer located between the second gate insulating layer and the second gate electrode and partially overlapping with the second active layer.

[0028] The display device can further include a scan driving circuit configured to output a scan signal to the scan line, wherein the scan driving circuit includes a third transistor, the third transistor includes a third active layer having an oxide semiconductor and a third gate electrode located on the third active layer, and the third transistor is configured such that the first oxide layer is not located between the third active layer and the third gate electrode.

[0029] According to another embodiment of the present disclosure, a display device includes a substrate, a first active layer, a second active layer, a gate insulating layer, a first gate electrode, a second gate electrode, an interlayer insulating layer, a first source electrode, a first drain electrode, a second source electrode, a second drain electrode, and an oxide layer. The substrate includes a display region and a non-display region. The first active layer is located in the display region, and the second active layer is located in the non-display region. The gate insulating layer is located on the first active layer and the second active layer. The first gate electrode is located on the gate insulating layer and partially overlaps with the first active layer. The second gate electrode is located on the gate insulating layer and partially overlaps with the second active layer. The interlayer insulating layer is located on the first gate electrode and the second gate electrode. The first source electrode and the first drain electrode are located on the interlayer insulating layer and in the display region. The second source electrode and the second drain electrode are located in the non-display region. The oxide layer is located on the gate insulating layer and has a crystalline oxide containing tin (Sn). The first active layer and the second active layer include an oxide semiconductor.

[0030] The oxide layer may include a first oxide layer located between the first gate electrode and the gate insulating layer, and the width of the first oxide layer may be greater than the width of the first gate electrode.

[0031] The first active layer may include a first conductive region, a second conductive region, and a channel region located between the first conductive region and the second conductive region, and at least a part of the first oxide layer may overlap with the channel region of the first active layer.

[0032] The display device may further include an interlayer insulating layer located on the first gate electrode. The first source electrode contacts the first conductive region through a first contact hole passing through the interlayer insulating layer, and the first drain electrode contacts the second conductive region through a second contact hole passing through the interlayer insulating layer.

[0033] The display device may further include a first light-blocking layer located below the first active layer and a buffer layer located between the first active layer and the first light-blocking layer. The first source electrode contacts the first light-blocking layer through a third contact hole passing through the interlayer insulating layer and the buffer layer.

[0034] The oxide layer may not be located between the second gate electrode and the gate insulating layer.

[0035] The display device may further include an interlayer insulating layer located on the second gate electrode. The second active layer includes a third conductive region, a fourth conductive region, and a channel region located between the third conductive region and the fourth conductive region. The second source electrode contacts the third conductive region through a fourth contact hole passing through the interlayer insulating layer, and the second drain electrode contacts the fourth conductive region through a fifth contact hole passing through the interlayer insulating layer.

[0036] According to an embodiment of the present disclosure, a method of manufacturing a display device includes: forming a substrate, an active layer on the substrate, and a gate insulating layer on the active layer; forming an oxide layer on the gate insulating layer and having a crystalline oxide containing tin (Sn), and a metal layer on the oxide layer; performing a first etching for etching at least a part of the metal layer to form a gate electrode; and performing a second etching for etching at least a part of the oxide layer and the gate insulating layer to form a first oxide layer.

[0037] The active layer may include a first active layer and a second active layer having an oxide semiconductor, wherein the gate electrode includes a first gate electrode overlapping with the first active layer and a second gate electrode overlapping with the second active layer, and wherein the first oxide layer is located between the first gate electrode and the first active layer.

[0038] The width of the first oxide layer may be greater than the width of the first gate electrode.

[0039] The first oxide layer may not be located between the second active layer and the second gate electrode.

[0040] The first etching may include a wet etching process, and the second etching includes a dry etching process. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The above and other aspects and features of the present disclosure will become more apparent by referring to the embodiments of the present disclosure described in detail with reference to the accompanying drawings, in which:

[0042] Figure 1 is a plan view of a display device according to some embodiments;

[0043] Figure 2 is a schematic plan view of a display device according to some embodiments;

[0044] Figure 3 is a circuit diagram showing one pixel of Figure 2 according to some embodiments of the present disclosure;

[0045] Figure 4 is a circuit diagram showing one pixel of Figure 2 according to some embodiments of the present disclosure;

[0046] Figure 5 is a circuit diagram showing an example of a Figure 2 scan driving circuit of;

[0047] Figure 6 is a circuit diagram showing an example of a Figure 2 data voltage distribution circuit of;

[0048] Figure 7is a plan view of a first transistor according to some embodiments;

[0049] Figure 8 is a cross-sectional view taken along line I-I' of Figure 7 ;

[0050] Figure 9 is a plan view of a second transistor according to some embodiments;

[0051] Figure 10 is a cross-sectional view taken along line II-II' of Figure 9 ;

[0052] Figure 11 is Figure 8 an enlarged view of part Q of

[0053] Figure 12 is a graph showing the drive current according to the gate voltage of the first transistor according to some embodiments;

[0054] Figure 13 is a plan view showing an example of a pull-up transistor of a Figure 2 scan drive circuit of

[0055] Figure 14 is a cross-sectional view of an example taken along line IV-IV' of Figure 13 ;

[0056] Figure 15 is a flowchart showing a method of manufacturing a display device according to some embodiments;

[0057] Figure 16 and Figure 17 is a cross-sectional view showing locally a method of manufacturing a display device according to some embodiments;

[0058] Figure 18 is a flowchart showing a method of forming an oxide layer of a display device according to some embodiments;

[0059] Figures 19 to 23 is a cross-sectional view showing locally a method of manufacturing a display device according to some embodiments;

[0060] Figure 24 is a cross-sectional view of a second transistor according to another embodiment;

[0061] Figures 25 to 27 is a cross-sectional view showing Figure 24 the manufacturing process of the second transistor of

[0062] Figure 28 is a plan view of a second transistor according to another embodiment;

[0063] Figure 29 is a cross-sectional view taken along line III-III' of Figure 28 ; and

[0064] Figure 30 is a schematic cross-sectional view showing a part of a display device according to another embodiment. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0065] The features of the concepts of the present invention and the methods for implementing them can be more easily understood by referring to the detailed description of the embodiments and the accompanying drawings. Hereinafter, the embodiments will be described in more detail with reference to the drawings. However, the described embodiments can be implemented in various different forms and should not be construed as being limited only to the embodiments shown herein. Instead, these embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the aspects and features of the concepts of the present invention to those skilled in the art. Accordingly, processes, elements, and techniques that are not necessary for a person of ordinary skill in the art to fully understand the aspects and features of the concepts of the present invention may not be described.

[0066] Unless otherwise specified, the same reference numerals indicate the same elements throughout the drawings and the written description, and thus their descriptions will not be repeated. Additionally, for the sake of clarity, parts that are not relevant to the description of some embodiments may not be shown. In the drawings, for clarity, the relative sizes of elements, layers, and regions may be enlarged.

[0067] In this document, various embodiments are described with reference to cross-sectional views that are schematic illustrations of the embodiments and / or intermediate structures. Thus, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Additionally, for the purpose of describing embodiments in accordance with the concepts of the present disclosure, the specific structural or functional descriptions disclosed herein are merely illustrative. Therefore, the embodiments disclosed herein should not be construed as being limited to the specific shapes of the regions shown, but rather include deviations in shape caused by, for example, manufacturing.

[0068] For example, an implantation region shown as rectangular will typically have rounded corners or curved features and / or an implantation concentration gradient at its edges, rather than a binary change from the implantation region to the non-implantation region. Similarly, a buried region formed by implantation may generate some implantation in the region between the buried region and the surface for implantation. Accordingly, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to be limiting. Additionally, those of ordinary skill in the art will understand that the described embodiments can be modified in various different ways without departing from the spirit or scope of the present disclosure.

[0069] In the detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the various embodiments. It will be evident, however, that the various embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring the various embodiments.

[0070] It should be understood that although the terms “first,” “second,” “third,” etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, a first element, component, region, layer, or section discussed below could be termed a second element, component, region, layer, or section without departing from the spirit and scope of the present disclosure.

[0071] Spatial relative terms such as “beneath,” “below,” “lower,” “under,” “above,” “upper,” etc. may be used herein for ease of explanation to describe the relationship of one element or feature to another element or feature shown in the figures. It should be understood that, in addition to the orientation shown in the figures, the spatial relative terms are intended to also encompass different orientations of the device in use or operation. For example, if the device in the figures is turned over, an element described as “below,” “beneath,” or “under” other elements or features will then be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “under” can encompass both an orientation of above and below. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and the spatial relative descriptors used herein should be interpreted accordingly. Similarly, when a first part is described as disposed “on” a second part, this indicates that the first part is disposed at the upper or lower side of the second part, and is not limited to the upper side based on the direction of gravity.

[0072] Furthermore, in this specification, the phrase “on a plane” or “plan view” means observing the target portion from the top, and the phrase “in a sectional view” means observing a sectional view formed by vertically cutting the target portion from the side.

[0073] It should be understood that when an element, layer, region or component is referred to as being "on", "connected to" or "coupled to" another element, layer, region or component, the element, layer, region or component can be directly on the other element, layer, region or component, directly connected to or coupled to the other element, layer, region or component, or there may be intervening elements, layers, regions or components. However, "directly connected / directly coupled" refers to a component that directly connects or couples to another component without an intervening component. At the same time, other expressions describing the relationship between components such as "between", "adjacent to" or "next to" and "directly adjacent" can be similarly interpreted. In addition, it should also be understood that when an element or layer is referred to as being "between" two elements or layers, the element or layer can be the only element or layer between the two elements or layers, or there may also be one or more intervening elements or layers.

[0074] For the purposes of the present disclosure, statements such as "at least one" after a list of elements modify the entire list of elements, rather than individual elements in the list. For example, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. Throughout the specification, like reference numerals indicate like elements. As used herein, the phrase "and / or" includes any and all combinations of one or more of the associated listed items.

[0075] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting of the present disclosure. Unless the context clearly dictates otherwise, the singular forms "a" and "an" as used herein are also intended to include the plural forms. It should also be understood that when the terms "comprise", "comprising", "have", "having", "include" and "including" are used in this specification, they indicate the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. As used herein, the phrase "and / or" includes any and all combinations of one or more of the associated listed items.

[0076] As used herein, the terms "substantially", "about", "approximately" and similar terms are used as terms of approximation and not of degree, and are intended to account for the inherent variations in measured or calculated values that would be recognized by a person of ordinary skill in the art. Given the measurements involved and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), "about" or "approximately" as used herein includes the stated value and the mean within an acceptable variation of the particular value as determined by a person of ordinary skill in the art. For example, "about" can mean within one or more standard deviations, or within ±30%, 20%, 10%, 5% of the stated value. Additionally, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure".

[0077] When a particular embodiment can be implemented in different ways, the specific process order can be performed differently than the order described. For example, two consecutively described processes can be performed substantially simultaneously or in an order opposite to the described order.

[0078] Furthermore, any numerical range disclosed and / or recited herein is intended to include all sub-ranges of the same numerical precision subsumed within the recited range. For example, the range "1.0 to 10.0" is intended to include all sub-ranges between the recited minimum value 1.0 and the recited maximum value 10.0 (and including the recited minimum value 1.0 and the recited maximum value 10.0), that is, all sub-ranges having a minimum value greater than or equal to 1.0 and a maximum value less than or equal to 10.0, such as 2.4 to 7.6. Any maximum numerical limitation recited herein is intended to include all lower numerical limitations subsumed therein, and any minimum numerical limitation recited in this specification is intended to include all greater numerical limitations subsumed therein. Accordingly, the applicant reserves the right to amend this specification (including the claims) to expressly recite any sub-ranges subsumed within the ranges expressly recited herein.

[0079] The electronic or electrical devices and / or any other related devices or components according to embodiments of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application specific integrated circuit), software, or a combination of software, firmware, and hardware. For example, the various components of these devices can be formed on one integrated circuit (IC) chip or on separate IC chips. Additionally, the various components of these devices can be implemented on a flexible printed circuit film, tape carrier package (TCP), printed circuit board (PCB), or formed on a substrate.

[0080] Additionally, various components of these devices can be processes or threads that run on one or more processors in one or more computing devices to execute computer program instructions and interact with other system components to perform the various functions described herein. The computer program instructions are stored in a memory, which can be implemented in a computing device using standard memory devices (e.g., such as random access memory (RAM)). The computer program instructions can also be stored in other non-transitory computer-readable media (e.g., such as a CD-ROM, a flash drive, etc.). Moreover, those skilled in the art should recognize that the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a particular computing device can be distributed over one or more other computing devices without departing from the spirit and scope of some embodiments of the present disclosure.

[0081] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the technical field to which the inventive concept belongs. It should also be understood that terms such as those defined in a common dictionary should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or the specification, and should not be interpreted in an idealized or overly formal sense unless explicitly so defined herein.

[0082] Figure 1 is a plan view of a display device related to some embodiments.

[0083] Refer to Figure 1 , the display device 1 displays a dynamic image or a static image. The display device 1 can indicate any electronic device that provides a display screen. Examples of the display device 1 can include a television, a laptop computer, a monitor, a billboard, an Internet of Things device, a mobile phone, a smart phone, a tablet personal computer (PC), an electronic watch, a smart watch, a watch phone, a head-mounted display, a mobile communication terminal, an electronic notebook, an e-book, a portable multimedia player (PMP), a navigation device, a gaming machine, a digital camera, a portable video camera, etc. that provide a display screen.

[0084] The display device 1 includes a display panel that provides a display screen. Examples of the display panel can include an LED display panel, an organic light-emitting display panel, a quantum dot light-emitting display panel, a plasma display panel, and a field emission display panel. In the following description, the case where an LED display panel is applied as the display panel will be described, but the present disclosure is not limited thereto, and other display panels can be applied within the scope of the same technical concept.

[0085] The shape of the display device 1 can be variously modified. For example, the display device 1 can have a shape such as a rectangular shape elongated in the horizontal direction, a rectangular shape elongated in the vertical direction, a square shape, a quadrilateral shape with rounded (vertex) corners, other polygonal shapes, and / or a circular shape. The shape of the display area DA of the display device 1 can also be similar to the overall shape of the display device 1. In Figure 1 FIG. shows a display device 1 and a display area DA having a rectangular shape elongated in the horizontal direction.

[0086] The display device 1 may include a display area DA and a non-display area NDA. The display area DA is an area where an image can be displayed, and the non-display area NDA is an area where an image is not displayed. The display area DA may also be referred to as an active area, and the non-display area NDA may also be referred to as a non-active area.

[0087] The display area DA may substantially occupy the center of the display device 1. The display area DA may include a plurality of pixels PX. The plurality of pixels PX may be arranged in a matrix. In a plan view, the shape of each pixel PX may be a rectangular or square shape. However, the present disclosure is not limited thereto, and it may be a rhombus shape in which each side is inclined with respect to the first direction DR1.

[0088] Figure 2 is a schematic plan view of a display device according to some embodiments.

[0089] Referring to Figure 2 , the display device 1 includes a display panel 10, an integrated driving circuit 20, and a scan driving circuit 30. The integrated driving circuit 20 may include a timing controller and a data driver.

[0090] The display panel 10 may include a display area DA in which pixels PX are formed to display an image and a non-display area NDA as a peripheral area of the display area DA. When the display panel 10 includes a bent surface portion, the display area DA may be located on the bent surface portion. In this case, an image of the display panel 10 can also be observed on the bent surface portion.

[0091] Not only are the pixels PX located in the display area DA, but the scan lines SL, data lines DL, and power supply lines connected to the pixels PX may also be located in the display area DA. The scan lines SL may be formed to extend in the first direction DR1, and the data lines DL may be formed to extend in a second direction DR2 intersecting the first direction DR1. Each of the pixels PX may be connected to at least one of the scan lines SL and at least one of the data lines DL.

[0092] Each pixel PX may include a driving transistor, at least one switching transistor, a light-emitting element, and a capacitor. Since the switching transistor may be turned on when a scan signal is applied from the scan line SL, the data voltage of the data line DL may be applied to the gate electrode of the driving transistor. The driving transistor may be turned on according to the data voltage applied to the gate electrode, so that a driving current is supplied to the light-emitting element to emit light. The driving transistor and at least one switching transistor may be thin-film transistors. The light-emitting element may emit light according to the driving current of the driving transistor. The light-emitting element may be an organic light-emitting diode including a first electrode, an organic light-emitting layer, and a second electrode. The capacitor may be used to maintain a constant or stable data voltage applied to the gate electrode of the driving transistor.

[0093] The non-display area NDA may be defined as an area from the outside of the display area DA to the edge of the display panel 10. The scan driving circuit 30 for applying a scan signal to the scan line SL and the data voltage distribution circuit DMUX connected between the data line DL and the routing line RL in the non-display area NDA may be located in the non-display area NDA. In addition, the pad DP electrically connected to the integrated driving circuit 20 may be located in the non-display area NDA. In this case, the integrated driving circuit 20 and the pad DP may be located at one edge of the display panel 10.

[0094] The integrated driving circuit 20 is connected to the pad DP to receive digital video data and timing signals. The integrated driving circuit 20 converts the digital video data into analog positive / negative data voltages and supplies them to the data line DL through the routing line RL and the data voltage distribution circuit DMUX. In addition, the integrated driving circuit 20 generates and supplies a scan control signal for controlling the scan driving circuit 30 through the scan control line SCL. The pixel PX to which the data voltage is to be supplied is selected by the scan signal of the scan driving circuit 30, and the data voltage is supplied to the selected pixel PX. In addition, the integrated driving circuit 20 may supply a power voltage to the power line.

[0095] The integrated driving circuit 2 may be formed as an integrated circuit (IC) and may be mounted on the display panel 10 by a chip-on-glass (COG) method, a chip-on-plastic (COP) method, or an ultrasonic bonding method in the pad area, but the present disclosure is not limited thereto. For example, the integrated driving circuit 20 may be mounted on a separate circuit board.

[0096] The pad DP can be electrically connected to the integrated driving circuit 20. In some embodiments, the circuit board can be attached to the pad DP using an anisotropic conductive film. Accordingly, the leads of the circuit board can be electrically connected to the pad DP. The circuit board can be a flexible film, such as a flexible printed circuit board, a printed circuit board, or a chip on film. The circuit board can be bent toward the lower side of the display panel 10. In this case, one side of the circuit board can be attached to one edge of the display panel 10, and the other side of the circuit board can be located below the display panel 10 and can be connected to the system board on which the host system is installed.

[0097] The scan driving circuit 30 can be connected to the integrated driving circuit 20 through at least one scan control line SCL to receive a scan control signal. The scan driving circuit 30 can generate a scan signal according to the scan control signal and can sequentially output the scan signal to the scan line SL. Although Figure 2 it is shown that the scan driving circuit 30 is formed on one side of the display area DA, for example, in the non-display area NDA on the left side, but the present disclosure is not limited thereto. For example, the scan driving circuit 30 can be formed on multiple sides of the display area DA, for example, in the non-display areas NDA on the left side and the right side.

[0098] The data voltage distribution circuit DMUX can be connected between the routing line RL and the data line DL. The ratio of the number of routing lines RL connected to the data voltage distribution circuit DMUX to the number of data lines DL can be 1:q (q is an integer greater than or equal to 2). The data voltage distribution circuit DMUX can be used to distribute the data voltage applied to one routing line RL to a plurality of corresponding data lines DL.

[0099] The power supply circuit can generate the voltages required to drive the display panel 10 from the main power supply applied from the system board and can supply the voltages to the display panel 10. For example, the power supply circuit can generate a first power supply voltage and a second power supply voltage for driving the light-emitting elements EL (see Figure 3 ) of the display panel 10 and can supply them to the first voltage line VDD (see Figure 3 ) and the second voltage line VSS (see Figure 3 ) of the display panel 10. In addition, the power supply circuit can generate a driving voltage for driving the integrated driving circuit 20 and the scan driving circuit 30 from the main power supply and can supply them.

[0100] The power supply circuit can be formed as an integrated circuit and can be mounted on the circuit board, but the present disclosure is not limited thereto. For example, the power supply circuit can be integrally formed with the integrated driving circuit 20.

[0101] Figure 3 is a circuit diagram of one pixel related to some embodiments of the present disclosure Figure 2 ​

[0102] Reference Figure 3 , the pixel PX may include a first transistor TR1, a second transistor TR2, a light-emitting element EL, and a capacitor Cst. Although Figure 3 the pixel PX is shown to have a 2T1C (2 transistors - 1 capacitor) structure including one first transistor TR1, one second transistor TR2, and one capacitor Cst, the present disclosure is not limited thereto. Each pixel PX may include a greater number of transistors and / or multiple capacitors.

[0103] Each of the first transistor TR1 and the second transistor TR2 may include a first electrode, a second electrode, and a gate electrode. One of the first electrode and the second electrode may be a source electrode, and the other may be a drain electrode.

[0104] Each of the first transistor TR1 and the second transistor TR2 may be formed as a thin-film transistor. Further, although in Figure 3 each of the first transistor TR1 and the second transistor TR2 is shown to be formed as an N-type metal-oxide semiconductor field-effect transistor (MOSFET), the present disclosure is not limited thereto. Each of the first transistor TR1 and the second transistor TR2 may be formed as a P-type MOSFET. In this case, the positions of the source electrode and the drain electrode of each of the first transistor TR1 and the second transistor TR2 may be changed. In the following description, it is assumed that the first transistor TR1 and the second transistor TR2 are N-type MOSFETs.

[0105] The first transistor TR1 may be turned on according to a data voltage applied to the gate electrode, so that a driving current is supplied to the light-emitting element EL to emit light. That is, the first transistor TR1 may be a driving transistor. The gate electrode of the first transistor TR1 may be connected to the source electrode of the second transistor TR2, the source electrode of the first transistor TR1 may be connected to the first electrode of the light-emitting element EL, and the drain electrode of the first transistor TR1 may be connected to a first voltage line VDD to which a first power supply voltage is applied.

[0106] Since the second transistor TR2 is turned on when a scan signal is applied from the k-th scan line SLk (k is a positive integer), the data voltage of the data line DLj may be applied to the gate electrode of the first transistor TR1. That is, the second transistor TR2 may be a switching transistor. The gate electrode of the second transistor TR2 may be connected to the k-th scan line SLk, the source electrode of the second transistor TR2 may be connected to the gate electrode of the first transistor TR1, and the drain electrode of the second transistor TR2 may be connected to the j-th data line DLj.

[0107] The capacitor Cst may be connected between the gate electrode and the source electrode of the first transistor TR1. Accordingly, the capacitor Cst may be used to keep or stabilize the data voltage applied to the gate electrode of the first transistor TR1.

[0108] The light-emitting element EL can emit light according to the driving current of the first transistor TR1. The light-emitting element EL can be an organic light-emitting diode including a first electrode, an organic light-emitting layer, and a second electrode. The first electrode of the light-emitting element EL can be connected to the source electrode of the first transistor TR1, and the second electrode of the light-emitting element EL can be connected to a second voltage line VSS to which a second power supply voltage lower than the first power supply voltage is applied.

[0109] Figure 4 is a circuit diagram of a pixel related to some embodiments of the present disclosure Figure 2 .

[0110] Referring to Figure 4 , the pixel PX can include a first transistor TR1, a second transistor TR2, a sensing transistor SST, a light-emitting element EL, and a capacitor Cst. Figure 4 shows that the pixel PX has a 3T1C (3 transistors - 1 capacitor) structure including one first transistor TR1, one second transistor TR2, one sensing transistor SST, and one capacitor Cst. Except that Figure 4 the circuit diagram of Figure 4 also includes a sensing transistor SST and a reference line Vref, Figure 3 the circuit diagram of

[0111] Figure 4 is the same as the circuit diagram of

[0112] The sensing transistor SST can have an electrode (e.g., a source electrode) connected between the source electrode of the first transistor TR1 and the first electrode of the light-emitting element EL. The gate electrode of the sensing transistor SST can be connected to the k-th sensing signal line SSk, the drain electrode of the sensing transistor SST can be connected to the reference line Vref, and the source electrode of the sensing transistor SST can be connected to one end of the capacitor Cst. The sensing transistor SST is turned on by the sensing signal of the k-th sensing signal line SSk to supply the reference voltage transmitted through the reference line Vref to the source electrode of the first transistor TR1, or operates to sense the voltage or current of the source electrode of the first transistor TR1.

[0113] The reference line Vref can be connected to the scan driving circuit 30. In this case, the scan driving circuit 30 can sense the source electrode of the first transistor TR1 of each pixel PX in real time during the non-display period of the image, during the period of N frames (N is a positive number greater than or equal to 1), or during the period of multiple frames, and can generate a sensing result. On the other hand, the second transistor TR2 as a switching transistor and the sensing transistor SST as a sensing transistor can be turned on simultaneously. In this case, the sensing operation through the reference line Vref and the data output operation for outputting the data signal are separated from each other according to the time division method of the scan driving circuit 30.

[0114] In addition, the compensation target based on the sensing result can be a digital data signal, an analog data signal, gamma, etc. Further, the compensation circuit that generates the compensation signal based on the sensing result can be implemented as a circuit in the scan driving circuit 30, in the timing controller, or in the integrated driving circuit 20, or as a separate circuit.

[0115] However, the present disclosure is not limited thereto. In Figure 3 and Figure 4 , each pixel PX having a 2T1C structure and a 3T1C structure has been shown as an example, but in other embodiments, the pixel PX may include a larger number of transistors or capacitors. The description thereof will be omitted.

[0116] Figure 5 is a circuit diagram showing an example of the scan driving circuit of Figure 2 .

[0117] Referring to Figure 5 , as shown in Figure 5 , the scan driving circuit 30 may include stages STA connected independently of each other, and the stages STA may sequentially output a scan signal (e.g., via the output terminal OT) to the scan line SL.

[0118] As shown in Figure 5 , each of the stages STA includes a pull-up node NQ, a pull-down node NQB, a pull-up transistor TU that is turned on when the pull-up node NQ has a gate conduction voltage, a pull-down transistor TD that is turned on when the pull-down node NQB has a gate conduction voltage, and a node controller NC for controlling the charging and discharging of the pull-up node NQ and / or the pull-down node NQB.

[0119] The node controller NC can be connected to a start terminal STT input with a start signal or an output signal of the previous stage, a reset terminal RT input with an output signal of the next stage, a gate conduction voltage terminal VGHT to which a gate conduction voltage is applied, and a gate turn-off voltage terminal VGLT to which a gate turn-off voltage is applied.

[0120] The node controller NC controls the charging and discharging of the pull-up node NQ and the pull-down node NQB based on a start signal input to the start terminal STT or an output signal from a previous stage. To stably control the output of stage STA, when the pull-up node NQ has a gate-on voltage, the node controller NC makes the pull-down node NQB have a gate-off voltage, and when the pull-down node NQB has a gate-on voltage, the node controller NC makes the pull-up node NQ have a gate-off voltage. To this end, the node controller NC may include a plurality of transistors.

[0121] When stage STA is pulled up (for example, when the pull-up node NQ has a gate-on voltage), the pull-up transistor TU is turned on, and a clock signal input to the clock terminal CT is output to the output terminal OT. When stage STA is pulled down (for example, when the pull-down node NQB has a gate-on voltage), the pull-down transistor TD is turned on, and a gate-off voltage of the gate electrode of the gate-off voltage terminal VGLT is output to the output terminal OT.

[0122] The plurality of transistors of the node controller NC of stage STA, the pull-up transistor TU, and the pull-down transistor TD may be formed as thin film transistors. In addition, although Figure 5 it is shown that the plurality of transistors of the node controller NC of stage STA, the pull-up transistor TU, and the pull-down transistor TD are formed as N-type semiconductor transistors having N-type semiconductor characteristics, embodiments of the present disclosure are not limited thereto. That is, the plurality of transistors of the node controller NC of stage STA, the pull-up transistor TU, and the pull-down transistor TD may be formed as P-type semiconductor transistors having P-type semiconductor characteristics.

[0123] Figure 6 is a circuit diagram showing Figure 2 an example of a data voltage distribution circuit.

[0124] Referring to Figure 6 , the data voltage distribution circuit DMUX may time-division the data voltages supplied to the routing lines RL1 to RLp (p is an integer of 2 or greater), and may distribute the data voltages to a plurality of data lines DL1 to DLm (for example, m is an integer satisfying m = 2p) by using the respective distribution transistors MT1 and MT2 that are sequentially turned on by the distribution control signals supplied to the distribution control lines DM1 and DM2. Although Figure 6 it is shown that the data voltage distribution circuit DMUX time-divides the data voltages supplied to one routing line and distributes the data voltages to two data lines, embodiments of the present disclosure are not limited thereto.

[0125] The data voltage distribution circuit DMUX may include a first distribution transistor MT1 and a second distribution transistor MT2. The gate electrode of each of the first distribution transistors MT1 may be connected to a first distribution control line DM1, and the gate electrode of each of the second distribution transistors MT2 may be connected to a second distribution control line DM2.

[0126] The first distribution transistor MT1 and the second distribution transistor MT2 connected to a routing line may be connected to different data lines. For example, the first distribution transistor MT1 connected to the first routing line RL1 may be connected to the first data line DL1, and the second distribution transistor MT2 connected to the first routing line RL1 may be connected to the second data line DL2. The first distribution transistor MT1 connected to the p-th routing line RLp may be connected to the (m-1)-th data line DLm-1, and the second distribution transistor MT2 connected to the p-th routing line RLp may be connected to the m-th data line DLm.

[0127] When a first distribution control signal having a gate turn-on voltage is applied to the first distribution control line DM1, the first distribution transistor MT1 may be turned on. Accordingly, the routing lines RL1 to RLp may be respectively connected to odd-numbered data lines DL1, DL3, DL5,..., DLm-1. When a second distribution control signal having a gate turn-on voltage is applied to the second distribution control line DM2, the second distribution transistor MT2 may be turned on. Accordingly, the routing lines RL1 to RLp may be respectively connected to even-numbered data lines DL2, DL4, DL6,..., DLm. Therefore, the data voltage distribution circuit DMUX may time-division the data voltage supplied to the routing lines RL1 to RLp (p is an integer of 2 or more), and may distribute the data voltage to a plurality of data lines DL1 to DLm (m is an integer satisfying m = 2p).

[0128] The first distribution transistor MT1 and the second distribution transistor MT2 of the data voltage distribution circuit DMUX may be formed as thin film transistors. Although Figure 6 The first distribution transistor MT1 and the second distribution transistor MT2 of the data voltage distribution circuit DMUX are shown as N-type semiconductor transistors having N-type semiconductor characteristics, but the embodiments of the present disclosure are not limited thereto. That is, the first distribution transistor MT1 and the second distribution transistor MT2 of the data voltage distribution circuit DMUX may be formed as P-type semiconductor transistors having P-type semiconductor characteristics.

[0129] Hereinafter, the structure and arrangement of the transistors located in each pixel PX will be described.

[0130] Figure 7 is a plan view of a first transistor according to some embodiments. Figure 8 is along Figure 7A cross-sectional view taken along line I-I'. Figure 9 is a plan view of a second transistor according to some embodiments. Figure 10 is along Figure 9 A cross-sectional view taken along line II-II'.

[0131] Figures 7 to 10 It shows that the first transistor TR1 as a driving transistor and the second transistor TR2 as a switching transistor of the pixel PX are formed in a coplanar structure. The coplanar structure has a top-gate structure in which the gate electrode is formed above the active layer. However, the present disclosure is not limited thereto, and the first transistor TR1 and the second transistor TR2 of each pixel PX may have a bottom-gate structure in which the gate electrode is formed below the active layer.

[0132] Referring to Figures 7 to 10 , the display panel 10 includes a first substrate 110, a buffer layer 120, a first gate insulating layer 130, a first transistor TR1, a second transistor TR2, a first interlayer insulating layer 160, a first passivation layer 170, a first planarization layer 180, a first electrode 191, an organic light-emitting layer 192, a second electrode 193, a pixel defining layer 195, and a packaging layer 196 located in the display area DA.

[0133] According to some embodiments, the first transistor TR1 of each pixel PX includes a first gate electrode 310, a first active layer 350, a first oxide layer 370, a first source electrode 330, a first drain electrode 340, and a first light-blocking layer 360. The second transistor TR2 of the pixel PX includes a second gate electrode 410, a second active layer 450, a second source electrode 430, and a second drain electrode 440.

[0134] The first substrate 110 may provide regions for forming the first transistor TR1 and the second transistor TR2. The first substrate 110 may be made of plastic or glass.

[0135] The first light-blocking layer 360 may be located on the first substrate 110. The first light-blocking layer 360 may block light from being incident on the first active layer 350 from the first substrate 110. The first light-blocking layer 360 may reduce or prevent leakage current flowing in the first active layer 350 when light from the first substrate 110 is incident on the first active layer 350. The length of the first light-blocking layer 360 in the third direction DR3 and the length of the first light-blocking layer 360 in the fourth direction DR4 may (for example, respectively) be longer than the length of the first active layer 350 in the third direction DR3 and the length of the first active layer 350 in the fourth direction DR4. The first light-blocking layer 360 may be formed as a single layer or multiple layers made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) and / or their alloys.

[0136] The buffer layer 120 may be located on the first light-blocking layer 360. The buffer layer 120 may protect the first transistor TR1 and the second transistor TR2 of the pixel PX from moisture permeating through the first substrate 110. The buffer layer 120 may include a plurality of alternately stacked inorganic layers. For example, the buffer layer 120 may be formed of one or more inorganic layer multilayers alternately stacked with silicon oxide (SiO x ) layers, silicon nitride (SiN x ) layers, and silicon oxynitride (SiON) layers.

[0137] The first active layer 350 and the second active layer 450 may be located on the buffer layer 120. According to some embodiments, the first active layer 350 and the second active layer 450 may have an oxide semiconductor. In some embodiments, the first active layer 350 and the second active layer 450 may include indium tin oxide (ITO), indium tin gallium oxide (ITGO), indium gallium zinc oxide (IGZO), and / or indium gallium zinc tin oxide (IGZTO). However, the present disclosure is not limited thereto.

[0138] The first active layer 350 and the second active layer 450 may respectively include a first conductive region 350a and 450a, a second conductive region 350b and 450b, and a channel region 350c and 450c. The channel regions 350c and 450c may be respectively located between the first conductive regions 350a and 450a and the second conductive regions 350b and 450b.

[0139] The first gate insulating layer 130 is located on the first active layer 350 and the second active layer 450. The first gate insulating layer 130 may be formed of an inorganic material such as silicon oxide (SiO x ), silicon nitride (SiN x ), or a stacked structure thereof.

[0140] The first gate electrode 310 and the second gate electrode 410 are located on the first gate insulating layer 130. The first gate electrode 310 may overlap with the first active layer 350 with the first gate insulating layer 130 interposed therebetween, and the second gate electrode 410 may overlap with the second active layer 450 with the first gate insulating layer 130 interposed therebetween. For example, the first gate electrode 310 may overlap with the channel region 350c of the first active layer 350, and the second gate electrode 410 may overlap with the channel region 450c of the second active layer 450. The first gate electrode 310 and the second gate electrode 410 may be formed as a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) and / or their alloys.

[0141] Meanwhile, although Figure 8 and Figure 10It is shown that the first gate insulating layer 130 is only located between the first gate electrode 310 and the first active layer 350 and between the second gate electrode 410 and the second active layer 450, but embodiments of the present disclosure are not limited thereto. For example, the first gate insulating layer 130 may be formed on the upper surface and side surfaces of the first active layer 350 and the second active layer 450.

[0142] According to some embodiments, the first transistor TR1 may include a first oxide layer 370 located between the first gate insulating layer 130 and the first gate electrode 310. The first oxide layer 370 may be positioned to overlap at least with the channel region 350c of the first active layer 350. The first oxide layer 370 may overlap with the channel region 350c of the first active layer 350 to inject excessive oxygen (O) into it. In some embodiments, the width of the first oxide layer 370 measured in the third direction DR3 may be greater than the width of the channel region 350c measured in the third direction DR3.

[0143] An oxygen defect region may be partially formed in the first active layer 350 including an oxide semiconductor. The oxygen defect region may act as a factor reducing the device characteristics of the first active layer 350. In addition, when the first gate insulating layer 130 is located on the first active layer 350, hydrogen (H) from the first gate insulating layer 130 may penetrate into the oxygen defect region to form impurities.

[0144] The first oxide layer 370 according to some embodiments may supply excessive oxygen (O) to another adjacent layer (for example, supply to the first gate insulating layer 130). The excessive oxygen (O) supplied to the first gate insulating layer 130 may be injected into the channel region 350c of the first active layer 350 to reduce the number of oxygen defect regions formed in the first active layer 350.

[0145] When the first oxide layer 370 is located on the first gate insulating layer 130, excessive oxygen (O) is supplied to the first gate insulating layer 130, and the excessive oxygen (O) may be injected into the oxygen defect region of the first active layer 350. When excessive oxygen (O) is injected through the first oxide layer 370, hydrogen (H) penetrating into the oxygen defect region moves to the first gate insulating layer 130, and as the excessive oxygen (O) fills the region, the oxygen defect region may be reduced.

[0146] According to some embodiments, the oxygen concentration of the first active layer 350 may be greater than the oxygen concentration of the first oxide layer 370. The first active layer 350 receives excessive oxygen (O) from the first oxide layer 370 located on the first gate insulating layer 130 to increase the oxygen concentration, and the concentration of oxygen defect regions may be reduced. Accordingly, the first active layer 350 may have a high mobility, and the transistor including the first oxide layer 370 may have improved electrical characteristics. In the display device 1 according to some embodiments, in each pixel PX of the display panel 10, the first transistor TR1 serving as a driving transistor includes the first oxide layer 370 located between the first active layer 350 and the first gate electrode 310. Accordingly, the driving transistor may have improved electrical characteristics.

[0147] The first oxide layer 370 according to some embodiments may be a crystalline oxide containing tin (Sn). In some embodiments, the first oxide layer 370 may be formed of tin zinc oxide (TZO), tin gallium oxide (TGO), indium tin zinc oxide (ITZO), indium tin gallium oxide (ITGO), and / or indium tin zinc gallium oxide (ITZGO). However, the present disclosure is not limited thereto, and the first oxide layer 370 may be formed of an oxide containing tin (Sn) other than the above oxides. That is, the first oxide layer 370 may be an oxide having a content of tin (Sn) in the range of about 1 at.% to about 100 at.% relative to the total cation content.

[0148] During the manufacturing process of the display device 1, the first oxide layer 370 may be formed on the first gate insulating layer 130 through an etching process. When the first oxide layer 370 does not have a crystalline oxide, the first gate electrode 310 and the first oxide layer 370 may be etched simultaneously or substantially synchronously in one process.

[0149] When the first oxide layer 370 is removed in the same etching process as the first gate electrode 310, the side surface of the first oxide layer 370 may be etched more than the side surface of the first gate electrode 310, and undercut may occur. As the first oxide layer 370 is etched more than the first gate electrode 310, when the side surface of the first oxide layer 370 is recessed inward, the insulating material of the first interlayer insulating layer 160 formed in a subsequent process may not be deposited on the side surface of the first oxide layer 370. Accordingly, a defect (crack) in which the insulating material is not correctly deposited may occur in the first interlayer insulating layer 160 along the undercut formed in the first oxide layer 370, which may reduce the device characteristics and reliability of the first transistor TR1.

[0150] The first oxide layer 370 according to some embodiments may include a crystalline oxide containing tin (Sn), and may be formed through an etching process different from the etching process of the first gate electrode 310.

[0151] Figure 11 is Figure 8 an enlarged view of part Q of

[0152] Referring to Figure 11 , the first oxide layer 370 may include a crystalline oxide containing tin (Sn), and may be formed by an etching process different from the etching process used to form the first gate electrode 310. Accordingly, it is possible to reduce or prevent the possibility of an undercut phenomenon that may occur when the first oxide layer 370 is etched more than the first gate electrode 310, and it is possible to reduce or minimize the possibility of cracks in the first interlayer insulating layer 160. In addition, device characteristics can be improved by ensuring the structural stability of the first transistor TR1.

[0153] Meanwhile, as the first gate electrode 310 and the first oxide layer 370 are formed by different etching processes, the first oxide layer 370 may have a greater width than the first gate electrode 310. According to some embodiments, the width W370 of the first oxide layer 370 measured in one direction (e.g., in the third direction DR3) may be greater than the width W310 of the first gate electrode 310 measured in that direction. At least one end of the first oxide layer 370 may be formed to protrude more than one end of the first gate electrode 310. The first gate electrode 310 is located on the first oxide layer 370, and since the first gate electrode 310 has a narrower width, at least a portion of the upper surface of the first oxide layer 370 may be exposed. The exposed upper surface of the first oxide layer 370 may be in contact with the first interlayer insulating layer 160.

[0154] In the etching process for forming the first gate electrode 310, the oxide layer having a crystalline oxide is not etched. During the manufacturing process of the display device 1, the etching process for forming the first oxide layer 370 may be performed after the first gate electrode 310 is formed. As will be described later, a photoresist PR (see Figure 20 ) may be formed on the first gate electrode 310 for forming the first oxide layer 370. Since the photoresist PR is formed to have a greater width than the first gate electrode 310, the first oxide layer 370 having a width substantially the same as the width of the photoresist PR may have a greater width than the first gate electrode 310. Since the width W370 of the first oxide layer 370 is greater than the width W310 of the first gate electrode 310, undercut of the first oxide layer 370 can be prevented.

[0155] In addition, according to some embodiments, the width W370 of the first oxide layer 370 may be greater than the width W350c of the channel region 350c of the first active layer 350. As described above, the first oxide layer 370 may be located on the first active layer 350 to inject excessive oxygen (O) into the first active layer 350. To this end, the first oxide layer 370 may be formed to overlap at least the channel region 350c of the first active layer 350. Since the first oxide layer 370 located on the first gate insulating layer 130 has a width W370 greater than the width W350c of the channel region 350c of the first active layer 350, it may be positioned to overlap the entire region of the channel region 350c. Accordingly, at least a part of the first oxide layer 370 may also overlap the first conductive region 350a and the second conductive region 350b of the first active layer 350. However, the present disclosure is not limited thereto, and in some embodiments, the width W370 of the first oxide layer 370 may be substantially the same as the width W350c of the channel region 350c.

[0156] Figure 12 is a graph showing the drive current according to the gate voltage of the first transistor in some embodiments. Figure 12 is a graph showing the drive current A according to the gate voltage V of the first transistor TR1 serving as a driving transistor. In Figure 12 it, by changing the gate voltage V of the first transistor TR1 multiple times, the change in the drive current A was measured. In Figure 12 it, the dashed line represents the change in the drive current A caused by the change in the gate voltage V of the first transistor TR1 including an oxide layer without a crystalline phase in other embodiments, and the solid line represents the change in the drive current A caused by the change in the gate voltage V of the first transistor TR1 including the first oxide layer 370 having a crystalline oxide in some embodiments.

[0157] As described above, the first transistor TR1 constituting the driving transistor of the display device 1 includes the first oxide layer 370, thereby improving the electrical characteristics of the device. Moreover, the first oxide layer 370 has a crystalline oxide, thereby ensuring excellent device reliability.

[0158] Referring to Figure 12 it can be seen that when the first oxide layer 370 does not have a crystalline oxide ( Figure 12(the dashed line in ), as the gate voltage V changes and repeats several times, the value of the drive current A changes. As described above, when the first oxide layer 370 does not have crystalline oxide, undercut may occur under the first gate electrode 310, and cracks may occur in the first interlayer insulating layer 160 due to the undercut of the first oxide layer 370. The cracks formed in the first interlayer insulating layer 160 may cause structural defects in the first transistor TR1, resulting in difficulty in ensuring device characteristics. Accordingly, a non-constant drive current A may flow during the change in the gate voltage V repeating several times, and the device may have low reliability.

[0159] On the other hand, when the first oxide layer 370 has crystalline oxide ( Figure 12 the solid line in ), since undercut does not occur under the first gate electrode 310, the occurrence of cracks in the first interlayer insulating layer 160 can be prevented. Accordingly, the structural defects of the first transistor TR1 can be reduced, and excellent device characteristics can be ensured. As Figure 12 shown, in the first transistor TR1 involved in some embodiments, even if the change in the gate voltage V repeats several times, a constant drive current A can flow, and the device can have excellent reliability.

[0160] Referring again to Figures 7 to 10 , the first interlayer insulating layer 160 is located on the first gate electrode 310 and the second gate electrode 410. The first interlayer insulating layer 160 may be formed of an inorganic material such as silicon oxide (SiO x ), silicon nitride (SiN x ) or a stacked structure thereof.

[0161] The first interlayer insulating layer 160 may include a first contact hole CT1 passing through it to expose a part of the upper surface of the first active layer 350, and may also include a second contact hole CT2 passing through it to expose another part of the upper surface of the first active layer 350. That is, the first contact hole CT1 may be formed to expose the first conductive region 350a of the first active layer 350, and the second contact hole CT2 may be formed to expose the second conductive region 350b of the first active layer 350. In addition, a third contact hole CT3 passing through them to expose the first light blocking layer 360 may be formed in the first interlayer insulating layer 160 and the buffer layer 120.

[0162] In addition, the first interlayer insulating layer 160 may include a fourth contact hole CT4 passing through it to expose a part of the upper surface of the second active layer 450, and may also include a fifth contact hole CT5 passing through it to expose another part of the upper surface of the second active layer 450. That is, the fourth contact hole CT4 may be formed to expose the first conductive region 450a of the second active layer 450, and the fifth contact hole CT5 may be formed to expose the second conductive region 450b of the second active layer 450.

[0163] The first source electrode 330 and the first drain electrode 340 of the first transistor TR1, and the second source electrode 430 and the second drain electrode 440 of the second transistor TR2 are located on the first interlayer insulating layer 160.

[0164] The first source electrode 330 is in contact with a first conductive region 350a formed on one side of the first active layer 350 through a first contact hole CT1. The first drain electrode 340 is in contact with a second conductive region 350b formed on the other side of the first active layer 350 through a second contact hole CT2.

[0165] The second source electrode 430 is in contact with a first conductive region 450a formed on one side of the second active layer 450 through a fourth contact hole CT4. The second drain electrode 440 is in contact with a second conductive region 450b formed on the other side of the second active layer 450 through a fifth contact hole CT5.

[0166] A first passivation layer 170 is located on the first source electrode 330 and the second source electrode 430, and the first drain electrode 340 and the second drain electrode 440 of the first transistor TR1 and the second transistor TR2. The first passivation layer 170 can be formed of an inorganic material such as silicon oxide (SiO x ), silicon nitride (SiN x ), or a stacked structure thereof.

[0167] A first planarization layer 180 is located on the first passivation layer 170. The first planarization layer 180 can planarize the steps caused by thin film transistors such as the first transistor TR1 and the second transistor TR2. The first planarization layer 180 can be formed of an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0168] An EL element including a first electrode 191, an organic light emitting layer 192, and a second electrode 193 can be formed on the first planarization layer 180, and a pixel defining layer 195 can also be formed.

[0169] The first electrode 191 can be formed on the first planarization layer 180. The first electrode 191 can be connected to the first source electrode 330 of the first transistor TR1 through a contact hole CNT passing through the first passivation layer 170 and the first planarization layer 180.

[0170] The pixel defining layer 195 may be formed to cover the edges of the first electrode 191 on the first planarization layer 180 to define pixels. That is, the pixel defining layer 195 is used to define or divide pixels. Each of the pixels represents an area where the first electrode 191, the organic light emitting layer 192, and the second electrode 193 are sequentially stacked, and holes from the first electrode 191 and electrons from the second electrode 193 are combined with each other in the organic light emitting layer 192 to emit light.

[0171] The organic light emitting layer 192 may be located on the first electrode 191 and the pixel defining layer 195. The organic light emitting layer 192 may include a hole transport layer, a light emitting layer, and an electron transport layer. Additionally, the organic light emitting layer 192 may be formed in a stacked tandem structure of two or more, and in this case, a charge generation layer may be formed between the stacks.

[0172] The second electrode 193 may be formed on the organic light emitting layer 192. The second electrode 193 may be a common layer formed commonly for the pixels.

[0173] The light emitting element EL may be formed as a top emission type that emits light in the upward direction. In this case, the first electrode 191 may be formed of a metal material having a high reflectivity such as a stacked structure of aluminum (Al) and titanium (Ti) (Ti / Al / Ti), a stacked structure of Al and ITO (ITO / Al / ITO), an APC alloy, a stacked structure of an APC alloy and ITO (ITO / APC / ITO), etc. The APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu). In addition, the second electrode 193 may be formed of a transparent conductive material (TCO) such as ITO or IZO that can transmit light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the second electrode 193 is formed of a semi-transmissive conductive material, the light emitting efficiency can be improved due to the microcavity effect.

[0174] The encapsulation layer 196 may be formed on the second electrode 193 to reduce or prevent the penetration of oxygen or moisture. The encapsulation layer 196 may include at least one inorganic layer. The inorganic layer may be formed of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, and / or titanium oxide. Additionally, the encapsulation layer 196 may include at least one organic layer to reduce or prevent particles from penetrating the encapsulation layer 196 and entering the organic light emitting layer 192 and the second electrode 193. The organic layer may be formed of epoxy, acrylate, or polyurethane acrylate.

[0175] Meanwhile, each of the plurality of transistors, the pull-up transistor TU, and the pull-down transistor TD of the node controller NC of the scan driving circuit 30 may be formed to be Figure 9 and Figure 10The second transistor TR2 shown in [reference] is substantially the same. That is, in the pull-up transistor TU and the pull-down transistor TD of the scan driving circuit 30, an oxide layer having a crystalline oxide may not be located between the active layer and the gate electrode. In this case, the third gate electrode, the third active layer, the third source electrode, and the third drain electrode of each of the plurality of transistors of the node controller NC, the pull-up transistor TU, and the pull-down transistor TD of the scan driving circuit 30 are substantially the same as the second gate electrode 410, the second active layer 450, the second source electrode 430, and the second drain electrode 440 of the second transistor TR2 described above with reference to Figure 9 and Figure 10 and thus, a repetitive detailed description thereof will be omitted.

[0176] In addition, each of the first distribution transistor MT1 and the second distribution transistor MT2 of the data voltage distribution circuit DMUX may be formed to be substantially the same as the second transistor TR2 shown in Figure 9 and Figure 10 . That is, in each of the first distribution transistor MT1 and the second distribution transistor MT2 of the data voltage distribution circuit DMUX, an oxide layer having a crystalline oxide may be omitted from between the active layer and the gate electrode. In this case, the fourth gate, the fourth active layer, the fourth source electrode, and the fourth drain electrode of each of the first distribution transistor MT1 and the second distribution transistor MT2 of the data voltage distribution circuit DMUX are substantially the same as the second gate electrode 410, the second active layer 450, the second source electrode 430, and the second drain electrode 440 of the second transistor TR2 described above with reference to Figure 9 and Figure 10 and thus, a repetitive detailed description thereof will be omitted.

[0177] Figure 13 is a plan view showing an example of the pull-up transistor of the scan driving circuit shown in Figure 2 . Figure 14 is a cross-sectional view showing an example taken along line IV-IV' shown in Figure 13 .

[0178] Figure 13 and Figure 14 differ in that the third active layer 550 of the pull-up transistor TU of the scan driving circuit 30 includes polysilicon.

[0179] Referring to Figure 13 and Figure 14 , the pull-up transistor TU of the scan driving circuit 30 includes a third gate electrode 510, a third active layer 550, a third source electrode 530, and a third drain electrode 540.

[0180] The third active layer 550 may be located on the buffer layer 120 and may include polycrystalline silicon. The third active layer 550 may include a first high-concentration doped region 550a, a second high-concentration doped region 550b, a channel region 550c, a first low-concentration doped region 550d, and a second low-concentration doped region 550e. The channel region 550c may be formed of polycrystalline silicon doped with no impurities. The first high-concentration doped region 550a and the second high-concentration doped region 550b may be formed of polycrystalline silicon doped with high-concentration impurities. The first low-concentration doped region 550d and the second low-concentration doped region 550e may be formed of polycrystalline silicon doped with low-concentration impurities.

[0181] The first gate insulating layer 130 is located on the third active layer 550. The description of the first gate insulating layer 130 is the same as that referred to above Figures 7 to 10 described.

[0182] The third gate electrode 510 is located on the first gate insulating layer 130. The third gate electrode 510 may overlap with the third active layer 550 in a state where the first gate insulating layer 130 is interposed therebetween. For example, the third gate electrode 510 may overlap with the channel region 550c of the third active layer 550. In addition, the description of the third gate electrode 510 is the same as the description of the first gate electrode 310 and the second gate electrode 410 referred to above.

[0183] The first interlayer insulating layer 160 is located on the third gate electrode 510. The description of the first interlayer insulating layer 160 is the same as that referred to above Figures 7 to 10 described.

[0184] The first interlayer insulating layer 160 may include a seventh contact hole CT7 passing through the first interlayer insulating layer 160 to expose a part of the upper surface of the third active layer 550, and an eighth contact hole CT8 passing through the first interlayer insulating layer 160 to expose another part of the upper surface of the third active layer 550. The seventh contact hole CT7 may be formed to expose the first high-concentration doped region 550a of the third active layer 550, and the eighth contact hole CT8 may be formed to expose the second high-concentration doped region 550b of the third active layer 550.

[0185] The third source electrode 530 and the third drain electrode 540 of the pull-up transistor TU are located on the first interlayer insulating layer 160.

[0186] The third source electrode 530 is in contact with the first high-concentration doped region 550a formed on one side of the third active layer 550 through the seventh contact hole CT7. The third drain electrode 540 is in contact with the second high-concentration doped region 550b formed on the other side of the third active layer 550 through the eighth contact hole CT8.

[0187] The first passivation layer 170 is located on the third source electrode 530 and the third drain electrode 540 of the pull-up transistor TU.

[0188] The first planarization layer 180 may be formed on the first passivation layer 170 to planarize steps caused by thin film transistors such as the pull-up transistor TU.

[0189] Meanwhile, each of the plurality of transistors of the node controller NC of the scan driving circuit 30 and the pull-down transistor TD may be formed to be substantially the same as Figure 13 and Figure 14 the pull-up transistor TU shown in.

[0190] In addition, each of the first distribution transistor MT1 and the second distribution transistor MT2 of the data voltage distribution circuit DMUX may include a fourth gate electrode, a fourth active layer, a fourth source electrode, and a fourth drain electrode. Each of the first distribution transistor MT1 and the second distribution transistor MT2 of the data voltage distribution circuit DMUX may be formed to be substantially the same as Figure 13 and Figure 14 the pull-up transistor TU of the scan driving circuit 30 shown in. In this case, the fourth gate, the fourth active layer, the fourth source electrode, and the fourth drain electrode of each of the first distribution transistor MT1 and the second distribution transistor MT2 of the data voltage distribution circuit DMUX are substantially the same as the third gate electrode 510, the third active layer 550, the third source electrode 530, and the third drain electrode 540 of the pull-up transistor TU described above with reference to Figure 13 and Figure 14 and thus, a repeated detailed description thereof will be omitted.

[0191] Hereinafter, a manufacturing method of the display device 1 including the first transistor TR1 and the second transistor TR2 will be described.

[0192] Figure 15 is a flowchart showing a manufacturing method of a display device according to some embodiments. Figure 16 and Figure 17 are cross-sectional views partially showing a manufacturing method of a display device according to some embodiments. Figure 18 is a flowchart showing a method of forming an oxide layer of a display device according to some embodiments. Figures 19 to 23 is a cross-sectional view partially showing a manufacturing method of a display device according to some embodiments.

[0193] A manufacturing method of the display device 1 according to some embodiments may include: forming an oxide layer and a gate electrode on a gate insulating layer formed on an active layer. As described above, the first oxide layer 370 of the first transistor TR1 includes a crystalline oxide containing tin (Sn), and may be formed by an etching process different from that of the first gate electrode 310.

[0194] Referring to Figures 15 to 23 , first, asFigure 16 As shown, a first light-blocking layer 360 is formed on a first substrate 110 (S100), and a buffer layer 120 is formed on the first light-blocking layer 360 (S200). In an embodiment, the first light-blocking layer 360 may be formed by patterning a light-blocking metal layer formed on the first substrate 110 by a sputtering method using an etching process with a photoresist pattern. The buffer layer 120 may be formed by chemical vapor deposition. However, the present disclosure is not limited thereto.

[0195] Since the descriptions of the first light-blocking layer 360 and the buffer layer 120 are the same as those described above, their repeated detailed descriptions will be omitted. However, as will be described later, light-blocking layers other than the first light-blocking layer 360 may also be located on the first substrate 110. In this case, the other light-blocking layers may be formed in the same process as the first light-blocking layer 360.

[0196] Next, as Figure 17 shown, a first active layer 350 and a second active layer 450 are formed on the buffer layer 120 (S300). The first active layer 350 and the second active layer 450 may be formed by a patterning process using a photoresist after forming one layer by a sputtering method. However, the present disclosure is not limited thereto, and in some cases, they may be formed by atomic layer deposition.

[0197] Next, a first gate insulating layer 130 is formed on the first active layer 350 and the second active layer 450 (S400), and a first oxide layer 370, a first gate electrode 310, and a second gate electrode 410 are formed on the first gate insulating layer 130 (S500).

[0198] According to some embodiments, the method of manufacturing the display device 1 may include: forming the gate electrode and the oxide layer by performing two etching processes. The gate electrode and the oxide layer may be formed by partially etching and removing the metal layer and the oxide layer constituting the gate electrode, respectively. Here, the metal layer and the oxide layer may be partially removed by different etching processes.

[0199] As Figure 18 shown, the process of forming the gate electrode and the oxide layer may include: forming an oxide layer OXL and a metal layer MTL on the first gate insulating layer 130 (S510); performing a first etching process of etching a part of the metal layer MTL to form the first gate electrode 310 and the second gate electrode 410 (S520); forming a photoresist PR on the first gate electrode 310 and the second gate electrode 410 (S530); and performing a second etching process of etching a part of the oxide layer OXL and the first gate insulating layer 130 along the photoresist PR (S540).

[0200] The first gate electrode 310 and the second gate electrode 410 may be formed by a first etching process for etching the metal layer MTL, and the first oxide layer 370 may be formed by a second etching process for etching the oxide layer OXL and the first gate insulating layer 130. Hereinafter, the processes for forming the first gate electrode 310, the second gate electrode 410, and the first oxide layer 370 will be described in detail with reference to other drawings.

[0201] Meanwhile, in some embodiments, the first transistor TR1 may include the first oxide layer 370, but the second transistor TR2 may not include the first oxide layer 370. Accordingly, an etching process for forming the first oxide layer 370 may be performed on the first active layer 350, and the etching process may not be performed on the second active layer 450. However, the present disclosure is not limited thereto, and a case where the first oxide layer 370 is located on the first active layer 350 but not on the second active layer 450 will be described by way of example below.

[0202] First, as Figure 19 shown, the first gate insulating layer 130 is formed on the first active layer 350 and the second active layer 450 (S400), and the oxide layer OXL and the metal layer MTL are formed on the first gate insulating layer 130 (S510). The first gate insulating layer 130, the oxide layer OXL, and the metal layer MTL may be formed by chemical vapor deposition, but the present disclosure is not limited thereto. The oxide layer OXL may be located only on the first active layer 350 and not on the second active layer 450. As described above, since the second transistor TR2 does not include an oxide layer into which an excessive amount of oxygen (O) is implanted, only the first gate insulating layer 130 and the metal layer MTL may be formed on the second active layer 450. The metal layer MTL may be partially etched in a subsequent process to form the first gate electrode 310 and the second gate electrode 410.

[0203] When the oxide layer OXL is located on the first gate insulating layer 130, excessive oxygen (O) may be supplied from the oxide layer OXL to the first gate insulating layer 130. Subsequently, when a heat treatment process is performed on the oxide layer OXL, the excessive oxygen (O) supplied to the first gate insulating layer 130 is implanted into the first active layer 350. Hydrogen (H) contained in the oxygen defect region of the first active layer 350 moves to the first gate insulating layer 130, and the excessive oxygen (O) injected from the oxide layer OXL may reduce the number of oxygen defect regions in the first active layer 350. Since its description is the same as that described above, its repeated detailed description will be omitted.

[0204] The oxide layer OXL can be partially etched and removed in subsequent processes to form the first oxide layer 370. According to some embodiments, the oxide layer OXL can include a crystalline oxide containing tin (Sn). Its description is the same as that described above. The oxide layer OXL can be located on the first active layer 350, but not on the second active layer 450. As described above, since the first transistor TR1 includes the first oxide layer 370, but the second transistor TR2 does not include the first oxide layer 370, the oxide layer OXL can be located only on the first active layer 350. However, the present disclosure is not limited thereto.

[0205] Subsequently, a first etching process (S520) for partially etching the metal layer MTL is performed. The first etching process can be an etching process performed by a conventional method. In some embodiments, the first etching process is a patterning process using a photoresist and can be a wet etching process. The metal layer MTL can be partially etched and removed by the first etching process to form the first gate electrode 310 and the second gate electrode 410. In some embodiments, portions of the metal layer MTL other than the regions overlapping with a part of the first active layer 350 and the second active layer 450 can be removed, and the remaining regions can respectively constitute the first gate electrode 310 and the second gate electrode 410.

[0206] Next, referring to Figure 20 , a photoresist PR is formed on the first gate electrode 310 and the second gate electrode 410 (S530), and a second etching process (S540) for etching a part of the oxide layer OXL and the first gate insulating layer 130 is performed.

[0207] The photoresist PR can be formed to prevent a partial region of the oxide layer OXL from being etched. In an embodiment, the photoresist PR can be located on the first gate electrode 310 and the second gate electrode 410. The photoresist PR prevents the portion of the oxide layer OXL located below the first gate electrode 310 from being removed, thereby forming the first oxide layer 370 between the first gate electrode 310 and the first active layer 350. The second etching process can remove the oxide layer OXL and the first gate insulating layer 130 in the regions that do not overlap with the photoresist PR or the first gate electrode 310 and the second gate electrode 410. The first oxide layer 370 can be formed by the second etching process, and the first gate insulating layer 130 can be partially etched and removed.

[0208] In some embodiments, the second etching process and the first etching process may be different etching processes. For example, when the first etching process is a wet etching process, the second etching process may be a dry etching process. As described above, the oxide layer OXL may include a crystalline oxide containing tin (Sn), and in this case, the oxide layer OXL may not be etched in the first etching process (e.g., wet etching process) for forming the first gate electrode 310 and the second gate electrode 410, thereby preventing the formation of an undercut under the first gate electrode 310. In other words, the oxide layer OXL constituting the first oxide layer 370 may include a crystalline oxide so as not to be etched in the first etching process.

[0209] As Figure 21 shown, the first oxide layer 370 and the first gate insulating layer 130 may be formed by performing a second etching process. At the same time, according to some embodiments, the photoresist PR formed on the first gate electrode 310 may have a width measured in one direction that is greater than the width of the first gate electrode 310 measured in this one direction. The width W370 of the first oxide layer 370 formed by the second etching process measured in one direction (see Figure 11 ) may be greater than the width W310 of the first gate electrode 310 measured in this one direction (see Figure 11 ). At least one end of the first oxide layer 370 may be formed to protrude more than one end of the first gate electrode 310. These shapes of the first gate electrode 310 and the first oxide layer 370 may be formed by different etching processes (e.g., the first etching process and the second etching process, respectively). The detailed description thereof is the same as that described above with reference to Figure 11 the description.

[0210] Next, as Figure 22 shown, a first interlayer insulating layer 160, a first source electrode 330 and a second source electrode 430, and a first drain electrode 340 and a second drain electrode 440 (S600) are formed to form a first transistor TR1 and a second transistor TR2. The first source electrode 330 and the second source electrode 430, and the first drain electrode 340 and the second drain electrode 440 may be formed by patterning a metal layer formed on the first interlayer insulating layer 160 by means of a sputtering method using an etching process using a photoresist pattern. However, the present disclosure is not limited thereto.

[0211] Thereafter, as Figure 23 shown, a first passivation layer 170, a first planarization layer 180, a first electrode 191, an organic light-emitting layer 192, a pixel defining layer 195, a second electrode 193, and a packaging layer 196 (S700) are formed.

[0212] In the following, the structures of the first transistor TR1 and the second transistor TR2 according to another embodiment will be described.

[0213] According to some embodiments, the second transistor TR2 may also include a second oxide layer including a crystalline oxide containing tin (Sn) between the second active layer 450 and the second gate electrode 410.

[0214] Figure 24 is a cross-sectional view showing the second transistor according to another embodiment.

[0215] Referring to Figure 24 , the second transistor TR2_1 according to this embodiment may include a second oxide layer 470_1 between the second gate electrode 410_1 and the second active layer 450_1. The difference between this embodiment and the embodiment of Figure 10 is that the second transistor TR2_1 as the switching transistor of each pixel PX also has a second oxide layer 470_1, and the second oxide layer 470_1 includes a crystalline oxide containing tin (Sn). In the following description, redundant descriptions will be omitted, and the differences will be mainly described.

[0216] Figure 24 The second transistor TR2_1 of

[0217] may further include a second oxide layer 470_1. The second oxide layer 470_1 may be located on the first gate insulating layer 130, and may be located between the second gate electrode 410_1 and the second active layer 450_1. The second oxide layer 470_1 may be positioned to overlap at least the channel region 450c of the second active layer 450_1. As described above, the second oxide layer 470_1 may be formed by an etching process different from the etching process for forming the second gate electrode 410_1, and the width of the second oxide layer 470_1 measured in one direction (e.g., in the third direction DR3) may be greater than the width of the second gate electrode 410_1 measured in the same direction. That is, at least one end of the second oxide layer 470_1 may be formed to protrude more than one end of the second gate electrode 410_1.

[0218] Figures 25 to 27 is a cross-sectional view showing the manufacturing process of the second transistor of Figure 24 .

[0219] Referring to Figures 25 to 27, in the process of forming the oxide layer OXL and the metal layer MTL during the manufacturing process of the display device 1, the oxide layer OXL can be formed to overlap at least the first active layer 350 and the second active layer 450 on the first gate insulating layer 130. As Figure 25 shown, the oxide layer OXL can be formed on the first active layer 350 and the second active layer 450, and the metal layer MTL can be formed on the oxide layer OXL. Figure 25 The embodiment of Figure 19 differs from the embodiment of

[0220] in that the oxide layer OXL is formed on the second active layer 450. Accordingly, when the oxide layer OXL is partially etched by performing subsequent processes, the first oxide layer 370 and the second oxide layer 470 can be formed. Figure 26 As shown, the metal layer MTL is etched by a first etching process to form the first gate electrode 310 and the second gate electrode 410. Then, as Figure 26 shown, a photoresist PR is formed on the first gate electrode 310 and the second gate electrode 410. As described above, the photoresist PR formed on the first gate electrode 310 has a width greater than the width of the first gate electrode 310. Similarly, the photoresist PR formed on the second gate electrode 410 can also have a width greater than the width of the second gate electrode 410. The first oxide layer 370 and the second oxide layer 470 formed by the second etching process can respectively have widths greater than the widths of the first gate electrode 310 and the second gate electrode 410.

[0221] Referring to Figure 27 , as the oxide layer OXL and the first gate insulating layer 130 are etched by the second etching process, the first oxide layer 370 can be formed between the first active layer 350 and the first gate electrode 310, and the second oxide layer 470 can be formed between the second active layer 450 and the second gate electrode 410. Since its description is the same as that described above, its repeated detailed description will be omitted.

[0222] Meanwhile, according to some embodiments, the second transistor TR2 may also include a light-blocking layer similar to the first transistor TR1.

[0223] Figure 28 is a plan view showing a second transistor according to another embodiment. Figure 29 is a cross-sectional view taken along the Figure 28 line III-III' of

[0224] Referring to Figure 28 and Figure 29 , the second transistor TR2_2 according to this embodiment further includes a second light-blocking layer 460_2, and the second gate electrode 410_2 can be connected to the second light-blocking layer 460_2.​ and ​ the second transistor TR2_2 of ​ and ​ the second transistor TR2 is different in that the second gate electrode 410_2 is connected to the second light-blocking layer 460_2. In the following description, redundant descriptions will be omitted, and the differences will be mainly described.

[0225] ​ and ​ the second transistor TR2_2 of

[0226] The second light-blocking layer 460_2 is located on the first substrate 110. The second light-blocking layer 460_2 can reduce or prevent light from the outside from being incident on the second active layer 450_2 through the first substrate 110. The length of the second light-blocking layer 460_2 in the third direction DR3 and the length of the second light-blocking layer 460_2 in the fourth direction DR4 can (for example, respectively) be longer than the length of the second active layer 450_2 in the third direction DR3 and the length of the second active layer 450_2 in the fourth direction DR4. The second light-blocking layer 460_2 can be formed as a single layer or a multi-layer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) and / or their alloys. The buffer layer 120 can be formed on the second light-blocking layer 460_2.

[0227] The second gate electrode 410_2 can be in contact with the second light-blocking layer 460_2 through the sixth contact hole CT6. The sixth contact hole CT6 can be formed to pass through the first gate insulating layer 130 and the buffer layer 120 to expose the second light-blocking layer 460_2. In this case, the second gate electrode 410_2 and the second light-blocking layer 460_2 located below the second active layer 450_2 have the same voltage. That is, the second gate electrode 410_2 can be used as an upper gate electrode, and the second light-blocking layer 460_2 can be used as a lower gate electrode. Therefore, since the second transistor TR2_2 as a switching transistor can be driven by a double-gate method, when the second transistor TR2_2 is turned off, leakage current flowing into the channel region 450c_2 of the second active layer 450_2 of the second transistor TR2_2 can be prevented or reduced.

[0228] ​ is a schematic cross-sectional view showing a part of a display device according to another embodiment.

[0229] Referring to ​, the display device 1 according to the present embodiment may include a plurality of transistor layers TFTL1 and TFTL2. The transistor layers TFTL1 and TFTL2 may include a first transistor layer TFTL1 and a second transistor layer TFTL2 having different transistors, respectively. In some embodiments, a third transistor (e.g., a pull-up transistor) TR3_3 included in the scan driving circuit 30 may be located in the first transistor layer TFTL1, and a first transistor TR1_3 and a second transistor TR2_3 of each pixel PX may be located in the second transistor layer TFTL2 above the third transistor TR3_3 (e.g., at a layer higher than the third transistor TR3_3). ​ The display device 1 of ​ and ​ The difference from the display device of ​ is that the first transistor TR1 of ​ and the pull-up transistor TU of are located in different transistor layers TFTL1 and TFTL2. In the following description, redundant descriptions will be omitted, and the differences will be mainly described.

[0230] The first transistor layer TFTL1 includes a third transistor TR3_3 located in the non-display area NDA, and the third transistor TR3_3 includes a third gate electrode 510_3, a third active layer 550_3, a third source electrode 530_3, and a third drain electrode 540_3.

[0231] The third active layer 550_3 may be located on the buffer layer 120. The third active layer 550_3 may include polysilicon and may include a first high-concentration doped region 550a_3, a second high-concentration doped region 550b_3, a channel region 550c_3, a first low-concentration doped region 550d_3, and a second low-concentration doped region 550e_3. The channel region 550c_3 may be formed of polysilicon without doping impurities. The first high-concentration doped region 550a_3 and the second high-concentration doped region 550b_3 may be formed of polysilicon doped with high-concentration impurities. The first low-concentration doped region 550d_3 and the second low-concentration doped region 550e_3 may be formed of polysilicon doped with low-concentration impurities. However, the present disclosure is not limited thereto, and in some cases, the third active layer 550_3 may also be formed of an oxide semiconductor in the same manner as the first active layer 350_3.

[0232] A second gate insulating layer 230 is located on the third active layer 550_3. The second gate insulating layer 230 may be formed of, for example, silicon oxide (SiO x ), silicon nitride (SiN x ) or a stacked structure thereof.

[0233] The third gate electrode 510_3 is located on the second gate insulating layer 230. The third gate electrode 510_3 may overlap with the third active layer 550_3 with the second gate insulating layer 230 interposed therebetween. For example, the third gate electrode 510_3 may be formed as a single layer or a multi-layer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) and / or their alloys.

[0234] Meanwhile, in the drawings, the second gate insulating layer 230 is shown only between the third active layer 550_3 and the third gate electrode 510_3, but embodiments of the present disclosure are not limited thereto. That is, the second gate insulating layer 230 may also be formed on the upper surface and the side surface of the third active layer 550_3.

[0235] The second interlayer insulating layer 260 is located on the third gate electrode 510_3. The second interlayer insulating layer 260 may be formed of an inorganic material such as silicon oxide (SiO x ), silicon nitride (SiN x ) or a stacked structure thereof.

[0236] The second interlayer insulating layer 260 may include a seventh contact hole CT7 that passes through the second interlayer insulating layer 260 to expose a part of the upper surface of the third active layer 550_3, and an eighth contact hole CT8 that passes through the second interlayer insulating layer 260 to expose another part of the upper surface of the third active layer 550_3. That is, the seventh contact hole CT7 may be formed to expose the first highly doped region 550a_3 of the third active layer 550_3, and the eighth contact hole CT8 may be formed to expose the second highly doped region 550b_3 of the third active layer 550_3.

[0237] The third source electrode 530_3 and the third drain electrode 540_3 of the third transistor TR3_3 are located on the second interlayer insulating layer 260.

[0238] The third source electrode 530_3 is in contact with the first highly doped region 550a_3 formed on one side of the third active layer 550_3 through the seventh contact hole CT7. The third drain electrode 540_3 is in contact with the second highly doped region 550b_3 formed on the other side of the third active layer 550_3 through the eighth contact hole CT8.

[0239] The second passivation layer 270 is formed on the third source electrode 530_3 and the third drain electrode 540_3. The second passivation layer 270 may be formed of an inorganic layer (for example, a silicon oxide (SiO x ) layer, a silicon nitride (SiN x ) layer or a multi-layer thereof).

[0240] The second planarization layer 280 is located on the second passivation layer 270. The second planarization layer 280 can planarize the steps caused by thin film transistors such as the third transistor TR3_3. The second planarization layer 280 can be formed of an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, etc.

[0241] Instead of the buffer layer 120 described above with reference to ​ the insulating layer 121 can be located on the second planarization layer 280. In addition, the first interlayer insulating layer 160, the first passivation layer 170, and the first planarization layer 180 described above with reference to ​ can be formed on the insulating layer 121.

[0242] In ​ an embodiment of ​ different from the embodiment of

[0243] the first transistor layer TFTL1 including a plurality of transistors including a pull-up transistor, a pull-down transistor, and a node controller NC can be positioned, where the plurality of transistors of the pull-up transistor, the pull-down transistor, and the node controller NC are included in the scan driving circuit 30 located in the non-display area NDA. In addition, the second transistor layer TFTL2 including the first transistor TR1 and the second transistor TR2 which are the driving transistor and the switching transistor of each pixel PX can be located in the display area DA. Since the second transistor layer TFTL2 is located above the first transistor layer TFTL1, the transistors located in the display area DA can be positioned above the transistors located in the non-display area NDA. The light-emitting element EL including the first electrode 191, the organic light-emitting layer 192, and the second electrode 193 can be formed on the second transistor layer TFTL2. At the end of the detailed description, those skilled in the art will recognize that many changes and modifications can be made to the embodiments without substantially departing from the principles or spirit and scope of the present invention. Therefore, the embodiments disclosed in the present invention are used only in a general and descriptive sense and not for the purpose of limitation.

Claims

1. A display device, comprising: Pixels, the pixels being connected to a scan line and a data line intersecting the scan line, Each of the pixels includes: A light-emitting element; and A first transistor configured to control a driving current supplied to the light-emitting element according to a data voltage applied from the data line. The first transistor includes a first active layer and a first oxide layer. Among them, the first active layer has an oxide semiconductor, and the first oxide layer is located on the first active layer and has a crystalline oxide containing tin. Among them One of the pixels includes: A second transistor that applies the data voltage of a corresponding data line in the data lines to the first transistor according to a scan signal applied to a corresponding scan line in the scan lines; and Among them, the second transistor includes a second active layer having an oxide semiconductor, a second gate insulating layer located on the second active layer, and a second gate electrode located on the second gate insulating layer and overlapping the second active layer.

2. The display device according to claim 1, wherein The first oxide layer has a tin content in the range of 1 at.% to 100 at.% relative to the content of cations contained in the crystalline oxide.

3. The display device according to claim 2, wherein, The first oxide layer includes tin zinc oxide TZO, tin gallium oxide TGO, indium tin zinc oxide ITZO, indium tin gallium oxide ITGO, or indium tin zinc gallium oxide ITZGO.

4. The display device according to claim 3, wherein, The first active layer includes indium tin oxide ITO, indium tin gallium oxide ITGO, indium gallium zinc oxide IGZO, or indium gallium zinc tin oxide IGZTO.

5. The display device according to claim 1, wherein, The first transistor includes a first gate insulating layer located on the first active layer, and a first gate electrode located on the first gate insulating layer and overlapping the first active layer, and Among them, the first oxide layer is located between the first gate electrode and the first gate insulating layer.

6. The display device according to claim 5, wherein, The oxygen concentration in the first active layer is greater than the oxygen concentration in the first oxide layer.

7. The display device according to claim 5, wherein, The first active layer includes a first conductive region, a second conductive region, and a channel region located between the first conductive region and the second conductive region, and Among them, at least a part of the first oxide layer overlaps with the channel region of the first active layer.

8. The display device according to claim 7, wherein, The width of the first oxide layer is greater than the width of the channel region of the first active layer.

9. The display device according to claim 7, wherein, The first transistor further includes: A first interlayer insulating layer located on the first gate electrode; A first source electrode that contacts the first conductive region through a first contact hole passing through the first interlayer insulating layer; and A first drain electrode that contacts the second conductive region through a second contact hole passing through the first interlayer insulating layer.

10. The display device according to claim 9, wherein, The first transistor further includes: A first light-blocking layer located below the first active layer; and A buffer layer located between the first active layer and the first light-blocking layer, and Among them, the first source electrode contacts the first light-blocking layer through a third contact hole passing through the first interlayer insulating layer and the buffer layer.

11. The display device according to claim 5, wherein, At least one end of the first oxide layer protrudes outward beyond one end of the first gate electrode.

12. The display device according to claim 11, wherein, The width of the first oxide layer is greater than the width of the first gate electrode.

13. The display device according to claim 11, wherein, At least a part of the upper surface of the first oxide layer is in contact with the first interlayer insulating layer on the first gate electrode.

14. The display device according to claim 1, wherein, The second transistor further includes: A second oxide layer, which is located between the second gate insulating layer and the second gate electrode and partially overlaps with the second active layer.

15. The display device according to claim 14, further comprising: A scan driving circuit configured to output a scan signal to the scan line, wherein the scan driving circuit includes: A third transistor, which includes a third active layer having an oxide semiconductor and a third gate electrode located on the third active layer, and the third transistor is configured such that the first oxide layer is not located between the third active layer and the third gate electrode.

16. A display device, comprising: A substrate including a display area and a non-display area; A first active layer located in the display area; A second active layer located in the non-display area; A gate insulating layer located on the first active layer and the second active layer; A first gate electrode located on the gate insulating layer and partially overlapping with the first active layer; A second gate electrode located on the gate insulating layer and partially overlapping with the second active layer; An interlayer insulating layer located on the first gate electrode and the second gate electrode; A first source electrode and a first drain electrode, which are located on the interlayer insulating layer and in the display area; A second source electrode and a second drain electrode, which are located in the non-display area; And An oxide layer located on the gate insulating layer and having a crystalline oxide containing tin, wherein the first active layer and the second active layer include an oxide semiconductor.

17. The display device according to claim 16, wherein, The oxide layer includes a first oxide layer located between the first gate electrode and the gate insulating layer, and wherein the width of the first oxide layer is greater than the width of the first gate electrode.

18. The display device according to claim 17, wherein, The first active layer includes a first conductive region, a second conductive region, and a channel region located between the first conductive region and the second conductive region, and wherein at least a part of the first oxide layer overlaps with the channel region of the first active layer.

19. The display device according to claim 18, further comprising: An interlayer insulating layer located on the first gate electrode, wherein the first source electrode is in contact with the first conductive region through a first contact hole passing through the interlayer insulating layer, and wherein the first drain electrode is in contact with the second conductive region through a second contact hole passing through the interlayer insulating layer.

20. The display device according to claim 19, further comprising: A first light-blocking layer, the first light-blocking layer being located under the first active layer; and a buffer layer, the buffer layer being located between the first active layer and the first light-blocking layer, wherein the first source electrode is in contact with the first light-blocking layer via a third contact hole passing through the interlayer insulating layer and the buffer layer.

21. The display device according to claim 16, wherein, The oxide layer is not located between the second gate electrode and the gate insulating layer.

22. The display device according to claim 21, further comprising: an interlayer insulating layer, the interlayer insulating layer being located on the second gate electrode, wherein the second active layer includes a third conductive region, a fourth conductive region, and a channel region located between the third conductive region and the fourth conductive region, wherein the second source electrode is in contact with the third conductive region via a fourth contact hole passing through the interlayer insulating layer, and wherein the second drain electrode is in contact with the fourth conductive region via a fifth contact hole passing through the interlayer insulating layer.

23. A method of manufacturing a display device, the method comprising: forming a substrate, an active layer on the substrate, and a gate insulating layer on the active layer, the active layer including a first active layer and a second active layer, the second active layer including a third conductive region, a fourth conductive region, and a channel region located between the third conductive region and the fourth conductive region; forming an oxide layer on the gate insulating layer and having a crystalline oxide containing tin, and a metal layer on the oxide layer; performing a first etching for etching at least a part of the metal layer to form a first gate electrode and a second gate electrode; performing a second etching for etching at least a part of the oxide layer and the gate insulating layer to form a first oxide layer; forming a first interlayer insulating layer on the first gate electrode and a second interlayer insulating layer on the second gate electrode; and forming a second source electrode in contact with the third conductive region via a fourth contact hole passing through the second interlayer insulating layer, and a second drain electrode in contact with the fourth conductive region via a fifth contact hole passing through the second interlayer insulating layer.

24. The method according to claim 23, wherein, The first active layer and the second active layer have an oxide semiconductor, wherein the first gate electrode overlaps with the first active layer and the second gate electrode overlaps with the second active layer, and wherein the first oxide layer is located between the first gate electrode and the first active layer.

25. The method according to claim 24, wherein, The width of the first oxide layer is greater than the width of the first gate electrode.

26. The method according to claim 24, wherein, The first oxide layer is not located between the second active layer and the second gate electrode.

27. The method according to claim 24, wherein, The first etching includes a wet etching process, and the second etching includes a dry etching process.

Images