Semiconductor module arrangement and method for operating a semiconductor module arrangement

Abstract

A semiconductor module arrangement and a method for operating a semiconductor module arrangement are disclosed. The semiconductor module arrangement comprises an input stage comprising a first output terminal and a second output terminal, wherein a first inductive element is coupled to the first output terminal; an output stage comprising at least one controllable semiconductor element, a third input terminal coupled to the first inductive element, a fourth input terminal coupled to the second output terminal, a third output terminal and a fourth output terminal, the first inductive element being coupled between the first output terminal and the third input terminal; a first controllable semiconductor element and a first capacitive element coupled in series and between a common node between the first inductive element and the third input terminal and a common node between the second output terminal and the fourth input terminal; and a first diode element coupled in parallel to the first controllable semiconductor element.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor module arrangement comprising controllable semiconductor elements and a method for operating the semiconductor module arrangement. BACKGROUND

[0002] Semiconductor devices, such as power semiconductor modules, are widely used in automotive, industrial and consumer electronics applications to drive loads, convert power, etc. Such semiconductor devices can comprise one or more controllable semiconductor elements. For example, two or more controllable semiconductor elements can form a half-bridge arrangement. Many applications require fast switching of the controllable semiconductor elements while at the same time the overall losses of the arrangement are preferably low. Even further, the electrical strength of the arrangement should be sufficient to withstand even higher voltage overshoots that can occur instantaneously when the controllable semiconductor elements are turned off.

[0003] There is a general need for a semiconductor module arrangement that allows fast switching of controllable semiconductor elements while at the same time keeping the overall losses low and producing low voltage overshoots at turn-off. SUMMARY

[0004] A semiconductor module arrangement comprises an input stage comprising a first output terminal and a second output terminal, wherein a first inductive element is coupled to the first output terminal. The semiconductor module arrangement further comprises an output stage comprising at least one controllable semiconductor element, a third input terminal coupled to the first inductive element, a fourth input terminal coupled to the second output terminal, a third output terminal and a fourth output terminal, the first inductive element being coupled between the first output terminal and the third input terminal. The arrangement further comprises a first controllable semiconductor element and a first capacitive element, the first controllable semiconductor element and the first capacitive element being coupled in series between a common node between the first inductive element and the third input terminal and a common node between the second output terminal and the fourth input terminal, and a first diode element coupled in parallel to the first controllable semiconductor element, wherein a cathode terminal of the first diode element is coupled to the first capacitive element and an anode terminal of the first diode element is coupled to the common node between the first inductive element and the third input terminal.

[0005] A method for operating a semiconductor device comprises conducting at least one of the at least one controllable semiconductor element of an output stage, wherein a first inductive element is charged during the conducting operation of the at least one controllable semiconductor element, and wherein, once the conducting operation is completed, the energy stored in the first inductive element during the conducting operation is diverted to a first capacitive element via a first diode element. The method further comprises switching off at least one of the at least one controllable semiconductor element of the output stage, wherein the first controllable semiconductor element is in a blocking state at least during the conducting operation of the at least one controllable semiconductor element.

[0006] The application can be better understood with reference to the following drawings and description. The components in the drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the application. In the drawings, like reference numerals designate corresponding parts throughout the different views. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 A cross-sectional view of a semiconductor module device is schematically shown.

[0008] Figure 2 is a circuit diagram of a semiconductor device comprising a DC link capacitor.

[0009] Figure 3 An exemplary strip conductor for electrically coupling a DC link capacitor to a controllable semiconductor element is schematically shown.

[0010] Figure 4 is a circuit diagram of an exemplary semiconductor device.

[0011] Figure 5 Different voltages and currents in the semiconductor device of Figure 4 are schematically shown when conducting a transistor element.

[0012] Figure 6 Transistor voltages and transistor currents after switching off one of the transistor elements of the output stage of the device of Figure 4 are schematically shown.

[0013] Figure 7 Different voltages and currents in the semiconductor device of Figure 4 are schematically shown when switching off one of the transistor elements.

[0014] Figure 8 Different voltages and currents in the device of Figure 4 caused by conducting and switching off a transistor of the semiconductor device according to the first example are schematically shown. Figure 4

[0015] Figure 9 ​The voltage on the additional capacitor in the semiconductor device according to the first example is schematically shown. Figure 4

[0016] Figure 10 The different voltages and currents in the semiconductor device according to the second example are schematically shown. Figure 4 DETAILED DESCRIPTION

[0017] In the following detailed description, reference is made to the accompanying drawings. The drawings illustrate specific examples of the invention. It should be understood that the features and principles described in relation to one example can be combined with those of another unless specifically noted otherwise. In the description and in the claims, the naming of certain elements as a "first element", "second element", "third element" etc. should not be understood as a listing of elements in order of importance. Rather, such naming is only used to identify different "elements". That is, the presence of a "third element" does not require the presence of a "first element" and a "second element", for example. An electrical line as described herein can be a single conductive element, or comprise at least two separate conductive elements connected in series and / or in parallel. An electrical line can comprise a metallic and / or semiconducting material, and can be permanently conductive (i.e. not switchable). An electrical line can have a resistivity independent of the direction of the current flow through the electrical line. A semiconductor body as described herein can be made of a (doped) semiconducting material, and can be or be comprised in a semiconductor chip. A semiconductor body has an electrical connection pad and comprises at least one semiconductor element having an electrode. The pad being electrically connected to the electrode includes the pad being the electrode, and vice versa.

[0018] With reference to Figure 1 schematically shows a cross-sectional view of a power semiconductor module device 100. The power semiconductor module device 100 comprises a housing 17 and a semiconductor substrate 10. The semiconductor substrate 10 comprises a dielectric insulation layer 11, a (structured) first metallization layer 111 attached to the dielectric insulation layer 11, and a (structured) second metallization layer 112 attached to the dielectric insulation layer 11. The dielectric insulation layer 11 is arranged between the first metallization layer 111 and the second metallization layer 112.

[0019] ​​Each of the first metallization layer 111 and the second metallization layer 112 may be composed of or include one of the following materials: copper; copper alloy; aluminum; aluminum alloy; any other metal or alloy that remains solid during operation of the power semiconductor module device. The semiconductor substrate 10 may be a ceramic substrate, that is, a substrate in which the dielectric insulating layer 11 is a ceramic, such as a thin ceramic layer. The ceramic may be composed of or include one of the following materials: alumina; aluminum nitride; zirconium oxide; silicon nitride; boron nitride; or any other dielectric ceramic. For example, the dielectric insulating layer 11 may be composed of or include one of the following materials: Al2O3, AlN, SiC, BeO, or Si3N4. For example, the substrate 10 may be, for example, a direct copper bonding (DCB) substrate, a direct aluminum bonding (DAB) substrate, or an active metal bonding (AMB) substrate. Furthermore, the substrate 10 may be an insulating metal substrate (IMS). The insulating metal substrate typically includes a dielectric insulating layer 11 comprising a (filled) material, such as epoxy resin or polyimide. The material of the dielectric insulating layer 11 can, for example, be filled with ceramic particles. Such particles can include, for example, Si2O, Al2O3, AlN, or BN and can have a diameter between about 1 μm and about 50 μm. The substrate 10 can also be a conventional printed circuit board (PCB) having a non-ceramic dielectric insulating layer 11. For example, the non-ceramic dielectric insulating layer 11 can be composed of or include a curable resin.

[0020] A semiconductor substrate 10 is disposed within a housing 17. Figure 1 In the example shown, the semiconductor substrate 10 is disposed on the substrate 12 forming the ground surface of the housing 17, while the housing 17 itself comprises only sidewalls and a cover. However, this is merely an example. The housing 17 may further include a ground surface, and the semiconductor substrate 10 and (optionally) the substrate 12 may be disposed inside the housing 17. In some power semiconductor module devices 100, more than one semiconductor substrate 10 is disposed on a single substrate 12 or on the ground surface of the housing 17. In other power semiconductor module devices 100, the semiconductor substrate 10 itself may form the ground surface of the housing 17. In the latter case, the power semiconductor module device 100 generally does not include the substrate 12.

[0021] One or more semiconductor bodies 120 may be disposed on at least one semiconductor substrate 10. Each semiconductor body 120 disposed on at least one semiconductor substrate 10 may include a diode, an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), a JFET (Junction Field-Effect Transistor), a HEMT (High Electron Mobility Transistor), and / or any other suitable semiconductor element.

[0022] One or more semiconductor bodies 120 may be formed on at least one semiconductor substrate 10 to create a semiconductor device. Figure 1 In the example shown are only two semiconductor bodies 120. Figure 1 The second metallization layer 112 of the semiconductor substrate 10 is a continuous layer. Figure 1 In the example shown, the first metallization layer 111 is a structured layer. In this context, "structured layer" means that the first metallization layer 111 is not a continuous layer, but rather includes recesses between different portions of the layer. Figure 1 Such a recess is schematically shown. In this example, the first metallization layer 111 comprises three distinct portions. However, this is merely an example. Any other number of portions is possible. Different semiconductor bodies 120 can be mounted to the same or different portions of the first metallization layer 111. The different portions of the first metallization layer 111 may not have electrical connections to one or more other portions, or may be electrically connected to one or more other portions using, for example, bonding wires 13. Electrical connections 13 may also include, for example, connecting plates or conductive rails, to name just a few. One or more semiconductor bodies 120 may be electrically and mechanically connected to the semiconductor substrate 10 via a conductive connection layer 130. Such a conductive connection layer may be a solder layer, a conductive adhesive layer, or a sintered metal powder layer, such as a sintered silver powder layer.

[0023] According to other examples, the second metallization layer 112 can also be a structured layer. The second metallization layer 112 can also be omitted entirely. For example, the first metallization layer 111 can typically be a continuous layer.

[0024] Figure 1 The illustrated power semiconductor module device 100 also includes terminal elements 14. Terminal elements 14 are electrically connected to a first metallization layer 111 and provide electrical connection between the interior and exterior of the housing 17. A first end of each terminal element 14 may be electrically connected to the first metallization layer 111, while a second end 141 of each terminal element 14 protrudes from the housing 17. Terminal elements 14 may be electrically contacted from the outside at their respective second ends 141. A first portion of the terminal element 14 may extend through the interior of the housing 17 in a vertical direction y. The vertical direction y is perpendicular to the top surface of the semiconductor substrate 10, where the top surface of the semiconductor substrate 10 is the surface on which at least one semiconductor body 120 is mounted. However, Figure 1 The terminal element 14 shown is merely an example. The terminal element 14 can be implemented in any other manner and can be arranged anywhere within the housing 17. For example, one or more terminal elements 14 can be arranged close to or adjacent to the sidewalls of the housing 17. The terminal element 14 can also protrude vertically or horizontally through the sidewalls of the housing 17 instead of through the cover.

[0025] The semiconductor bodies 120 can each comprise a chip pad metallization (not specifically shown), for example, a source, drain, emitter, collector, anode, cathode or gate metallization. The chip pad metallization typically provides a contact surface for electrically connecting the semiconductor body 120. The chip pad metallization can for example electrically contact the connection layer 130, the terminal element 14 or the electrical connection 13. For example, the chip pad metallization can consist of or comprise a metal such as aluminum, copper, gold or silver. For example, the electrical connection 13 and the terminal element 14 can also consist of or comprise a metal such as copper, aluminum, gold or silver.

[0026] The power semiconductor module device 100 typically further comprises a casting compound 15. The casting compound 15 can for example consist of or comprise a silicone gel or can be a rigid molding compound. The casting compound 15 can at least partially fill the interior of the housing 17, thereby covering the components and electrical connections arranged on the semiconductor substrate 10. The terminal element 14 can be partially embedded in the casting compound 15. However, at least its second end portion 141 is not covered by the casting compound 15 and protrudes from the casting compound 15 through the housing 17 to the outside of the housing 17. The casting compound 15 is configured to protect the interior of the power semiconductor module device 100, in particular the components and electrical connections inside the housing 17, from certain environmental conditions and mechanical damage. It is also typically possible to dispense with the housing 17 and to protect the substrate 10 and any components mounted thereon only with the casting compound 15. In this case, the casting compound 15 can for example be a rigid material.

[0027] As mentioned above, two or more semiconductor bodies 120 can form a semiconductor device on at least one semiconductor substrate 10. According to one example, the two or more semiconductor bodies 120 can be arranged in a half-bridge arrangement. Any other semiconductor device comprising one, two or more than two controllable semiconductor elements each having a load path between a first load electrode (for example, a source electrode or an emitter electrode) and a second load electrode (for example, a drain electrode or a collector electrode) and a control electrode (for example, a gate electrode or a base electrode) is typically possible.

[0028] Reference is now made to Figure 2, a semiconductor device is schematically shown. The semiconductor device comprises an input stage 21 and an output stage 22. The input stage 21 comprises a first input terminal IN11, a second input terminal IN12, a first output terminal OUT11 and a second output terminal OUT12. The output stage 22 comprises a third input terminal IN21, a fourth input terminal IN22, a third output terminal OUT21 and a fourth output terminal OUT22. For example, the input stage 21 can be configured to perform an AC-DC conversion (converting an AC voltage provided at its input terminals IN11, IN12 to a DC voltage VI provided at its output terminals OUT11, OUT12) or a DC-DC conversion (converting a DC voltage provided at its input terminals IN11, IN12 to another DC voltage VI provided at its output terminals OUT11, OUT12). The output stage 22 can be configured to perform, for example, a DC-DC conversion (converting a DC voltage provided at its input terminals IN21, IN22 to another DC voltage provided at its output terminals OUT21, OUT22) or a DC-AC conversion (converting a DC voltage provided at its input terminals IN21, IN22 to an AC voltage provided at its output terminals OUT21, OUT22). According to another example, the input stage 21 can comprise a voltage source (e.g. a battery or a large capacitor) which provides a first voltage VI at its output terminals OUT11, OUT12. If the input stage 21 only comprises a voltage source, the input terminals IN11, IN12 can be omitted. Thus, the input terminals IN11, IN12 of the input stage 21 are indicated with dashed lines.

[0029] a DC link capacitor C DC_link may be coupled between the common node between the first output terminal OUT11 and the third input terminal IN21 and the common node between the second output terminal OUT12 and the fourth input terminal IN22. The DC link capacitor C DC_link is configured to provide a stabilized DC voltage at the input terminals IN21, IN22 of the output stage 22. The DC link capacitor C DC_link reduces the ripple and limits the fluctuations of the output voltage VI provided at the outputs OUT11, OUT12 of the input stage 21.

[0030] The output stage 22 can comprise at least one controllable semiconductor element. As mentioned above, each of the at least one controllable semiconductor element can be provided as a separate semiconductor body 120. The semiconductor body 120 may, for example, be arranged in the housing 17. For example, the DC link capacitor C DC_link may also be arranged in the same housing 17 as the semiconductor body 120. Different semiconductor bodies 120 of the device can be arranged on one or two semiconductor substrates 10 which are arranged within the same housing 17.

[0031] In many applications, it can be required to quickly switch at least one controllable semiconductor element of the output stage 22. If a high-performance power semiconductor module device is required, the DC link capacitor C DC_link The stray inductance generated between the at least one controllable semiconductor element of the output stage 22 can be high and can negatively influence the switching speed of the controllable semiconductor element. This can in turn negatively influence the overall losses of the power semiconductor module device. High stray inductance can further lead to high voltage overshoots at the moment of turning off the at least one controllable semiconductor element. This requires the semiconductor body 120 of the semiconductor device to have a sufficiently high electrical strength.

[0032] To reduce the DC link capacitor C DC_link stray inductance between the at least one controllable semiconductor element of the output stage 22, the device can comprise an additional capacitor C s For example, such an additional capacitor C s may also be referred to as a snubber capacitor. The additional capacitor C s may be coupled in parallel to the DC link capacitor C DC_link (not specifically shown in Figure 2 ). The additional capacitor C s and the at least one controllable semiconductor element can be arranged close to each other (next to each other) within the housing 17. That is, the distance between the additional capacitor C s and the at least one controllable semiconductor element of the output stage 22 can be as short as possible. According to another example, the additional capacitor C s may be arranged outside the housing 17, for example on an external printed circuit board. A low-inductance connection element can be used to electrically couple the additional capacitor C s to elements arranged inside the housing 17.

[0033] An exemplary electrical connection between the additional capacitor C s and the at least one controllable semiconductor element of the output stage 22 is schematically shown in Figure 3 . In particular, Figure 3 an exemplary electrical connection between the additional capacitor C sA strip conductor of controllable semiconductor elements (e.g. transistors) electrically coupled to the output stage 22. The strip conductor can comprise a first conductive layer 31 and a second conductive layer 32. Each of the first conductive layer 31 and the second conductive layer 32 can have a width w1 in a first direction, a length l1 in a second direction, and a thickness d1 in a third direction, the first, second, and third directions being perpendicular to each other, wherein the thickness d1 is much smaller than each of the width w1 and the length l1 (e.g. d1 < 0.5*w1, or d1 < 0.5*l1). The first conductive layer 31 is arranged above and parallel to the second conductive layer 32. The first conductive layer 31 can be arranged at a distance d2 above the second conductive layer 32 along the third direction. A dielectric insulating layer (not specifically shown in Figure 3 ) can be arranged between the first conductive layer 31 and the second conductive layer 32 to dielectrically isolate the first conductive layer 31 from the second conductive layer 32. The controllable semiconductor elements (e.g. transistors) can be arranged at one end of the first conductive layer 31 and the second conductive layer 32, and the additional capacitor C s may be arranged at the opposite end of the first conductive layer 31 and the second conductive layer 32 along the second direction as indicated by the dashed arrow in Figure 3 . The current can flow from the controllable semiconductor elements (e.g. transistors) through the first conductive layer 31 to the additional capacitor C s , and back from the additional capacitor C s to the controllable semiconductor elements through the second conductive layer 32. The direction of the current flow is indicated by the solid arrow in Figure 3 .

[0034] By reducing the length l1 of the first conductive layer 31 and the second conductive layer 32, the distance between the controllable semiconductor elements and the additional capacitor C s is reduced, and thus the stray inductance can also be reduced. However, reducing the length l1 of the first conductive layer 31 and the second conductive layer 32 increases the overall cost of the power semiconductor module device. The width w1 can be chosen to be relatively large in order to reduce the ohmic resistance of the first conductive layer 31 and the second conductive layer 32. For the stray inductance L stray of this device, the following dependency applies:

[0035]

[0036] In this context, the term "proximity of the controllable semiconductor elements with respect to the additional capacitor C s and the output stage 22" refers to electrical proximity. That is, it refers to the connection that causes the stray inductance L stray .

[0037] In many power semiconductor module devices, it is difficult or even impossible to place the additional capacitor C scontrollable semiconductor elements arranged in close proximity to the output stage, wherein, as with Figure 3 The (short) electrical connection (e.g. a strip conductor) described is arranged between the additional capacitor C s and the controllable semiconductor elements of the output stage 22.

[0038] Reference is now made to Figure 4 schematically illustrating a circuit arrangement with reduced turn-off overvoltage, reduced oscillation amplitude during switching operation, and reduced switching losses. The input stage is not specifically shown in Figure 4 . The input stage can comprise a DC-DC converter, an AC-DC converter, a battery, or any other kind of voltage source, as described above.

[0039] In the example shown in Figure 4 , the output stage 22 comprises a half-bridge. However, this is merely an example. The output stage 22 can be implemented in any other suitable way. According to one example, the output stage 22 comprises more than one half-bridge. For example, Figure 4 The half-bridge in the example shown comprises a second controllable semiconductor element T2 and a third controllable semiconductor element T3, such as an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), a JFET (Junction Field-Effect Transistor), or a HEMT (High Electron Mobility Transistor), and two diode elements D2, D3.

[0040] The half-bridge is configured to convert a DC voltage V1 provided at the output terminals OUT11, OUT12 of the input stage into an AC voltage provided at the output node OUT of the output stage 22. The AC voltage can be provided to a load (not shown) coupled to the output node OUT of the output stage 22, for example. The half-bridge is coupled between a third input terminal IN21 configured to be operably coupled to a first electrical potential and a fourth input terminal IN22 configured to be operably coupled to a second electrical potential. The first electrical potential can be a positive electrical potential, and the second electrical potential can be a negative electrical potential, to supply the DC voltage via the third input terminal IN21 and the fourth input terminal IN22.

[0041] The half-bridge comprises one high-side switch T2 (also referred to as second controllable semiconductor element, second transistor, or second switch) and one low-side switch T3 (also referred to as third controllable semiconductor element, third transistor, or third switch) coupled in series to each other and between the third input terminal IN21 and the fourth input terminal IN22. The half-bridge can be configured to drive a load (not specifically shown) at its output node OUT. The load may, for example, be an inductive load. The output node OUT is electrically connected to a common node between the high-side switch T2 and the low-side switch T3.

[0042] In Figure 4 The circuit arrangement of Fig. 1 comprises a half-bridge. Each controllable semiconductor element T2, T3 of the half-bridge is implemented as a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). Each of the controllable semiconductor elements T2, T3 can comprise an external freewheeling diode element D2, D3 coupled in parallel to the respective controllable semiconductor element T2, T3. According to another example, each of the controllable semiconductor elements T2, T3 of the output stage 22 comprises two or more individual switching elements (not specifically shown) electrically coupled in parallel to each other.

[0043] Each of the second controllable semiconductor element T2 and the third controllable semiconductor element T3 comprises a control electrode G2, G3 and a controllable load path between a first load electrode (e.g. source electrode) S2, S3 and a second load electrode (e.g. drain electrode) D2, D3. The load paths of the second controllable semiconductor element T2 and the third controllable semiconductor element T3 are coupled in series and between the third input terminal IN21 and the fourth input terminal IN22.

[0044] Figure 4 The illustrated arrangement further comprises a first inductive element LI coupled between the first output terminal OUT11 and the third input terminal IN21. The DC link capacitor C DC_link is coupled in parallel to the voltage source 23 between the first output terminal OUT11 and the second output terminal OUT12. An additional capacitor C s and the first controllable semiconductor element T1 is coupled in series and between the common node between the first inductive element LI and the third input terminal IN21 and the common node between the second output terminal OUT12 and the fourth input terminal IN22. The first controllable semiconductor element T1 comprises a control electrode G1 and a controllable load path between a first load electrode (e.g. source electrode) S1 and a second load electrode (e.g. drain electrode) D1. A first diode element D1 is coupled in parallel to the first controllable semiconductor element T1 and between the common node between the first inductive element LI and the third input terminal IN21 and the additional capacitor C s . The first diode element D1 comprises an anode terminal A1 and a cathode terminal C1. The anode terminal A1 of the first diode element D1 is coupled to the common node between the first inductive element LI and the third input terminal IN21. The cathode terminal C1 of the first diode element D1 is coupled to the additional capacitor C s .

[0045] In Figure 4In the illustrated device, the stray inductance is relatively high when one of the controllable semiconductor elements T2 and T3 of the output stage 22 is turned on, while the first controllable semiconductor element T1 is turned off. This is because the redirection path in this first case passes through the first inductor element L1. The stray inductance is relatively low when one of the controllable semiconductor elements T2 and T3 of the output stage 22 is turned off, while the first controllable semiconductor element T1 is turned on (T1 is in a conductive state). This is because the redirection path in the latter case passes through the additional capacitor C. s In other words, the effective stray inductance changes depending on whether the first controllable semiconductor element is on or off. This allows for rapid switching of the controllable semiconductor elements T2 and T3 of output stage 22. The circuit does not operate resonantly or quasi-resonantly. Furthermore, the circuit does not require any additional capacitors coupled in parallel with the controllable semiconductor elements T2 and T3 of output stage 22.

[0046] Additional capacitor C s The controllable semiconductor elements T2 and T3 are coupled as close as possible to and with the lowest possible inductance to the output stage 22. In this context, "close to" and "low inductance" means including an additional capacitor C. s The parasitic inductance in the loop of the first controllable semiconductor element T1, the second controllable semiconductor element T2, and the third controllable semiconductor element T3 is lower than the inductance of the first inductor element L1. According to one example, the parasitic inductance L... par For L par <0.5*L1. According to another example, the parasitic inductance L par For L par <0.1*L1.

[0047] exist Figure 4 In the example shown, the first controllable semiconductor element T1 and the first diode element D1 allow the additional capacitor C to operate even when the first controllable semiconductor element T1 is not conducting (in a blocking state). s Charging is initiated. If the first controllable semiconductor element T1 is not conductive, the current I... s The current can flow through the first diode element D1 to the additional capacitor C. s On the other hand, the first diode element D1 prevents current from flowing in the opposite direction. That is, when the first controllable semiconductor element T1 is in the blocking state, the additional capacitor C... s It can be charged, and at the same time prevents current from flowing out of the additional capacitor C. s Outflow. Therefore, the additional capacitor C... s It remains charged until the first controllable element T1 is turned on (in a conductive state).

[0048] If including C s The parasitic inductance L in the loops T1, T2, and T3par The minimum required capacity of the additional capacitor C s can be calculated as follows:

[0049]

[0050]

[0051] where L1 is the inductance of the first inductive element L1, I Last is the load current provided to a load coupled to the output node OUT of the output stage 22, C s is the capacitance of the additional capacitor C s , V max is the maximum allowed overvoltage which the device can withstand without permanent damage, and V DC is the voltage across the DC-link capacitor C DC_link .

[0052] According to one example, the following conditions apply: V DC = 600 V, V max = 750 V, I Last = 300 A, L1 = 40 nH. In this example, the capacitance of the additional capacitor C s can be calculated as:

[0053]

[0054] To prevent the energy stored in the first inductive element L1 from being converted into heat before the controllable semiconductor elements T2, T3 of the output stage 22 are turned off, the voltage rise caused by the charging of the additional capacitor C s during turn-off can be as low as possible. This requires that the period duration T of the oscillation circuit formed by the first inductive element L1 and the additional capacitor C s is significantly larger than the switching time t off of the controllable semiconductor elements T2, T3 of the output stage 22. For example, the period duration T of the oscillation circuit can be at least 5 times or at least 7 times larger than the switching time t off of the controllable semiconductor elements T2, T3 of the output stage 22. For example, if the voltage rise is limited to 30 V = 0.05 * 600 V in case of a turn-off time t off of 50 ns, the following applies:

[0055]

[0056] For 1 / ω » t off , which can be simplified by a Taylor series expansion:

[0057]

[0058] This makes it possible to have an additional capacitor C s The capacitance of which is calculated as:

[0059]

[0060] This makes the period duration T or the eigenfrequency f, respectively, to be:

[0061]

[0062]

[0063] For a practical interpretation, a factor of approximately 10 to 50 arises between the period duration T and the turn-off time t off . A smaller factor can lead to an increased switching loss of the first controllable semiconductor element T1, a larger factor can lead to a larger and more expensive additional capacitor C s .

[0064] The blocking effect of the first diode element D1 and the first controllable semiconductor element T1 leads to a significantly reduced buffer effect of the additional capacitor C s when switching on at least one controllable semiconductor element T2, T3 of the output stage 22. Thus, when switching on the controllable semiconductor elements T2, T3 of the output stage relatively quickly, a significant voltage arises on the first inductive element L1, which reduces the switching loss on switching on compared to other devices. The voltage arising on the first inductive element L1 causes the first inductive element L1 to be charged. Once the switching-on operation of at least one controllable element T2 or T3 of the output stage 22 is complete, the energy stored in the first inductive element L1 is diverted to the additional capacitor C s via the first diode element D1. Without the blocking capability of the first diode element D1 and the first controllable semiconductor element T1, this energy would oscillate between the first inductive element L1 and the additional capacitor C s . This would lead to a damping loss in the device. In the described device, however, the first diode element D1 interrupts this oscillation after charging the additional capacitor C s and the energy will be stored in the additional capacitor C s . This is shown exemplarily in Figure 5 , Figure 5 several voltages and currents in relation to one another over time in the device of Figure 4 are shown.

[0065] Figure 5 Only the general course of the different voltages and currents is intended to be illustrated. Therefore, no specific values are specified in the figures. In Figure 5 , it is indicated at which point in time the additional capacitor C sCharging. This occurs, for example, at the transistor voltage V of the second controllable semiconductor element T2. DS This occurs shortly after the drop (T2 turns on). The transistor current I through the second controllable semiconductor element T2... D2 It rises and oscillates for a short period before stabilizing at a constant level. This is achieved through an additional capacitor C. s capacitor current I s The rise, while the additional capacitor C s It is being charged. This can be seen from the second controllable semiconductor element T2, where the additional capacitor C... s It does not function during conduction.

[0066] When the current I D2 When the current flows through the corresponding controllable semiconductor element T2 or T3 and is subsequently turned off, if the system does not include an additional capacitor C s This will lead to a large number of shutdown overvoltages. This is Figure 6 The diagram illustrates that, Figure 6 This shows the situation without an additional capacitor C. s The transistor voltage V after the corresponding controllable semiconductor element T2 or T3 is turned off in the device. DS and transistor current I D It can be seen that the current I flowing through the controllable semiconductor element T2 or T3 D Initially, it is at a certain (high) value. When the controllable semiconductor elements T2 and T3 are turned off, the transistor current I... D The voltage V across the controllable semiconductor elements T2 and T3 oscillates for a certain period of time before reaching equilibrium at a lower value (e.g., zero). DS It increases from an initial low value. Transistor voltage V DS The voltage rises sharply after the controllable semiconductor elements T2 and T3 are turned off, but before it balances out when the controllable semiconductor elements T2 and T3 are fully turned off. This overvoltage can cause significant losses in the corresponding controllable semiconductor elements T2 and T3. This increased loss essentially corresponds to the energy stored in the first inductor element L1 before the controllable semiconductor elements T2 and T3 are turned off. Most of this energy is converted into heat in the corresponding semiconductor body. The remaining portion of the energy remains in the system and oscillates between the stray inductance and the parasitic capacitance of the corresponding controllable semiconductor element T2 or T3, and is converted into heat due to its ohmic portion.

[0067] exist Figure 4 In the device, this problem is solved by allowing energy pre-stored in the first inductor L1 to be diverted to the additional capacitor C. s This needs to be addressed. Once the transistor voltage V is turned off when the controllable semiconductor elements T2 and T3 are switched off... DS Exceeding the additional capacitor Cs The first diode element D1 conducts current. The current then flows from the first inductive element L1 to the additional capacitor C s When the capacitor voltage V s reaches its maximum value (the capacitor current I s = 0), the first diode element D1 blocks, the additional capacitor C s retains the energy. This is schematically shown in Figure 7 .

[0068] The overvoltage occurring when the controllable semiconductor element T2 or T3 is turned off is reduced, which makes the parasitic transistor capacitance (the parasitic capacitance of the respective controllable semiconductor element T2, T3) at the moment when the channel of the controllable semiconductor element T2, T3 is closed (the controllable semiconductor element T2, T3 is completely blocked) significantly smaller than in the case of a device without the additional capacitor C s This makes the oscillation amplitude significantly smaller than in the device without the additional capacitor C s .

[0069] In the above example, the first controllable semiconductor element T1 has been assumed to be non-conducting (blocked). With each switching operation, the oscillation between the first inductive element L1 and the additional capacitor C s has been interrupted by the first diode element D1. The oscillation energy is stored in the additional capacitor C s and can subsequently be used in different ways. One exemplary way of using the energy stored in the additional capacitor C s will be described in the following.

[0070] According to a first example, during the on operation of the controllable semiconductor element T2 or T3 of the output stage, the first inductive element L1 is charged. The energy stored in the first inductive element is then stored in the additional capacitor C s before the controllable semiconductor element T2 or T3 is turned off again. The higher the quality of the oscillation circuit, the more energy from the first inductive element L1 is stored in the additional capacitor C s .

[0071] According to one example, before the controllable semiconductor element T2 or T3 is turned off, the first controllable semiconductor element T1 is turned on (changed from the blocked state to the conducting state). When the first controllable semiconductor element T1 is turned on, the additional capacitor C s is discharged. The resulting discharge current from the additional capacitor C s is superimposed with the current of the first inductive element L1. The resulting course of the current and voltage corresponds to the course of the current and voltage of the oscillation circuit. The respective frequency and period duration T can be calculated as:

[0072]

[0073]

[0074] If the quality of the oscillation circuit is high, then the additional capacitor C s conducts a current I s which reaches its maximum after a quarter of an oscillation period. The more energy is stored in the additional capacitor C s , the higher the current I s which can be obtained in the additional capacitor C s . In a real system in which damping losses occur, the current in the additional capacitor C s may not be able to divert the current I DC_link from the first inductive element L1 completely. When the current I s through the additional capacitor C s reaches its maximum, the voltage V s over the additional capacitor C s corresponds to the first voltage V1. This is shown schematically in Figure 8 . In Figure 9 , the instant at which the first controllable semiconductor element T1 is switched on is indicated. Next, the additional capacitor C s discharges. As soon as the additional capacitor C s discharges, the controllable semiconductor element T2 or T3 which was previously in the conducting state is switched off. The transistor current I D2 tends towards zero. The current I s through the additional capacitor C s rises until the first controllable semiconductor element T1 is switched off again. The voltage V s over the additional capacitor C s drops while the first controllable semiconductor element T1 is conducting. After the respective controllable semiconductor element T2 or T3 has been switched off, the voltage V DS over the controllable semiconductor element T2 or T3 rises.

[0075] After the controllable semiconductor element T2 or T3 has been switched off, the energy remaining in the first inductive element L1 is discharged to the additional capacitor C s . Since the first controllable semiconductor element T1 is in the conducting state only over half an oscillation period and is switched off again at the zero crossing of the current I s through the additional capacitor C s , the average losses of the first controllable semiconductor element T1 are relatively low, thus allowing the respective semiconductor body to be designed smaller.

[0076] To keep the period duration T of the oscillation constant and further to avoid an extended tracking within the control circuit of the timing of the switching signals of the first controllable semiconductor element T1 and the controllable semiconductor elements T2 and T3 switching the output stage, an additional capacitor C s implemented as a linear capacitor, i.e. independent of voltage and temperature. Other switching operations result in a clearing mode during which the voltage V s on the additional capacitor C s is discharged. This is schematically shown in Figure 10 .

[0077] According to another example, the energy stored in the first inductive element L1 when the controllable semiconductor element T2 or T3 of the output stage is switched off can be stored in the additional capacitor C s . This allows storing the energy of several switching operations. In comparison to the above example, the current I DC_link through the first inductive element L1 can be completely diverted. This alternative can provide benefits for devices of the oscillation circuit which have a relatively low quality, e.g. due to design reasons. The voltages and currents generated in a device operating according to the alternative thereof are schematically shown in Figure 10 . In ​ , the moments of storing energy in the additional capacitor C s are indicated. This diagram shows the voltage V s on the additional capacitor C s , the current I s through the additional capacitor C s and the voltage V DS on the respective controllable semiconductor element T2, T3 of the output stage 22. In other words, in this example, the first controllable semiconductor element T1 remains in a blocking state (non-conducting state) for at least two switching periods of the output stage 22, wherein each switching period comprises switching on and off at least one controllable semiconductor element T2 or T3 of the at least one controllable semiconductor element of the output stage 22.

[0078] According to another example, the energy of the switching off operation can be stored in the additional capacitor C s and the additional capacitor C s may be discharged just before the switching off operation of the controllable semiconductor element T2 or T3 of the output stage 22 of the subsequent. This alternative can be advantageous if the stray inductance of the device is already relatively small or if the switching on operation is relatively slow. In this case, only very little energy can be stored in the additional capacitor C sThe energy of only a single turn-off operation is stored. The additional capacitor C s has a limiting voltage effect. Just before the subsequent turn-off operation, the additional capacitor C s is discharged again.

[0079] This last alternative provides very low losses at turn-on and reduced losses at turn-off. The recovery losses are average, while the decay losses are very low. The overvoltage is low and an additional capacitor C s of average size is required. The stray inductance can be slightly increased. This device can be used in any desired power range.

[0080] The additional capacitor C s and the first controllable semiconductor element T1 can be implemented, for example, as an output stage 22 within the same semiconductor module (the same housing 17). In other words, i.e., the output stage 22 can comprise the additional capacitor C s and the first controllable semiconductor element T1. However, this is merely an example. The additional capacitor C s and the first controllable semiconductor element T1 can also be implemented as an external capacitor and an external switch arranged outside the housing 17 of the output stage 22.

Claims

1. A semiconductor module arrangement comprising: an input stage (21) comprising a first output terminal (OUT11) and a second output terminal (OUT12), wherein a first inductive element (LI) is coupled to the first output terminal (OUT11); an output stage (22) comprising at least one controllable semiconductor element (T2, T3), a third input terminal (IN21) coupled to the first inductive element (LI), a fourth input terminal (IN22) coupled to the second output terminal (OUT12), a third output terminal (OUT21) and a fourth output terminal (OUT22), the first inductive element (LI) being coupled between the first output terminal (OUT11) and the third input terminal (IN21); The first controllable semiconductor element (T1) and the first capacitor element (C) s The first controllable semiconductor element (T1) and the first capacitor element (C) s They are connected in series and between a common node between the first inductor (L1) and the third input terminal (IN21) and a common node between the second output terminal (OUT12) and the fourth input terminal (IN22); and a first diode element (D1) coupled in parallel to the first controllable semiconductor element (T1), wherein a cathode terminal (C1) of the first diode element (D1) is coupled to the first capacitance element (C s ) and an anode terminal (A1) of the first diode element (D1) is coupled to a common node between the first inductance element (L1) and the third input terminal (IN21), wherein the first inductive element (L1) and the first capacitive element (C s ) form an oscillation circuit; an oscillation occurring in the oscillation circuit has a first period duration; a first switching time is required to switch a controllable semiconductor element (T2, T3) of the at least one controllable semiconductor element (T2, T3) of the output stage (22) from a conductive state to a non-conductive state; and the first period duration is greater than the first switching time.

2. The semiconductor module device according to claim 1, wherein, the output stage (22) comprises at least two controllable semiconductor elements (T2, T3) arranged in at least one half-bridge configuration.

3. The semiconductor module device according to claim 1, wherein, the first period duration is between about 10 times and about 50 times the first switching time.

4. The semiconductor module arrangement according to any one of claims 1 to 3, wherein, the output stage (22) is configured to convert a DC voltage provided at its input terminals (IN21, IN22) to another DC voltage provided at its output terminals (OUT21, OUT22).

5. The semiconductor module arrangement according to any one of claims 1 to 3, wherein, the output stage (22) is configured to convert a DC voltage provided at its input terminals (IN21, IN22) to an AC voltage provided at its output terminals (OUT21, OUT22).

6. The semiconductor module apparatus of any one of claims 1 to 3, further comprising: a DC link capacitor (C DC_link ) coupled between the first output terminal (OUT11) and the second output terminal (OUT12) of the input stage (21).

7. The semiconductor module arrangement according to any one of claims 1 to 3, wherein, each of the controllable semiconductor elements (T1, T2, T3) comprises at least one of an IGBT, a MOSFET, a JFET or a HEMT.

8. A method for operating a semiconductor module arrangement according to any one of claims 1 to 7, the method comprising: conducting at least one of the at least one controllable semiconductor element (T2) of the output stage (22), wherein the first inductive element (LI) is charged during the conducting operation of the at least one controllable semiconductor element (T2), and wherein, once the conducting operation is completed, the energy stored in the first inductive element (LI) during the conducting operation is diverted to the first capacitive element (C s ) via the first diode element (D1) and the second diode element (D2); and switching off at least one controllable semiconductor element (T2) of the at least one controllable semiconductor element of the output stage (22).

9. The method of claim 8, wherein, at least during the turn-on operation of the at least one controllable semiconductor element (T2), the first controllable semiconductor element (T1) is in a blocking state.

10. The method according to claim 9, further comprising: After turning on at least one of the at least one controllable semiconductor element (T2) of the output stage (22) and before turning off again at least one of the at least one controllable semiconductor element (T2) of the output stage (22), the first controllable semiconductor element (T1) is turned on, thereby allowing discharging of the first capacitive element (C s ).

11. The method of claim 10, further comprising: switching off the first controllable semiconductor element (T1).

12. The method of claim 11, wherein, Once the first capacitor element (C s ) is completely discharged, or after half an oscillation period of the oscillation circuit formed by the first inductor element (L1) and the first capacitor element (C s ), or at the moment of zero crossing of the current (I s ) flowing through the first capacitor element (C s ), the first controllable semiconductor element (T1) is switched off again.

13. The method of claim 9, wherein, the first controllable semiconductor element (T1) remains in a blocking state for at least two switching cycles of the output stage (22), wherein each switching cycle comprises turning on and off at least one controllable semiconductor element (T2, T3) of the at least one controllable semiconductor element of the output stage (22).

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