Semiconductor device

Abstract

A semiconductor device is disclosed. The semiconductor device includes: an interlayer insulating layer provided on a substrate; a plurality of middle interconnects provided in the interlayer insulating layer; pads provided on the interlayer insulating layer; upper interconnects provided on the interlayer insulating layer; a protective insulating layer covering the edges of the pads, the upper interconnects, and the horizontal gaps between the pads and the upper interconnects, the protective insulating layer having openings in the pads; and bumps provided on the pads, the bumps extending on the protective insulating layer and overlapping the upper interconnects in a top-down view. At least one of the middle interconnects among the middle interconnects in the plurality that are closest to the pads in the vertical direction has a first vertical thickness, the pads have a second vertical thickness that is two to 100 times the first vertical thickness, the length of the gap between the pads and the upper interconnects is 1 μm or greater, and the upper surface of the protective insulating layer is flat.

Description

[0001] This patent application claims the priority and benefits of Korean Patent Application No. 10-2019-0097284, filed on Aug. 9, 2019, with the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Devices and methods consistent with example embodiments relate to semiconductor devices having a thick metal layer and bumps and methods of forming such semiconductor devices. Background Art

[0003] Research is being conducted on semiconductor devices employing bumps formed on electrode pads (also referred to as pads). The shape of the bumps can be determined by the structure of a protective insulating layer adjacent to the electrode pads and the bumps. Steps in the bumps cause problems such as increased contact resistance and bonding defects. Summary of the Invention

[0004] Example embodiments of the inventive concept are intended to provide a semiconductor device having improved current drivability, a high signal transmission rate, and high physical / chemical reliability and a method of forming the same.

[0005] According to some embodiments, a semiconductor device includes: an interlayer insulating layer disposed on a substrate; a plurality of middle interconnects disposed in the interlayer insulating layer; a pad disposed on the interlayer insulating layer; an upper interconnect disposed on the interlayer insulating layer; a protective insulating layer covering an edge of the pad, the upper interconnect, and a horizontal gap between the pad and the upper interconnect, the protective insulating layer having an opening on the pad; and a bump disposed on the pad, the bump extending on the protective insulating layer and overlapping the upper interconnect in a top-down view. At least one of the middle interconnects among the middle interconnects closest to the pad in the vertical direction has a first vertical thickness, the pad has a second vertical thickness that is two to 100 times the first vertical thickness, a length of the gap between the pad and the upper interconnect is 1 μm or greater, and an upper surface of the protective insulating layer is flat.

[0006] According to some embodiments, a semiconductor device includes: an interlayer insulating layer disposed on a substrate; a plurality of active / passive elements disposed on the substrate; a plurality of middle interconnects disposed in the interlayer insulating layer; pads disposed on the interlayer insulating layer; upper interconnects disposed on the interlayer insulating layer; a protective insulating layer covering edges of the pads, the upper interconnects, and a gap between the pads and the upper interconnects, the protective insulating layer having an opening on the pads; bumps disposed on the pads, the bumps extending on the protective insulating layer and vertically overlapping with the upper interconnects; and vias passing through the substrate and connected to the plurality of middle interconnects or the pads. One of the middle interconnects among the middle interconnects closest to the pads in the vertical direction has a first vertical thickness, the pads have a second vertical thickness that is two to 100 times the first vertical thickness, the gap between the pads and the upper interconnects is 1 μm or greater, and an upper surface of the protective insulating layer is flat.

[0007] According to some embodiments, a semiconductor device includes: an interlayer insulating layer disposed on a substrate; a plurality of middle interconnects disposed in the interlayer insulating layer; pads disposed on the interlayer insulating layer; upper interconnects disposed on the interlayer insulating layer; a protective insulating layer covering edges of the pads, the upper interconnects, and a gap between the pads and the upper interconnects, the protective insulating layer having an opening on the pads; and bumps disposed on the pads, the bumps extending on the protective insulating layer and vertically overlapping with the upper interconnects. One of the middle interconnects among the middle interconnects closest to the pads in the vertical direction has a first vertical thickness, the pads have a second vertical thickness that is two to 100 times the first vertical thickness, and a horizontal length of the gap between the pads and the upper interconnects is greater than or equal to the second vertical thickness, and an upper surface of the protective insulating layer is flat. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figures 1 to 3 are cross-sectional views each showing a part of a semiconductor device according to an embodiment of the inventive concept.

[0009] Figure 4 shows Figures 1 to 3 a magnified view of a part of

[0010] Figures 5 to 8 are cross-sectional views each showing a part of a semiconductor device according to an embodiment of the inventive concept.

[0011] Figure 9 is a cross-sectional view showing a semiconductor device according to an embodiment of the inventive concept.

[0012] Figure 10 is Figure 9 a magnified view of a part of

[0013] Figure 11 is Figure 9 an enlarged view of some components of

[0014] Figures 12 to 22 is a cross-sectional view for describing a method of forming a semiconductor device according to an embodiment of the inventive concept. Detailed Description

[0015] Figures 1 to 3 are cross-sectional views each showing a part of a semiconductor device according to an embodiment of the inventive concept. Figure 4 is a view showing Figures 1 to 3 an enlarged view of a part of. A semiconductor device according to an embodiment of the inventive concept may include a thick top metal (TTM). A semiconductor device as described herein may include a semiconductor chip or die including connection terminals for external devices, a semiconductor device may include a semiconductor package, wherein the semiconductor package includes one or more semiconductor chips disposed on a package substrate and includes connection terminals for external devices, or a semiconductor device may include a package-on-package device.

[0016] Referring to Figure 1 , a semiconductor device according to an embodiment of the inventive concept may include a substrate 21, a plurality of interlayer insulating layers 31, 32, 33, 34, and 35, a plurality of middle interconnects 41 and 42, a plurality of contact plugs 52, pads 61, a plurality of upper interconnects 62, a plurality of protective insulating layers 71 and 72, an opening 73W, and a first bump 89. The plurality of interlayer insulating layers 31, 32, 33, 34, and 35 may include a first interlayer insulating layer 31, a second interlayer insulating layer 32, a third interlayer insulating layer 33, a fourth interlayer insulating layer 34, and a fifth interlayer insulating layer 35. Two or more adjacent ones of the plurality of interlayer insulating layers 31, 32, 33, 34, and 35 may be described together as an interlayer insulating layer. The plurality of middle interconnects 41 and 42 may include a plurality of first middle interconnects 41 and a plurality of second middle interconnects 42. The plurality of protective insulating layers 71 and 72 may be described together as a protective insulating layer and may include a first protective insulating layer 71 and a second protective insulating layer 72. The first bump 89 may include a pillar structure 85 and solder 87. The pillar structure 85 may have a generally flat top surface and a bottom surface and substantially vertical side surfaces. The solder 87 may have a generally flat bottom surface but has a circular and curved top surface and side surfaces. The pillar structure 85 may include a barrier layer 81, a seed layer 82, and a pillar 83. The pillar structure 85 may include a first portion 85A and a second portion 85B.

[0017] It will be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. For example, as a naming convention, unless the context otherwise indicates, these terms are only used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, without departing from the teachings of the present invention, the first element, first component, first region, first layer, or first part discussed in one part of the specification may be named the second element, second component, second region, second layer, or second part in another part of the specification or in the claims. Additionally, in some cases, even if the terms "first", "second", etc. are not used in the specification to describe, they may still be referred to as "first" or "second" in the claims to distinguish the claimed elements that are different from each other.

[0018] In addition, the various pads of the device described herein may be conductive terminals connected to the internal wiring of the device and may transfer signals and / or power voltages between the internal wiring and / or internal circuit of the device and an external source. For example, the chip pads of a semiconductor chip may be electrically connected to the integrated circuit of the semiconductor chip and the device to which the semiconductor chip is connected, and may transfer power voltages and / or signals between the integrated circuit of the semiconductor chip and the device to which the semiconductor chip is connected. The various pads may be provided on or near the outer surface of the device and generally may have a flat surface area (generally larger than the corresponding surface area of the internal wiring to which they are connected) to facilitate connection to other terminals such as bumps or solder balls and / or external wiring.

[0019] The first interlayer insulating layer 31 to the fifth interlayer insulating layer 35 may be sequentially stacked on the substrate 21. Each of the plurality of middle interconnects 41 and 42 may be provided in the first interlayer insulating layer 31 to the fifth interlayer insulating layer 35 on the substrate 21. Compared with the plurality of first middle interconnects 41, the plurality of second middle interconnects 42 may be provided relatively farther from the upper surface of the substrate 21. For example, the plurality of first middle interconnects 41 may be provided in the first interlayer insulating layer 31. The plurality of second middle interconnects 42 may be provided in the second interlayer insulating layer 32. The plurality of second middle interconnects 42 may exhibit a first thickness d1.

[0020] Multiple contact plugs 52 may extend into the multiple interlayer insulating layers 31, 32, 33, 34, and 35. In an embodiment, each of the multiple contact plugs 52 may pass through the fifth interlayer insulating layer 35, the fourth interlayer insulating layer 34, and the third interlayer insulating layer 33, and may contact a corresponding one of the multiple second middle interconnects 42. It will be understood that when an element is referred to as being "connected" or "coupled" to another element or "on" another element, the element may be directly connected or directly coupled to the other element or on the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, or "contacting" another element or "in contact" with another element, there are no intervening elements. Other words used to describe the relationship between elements should be interpreted in a similar manner (e.g., "between" versus "directly between", "adjacent" versus "directly adjacent", etc.). Unless the context otherwise indicates, the term "contact" as used herein refers to direct connection (i.e., touching).

[0021] The pad 61 and the multiple upper interconnects 62 may be disposed at a level (e.g., a higher vertical level) higher than the level of the multiple middle interconnects 41 and 42 relative to the top surface of the substrate 21. In an embodiment, the pad 61 and the multiple upper interconnects 62 may be directly disposed on the fifth interlayer insulating layer 35. The pad 61 and the multiple upper interconnects 62 may be physically and electrically connected to the multiple contact plugs 52. For example, each of the multiple upper interconnects 62 and the pad 61 may contact the upper surface of at least a corresponding one of the multiple contact plugs 52.

[0022] The multiple middle interconnects 41 and 42 may be disposed between the pad 61 and the substrate 21. The pad 61 and the multiple upper interconnects 62 may be physically and electrically connected to the multiple second middle interconnects 42 via the multiple contact plugs 52. The multiple second middle interconnects 42 may be closer to the pad 61 in the vertical direction than the multiple first middle interconnects 41, and may be the middle interconnects among the middle interconnects 41 and 42 that are closest to the pad 61 in the vertical direction (e.g., closest to the pad 61 in the vertical direction). In an embodiment, a selected one of the multiple second middle interconnects 42 may be the closest to the pad 61 among the multiple middle interconnects 41 and 42. In addition, a selected one of the multiple second middle interconnects 42 may be electrically connected to the pad 61, for example, via a contact plug 52. Each of the multiple middle interconnects 41 and 42 may have a lateral width greater than its vertical height. Each of the multiple contact plugs 52 may have a vertical height greater than its lateral width.

[0023] The pad 61 may exhibit a second thickness d2. Each of the plurality of upper interconnects 62 may exhibit a third thickness d3. In an embodiment, the pad 61 and the plurality of upper interconnects 62 may comprise the same material formed simultaneously. The third thickness d3 may be substantially equal to the second thickness d2. The pad 61 and the plurality of upper interconnects 62 may be disposed at substantially the same vertical level. The lower surface of the pad 61 and the lower surfaces of the plurality of upper interconnects 62 may be substantially coplanar. The upper surface of the pad 61 and the upper surfaces of the plurality of upper interconnects 62 may be substantially coplanar.

[0024] When referring to orientation, layout, position, shape, dimension, composition, quantity or other measures, terms such as "same (identical)", "equal", "flat" or "coplanar" as used herein do not necessarily mean exactly the same orientation, layout, position, shape, dimension, composition, quantity or other measures, but are intended to encompass nearly the same orientation, layout, position, shape, dimension, composition, quantity or other measures within an acceptable range of variation that may occur, for example, due to manufacturing processes. Unless the context or other statements indicate otherwise, the term "substantially" may be used herein to emphasize this meaning. For example, items described as "substantially the same", "substantially equal" or "substantially flat" may be exactly the same, equal or flat, or may be the same, equal or flat within an acceptable range of variation that may occur, for example, due to manufacturing processes.

[0025] The second thickness d2 may be greater than the first thickness d1. The second thickness d2 may be at least twice the first thickness d1. In an embodiment, the second thickness d2 may be from two to one hundred times the first thickness d1, and in some embodiments, the second thickness d2 may be from three to ten times the first thickness d1. The second thickness d2 may be 1 μm or greater. In an embodiment, the second thickness d2 may be in the range of 1 μm to 5 μm. In some embodiments, the first thickness d1 may be in the range of 0.01 μm to 0.5 μm. For example, in one embodiment, the second thickness d2 may be about 2.5 μm. The interconnect resistance may be reduced due to the thickness of the pad 61 and the thicknesses of the plurality of upper interconnects 62 (i.e., the second thickness d2 and the third thickness d3). The configuration of the pad 61 and the plurality of upper interconnects 62 may have the effect of increasing current drivability.

[0026] Each of the plurality of upper interconnects 62 can be arranged adjacent to the pad 61. Each of the plurality of upper interconnects 62 can be spaced apart from the pad 61. Each gap G1 between the plurality of upper interconnects 62 and the pad 61 can be 1 μm or greater. Each of the gaps G1 between the plurality of upper interconnects 62 and the pad 61 can be in the range of 1 μm to 10 μm. In an embodiment, each of the gaps G1 can be in the range of 2.5 μm to 7.2 μm. Each of the gaps G1 between the plurality of upper interconnects 62 and the pad 61 can be greater than or equal to the second thickness d2. Due to the gap G1 between the plurality of upper interconnects 62 and the pad 61, signal delays such as resistance-capacitance (RC) delay can be minimized. The configuration of the pad 61 and the plurality of upper interconnects 62 can have the effect of improving the operating speed. Although not shown in Figure 1 it, in an exemplary embodiment showing features similar to Figure 1 or other drawings, when viewed from a top-down view, the pad 61 has a substantially circular shape or can have a square, rectangular, or linear shape (e.g., an elongated rectangular shape), and the upper interconnect 62 has a linear shape (e.g., an elongated rectangular shape).

[0027] The plurality of protective insulating layers 71 and 72 can cover the edges of the pad 61 (e.g., one side or multiple sides and the adjacent upper surface of the pad 61), the plurality of upper interconnects 62, and the gap G1 between the pad 61 and the plurality of upper interconnects 62. The opening 73W can be provided in the pad 61 and pass through the plurality of protective insulating layers 71 and 72. For example, the opening 73W can pass through the entire second protective insulating layer 72 and a portion of the first protective insulating layer 71. The upper surfaces of the plurality of protective insulating layers 71 and 72 can be substantially flat.

[0028] The first protective insulating layer 71 can cover the edges of the pad 61, the plurality of upper interconnects 62, and the gap G1 between the pad 61 and the plurality of upper interconnects 62. The upper surface of the first protective insulating layer 71 can be substantially flat. The second protective insulating layer 72 can be provided on the first protective insulating layer 71. The second protective insulating layer 72 can include a material different from that of the first protective insulating layer 71 or be formed of a material different from that of the first protective insulating layer 71. The upper surface of the second protective insulating layer 72 can be substantially flat.

[0029] In an exemplary embodiment, each of the first protective insulating layer 71 and the second protective insulating layer 72 can include a single-layer or multi-layer structure. Each of the first protective insulating layer 71 and the second protective insulating layer 72 can include a first oxide layer such as a high-density plasma (HDP) oxide, a second oxide layer using tetraethyl orthosilicate (TEOS) or fluorinated tetraethyl orthosilicate (FTEOS), or a combination of the first oxide layer and the second oxide layer.

[0030] The first bump 89 can be disposed on the pad 61 and extend over the plurality of protective insulating layers 71 and 72, and be stacked with the plurality of upper interconnects 62. The first bump 89 can extend into the plurality of protective insulating layers 71 and 72 and can be connected to the pad 61 through the opening 73W (e.g., by contacting the pad 61 through the opening 73W). In this way, a first portion of the bottom surface of the first bump 89 can contact the top surface of the pad 61 through the opening 73W, and a second portion of the bottom surface of the first bump 89 can contact the top surface of the uppermost layer in the protective insulating layers (e.g., layers 71 and 72). The column structure 85 can be disposed on the pad 61 and extend over the plurality of protective insulating layers 71 and 72, and be stacked with the plurality of upper interconnects 62. The column structure 85 can extend into the plurality of protective insulating layers 71 and 72 and be connected to the pad 61 through the opening 73W. The solder 87 can be disposed on the column structure 85.

[0031] A first portion 85A of the column structure 85 can be disposed on the opening 73W. A second portion 85B of the column structure 85 can extend over the plurality of protective insulating layers 71 and 72. The second portion 85B can be stacked with the edge of the pad 61, the plurality of upper interconnects 62, and the gap G1 between the pad 61 and the plurality of upper interconnects 62. For example, in one embodiment, the column structure 85 and the solder 87 are substantially circular when viewed from a top-down view, and the first portion 85A is surrounded by the second portion 85B, and each of the first portion 85A and the second portion 85B is substantially circular.

[0032] The lower surface of the second portion 85B can contact the top of the second protective insulating layer 72. The lower surface of the second portion 85B can be formed to be substantially flat. The first portion 85A can extend into the plurality of protective insulating layers 71 and 72 and can be connected to the pad 61 through the opening 73W. The lower surface of the first portion 85A can contact the pad 61. The upper surface of the first portion 85A can be closer to the substrate 21 than the upper surface of the second portion 85B. The upper surface of the second portion 85B can be formed to be substantially flat. Due to the flat configuration of the first protective insulating layer 71, the second protective insulating layer 72, and the column structure 85, the physical and chemical reliability of the first bump 89 can be ensured.

[0033] Refer to Figure 2, A semiconductor device according to an embodiment of the inventive concept may include a substrate 21, a plurality of interlayer insulating layers 31, 32, 33, 34, and 35, a plurality of middle interconnects 41 and 42, a plurality of contact plugs 52, pads 61, upper interconnects 62, a plurality of protective insulating layers 71 and 72, an opening 73W, and a first bump 89. The upper interconnect 62 may be disposed on one side of the pad 61. The pad 61 and the upper interconnect 62 may be disposed at substantially the same level. The upper surface of each of the first protective insulating layer 71 and the second protective insulating layer 72 may be substantially flat.

[0034] Referring to Figure 3 , A semiconductor device according to an embodiment of the inventive concept may include a substrate 21, a plurality of interlayer insulating layers 31, 32, 33, 34, and 35, a plurality of middle interconnects 41 and 42, a plurality of contact plugs 52, pads 61, a plurality of protective insulating layers 71 and 72, an opening 73W, and a first bump 89. This example does not include the upper interconnect 62. The upper surface of each of the first protective insulating layer 71 and the second protective insulating layer 72 may be substantially flat.

[0035] Referring to Figure 4 , Each of the plurality of upper interconnects 62 and the pad 61 may include a lower barrier layer 65, a conductive layer 66, and an upper barrier layer 67. The conductive layer 66 may be disposed between the lower barrier layer 65 and the upper barrier layer 67. In an embodiment, the lower barrier layer 65 may include a titanium (Ti) layer. The conductive layer 66 may include an aluminum (Al) layer or a copper (Cu) layer. The upper barrier layer 67 may include a titanium / titanium nitride (Ti / TiN) layer (e.g., the upper barrier layer 67 may include more than one layer, such as a titanium layer covered with a titanium nitride layer).

[0036] Figures 5 to 8 is a cross-sectional view showing a part of a semiconductor device according to an embodiment of the inventive concept.

[0037] Referring to Figure 5 , A semiconductor device according to an embodiment of the inventive concept may include a substrate 21, a plurality of interlayer insulating layers 31, 32, 33, 34, and 35, a plurality of middle interconnects 41 and 42, a plurality of contact plugs 52, pads 61, a plurality of upper interconnects 62, a plurality of protective insulating layers 76 and 77, an opening 73W, and a first bump 89. The plurality of protective insulating layers 76 and 77 may include a first protective insulating layer 76 and a second protective insulating layer 77.

[0038] In an embodiment, the first protective insulating layer 76 may include silicon nitride, and the second protective insulating layer 77 may include silicon oxide. The first protective insulating layer 76 may conformally cover the surfaces of the fifth interlayer insulating layer 35, the pad 61, and the plurality of upper interconnects 62. The second protective insulating layer 77 may cover the first protective insulating layer 76. The opening 73W may pass through the second protective insulating layer 77 and the first protective insulating layer 76. The upper surface of the second protective insulating layer 77 may include a plurality of recessed portions, each of the plurality of recessed portions being disposed between the pad 61 and one of the plurality of upper interconnects 62. The lower surface of the column structure 85 may include a plurality of protruding portions, the plurality of protruding portions being disposed between the pad 61 and the plurality of upper interconnects 62 in a top-down view and corresponding to the plurality of recessed portions of the second protective insulating layer 77. The upper surface of the column structure 85 may include a plurality of recessed portions, the plurality of recessed portions being disposed between the pad 61 and the plurality of upper interconnects 62 in a top-down view, and the plurality of recessed portions corresponding to the plurality of protruding portions of the column structure 85 and the plurality of recessed portions of the second protective insulating layer 77 and being vertically stacked with the plurality of protruding portions of the column structure 85 and the plurality of recessed portions of the second protective insulating layer 77.

[0039] Referring to Figure 6 , a semiconductor device according to an embodiment of the inventive concept may include a substrate 21, a plurality of interlayer insulating layers 31, 32, 33, 34, and 35, a plurality of middle interconnects 41 and 42, a plurality of contact plugs 52, a pad 61, a plurality of upper interconnects 62, a plurality of protective insulating layers 71, 72, and 74, an opening 73W, and a first bump 89. The plurality of protective insulating layers 71, 72, and 74 may include a first protective insulating layer 71, a second protective insulating layer 72, and a third protective insulating layer 74. The third protective insulating layer 74 may be disposed between the first protective insulating layer 71 and the second protective insulating layer 72. The third protective insulating layer 74 may include a material different from that of the second protective insulating layer 72 or may be formed of a material different from that of the second protective insulating layer 72. The third protective insulating layer 74 may be formed from the first protective insulating layer 71 in a later process. The bottom surface of the third protective insulating layer 74 may contact the top surface of the first protective insulating layer 71 at the interface between the third protective insulating layer 74 and the first protective insulating layer 71.

[0040] The upper surfaces of the first protective insulating layer 71, the pad 61, and the plurality of upper interconnects 62 may be substantially coplanar. The first protective insulating layer 71 may fill the gap G1 between the pad 61 and the plurality of upper interconnects 62. The third protective insulating layer 74 may cover the edge of the pad 61, the plurality of upper interconnects 62, and the gap G1 between the pad 61 and the plurality of upper interconnects 62. The upper surface of each of the first protective insulating layer 71, the second protective insulating layer 72, and the third protective insulating layer 74 may be substantially flat. The opening 73W may pass through the second protective insulating layer 72 and the third protective insulating layer 74. The width of the opening 73W may be substantially the same in the vertical direction. That is, from a cross-sectional view, the opening 73W may be rectangular.

[0041] Reference Figure 7 , a semiconductor device according to an embodiment of the inventive concept may include a substrate 21, a plurality of interlayer insulating layers 31, 32, 33, 34 and 35, a plurality of middle interconnects 41 and 42, a plurality of contact plugs 52, a pad 61, a plurality of upper interconnects 62, a plurality of protective insulating layers 71, 72 and 74, an opening 73W and a first bump 89. The opening 73W may be trapezoidal in shape from a cross-sectional view and have a lower width that is smaller than its upper width. The sidewalls of the opening 73W may be inclined so that the width of the opening 73W increases in a direction away from the top surface of the substrate 21.

[0042] Reference Figure 8 , a semiconductor device according to an embodiment of the inventive concept may include a substrate 21, a plurality of interlayer insulating layers 31, 32, 33, 34, and 35, a plurality of middle interconnections 41 and 42, a plurality of contact plugs 52, a pad 61, a plurality of upper interconnections 62, a plurality of protective insulating layers 71, 72, and 78, an opening 73W, and a first bump 89. The plurality of protective insulating layers 71, 72, and 78 may include a first protective insulating layer 71, a second protective insulating layer 72, and a third protective insulating layer 78.

[0043] The third protective insulating layer 78 may be disposed on the second protective insulating layer 72. In an embodiment, the third protective insulating layer 78 may include photosensitive polyimide (PSPI). The opening 73W may pass through the third protective insulating layer 78, the second protective insulating layer 72, and the first protective insulating layer 71. From a cross-sectional view, the opening 73W may be partially rectangular and may be partially trapezoidal. The first bump 89 may extend into the plurality of protective insulating layers 71, 72, and 78 and be connected to the pad 61 through the opening 73W.

[0044] Figure 9 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the inventive concept. Figure 10 yes Figure 9 An enlarged view of portion 90. Figure 11 yes Figure 9An enlarged view of some components. According to certain embodiments of the inventive concept, a semiconductor device may include a multi-chip package. In an embodiment, the semiconductor device may include a high bandwidth memory (HBM). In an embodiment, the semiconductor device may include a dynamic random access memory (DRAM).

[0045] Referring to Figure 9 , the semiconductor device may include a printed circuit board (PCB) PC, an interposer IP, a plurality of semiconductor chips CP, LD, and MD1 to MD4, a plurality of bumps 89, 489, 589, and 689, and a sealant 99. The plurality of semiconductor chips CP, LD, and MD1 to MD4 may include a microprocessor CP, a control chip LD (e.g., a controller), and a plurality of memory chips MD1 to MD4. The plurality of memory chips MD1 to MD4 may include a first memory chip MD1, a second memory chip MD2, a third memory chip MD3, and a fourth memory chip MD4. At least some of the plurality of memory chips MD1 to MD4 may include a plurality of vias 93. The plurality of bumps 89, 489, 589, and 689 may include a plurality of first bumps 89, a plurality of second bumps 489, a plurality of third bumps 589, and a plurality of fourth bumps 689.

[0046] The PCB PC may include a rigid PCB, a flexible PCB, or a rigid-flexible PCB. The PCB PC may include a multi-layer circuit substrate. The PCB PC may correspond to a package substrate or a motherboard. The plurality of fourth bumps 689 may be disposed on the lower surface of the PCB PC. The interposer IP may be disposed on the PCB PC. The plurality of third bumps 589 may be disposed between the PCB PC and the interposer IP. In the case where the PCB PC corresponds to the motherboard, the interposer IP may correspond to the package substrate.

[0047] The plurality of semiconductor chips CP, LD, and MD1 to MD4 may be disposed on the interposer IP. The interposer IP may include a semiconductor substrate such as a silicon interposer. In an embodiment, the microprocessor CP and the control chip LD are disposed on the interposer IP. The plurality of second bumps 489 may be disposed between the microprocessor CP and the interposer IP and between the control chip LD and the interposer IP. The microprocessor CP may include various types of processors such as a graphics processing unit (GPU) or an application processor (AP). The control chip LD may include various elements such as a memory controller. The control chip LD may be connected to the microprocessor CP via the interposer IP and the plurality of second bumps 489.

[0048] The plurality of memory chips MD1 to MD4 may be sequentially stacked on the control chip LD. Each of the plurality of memory chips MD1 to MD4 may include a reference to Figures 1 to 8Multiple components similar to the described components. For example, each of the multiple memory chips MD1 to MD4 may include multiple first bumps 89. In an embodiment, the multiple first bumps 89 may be disposed between the multiple memory chips MD1 to MD4 and between the first memory chip MD1 and the control chip LD. The multiple memory chips MD1 to MD4 may be connected to the control chip LD via the multiple first bumps 89 and the multiple through electrodes 93.

[0049] The sealant 99 may be disposed on the control chip LD to cover the multiple memory chips MD1 to MD4. The sealant 99 may include an epoxy molding compound (EMC), underfill, or a combination thereof.

[0050] In an exemplary embodiment, the control chip LD may include a main chip. Each of the multiple memory chips MD1 to MD4 may represent a slave chip. In an exemplary embodiment, the first memory chip MD1 may represent the main chip. Each of the second memory chip MD2, the third memory chip MD3, and the fourth memory chip MD4 may represent a slave chip.

[0051] Refer to Figure 9 and Figure 10 , the third memory chip MD3 may include a through electrode 93, a protruding electrode 95, a base insulating layer 97, a base 21, multiple interlayer insulating layers 31, 32, 33, 34, and 35, multiple middle interconnects 41 and 42, multiple contact plugs 52, pads 61, multiple upper interconnects 62, multiple protective insulating layers 71 and 72, and a first bump 89. The base insulating layer 97 may cover one surface of the base 21. The base 21 may be disposed between the base insulating layer 97 and the first interlayer insulating layer 31. The protruding electrode 95 may be disposed on the base insulating layer 97. The through electrode 93 may pass through the base 21 and may be connected to a corresponding one of the multiple first middle interconnects 41 and the protruding electrode 95. In an embodiment, the through electrode 93 may pass through the base 21 and may be connected to a corresponding one of the multiple second middle interconnects 42 or the pad 61.

[0052] The second memory chip MD2 may include a structure similar to that of the third memory chip MD3. The solder 87 of the third memory chip MD3 may be attached to the protruding electrode 95 of the second memory chip MD2. The solder 87 of the fourth memory chip MD4 may be attached to the protruding electrode 95 of the third memory chip MD3.

[0053] Refer to Figures 9 to 11 , each of the multiple semiconductor chips CP, LD, and MD1 to MD4 may include multiple active / passive elements. In an embodiment, the multiple active / passive elements may include multiple unit transistors 149 and multiple unit capacitors 159 disposed on the base 21.

[0054] For example, each of the plurality of memory chips MD1 to MD4 may include a substrate 21, a device isolation layer 123, a sixth interlayer insulating layer 131, a seventh interlayer insulating layer 132, a plurality of cell transistors 149, bit lines BL, a plurality of buried contact plugs BC, and a plurality of cell capacitors 159. Each of the plurality of cell transistors 149 may include a gate electrode 141, a gate dielectric layer 143, and a plurality of source / drain regions 145. Each of the plurality of cell capacitors 159 may include a first electrode 151, a capacitor dielectric layer 153, and a second electrode 155.

[0055] The plurality of cell transistors 149 and the plurality of cell capacitors 159 may constitute a plurality of memory cells MC. Each of the plurality of cell transistors 149 may correspond to a recessed channel transistor. In an embodiment, each of the plurality of cell transistors 149 may include a fin field effect transistor (finFET), a multi-bridge channel (MBC) transistor, a nanowire transistor, a vertical transistor, a recessed channel transistor, a three-dimensional (3D) transistor, a planar transistor, or a combination thereof. The first electrode 151 may be referred to as a lower electrode, a storage electrode, or a storage node. The second electrode 155 may be referred to as an upper electrode, a plate electrode, or a plate node. Each of the plurality of cell capacitors 159 may include various types of three-dimensional (3D) capacitors.

[0056] The sixth interlayer insulating layer 131 may be disposed at a level similar to that of Figure 1 the first interlayer insulating layer 31. The seventh interlayer insulating layer 132 may be disposed at a level similar to that of Figure 1 the second interlayer insulating layer 32 or the third interlayer insulating layer 33. The plurality of cell transistors 149 and the plurality of cell capacitors 159 may be electrically connected to at least one of the corresponding Figure 1 plurality of middle interconnects 41 and 42, pads 61, and plurality of upper interconnects 62.

[0057] Figures 12 to 19 is a cross-sectional view for describing a method of forming a semiconductor device according to an embodiment of the inventive concept.

[0058] Referring to Figure 12 , a plurality of interlayer insulating layers 31, 32, 33, 34, and 35, a plurality of middle interconnects 41 and 42, a plurality of contact plugs 52, pads 61, and a plurality of upper interconnects 62 are formed on the substrate 21. The plurality of interlayer insulating layers 31, 32, 33, 34, and 35 may include a first interlayer insulating layer 31, a second interlayer insulating layer 32, a third interlayer insulating layer 33, a fourth interlayer insulating layer 34, and a fifth interlayer insulating layer 35. The plurality of middle interconnects 41 and 42 may include a plurality of first middle interconnects 41 and a plurality of second middle interconnects 42.

[0059] The substrate 21 may include a semiconductor substrate such as a silicon wafer or a silicon-on-insulator (SOI) wafer. A plurality of interlayer insulating layers 31, 32, 33, 34, and 35 may be stacked on the substrate 21. The plurality of interlayer insulating layers 31, 32, 33, 34, and 35 may include silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, high-k dielectrics, or a combination thereof. The fourth interlayer insulating layer 34 may correspond to an etch stop layer. The fourth interlayer insulating layer 34 may include a material different from that of the fifth interlayer insulating layer 35, or may be formed of a material different from that of the fifth interlayer insulating layer 35. For example, the first interlayer insulating layer 31, the second interlayer insulating layer 32, the third interlayer insulating layer 33, and the fifth interlayer insulating layer 35 may include silicon oxide, and the fourth interlayer insulating layer 34 may include silicon nitride.

[0060] Each of the plurality of middle interconnects 41 and 42 and the plurality of contact plugs 52 may include a conductive material such as metal, metal nitride, metal silicide, metal oxide, polysilicon, conductive carbon, or a combination thereof, or may be formed of a conductive material such as metal, metal nitride, metal silicide, metal oxide, polysilicon, conductive carbon, or a combination thereof. Each individual middle interconnect 41 or 42 may have a monolithic structure formed of a continuous single-piece material. In an embodiment, a plurality of first middle interconnects 41 may be formed in the first interlayer insulating layer 31. A plurality of second middle interconnects 42 may be formed in the second interlayer insulating layer 32. Each of the plurality of second middle interconnects 42 may exhibit a first thickness d1.

[0061] The plurality of contact plugs 52 may extend into one or more of the plurality of interlayer insulating layers 31, 32, 33, 34, and 35. In an embodiment, each of the plurality of contact plugs 52 passes through the fifth interlayer insulating layer 35, the fourth interlayer insulating layer 34, and the third interlayer insulating layer 33, and contacts a corresponding one of the plurality of second middle interconnects 42. The formation of the plurality of middle interconnects 41 and 42 and the plurality of contact plugs 52 may include a plurality of thin film formation processes and patterning processes.

[0062] A pad 61 and a plurality of upper interconnects 62 may be formed on the fifth interlayer insulating layer 35. The formation of the pad 61 and the plurality of upper interconnects 62 may include a thin film formation process and a patterning process. Each of the plurality of upper interconnects 62 and the pad 61 may include a conductive material such as a metal, a metal nitride, a metal silicide, a metal oxide, polysilicon, conductive carbon, or a combination thereof, or may be formed of a conductive material such as a metal, a metal nitride, a metal silicide, a metal oxide, polysilicon, conductive carbon, or a combination thereof. Each of the plurality of upper interconnects 62 and the pad 61 may include a single-layer or multi-layer structure. Each of the plurality of upper interconnects 62 and the pad 61 may each have an integral structure formed of a continuous single-piece material. In an embodiment, each of the plurality of upper interconnects 62 and the pad 61 may include aluminum (Al), copper (Cu), nickel (Ni), cobalt (Co), silver (Ag), platinum (Pt), ruthenium (Ru), tungsten (W), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof, or may be formed of aluminum (Al), copper (Cu), nickel (Ni), cobalt (Co), silver (Ag), platinum (Pt), ruthenium (Ru), tungsten (W), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof.

[0063] A plurality of middle interconnects 41 and 42 may be formed between the pad 61 and the substrate 21. Each of the plurality of upper interconnects 62 and the pad 61 may at least contact a corresponding one of the plurality of contact plugs 52. In an embodiment, among the plurality of middle interconnects 41 and 42, a selected one of the plurality of second middle interconnects 42 is closest to the center of the pad 61 in a top-down view.

[0064] The pad 61 may exhibit a second thickness d2. Each of the plurality of upper interconnects 62 may exhibit a third thickness d3. In an embodiment, the pad 61 and the plurality of upper interconnects 62 may include the same material formed simultaneously and may be formed of the same material formed simultaneously. The third thickness d3 may be substantially equal to the second thickness d2. The pad 61 and the plurality of upper interconnects 62 may be formed at substantially the same vertical level. The second thickness d2 may be greater than the first thickness d1. The second thickness d2 may be two to 100 times the first thickness d1. The second thickness d2 may be 1 μm or greater. In an embodiment, the second thickness d2 may be in the range of 1 μm to 5 μm. For example, the second thickness d2 may be about 2.5 μm.

[0065] Each of the plurality of upper interconnects 62 can be formed adjacent to the pad 61 (e.g., adjacent to the pad 61 in the horizontal direction). Each gap G1 between the plurality of upper interconnects 62 and the pad 61 can be 1 μm or greater. Each of the gaps G1 between the plurality of upper interconnects 62 and the pad 61 can be in the range of 1 μm to 10 μm. In an embodiment, each of the gaps G1 can be in the range of 2.5 μm to 7.2 μm. Each of the gaps G1 between the plurality of upper interconnects 62 and the pad 61 can be greater than or equal to the second thickness d2.

[0066] Referring to Figure 13 , a first protective insulating layer 71 is formed on the fifth interlayer insulating layer 35. The first protective insulating layer 71 can cover the pad 61, the plurality of upper interconnects 62, and the gap G1 between the pad 61 and the plurality of upper interconnects 62. The first protective insulating layer 71 can include silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or a combination thereof, or be formed of silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or a combination thereof. In an embodiment, the first protective insulating layer 71 can include a silicon oxide layer formed using tetraethyl orthosilicate (TEOS). The upper surface of the first protective insulating layer 71 can be formed at a level higher than the level of the uppermost ends (e.g., the top surfaces) of the pad 61 and the plurality of upper interconnects 62.

[0067] Referring to Figure 14 , the upper surface of the first protective insulating layer 71 can be formed to be substantially flat using a planarization process. The planarization process can include a chemical mechanical polishing (CMP) process, an etch-back process, or a combination thereof. In an embodiment, the first protective insulating layer 71 covers the pad 61, the plurality of upper interconnects 62, and the gap G1 between the pad 61 and the plurality of upper interconnects 62.

[0068] Referring to Figure 15 , a second protective insulating layer 72 is formed on the first protective insulating layer 71. The second protective insulating layer 72 can include a material different from that of the first protective insulating layer 71. In an embodiment, the second protective insulating layer 72 includes silicon nitride. The second protective insulating layer 72 can cover the upper surface of the first protective insulating layer 71 with a constant thickness. The upper surface of the second protective insulating layer 72 can be formed to be substantially flat.

[0069] Referring to Figure 16, a patterning process can be used to form the opening 73W to pass through the second protective insulating layer 72 and the first protective insulating layer 71 and expose the upper surface of the pad 61. In an embodiment, the opening 73W can be arranged within the center of the pad 61. The edges of the pad 61 can remain covered by the first protective insulating layer 71 and the second protective insulating layer 72. The opening 73W can present various cross-sectional shapes, such as a rectangular shape or a trapezoidal shape having a lower horizontal width smaller than its upper horizontal width. In the following description, it can be assumed that the lower horizontal width and the upper horizontal width of the opening 73W are substantially the same. From a top-down view, the opening 73W can have, for example, a circular shape, a square or rectangular shape, or a linear shape.

[0070] Referring to Figure 17 , a barrier layer 81 and a seed layer 82 are sequentially formed on the second protective insulating layer 72. The barrier layer 81 can include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof, or be formed of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof. The seed layer 82 can include copper (Cu) or be formed of copper (Cu). The barrier layer 81 can extend into the opening 73W. The barrier layer 81 contacts the upper surface of the pad 61. The seed layer 82 conformally covers the upper surface of the barrier layer 81.

[0071] Referring to Figure 18 , a mask pattern 80 is formed on the seed layer 82. Posts 83 are formed on the seed layer 82. The posts 83 can include nickel (Ni), copper (Cu), aluminum (Al), silver (Ag), platinum (Pt), ruthenium (Ru), tin (Sn), gold (Au), tungsten (W), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof, or be formed of nickel (Ni), copper (Cu), aluminum (Al), silver (Ag), platinum (Pt), ruthenium (Ru), tin (Sn), gold (Au), tungsten (W), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof. For example, the posts 83 can include a nickel layer. The posts 83 can be formed using an electroplating process. The posts 83 can be defined by the mask pattern 80.

[0072] The barrier layer 81, the seed layer 82, and the posts 83 can constitute a post structure 85. The post structure 85 can include a first portion 85A and a second portion 85B. The first portion 85A can be arranged on the opening 73W. The second portion 85B can extend on the second protective insulating layer 72. The second portion 85B can overlap with the edge of the pad 61, the plurality of upper interconnects 62, and the gap G1 between the pad 61 and the plurality of upper interconnects 62.

[0073] The upper surface of the first portion 85A may be closer to the substrate 21 than the upper surface of the second portion 85B. The lower surface of the second portion 85B may be formed to be substantially flat. The upper surface of the second portion 85B may be formed to be substantially flat.

[0074] Referring to Figure 19 , solder 87 is formed on the pillar structure 85. The solder 87 may include Sn, Ag, Cu, Ni, Au, or a combination thereof, or may be formed of Sn, Ag, Cu, Ni, Au, or a combination thereof. For example, the solder 87 may be a Sn - Ag - Cu layer. An interfacial metal layer may be further formed between the pillar structure 85 and the solder 87, but its description will be omitted for simplicity.

[0075] Referring again to Figure 1 and Figure 19 , the mask pattern 80 may be removed to expose the side surfaces of the pillars 83 and the solder 87. The seed layer 82 and the barrier layer 81 may be partially removed to partially expose the upper surface of the second protective insulating layer 72. The seed layer 82 and the barrier layer 81 may define a gap G1 between the pad 61 and the pillar 83, between the second protective insulating layer 72 and the pillar 83 at the edge of the pad 61, between the second protective insulating layer 72 and the pillar 83 on the gap G1 between the pad 61 and the plurality of upper interconnects 62, and between the second protective insulating layer 72 and the pillar 83 on the plurality of upper interconnects 62.

[0076] An annealing process such as a reflow process may be used to round the solder 87. In an embodiment, the lateral width of the solder 87 may be greater than the lateral width of the pillar 83. The upper surface of the solder 87 may have a curved hemispherical shape.

[0077] Figures 20 to 22 is a cross - sectional view for describing a method of forming a semiconductor device according to an embodiment of the inventive concept.

[0078] Referring to Figure 20 , a planarization process may be used to form the upper surface of the first protective insulating layer 71 to be substantially flat. The upper surfaces of the first protective insulating layer 71, the pad 61, and the plurality of upper interconnects 62 may be substantially coplanar and exposed. The first protective insulating layer 71 may fill the gap G1 between the pad 61 and the plurality of upper interconnects 62.

[0079] Referring to Figure 21, a third protective insulating layer 74 is formed on the first protective insulating layer 71, the pad 61, and the plurality of upper interconnects 62. The second protective insulating layer 72 may be formed on the third protective insulating layer 74. The third protective insulating layer 74 may include a material different from that of the second protective insulating layer 72. For example, each of the first protective insulating layer 71 and the third protective insulating layer 74 may include a silicon oxide layer formed using tetraethyl orthosilicate (TEOS). The second protective insulating layer 72 may include a silicon nitride layer. The upper surfaces of the first protective insulating layer 71, the third protective insulating layer 74, and the second protective insulating layer 72 may each be formed to be substantially flat.

[0080] Referring to Figure 22 , an opening 73W may be formed to pass through the second protective insulating layer 72 and the third protective insulating layer 74 and expose the upper surface of the pad 61 using a patterning process.

[0081] According to an exemplary embodiment of the inventive concept, a pad and an upper interconnect having a thickness at least twice that of the thickness of the middle interconnect may be provided. The protective insulating layer may cover the edge of the pad, the upper interconnect, and the gap between the pad and the upper interconnect, and have an opening on the pad. A bump may be provided on the pad. The bump may extend on the protective insulating layer and overlap with the upper interconnect. The gap between the pad and the upper interconnect may be 1 μm or greater. The upper surface of the protective insulating layer may be substantially flat. A semiconductor device having excellent current drivability, a high signal transmission rate, and high physical / chemical reliability can be realized.

[0082] Although embodiments of the inventive concept have been described with reference to the accompanying drawings, those skilled in the art should understand that various modifications can be made without departing from the scope of the inventive concept and without changing its essential features. Therefore, the above embodiments should be considered only in a descriptive sense and not for the purpose of limitation.

Claims

1. A semiconductor device, the semiconductor device comprising: An interlayer insulating layer disposed on a substrate; A plurality of middle interconnects disposed in the interlayer insulating layer; A pad disposed on the interlayer insulating layer; An upper interconnect disposed on the interlayer insulating layer; A protective insulating layer covering an edge of the pad, the upper interconnect, and a gap between the pad and the upper interconnect, the protective insulating layer having an opening on the pad; and A bump disposed on the pad, the bump extending on the protective insulating layer and overlapping with the upper interconnect in a top-down view, Wherein, at least one of the middle interconnects among the middle interconnects of the plurality of middle interconnects that is closest to the pad in the vertical direction has a first vertical thickness, The pad has a second vertical thickness that is two times to 100 times the first vertical thickness, The length of the gap between the pad and the upper interconnect is 1 μm or greater, and The upper surface of the protective insulating layer is flat.

2. The semiconductor device according to claim 1, wherein, The second vertical thickness has a value within a range between 1 μm and 5 μm.

3. The semiconductor device according to claim 1, wherein, The gap between the pad and the upper interconnect has a length greater than or equal to the second vertical thickness.

4. The semiconductor device according to claim 1, wherein, The gap between the pad and the upper interconnect has a length within a range between 2.5 μm and 10 μm.

5. The semiconductor device according to claim 1, wherein, The upper interconnect and the pad have the same vertical thickness.

6. The semiconductor device according to claim 1, wherein, The protective insulating layer includes: A first protective insulating layer; and A second protective insulating layer disposed on the first protective insulating layer and including a material different from that of the first protective insulating layer, such that the first protective insulating layer is located between the substrate and the second protective insulating layer, Wherein, the upper surface of the first protective insulating layer is flat.

7. The semiconductor device according to claim 6, wherein, The first protective insulating layer covers the edge of the pad, the upper interconnect, and the gap between the pad and the upper interconnect.

8. The semiconductor device according to claim 6, wherein, The first protective insulating layer includes silicon oxide, and The second protective insulating layer includes silicon nitride.

9. The semiconductor device according to claim 6, the semiconductor device further comprising a third protective insulating layer disposed between the first protective insulating layer and the second protective insulating layer and including a material different from that of the second protective insulating layer, Among them, The upper surfaces of the first protective insulating layer, the pad, and the upper interconnect are coplanar.

10. The semiconductor device according to claim 9, wherein, The third protective insulating layer covers the edge of the pad, the upper interconnect, and the gap between the pad and the upper interconnect.

11. The semiconductor device according to claim 1, wherein, The bump includes: A column structure disposed on the pad, the column structure extending on the protective insulating layer and overlapping with the upper interconnect in the vertical direction; And Solder disposed on the column structure, Wherein, the column structure includes: a first portion disposed on and extending into the opening; and a second portion extending on the protective insulating layer and overlapping with the upper interconnect in the vertical direction, Wherein, the lower surface of the second portion is flat.

12. The semiconductor device according to claim 11, wherein, The upper surface of the first portion is closer to the upper surface of the substrate than the upper surface of the second portion.

13. The semiconductor device according to claim 11, wherein, The upper surface of the second portion is flat.

14. The semiconductor device according to claim 11, wherein, The column structure includes nickel, copper, titanium, titanium nitride, tantalum, tantalum nitride, or a combination thereof.

15. The semiconductor device according to claim 1, the semiconductor device further comprising a contact plug disposed in the vertical direction between the pad and the plurality of middle interconnects.

16. The semiconductor device according to claim 15, wherein, Each of the plurality of middle interconnects has a lateral width greater than its vertical height, and The contact plug has a vertical height greater than its lateral width.

17. A semiconductor device, the semiconductor device comprising: An interlayer insulating layer disposed on a substrate; A plurality of active / passive elements disposed on the substrate; A plurality of middle interconnects disposed in the interlayer insulating layer; A pad disposed on the interlayer insulating layer; An upper interconnect disposed on the interlayer insulating layer; A protective insulating layer covering an edge of the pad, the upper interconnect, and a gap between the pad and the upper interconnect, the protective insulating layer having an opening on the pad; A bump disposed on the pad, the bump extending over the protective insulating layer and vertically overlapping with the upper interconnect; And A through electrode passing through the substrate and connected to the plurality of middle interconnects or the pad, wherein, among the plurality of middle interconnects, one of the middle interconnects closest to the pad in the vertical direction is electrically connected to the pad and has a first vertical thickness, the pad has a second vertical thickness that is two times to 100 times the first vertical thickness, the length of the gap between the pad and the upper interconnect is 1 μm or greater, and the upper surface of the protective insulating layer is flat.

18. The semiconductor device according to claim 17, wherein the semiconductor device comprises: A plurality of semiconductor chips sequentially stacked on a printed circuit board, wherein at least one of the plurality of semiconductor chips includes: The interlayer insulating layer disposed on the substrate; The plurality of active / passive elements disposed on the substrate; The plurality of middle interconnects disposed in the interlayer insulating layer; The pad disposed on the interlayer insulating layer; The upper interconnect disposed on the interlayer insulating layer; The protective insulating layer covering the edge of the pad, the upper interconnect, and the gap between the pad and the upper interconnect; The bump disposed on the pad, the bump extending over the protective insulating layer and vertically overlapping with the upper interconnect; and The through electrode passing through the substrate and connected to the plurality of middle interconnects or the pad.

19. The semiconductor device according to claim 18, wherein, The plurality of semiconductor chips include a plurality of memory chips sequentially stacked.

20. The semiconductor device according to claim 19, wherein, The plurality of active / passive elements include: Unit transistors; and Unit capacitors connected to the unit transistors.

21. A semiconductor device, the semiconductor device comprising: An interlayer insulating layer disposed on a substrate; A plurality of middle interconnects disposed in the interlayer insulating layer; A pad disposed on the interlayer insulating layer; An upper interconnect disposed on the interlayer insulating layer; A protective insulating layer covering an edge of the pad, the upper interconnect, and a gap between the pad and the upper interconnect, the protective insulating layer having an opening on the pad; and A bump disposed on the pad, the bump extending over the protective insulating layer and vertically overlapping with the upper interconnect, wherein, among the plurality of middle interconnects, one of the middle interconnects closest to the pad in the vertical direction has a first vertical thickness, the pad has a second vertical thickness that is two times to 100 times the first vertical thickness, the horizontal length of the gap between the pad and the upper interconnect is greater than or equal to the second vertical thickness, and the upper surface of the protective insulating layer is flat.

22. The semiconductor device according to claim 21, wherein, The second vertical thickness has a value in the range between 1 μm and 5 μm.

23. The semiconductor device according to claim 21, wherein, The gap between the pad and the upper interconnect has a length in the range between 1 μm and 10 μm.

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