Semiconductor device including support pattern and method for manufacturing semiconductor device

Abstract

A semiconductor device including a support pattern and a method for manufacturing the semiconductor device are disclosed. The semiconductor device may include a plurality of vertical structures on a substrate and a support pattern contacting sidewalls of the plurality of vertical structures. The support pattern may include a plurality of support holes extending through the support pattern. The plurality of support holes may include a first support hole and a second support hole spaced apart from each other, and the first support hole may have a shape or size different from that of the second support hole.

Description

Technical Field

[0001] The inventive concept relates to a semiconductor device including a support pattern and a method of manufacturing the semiconductor device. Background Art

[0002] Semiconductor devices are beneficial in the electronics industry due to their small size, versatility and / or low manufacturing cost. With the significant development of the electronics industry, semiconductor devices are being highly integrated. For the high integration of semiconductor devices, the line width of the pattern of the semiconductor device is being reduced. Therefore, new exposure techniques and / or expensive exposure techniques can be used to form fine patterns. Various studies have been conducted recently for new integration techniques. Summary of the invention

[0003] Some example embodiments of the inventive concepts provide a semiconductor device having improved reliability.

[0004] Some example embodiments of the inventive concepts provide a method of manufacturing a semiconductor device, which may reduce manufacturing costs.

[0005] According to some example embodiments of the inventive concept, a semiconductor device may include a plurality of vertical structures on a substrate and a support pattern contacting sidewalls of the plurality of vertical structures. The support pattern may include a plurality of support holes extending through the support pattern. The plurality of support holes may include a first support hole and a second support hole spaced apart from each other, and the first support hole may have a shape or size different from that of the second support hole.

[0006] According to some example embodiments of the inventive concept, a semiconductor device may include a plurality of word lines in a substrate and parallel to each other, and a plurality of first impurity regions and a plurality of second impurity regions in the substrate. One of the plurality of first impurity regions and the plurality of second impurity regions may be between two adjacent word lines in the plurality of word lines, and the plurality of first impurity regions and the plurality of second impurity regions may be spaced apart from each other. The semiconductor device may also include a plurality of bottom electrodes and a plurality of storage node contacts, the plurality of bottom electrodes being on the substrate and electrically connected to the plurality of first impurity regions, respectively. Each of the plurality of storage node contacts may electrically connect a corresponding bottom electrode in the plurality of bottom electrodes to a corresponding first impurity region in the plurality of first impurity regions. The semiconductor device may also include: a plurality of landing pads; a plurality of bit lines, on the substrate and electrically connected to the plurality of second impurity regions, respectively, the plurality of bit lines crossing the plurality of word lines; a plurality of bit line contacts, between corresponding bit lines in the plurality of bit lines and corresponding second impurity regions in the plurality of second impurity regions; and a support pattern contacting a first portion of a sidewall of each of the plurality of bottom electrodes. Each of the plurality of landing pads may be between a corresponding storage node contact in the plurality of storage node contacts and a corresponding bottom electrode in the plurality of bottom electrodes. The support pattern may include a plurality of support holes, and a second portion of a side wall of each of the plurality of bottom electrodes defines a corresponding support hole in the plurality of support holes. The plurality of support holes may include a first support hole and a second support hole spaced apart from each other. When viewed in a plan view, the support pattern may include a first inner sidewall defining the first support hole and defining the circumference of a circle. When viewed in a plan view, the support pattern may include a second inner sidewall defining the second support hole and respectively defining the sides of a triangle.

[0007] According to some example embodiments of the inventive concept, a method of manufacturing a semiconductor device may include: forming a mold layer and a support layer on a substrate; forming a plurality of vertical structures extending through the support layer and the mold layer and including six vertical structures, the six vertical structures being arranged in a honeycomb shape when viewed in a plan view; forming a first mask layer on the support layer; forming a plurality of second mask patterns on the first mask layer, each of the plurality of second mask patterns overlapping portions of three adjacent vertical structures and having a circular shape when viewed in a plan view; and forming a plurality of mask spacers on the first mask layer. Each of the plurality of mask spacers may be on a sidewall of a corresponding second mask pattern in the plurality of second mask patterns, the plurality of mask spacers may contact each other, and the first mask layer may be exposed to a first space between the three adjacent mask spacers. The method may further include: removing the plurality of second mask patterns to form a plurality of second spaces exposing the first mask layer; using the plurality of mask spacers as an etching mask, by etching the first mask layer, forming a first mask pattern; and using the first mask pattern as an etching mask, by etching the support layer, forming a plurality of support holes in the support layer. When viewed in a plan view, each of the plurality of mask spacers may have a ring shape, and a sidewall of each of the plurality of vertical structures may include a portion defining a corresponding support hole of the plurality of support holes. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 Plan views showing semiconductor devices according to some example embodiments of the inventive concepts are illustrated.

[0009] Figure 2 Shown along Figure 1 Cross-sectional view taken along lines K-K' and J-J'.

[0010] Figure 3A and Figure 3B Plan views showing semiconductor devices according to some example embodiments of the inventive concepts are illustrated.

[0011] Figure 4 Shown along Figure 3A or Figure 3B A cross-sectional view taken along lines AA' and BB'.

[0012] Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A and Fig. 9A Shows the display manufacturing has Figure 3A A plan view of a semiconductor device of the method of the present invention is a plan view of the semiconductor device of the method.

[0013] Figure 5B , Figure 6B, Figure 7B , Figure 8B and Fig. 9B The Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A and Fig. 9A A cross-sectional view taken along lines AA' and BB'. DETAILED DESCRIPTION

[0014] Some example embodiments of the present inventive concept will now be described in detail with reference to the accompanying drawings to help clearly explain the present inventive concept.

[0015] Figure 1 Plan views showing semiconductor devices according to some example embodiments of the inventive concepts are illustrated. Figure 2 Shown along Figure 1 Cross-sectional view taken along lines K-K' and J-J'.

[0016] Reference Figure 1 and Figure 2 , a substrate (eg, a semiconductor substrate) 1 may be provided with a device isolation pattern 302 defining an active portion ACT thereon. Each of the active portions ACT may have an isolated shape. In some embodiments, as Figure 1 As shown, the active portions ACT may be spaced apart from each other. The substrate 1 may be a semiconductor substrate. When viewed in a plan view, each of the active portions ACT may have a bar shape elongated along the first direction X1. When viewed in a plan view, the active portion ACT may correspond to a portion of the semiconductor substrate 1 surrounded by the device isolation pattern 302. The semiconductor substrate 1 may include a semiconductor material. The active portions ACT may be arranged parallel to each other in the first direction X1, so that one of the active portions ACT may have an end portion adjacent to the central portion of an adjacent active portion in the active portion ACT. As used herein, "when viewed in a plan view" may be interchangeable with "when viewed in a plan view".

[0017] The word line WL may extend across the active portion ACT or may cross the active portion ACT. The word line WL may be disposed in a groove formed on the device isolation pattern 302 and the active portion ACT. The word line WL may be parallel to a second direction X2 that intersects the first direction X1. In some embodiments, each of the word lines WL may extend longitudinally in the second direction X2, such as Figure 1As shown. The word line WL may be formed of a conductive material. A gate dielectric layer 307 may be disposed between each of the word lines WL and an inner surface of a corresponding one of the grooves. Although not shown, each of the grooves may have a bottom surface that is relatively deep in the device isolation pattern 302 and relatively shallow in the active portion ACT. The gate dielectric layer 307 may include one or more of thermal oxide, silicon nitride, silicon oxynitride, and a high-k dielectric. Each of the word lines WL may have a curved bottom surface.

[0018] The first doped region 312a may be disposed in the active portion ACT between a pair of word lines WL, and a pair of second doped regions 312b may be disposed in opposite edges of each active portion ACT. The first doped region 312a and the second doped region 312b may be doped with, for example, N-type impurities. The first doped region 312a may correspond to a common drain region, and the second doped region 312b may correspond to a source region. The transistor may be composed of each of the word lines WL and its adjacent first and second doped regions 312a and 312b. Because the word lines WL are disposed in the grooves, each of the word lines WL may have a channel region therebelow, the length of which increases within a limited plane area. Therefore, short channel effects, etc. may be reduced or minimized.

[0019] The word line WL may have a top surface lower than the top surface of the active portion ACT. In some embodiments, the word line WL may be recessed toward the substrate 1 relative to the active portion ACT. A word line capping pattern 310 may be disposed on each of the word lines WL. The word line capping pattern 310 may have a linear shape extending in a longitudinal direction of the word line WL and may cover the entire top surface of the word line WL. The groove may have an inner space not occupied by the word line WL, and the word line capping pattern 310 may fill (e.g., partially fill or completely fill) the unoccupied inner space of the groove. The word line capping pattern 310 may be formed of, for example, a silicon nitride layer.

[0020] The interlayer dielectric pattern 305 may be disposed on the semiconductor substrate 1. The interlayer dielectric pattern 305 may be formed of a single layer or a multilayer including one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. In a plan view, the interlayer dielectric pattern 305 may be formed to have an island shape spaced apart from each other. The interlayer dielectric pattern 305 may be formed to simultaneously cover the ends of two adjacent active portions ACT.

[0021] An upper portion of the semiconductor substrate 1, an upper portion of the device isolation pattern 302, and an upper portion of the word line capping pattern 310 may be partially recessed to form a first recess region R1. The first recess region R1 may have a sidewall aligned with a sidewall of the interlayer dielectric pattern 305.

[0022] The bit lines BL may be disposed on the interlayer dielectric pattern 305. The bit lines BL may extend across the word line capping pattern 310 and the word lines WL or may cross the word line capping pattern 310 and the word lines WL. The bit lines BL may be parallel to a third direction X3 that intersects the first direction X1 and the second direction X2. In some embodiments, each of the bit lines BL may extend longitudinally in the third direction X3, such as Figure 1 As shown. Each of the bit lines BL may include, for example, a bit line polysilicon pattern 330, a bit line ohmic pattern 331, and a bit line metal-containing pattern 332 stacked in sequence. The bit line polysilicon pattern 330 may include doped polysilicon and / or undoped polysilicon. The bit line ohmic pattern 331 may include a metal silicide layer. The bit line metal-containing pattern 332 may include one or more of a metal (e.g., tungsten, titanium, and tantalum) and a conductive metal nitride (e.g., titanium nitride, tantalum nitride, and tungsten nitride). A bit line cap pattern 337 may be disposed on each of the bit lines BL. The bit line cap pattern 337 may be formed of a dielectric material such as a silicon nitride layer.

[0023] The bit line contact DC may be disposed in the first recessed region R1 intersecting the bit line BL. The bit line contact DC may include doped polysilicon and / or undoped polysilicon. The bit line contact DC may have a sidewall in contact with a side surface of the interlayer dielectric pattern 305. Figure 1 When viewed in the illustrated plan view, the bit line contact DC may have a concave side surface in contact with the interlayer dielectric pattern 305. The bit line contact DC may electrically connect the first doped region 312a to the bit line BL.

[0024] The first recessed region R1 may have a space not occupied by the bit line contact DC, and the lower buried dielectric pattern 341 may occupy that space of the first recessed region R1. The lower buried dielectric pattern 341 may be formed of a single layer or multiple layers including one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0025] The storage node contact BC may be disposed between a pair of adjacent bit lines BL. The storage node contacts BC may be spaced apart from each other. The storage node contact BC may include doped polysilicon and / or undoped polysilicon. The storage node contact BC may have a concave top surface. Between the bit lines BL, a dielectric pattern (not shown) may be disposed between the storage node contacts BC.

[0026] The bit line spacer SP may be interposed between the bit line BL and the storage node contact BC. The bit line spacer SP may include a first sub-spacer 321 and a second sub-spacer 325 spaced apart from each other across a gap region GP. The gap region GP may also be referred to as an air gap. The first sub-spacer 321 may cover the sidewalls of the bit line BL and the sidewalls of the bit line cap pattern 337. The second sub-spacer 325 may be adjacent to the storage node contact BC. In some embodiments, the first sub-spacer 321 and the second sub-spacer 325 may include the same material. For example, the first sub-spacer 321 and the second sub-spacer 325 may include a silicon nitride layer.

[0027] The second subspacer 325 may have a bottom surface lower than the top surface of the interlayer dielectric pattern 305. The second subspacer 325 may have a top end whose level is lower than that of the top end of the first subspacer 321. The first subspacer 321 may extend to cover the sidewall of the bit line contact DC and also cover the sidewall and bottom surface of the first recessed region R1. For example, the first subspacer 321 may be interposed between the bit line contact DC and the lower buried dielectric pattern 341, between the word line capping pattern 310 and the lower buried dielectric pattern 341, between the semiconductor substrate 1 and the lower buried dielectric pattern 341, and between the device isolation pattern 302 and the lower buried dielectric pattern 341.

[0028] The storage node ohmic layer 309 may be disposed on the storage node contact BC. The storage node ohmic layer 309 may include a metal silicide. The diffusion stop pattern 311a may conformally cover the storage node ohmic layer 309, the first subspacer 321 and the second subspacer 325, and the bit line capping pattern 337. The diffusion stop pattern 311a may include, for example, a metal nitride, such as a titanium nitride layer and a tantalum nitride layer. The landing pad 11 may be disposed on the diffusion stop pattern 311a. The landing pad 11 may be formed of a material containing a metal such as tungsten. The landing pad 11 may have an upper portion that covers the top surface of the bit line capping pattern 337 and has a width greater than the width of the storage node contact BC. The center of the landing pad 11 may deviate from the center of the storage node contact BC in the second direction X2. A portion of the bit line BL may overlap vertically with the landing pad 11. The bit line capping pattern 337 may have a first upper sidewall that overlaps with the landing pad 11 and is covered by the third subspacer 327. The second recessed region R2 may be formed on the second upper sidewall of the bit line capping pattern 337. The second upper sidewall of the bit line capping pattern 337 may be opposite to the first upper sidewall thereof. As used herein, "element A vertically overlaps element B" (or similar language) means that there is at least one vertical line intersecting both element A and element B. As used herein, the vertical direction refers to a direction perpendicular to the upper surface of the semiconductor substrate 1.

[0029] The sum of the widths of the first subspacer 321 and the third subspacer 327 at the upper portion of the bit line spacer SP may be smaller than the sum of the widths of the first subspacer 321, the gap region GP, ​​and the second subspacer 325 at the lower portion of the bit line spacer SP. Such a configuration may increase a formation margin for the landing pad 11. As a result, disconnection between the landing pad 11 and the storage node contact BC may be reduced or possibly prevented.

[0030] The separation dielectric pattern 3 may be disposed on the second recessed region R2. The separation dielectric pattern 3 may define the top end of the gap region GP. The separation dielectric pattern 3 may include a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, a silicon carbon nitride layer and / or a porous layer. The separation dielectric pattern 3 may have a top surface coplanar with the top surface of the landing pad 11. The separation dielectric pattern 3 may be covered by an etch stop layer 5 between the bottom electrodes 13 to be discussed below. The etch stop layer 5 may include, for example, a dielectric material such as a silicon nitride layer, a silicon oxide layer and / or a silicon oxynitride layer. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items.

[0031] The bottom electrode 13 may be disposed on the corresponding landing pad 11. Each of the bottom electrodes 13 may be electrically connected to the corresponding second doped region in the second doped region 312b through the corresponding landing pad 11 and the corresponding storage node contact BC. The bottom electrode 13 may include one or more of a doped polysilicon layer, a metal nitride layer (such as a titanium nitride layer) and a metal layer (such as a tungsten layer, an aluminum layer and a copper layer). The bottom electrode 13 may have a circular column shape, a hollow cylindrical shape or a cup shape. The support pattern 9p may connect the upper sidewalls of adjacent bottom electrodes 13. The support pattern 9p may include, for example, a dielectric material, such as a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer and / or a silicon carbon nitride layer (e.g., SiCN). The support pattern 9p will be discussed in further detail below. As used herein, "an element having a circular column shape" may refer to an element having a cylindrical shape including a circular bottom surface and a vertical portion protruding from the circular bottom surface in a vertical direction. The vertical portion of the element may or may not have a sidewall perpendicular to the circular bottom surface. The vertical portion of the element may have curved sidewalls (e.g., concave sidewalls or convex sidewalls). An element having a cylindrical shape may have a uniform width along its height direction, or may have a non-uniform width along its height direction. An "element having a cylindrical shape" may be referred to as a "vertical structure."

[0032] The dielectric layer 31 may cover the surface of the bottom electrode 13 and the surface of the support pattern 9p. The dielectric layer 31 may be formed of, for example, a metal oxide layer (such as an aluminum oxide layer) having a dielectric constant greater than that of a silicon oxide layer.

[0033] The dielectric layer 31 may be covered by a top electrode 33. The top electrode 33 may include one or more of a doped polysilicon layer, a doped silicon germanium layer, a metal nitride layer (such as a titanium nitride layer), and a metal layer (such as a tungsten layer, an aluminum layer, and a copper layer). The capacitor CAP may be composed of the bottom electrode 13, the dielectric layer 31, and the top electrode 33.

[0034] Figure 3A and Figure 3B Plan views showing semiconductor devices according to some example embodiments of the inventive concepts are illustrated. Figure 4 Shown along Figure 3A or Figure 3B A cross-sectional view taken along lines AA' and BB'.

[0035] Reference Figure 3A , Figure 3B and Figure 4 , a semiconductor substrate 1, a separation dielectric pattern 3, a landing pad 11, an etch stop layer 5, a bottom electrode 13, a support pattern 9p, a dielectric layer 31, a top electrode 33 and an upper interlayer dielectric layer 35 may be provided. The structure below the bottom electrode 13 may be the same as that of the above reference Figure 1 and Figure 2 The structures discussed are the same or similar. Figure 4 , for simplicity, only the semiconductor substrate 1, the separation dielectric pattern 3, and the landing pad 11 are shown below the bottom electrode 13. The support pattern 9p may contact the sidewalls of all the bottom electrodes 13. The support pattern 9p may include support holes H1, H2, and H3. In some embodiments, each of the support holes H1, H2, and H3 of the support pattern 9p may extend through the support pattern 9p in a vertical direction.

[0036] When in Figure 3A and Figure 3B When viewed in the plan view shown, the bottom electrode 13 can be arranged in a honeycomb shape. For example, when the centers of six bottom electrodes 13 adjacent to (or substantially equally spaced apart from) one (i.e., a single) bottom electrode 13 are connected and surrounding the one (i.e., a single) bottom electrode 13, a hexagon can be obtained. Each of the support holes H1, H2, and H3 can simultaneously expose the side walls of three bottom electrodes 13 adjacent to each other. In some embodiments, the adjacent portions of the side walls of the three bottom electrodes 13 can define one of the support holes H1, H2, and H3, and the layer (e.g., dielectric layer 31) in the one of the support holes H1, H2, and H3 can contact those portions of the side walls of the three bottom electrodes 13. The support holes H1, H2, and H3 may include a first support hole H1, a second support hole H2, and a third support hole H3. The bottom electrode 13 may include a first bottom electrode 13a, a second bottom electrode 13b, and a third bottom electrode 13c.

[0037] For example, refer to Figure 3A , when viewed in a plan view, when the inner side walls of the first support hole H1 are connected, a first triangle T1 can be obtained. Those inner side walls of the first support hole H1 are defined by the support pattern 9p and can be straight. The first support hole H1 can expose the side walls of three first bottom electrodes 13a adjacent to each other. The three first bottom electrodes 13a adjacent to each other may include corresponding side walls, and portions of these side walls of the three first bottom electrodes 13a may define a single first support hole H1. The layer (e.g., dielectric layer 31) in the single first support hole H1 may contact those portions of the side walls of the three first bottom electrodes 13a. The first bottom electrode 13a may be disposed on the corresponding vertices of the first triangle T1. When viewed in a plan view, when the inner side walls of the second support hole H2 are connected, a second triangle T2 can be obtained. Those inner side walls of the second support hole H2 are defined by the support pattern 9p and can be straight. The second support hole H2 can expose the side walls of three second bottom electrodes 13b adjacent to each other. The second bottom electrode 13b may be disposed at the corresponding center of the side of the second triangle T2. Three second bottom electrodes 13b adjacent to each other may include corresponding side walls, and portions of these side walls of the three second bottom electrodes 13b may define a single second support hole H2. The layer (e.g., dielectric layer 31) in the single second support hole H2 may contact those portions of the side walls of the three second bottom electrodes 13b. When the inner side walls of the third support hole H3 are connected, a circle C may be obtained. Those inner side walls of the third support hole H3 are defined by the support pattern 9p and may be curved. In some embodiments, as Figure 3A In the plan view shown, each of those inner side walls of the third support hole H3 may be a portion of the circumference of the circle C. The third support hole H3 may expose the side walls of three third bottom electrodes 13c adjacent to each other. The first triangle T1 and the second triangle T2 may have the same size (eg, the length of the side). In some embodiments, as Figure 3A As shown, the side of the first triangle T1 may have a first length, and the first length is equal to the second length of the side of the second triangle T2. The size of the first triangle T1 and the second triangle T2 (e.g., the length of the side) may be different from the size of the circle C (e.g., the diameter). When the centers of the first support holes H1 and the second support holes H2 of the six triangles T1 and T2 arranged around a third support hole H3 forming the circle C are connected, a hexagon may be obtained. For example, three first support holes H1 and three second support holes H2 may be arranged around a third support hole H3 that shapes the circle C. In some embodiments, the three first support holes H1 and the three second support holes H2 may be arranged in an alternating order around a single third support hole H3, and the centers of those three first support holes H1 and the three second support holes H2 may overlap with the vertices of the hexagon HX, respectively, as shown in FIG. Figure 3A shown.

[0038] In some embodiments, the support pattern 9p may include three first inner side walls defining the first support hole H1 and respectively defining the sides of the first triangle T1, such as Figure 3A In some embodiments, the support pattern 9p may include six second inner sidewalls defining the second support hole H2, and the pairs of second inner sidewalls respectively define the sides of the second triangle T2, as shown in FIG. Figure 3A In some embodiments, the support pattern 9p may include three third inner sidewalls defining the third support hole H3 and defining the circumference of the circle C, such as Figure 3A As used herein, "a sidewall defines a side of a triangle" (or similar language) means that the sidewall defines a portion of the side of a triangle, and does not necessarily mean that the sidewall defines the entire side of the triangle. As used herein, "a sidewall defines a circumference of a circle" (or similar language) means that the sidewall defines a portion of the circumference of a circle, and does not necessarily mean that the sidewall defines the entire circumference of a circle.

[0039] In some embodiments, the first support hole H1, the third support hole H3 and the second support hole H2 may be adjacent to each other and may be arranged in sequence along a direction different from the second direction X2 and the third direction X3, such as Figure 3A When the first supporting hole H1, the third supporting hole H3, and the second supporting hole H2 are adjacent to each other, there is no intermediate supporting hole between the first supporting hole H1 and the third supporting hole H3 and between the third supporting hole H3 and the second supporting hole H2.

[0040] In some embodiments, reference Figure 3B , when viewed in a plan view, when the inner side walls of any one of the first support hole H1 and the second support hole H2 are connected, a first circle C1 may be obtained. Those inner side walls of one of the first support hole H1 and the second support hole H2 are defined by the support pattern 9p and may be curved. In some embodiments, in the case of Figure 3B In the plan view shown in FIG. 1 , the inner side walls of one of the first support hole H1 and the second support hole H2 may define the circumference of the first circle C1. When the inner side walls of the third support hole H3 are connected, a second circle C2 may be obtained. The inner side walls of the third support hole H3 are defined by the support pattern 9p and may be curved. In some embodiments, in the example Figure 3B In the plan view shown, those inner side walls of the third support hole H3 can define the circumference of the second circle C2. The first circle C1 can have a first diameter D1. The second circle C2 can have a second diameter D2. The first diameter D1 can be different from the second diameter D2. For example, the first diameter D1 can be greater than the second diameter D2.

[0041] In some embodiments, the support pattern 9p may include inner sidewalls defining a single support hole (eg, the first support hole H1 or the second support hole H2), and these inner sidewalls of the support pattern 9p may define the circumference of the first circle C1, such as Figure 3B In some embodiments, the support pattern 9p may include three inner sidewalls defining a single third support hole H3, and these inner sidewalls of the support pattern 9p may define the circumference of the second circle C2, as shown in FIG. Figure 3B shown.

[0042] The support pattern 9p can be as follows Figure 4 As shown, the top surface has a top surface coplanar with the top surface of the bottom electrode 13, or as shown Figure 2 The support pattern 9p may have a top surface lower than the top surface of the bottom electrode 13. Figure 4 or Figure 2 A single layer structure as shown, or a multi-layer structure having multiple layers at different levels.

[0043] Figure 5A , 6A , 7A, 8A and Fig. 9A Shows the display manufacturing has Figure 3A A plan view of a semiconductor device of the method of the present invention is a plan view of the semiconductor device of the method. Figure 5B , 6B , 7B, 8B and Fig. 9B The Figure 5A , 6A , 7A, 8A and Fig. 9A A cross-sectional view taken along lines AA' and BB'.

[0044] Reference Figure 5A and Figure 5B , the landing pad 11 and the separation dielectric pattern 3 may be formed on the semiconductor substrate 1. It should be understood that in addition to the landing pad 11 and the separation dielectric pattern 3, other components (such as Figure 2). The etch stop layer 5, the mold layer 7, and the support layer 9 may be sequentially formed on the landing pad 11 and the separated dielectric pattern 3. The mold layer 7 may be formed of a material having an etching selectivity relative to both the etch stop layer 5 and the support layer 9. For example, the mold layer 7 may be formed of a silicon oxide layer. The support layer 9, the mold layer 7, and the etch stop layer 5 may be sequentially etched to form a bottom electrode hole 12 exposing the landing pad 11. A conductive layer may be formed to fill (e.g., partially fill or completely fill) the bottom electrode hole 12, and a back etch process and / or a chemical mechanical polishing (CMP) process may be performed to form a bottom electrode 13 in the bottom electrode hole 12. The bottom electrode 13 may be arranged in a honeycomb shape HB. For example, when the centers of six bottom electrodes 13 adjacent to (or substantially equally spaced apart from) one bottom electrode 13 and surrounding the one bottom electrode 13 are connected, a hexagon may be obtained. The bottom electrode 13 may include a first bottom electrode 13a, a second bottom electrode 13b, and a third bottom electrode 13c.

[0045] Reference Fig. 6A and Figure 6B , a first mask layer 15 may be formed on the support layer 9. The first mask layer 15 may include a material having an etching selectivity relative to the support layer 9, such as a polysilicon layer, a silicon carbon nitride layer, and / or a silicon oxynitride layer. A second mask pattern 17 may be formed on the first mask layer 15. The second mask patterns 17 may be spaced apart from each other and each may have a circular shape when viewed in a plan view. The second mask pattern 17 may be formed of a material having an etching selectivity relative to the first mask layer 15, which material may include, for example, a photoresist pattern, a spin-on hard mask (SOH) layer, a spin-on carbon (SOC) layer, and / or an amorphous carbon layer (ACL). One second mask pattern 17 may be arranged to overlap three third bottom electrodes 13c adjacent to each other at the same time. At least one bottom electrode 13 may be arranged between the second mask patterns 17 and not overlap the second mask pattern 17. The total number of the second mask patterns 17 may be less than the total number of the support holes H1, H2, and H3 to be formed later. The interval or shortest distance between the second mask patterns 17 may be greater than the interval or shortest distance between the supporting holes H1, H2 and H3 to be formed later (eg, the shortest distance between the first hole H1 and the second hole H2 closest to the first hole H1). The second mask pattern 17 may be formed by using an immersion lithography apparatus.

[0046] The third mask layer 15 may be conformally formed on the first mask layer 15 and then anisotropically etched to form a mask spacer 19 covering the sidewalls of the second mask pattern 17. The mask spacer 19 may be formed of a material having an etching selectivity relative to both the first mask layer 15 and the second mask pattern 17, such as a silicon oxide layer. When viewed in a plan view, the mask spacers 19 may each have a ring shape. The mask spacers 19 may contact each other. The mask spacer 19 may have an edge overlapping the first bottom electrode 13a. The second bottom electrode 13b may be spaced apart from both the edge of the mask spacer 19 and the second mask pattern 17. In some embodiments, in the example Fig. 6A In the illustrated plan view, the second bottom electrode 13 b may be spaced apart from both the edge of the mask spacer 19 and the second mask pattern 17 .

[0047] The first space S1 and the second space S2 may be formed between the mask spacers 19, and the first mask layer 15 may be exposed. For example, the first space S1 may be formed between three mask spacers 19 adjacent to each other. The second space S2 spaced apart from the first space S1 may be formed between another three mask spacers 19 adjacent to each other. When viewed in a plan view, the first space S1 and the second space S2 may each have a triangular shape. The first bottom electrode 13a may overlap an edge of the first space S1. The second bottom electrode 13b may be adjacent to an edge of the second space S2.

[0048] Reference Fig. 7A and Figure 7B , an isotropic etching process may be performed so that the second mask pattern 17 may be selectively removed to form a third space S3 surrounded by the mask spacer 19 and exposing the first mask layer 15. The third space S3 may expose the inner sidewall of the mask spacer 19. When viewed in a plan view, the third space S3 may have a circular shape. The third space S3 may have an edge overlapping three third bottom electrodes 13c adjacent to each other.

[0049] Reference Fig. 7A , Figure 7B , Fig. 8A and Figure 8B, the first mask layer 15 may be etched using the mask spacer 19 as an etching mask to form a first mask pattern 15p. In this case, the first space S1 and the second space S2 may be transferred onto the first mask pattern 15p to form a triangular first opening OP1 and a triangular second opening OP2. In addition, the third space S3 may be transferred onto the first mask pattern 15p to form a circular third opening OP3. The first opening OP1 may expose portions of the top surfaces of the three first bottom electrodes 13a adjacent to each other, and may also expose the top surface of the support layer 9 between the first bottom electrodes 13a. The second opening OP2 may expose portions of the top surfaces of the three second bottom electrodes 13b adjacent to each other, and may also expose the top surface of the support layer 9 between the second bottom electrodes 13b. The third opening OP3 may expose portions of the top surfaces of the three third bottom electrodes 13c adjacent to each other, and may also expose the top surface of the support layer 9 between the third bottom electrodes 13c.

[0050] Reference Fig. 8A , Figure 8B , Fig. 9A and Fig. 9B , the support layer 9 may be etched using the first mask pattern 15p as an etching mask to form a support pattern 9p. In this case, the first opening OP1 and the second opening OP2 may be transferred to the support pattern 9p to form a first support hole H1 that is approximately triangular and a second support hole H2 that is approximately triangular. In addition, the third opening OP3 may be transferred to the support pattern 9p to form a third support hole H3 that is approximately circular. The first support hole H1 may expose portions of the side walls of the three first bottom electrodes 13a that are adjacent to each other, and may also expose the top surface of the mold layer 7 between the first bottom electrodes 13a. The second support hole H2 may expose portions of the side walls of the three second bottom electrodes 13b that are adjacent to each other, and may also expose the top surface of the mold layer 7 between the second bottom electrodes 13b. The third support hole H3 may expose portions of the side walls of the three third bottom electrodes 13c that are adjacent to each other, and may also expose the top surface of the mold layer 7 between the third bottom electrodes 13c.

[0051] Subsequently, an isotropic etching process may be performed to remove the mold layer 7 through the support holes H1, H2, and H3, thereby exposing the surface of the support pattern 9p, the surface of the bottom electrode 13, and the surface of the etch stop layer 5. In this case, the support pattern 9p may reduce or possibly prevent the collapse of the bottom electrode 13. The dielectric layer 31 and the top electrode 33 may be sequentially formed.

[0052] In the present inventive concept, the following process options may be selected to control the size and shape of the first support hole H1 , the second support hole H2 , and the third support hole H3 .

[0053] The improvement of the isotropy or anisotropy of the etching gas may control the size and shape of the first supporting hole H1 , the second supporting hole H2 , and the third supporting hole H3 .

[0054] For example, when forming the first mask pattern 15p or when forming the support pattern 9p, the improvement of the directionality of the etching gas (ie, the etchant) can allow the first support hole H1, the second support hole H2, and the third support hole H3 to have shapes that are almost identically transferred from the initial shapes of the first space S1, the second space S2, and the third space S3. In this case, the first support hole H1 and the second support hole H2 can be shaped as a triangle.

[0055] When forming the first mask pattern 15p or the support pattern 9p, the improvement of the isotropy of the etching gas (ie, the etchant) can form the first support hole H1 and the second support hole H2 into a nearly circular shape, such as Figure 3B In this case, depending on the etching degree of the first mask pattern 15p or the support pattern 9p, the first support hole H1 and the second support hole H2 may be formed to have a size different from that of the third support hole H3.

[0056] In some embodiments, in order to increase the planar size (eg, width) of the support holes H1 , H2 , and H3 , a process may be additionally performed to reduce the size of the mask spacers 19 before etching the first mask layer 15 .

[0057] In some embodiments, when the support layer 9 is etched to form the support pattern 9p, an over-etching process may be performed on the support layer 9 so that the etchant may hit the top surface of the mold layer 7 and then may move laterally to widen the first support hole H1, the second support hole H3, and the third support hole H3. Figure 3B When viewed in the plan view shown in FIG. 1 , the first support hole H1 and the second support hole H2 may be formed in an approximately circular shape. Figure 3A The first support hole H1 and the second support hole H2 may be formed in an approximately triangular shape when viewed in the plan view shown.

[0058] In some embodiments, the thickness of the first mask layer 15 can be adjusted to control the size and shape of the first support hole H1, the second support hole H2, and the third support hole H3. The increase in the thickness of the first mask layer 15 can form the first support hole H1 and the second support hole H2 to be Figure 3B The first mask layer 15 has a substantially circular shape when viewed in the plan view shown in FIG. The reduction in thickness of the first mask layer 15 can form the first support hole H1 and the second support hole H2 into a substantially circular shape when viewed in the plan view shown in FIG. Figure 3A The approximately triangular shape when viewed in plan view is shown.

[0059] In the present inventive concept, because the intervals or the shortest distances between the second mask patterns 17 are greater than the intervals or the shortest distances between the support holes H1, H2, and H3 (e.g., the shortest distance between the first support hole H1 and the second support hole H2 closest to the first support hole H1), the second mask pattern 17 can be formed by using a relatively low-priced immersion lithography apparatus instead of a relatively high-priced EUV exposure apparatus. As a result, the manufacturing cost can be reduced.

[0060] In addition, the mask spacer 19 may be used to form the support holes H1, H2, and H3 that expose the side surfaces of all the bottom electrodes 13. Therefore, when an etching process is used to remove the mold layer 7 through the support holes H1, H2, and H3, the etching process may be performed so that the etchant may have a uniform concentration regardless of the position and the bottom electrode 13 may not be over-etched. In addition, when forming the dielectric layer 31 and the top electrode 33, the source gas may have a uniform concentration regardless of the position, and thus the dielectric layer 31 and the top electrode 33 may each be formed to have a regular thickness (e.g., a uniform thickness) as a whole. As a result, the semiconductor device may be manufactured to have improved reliability.

[0061] The semiconductor device according to the inventive concept may be configured such that the support holes of the support pattern expose the sidewalls of all the bottom electrodes, which may lead to an improvement in the reliability of the semiconductor device.

[0062] Furthermore, in the method of manufacturing a semiconductor device according to the inventive concept, the second mask pattern may be formed by using a relatively low-priced immersion lithography apparatus instead of a relatively high-priced EUV exposure apparatus, which may lead to a reduction in manufacturing cost.

[0063] Although the present invention has been described in conjunction with some of the example embodiments of the inventive concept illustrated in the accompanying drawings, it will be appreciated by those skilled in the art that various changes and modifications may be made without departing from the scope of the inventive concept. It will be apparent to those skilled in the art that various possible modifications and changes may be made to the example embodiments of the inventive concept without departing from the scope of the inventive concept.

[0064] This application claims the priority benefit of Korean Patent Application No. 10-2019-0096895 filed on August 8, 2019 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: a plurality of vertical structures on a substrate; as well as a support pattern contacting sidewalls of the plurality of vertical structures, in The support pattern includes a plurality of support holes extending through the support pattern, The plurality of supporting holes include a plurality of first supporting holes, a plurality of second supporting holes and a plurality of third supporting holes, Around each of the third supporting holes at the center of the hexagon, three first supporting holes of the plurality of first supporting holes and three second supporting holes of the plurality of second supporting holes are spaced apart from each other and arranged in an alternating order, The centers of the three first supporting holes and the three second supporting holes overlap with the vertices of the hexagon, respectively; and Each of the first supporting holes has a shape or size different from a shape or size of each of the second supporting holes.

2. The semiconductor device according to claim 1, wherein When viewed in plan, the support pattern includes a first inner sidewall defining each of the first support holes and defining a circumference of a circle, and When viewed in a plan view, the support pattern includes second inner side walls that define each of the second support holes and respectively define sides of a triangle.

3. The semiconductor device according to claim 1, wherein When viewed in plan view, the support pattern comprises a first inner sidewall defining each of the first support holes and defining a circumference of a first circle, When viewed in plan view, the support pattern includes a second inner sidewall defining each of the second support holes and defining a circumference of a second circle; and A diameter of the first circle is different from a diameter of the second circle. 4 . The semiconductor device of claim 1 , wherein the sidewall of each of the plurality of vertical structures includes a portion defining a corresponding supporting hole of the plurality of supporting holes. 5 . The semiconductor device according to claim 1 , wherein the plurality of vertical structures include three vertical structures adjacent to each other, and the three vertical structures define each of the first supporting holes or each of the second supporting holes.

6. The semiconductor device according to claim 1, wherein When viewed in plan view, the support pattern comprises a first inner side wall defining each of the first support holes and defining a circumference of a circle, When viewed in plan view, the support pattern includes a second inner side wall, the second inner side wall defines each of the second support holes and respectively defines the sides of the first triangle, When viewed in plan, the support pattern includes a third inner sidewall that defines each of the third support holes and respectively defines sides of the second triangle, and When viewed in a plan view, one of the first support holes, one of the second support holes, and one of the third support holes are adjacent to each other and arranged along a first direction, with the one of the first support holes being between the one of the second support holes and the one of the third support holes.

7. A semiconductor device comprising: a plurality of word lines in the substrate and parallel to each other; a plurality of first impurity regions and a plurality of second impurity regions in the substrate, wherein one of the plurality of first impurity regions and the plurality of second impurity regions is between two adjacent word lines among the plurality of word lines, and the plurality of first impurity regions and the plurality of second impurity regions are spaced apart from each other; a plurality of bottom electrodes on the substrate and electrically connected to the plurality of first impurity regions respectively; a plurality of storage node contacts, wherein each of the plurality of storage node contacts electrically connects a corresponding bottom electrode of the plurality of bottom electrodes to a corresponding first impurity region of the plurality of first impurity regions; a plurality of landing pads, wherein each of the plurality of landing pads is between a corresponding storage node contact of the plurality of storage node contacts and a corresponding bottom electrode of the plurality of bottom electrodes; a plurality of bit lines on the substrate and electrically connected to the plurality of second impurity regions, respectively, the plurality of bit lines crossing the plurality of word lines; a plurality of bit line contacts, wherein each of the plurality of bit line contacts is between a corresponding bit line of the plurality of bit lines and a corresponding second impurity region of the plurality of second impurity regions; as well as a support pattern in contact with a first portion of a sidewall of each of the plurality of bottom electrodes; in The support pattern includes a plurality of support holes, and the second portion of the sidewall of each of the plurality of bottom electrodes defines a corresponding support hole of the plurality of support holes, The plurality of supporting holes include a plurality of first supporting holes, a plurality of second supporting holes and a plurality of third supporting holes, Around each of the third supporting holes at the center of the hexagon, three first supporting holes of the plurality of first supporting holes and three second supporting holes of the plurality of second supporting holes are spaced apart from each other and arranged in an alternating order, The centers of the three first supporting holes and the three second supporting holes overlap with the vertices of the hexagon respectively. When viewed in plan, the support pattern includes a first inner sidewall defining each of the first support holes and defining a circumference of a circle, and When viewed in a plan view, the support pattern includes second inner side walls that define each of the second support holes and respectively define sides of a triangle. 8 . The semiconductor device according to claim 7 , wherein the plurality of bottom electrodes include three bottom electrodes adjacent to each other, and the three bottom electrodes define each of the first supporting holes among the plurality of supporting holes.

9. The semiconductor device according to claim 7, further comprising bit line spacers on corresponding sidewalls of the plurality of bit lines, Each of the bit line spacers includes a first sub-spacer and a second sub-spacer, and the first sub-spacer and the second sub-spacer are spaced apart from each other by a gap region between the first sub-spacer and the second sub-spacer.

10. The semiconductor device according to claim 7, wherein the triangle is a first triangle, When viewed in plan, the support pattern includes a third inner sidewall that defines each of the third support holes and respectively defines sides of the second triangle, and When viewed in a plan view, each of the second supporting holes and each of the third supporting holes have different respective shapes.

11. The semiconductor device according to claim 10, wherein When viewed in a plan view, one of the first support holes, one of the second support holes, and one of the third support holes are adjacent to each other and arranged along a first direction, and the one of the first support holes is between the one of the second support holes and the one of the third support holes.

12. The semiconductor device according to claim 7, further comprising a plurality of separation dielectric patterns, wherein one of the plurality of separation dielectric patterns is interposed between two adjacent landing pads among the plurality of landing pads, and Wherein top surfaces of the plurality of separated dielectric patterns are coplanar with top surfaces of the plurality of landing pads.

13. A method for manufacturing a semiconductor device, the method comprising: forming a molding layer and a supporting layer on a substrate; forming a plurality of vertical structures extending through the support layer and the molding layer and including six vertical structures arranged in a honeycomb shape when viewed in a plan view; forming a first mask layer on the support layer; forming a plurality of second mask patterns on the first mask layer, each of the plurality of second mask patterns overlapping portions of three adjacent vertical structures and having a circular shape when viewed in a plan view; forming a plurality of mask spacers on the first mask layer, wherein each of the plurality of mask spacers is on a sidewall of a corresponding second mask pattern among the plurality of second mask patterns, wherein the plurality of mask spacers contact each other, and wherein the first mask layer is exposed to a first space between three adjacent mask spacers; removing the plurality of second mask patterns to form a plurality of second spaces exposing the first mask layer; forming a first mask pattern by etching the first mask layer using the plurality of mask spacers as an etching mask; as well as forming a plurality of supporting holes in the supporting layer by etching the supporting layer using the first mask pattern as an etching mask, wherein each of the plurality of mask spacers has a ring shape when viewed in a plan view, and The sidewall of each of the plurality of vertical structures includes a portion defining a corresponding support hole of the plurality of support holes.

14. The method of claim 13, wherein the plurality of support holes comprises: a first supporting hole formed when the first space is transferred to the supporting layer; as well as a plurality of second supporting holes, the plurality of second supporting holes being formed when the second space is transferred to the supporting layer, Wherein the first supporting hole has a shape or size different from a shape or size of each of the plurality of second supporting holes.

15. The method according to claim 14, wherein When viewed in plan, the support layer includes a first inner sidewall defining the first support hole and defining a circumference of a circle, and When viewed in a plan view, the support layer includes second inner sidewalls that define a single second support hole among the plurality of second support holes and respectively define sides of a triangle.

16. The method according to claim 14, wherein When viewed in plan view, the support layer includes a first inner sidewall defining the first support hole and defining a circumference of a first circle, When viewed in plan view, the support layer includes a second inner sidewall defining a single second support hole of the plurality of second support holes and defining a circumference of a second circle; and A diameter of the first circle is different from a diameter of the second circle.

17. The method according to claim 13, wherein Etching the first mask layer or etching the support layer includes performing anisotropic etching to form one or more of the plurality of support holes having a triangular shape, or Etching the first mask layer or etching the support layer includes performing isotropic etching to form the plurality of support holes having a circular shape. 18 . The method of claim 13 , wherein etching the support layer comprises over-etching the support layer to form the plurality of support holes having a circular shape.

Images