Vertical memory device

Abstract

A vertical memory device is provided, the vertical memory device comprising: a substrate having a cell region, a through-via region located on opposite sides of the cell region, and a molding region surrounding the cell region and the through-via region; gate electrodes spaced apart from each other along a first direction perpendicular to an upper surface of the substrate and extending in a second direction parallel to the upper surface of the substrate; a channel extending along the first direction on the cell region and extending through at least a portion of the stacked gate electrodes; and a first molding comprising first and second layers alternately and repeatedly stacked along the first direction on the molding region, the first and second layers comprising insulating materials different from each other, and each second layer of the first molding being located at the same height and in contact with a corresponding one of the gate electrodes.

Description

[0001] Korean Patent Application No. 10-2019-0095919, entitled “VERTICAL MEMORY DEVICE AND METHOD OF MANUFACTURING VERTICAL MEMORY DEVICE,” filed on August 7, 2019 in the Korean Intellectual Property Office is hereby incorporated by reference in its entirety. Technical Field

[0002] Embodiments relate to vertical memory devices and methods of manufacturing vertical memory devices. Background Art

[0003] In a method for manufacturing a VNAND flash memory device, an insulating layer and a sacrificial layer may be alternately and repeatedly stacked on a substrate including a chip region and a scribe line (S / L) region to form a mold layer, and an etching process may be performed to pattern the mold layer into a stepped shape. As the etching process is performed, a portion of the mold layer formed on the S / L region may be removed, and an insulating interlayer may be formed to fill the removed portion of the mold layer. The number of levels of the mold layer may be increased, and the thickness of the insulating interlayer may also be increased correspondingly thereto. Summary of the invention

[0004] According to example embodiments, a vertical memory device is provided. The vertical memory device may include: a substrate including a cell region, a through-hole region formed on each of two sides of the cell region, and a molding region surrounding the cell region and the through-hole region; a gate electrode structure including gate electrodes stacked to be spaced apart from each other along a first direction substantially perpendicular to an upper surface of the substrate, each gate electrode extending in a second direction substantially parallel to the upper surface of the substrate; a channel extending along a first direction on the cell region of the substrate and extending through at least a portion of the gate electrode structure; and a first molding including a first layer and a second layer alternately and repeatedly stacked along the first direction on the molding region of the substrate, the first layer and the second layer including insulating materials different from each other. Each first layer of the first molding may be formed at the same height and in contact with a corresponding gate electrode in the gate electrode of the gate electrode structure.

[0005] According to example embodiments, a vertical memory device is provided. The vertical memory device may include: a gate electrode structure including gate electrodes stacked on a substrate to be spaced apart from each other along a first direction substantially perpendicular to an upper surface of the substrate, each gate electrode extending in a second direction substantially parallel to an upper surface of the substrate, and the gate electrode structures being spaced apart from each other in a third direction substantially parallel to the upper surface of the substrate and intersecting the second direction; a channel extending along a first direction on the substrate and extending through at least a portion of the gate electrode structure; and a first molding including a first layer and a second layer alternately and repeatedly stacked along a first direction on the substrate, and contacting at least one of the gate electrode structures formed at both ends in the third direction. Each gate electrode structure may have a stepped shape, each gate electrode as each stepped step layer, and a portion of the first molding opposite to the gate electrode structure may have a stepped shape, a first layer and a second layer sequentially stacked together as each stepped step layer. The first layer included in each stepped step layer of the first molding and the stepped step layer corresponding thereto in the stepped step layer of the gate electrode structure may be formed at the same height as each other.

[0006] According to an example embodiment, a vertical memory device is provided. The vertical memory device may include: a circuit pattern located on a substrate; a base pattern located on the circuit pattern; a gate electrode structure including gate electrodes stacked on the base pattern along a first direction substantially perpendicular to an upper surface of the substrate to be spaced apart from each other, each gate electrode extending in a second direction substantially parallel to the upper surface of the substrate, and the gate electrode structures being spaced apart from each other in a third direction substantially parallel to the upper surface of the substrate and intersecting the second direction; a channel extending along the first direction on the base pattern and extending through at least a portion of the gate electrode structure; a charge storage structure located on an outer sidewall of each channel; a common source pattern (CSP) formed between gate electrode structures adjacent to each other in the third direction, each a first molding member including a first layer and a second layer alternately and repeatedly stacked along the first direction on the base pattern and contacting with a side wall of at least one of the gate electrode structures formed at both ends in the third direction; a second molding member formed between adjacent gate electrode structures formed on a central portion of the third direction among the gate electrode structures, extending in the second direction and including a first pattern and a second pattern alternately and repeatedly stacked along the first direction, the first pattern and the second pattern respectively including substantially the same material as the first layer and the second layer; and a through via extending along the first direction between the gate electrode structure and the first molding member and electrically connected to the circuit pattern.

[0007] According to example embodiments, a method for manufacturing a vertical memory device is provided. The method may include: alternately and repeatedly stacking insulating layers and sacrificial layers along a first direction to form a mold layer on a substrate, the substrate including a cell region, a through-hole region formed on each of both sides of the cell region, a mold region surrounding the cell region and the through-hole region, and a scribe line (S / L) region surrounding the mold region, the first direction being substantially perpendicular to an upper surface of the substrate; removing a portion of the mold layer formed on the through-hole region and portions of the cell region and the mold region adjacent to the through-hole region to form a first mold and a second mold, the first mold being formed on the mold region and the S / L region, and the second mold being formed on the cell region; forming a channel extending through the second mold; forming an opening extending through the second mold; and replacing each sacrificial layer included in the second mold with a gate electrode through the opening.

[0008] According to example embodiments, a method for manufacturing a vertical memory device is provided. The method may include: alternately and repeatedly stacking insulating layers and sacrificial layers along a first direction to form a mold layer on a substrate along the first direction, the first direction being substantially perpendicular to an upper surface of the substrate; forming a first opening extending through the mold layer to partially remove the mold layer, a portion of the mold layer surrounding the first opening having a stepped shape; forming a channel extending through the mold layer; forming a second opening extending through the mold layer; and replacing the sacrificial layers included in the mold layer with gate electrodes through the second openings, respectively. When the sacrificial layers are replaced with gate electrodes, the sacrificial layers included in edge portions of the mold layer may not be replaced.

[0009] According to example embodiments, a method for manufacturing a vertical memory device is provided. The method may include: alternately and repeatedly stacking insulating layers and sacrificial layers along a first direction to form a mold layer on a substrate along the first direction, the first direction being substantially perpendicular to an upper surface of the substrate; partially removing the mold layer to form a plurality of first openings along a second direction substantially parallel to the upper surface of the substrate, each first opening extending through the mold layer and extending in a third direction substantially parallel to the upper surface of the substrate and intersecting the second direction, a portion of the mold layer surrounding each first opening having a stepped shape; forming a channel extending through a portion between the first openings of the mold layer and extending in the first direction; forming a plurality of second openings extending through the portion of the mold layer and extending in the second direction; forming a plurality of molds spaced apart from each other along the third direction; and replacing the sacrificial layers included in the plurality of molds with gate electrodes respectively through the second openings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Features will become apparent to those skilled in the art by describing exemplary embodiments in detail with reference to the accompanying drawings, in which:

[0011] Figures 1 to 5A plan view and a perspective view of a vertical memory device according to example embodiments are shown.

[0012] Figures 6 to 25 Plan views and cross-sectional views illustrate stages in a method of fabricating a vertical memory device according to example embodiments.

[0013] Fig.26 , Fig.27A and Fig.27B A plan view and a perspective view of a vertical memory device according to example embodiments are shown.

[0014] Figures 28 to 33 A plan view and a perspective view of a vertical memory device according to example embodiments are shown.

[0015] Fig.34 and Fig.35 A cross-sectional view of a vertical memory device according to example embodiments is shown. DETAILED DESCRIPTION

[0016] A vertical memory device and a method of manufacturing the vertical memory device according to example embodiments will be described more fully hereinafter with reference to the accompanying drawings.

[0017] Hereinafter, a vertical direction substantially perpendicular to the upper surface of the substrate is defined as a first direction, and two directions intersecting each other among horizontal directions substantially parallel to the upper surface of the substrate are defined as a second direction and a third direction, respectively. In example embodiments, the second direction and the third direction may be orthogonal to each other.

[0018] Figures 1 to 5 1 is a plan view and a perspective view showing a vertical memory device according to an example embodiment. Specifically, Figure 1 , Figure 2 and Figure 4 It is a floor plan. Figure 3 and Figure 5 It is a perspective view.

[0019] Figure 2 and Figure 4 They are Figure 1 The plane graph of area X and area Y, Figure 3 and Figure 5 They are Figure 1 A perspective view of area X and area Y. Figure 3 and Figure 5 In all perspective views of FIG. 1 , components such as an insulating interlayer, a cover pattern, a CSP, etc. are not shown to avoid complexity of the drawings.

[0020] Reference Figure 1, the substrate 100 may include a first region I and a second region II surrounding the first region I. A plurality of first regions I of the substrate 100 may be formed along each of the second direction and the third direction, and the second region II of the substrate 100 may be formed to surround each of the first regions I. For example, Figure 1 As shown in , the plurality of first regions I may be arranged to be spaced apart from each other in a matrix pattern in each of the second direction and the third direction.

[0021] The substrate 100 may include, for example, silicon, germanium, silicon-germanium, or a III-V compound such as GaP, GaAs, GaSb, etc. In some embodiments, the substrate 100 may be, for example, a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0022] The first region I of the substrate 100 may be a chip region in which a semiconductor chip is formed, and the second region II of the substrate 100 may be a scribe line (S / L) region surrounding the chip region. In example embodiments, an alignment key for aligning an exposure mask used in a photolithography process to a correct position, a test element group (TEG) for detecting a leakage current of a vertical memory device, and the like may be formed on the second region II of the substrate 100.

[0023] In an example embodiment, the vertical memory device may have a cell over peri (COP) structure. That is, the circuit pattern for driving the memory cell formed in the cell area included in the first region I of the substrate 100 may not be formed around the memory cell, but may be formed below the memory cell. Therefore, the circuit pattern area (i.e., where the circuit pattern is formed) and the cell area may be vertically stacked on the substrate 100, and the circuit pattern may be referred to as a lower circuit pattern. However, the embodiment is not limited thereto, and even when the vertical memory device has a COP structure, the peripheral circuit area (i.e., where a portion of the circuit pattern is formed) may be further formed around the cell area.

[0024] Reference Figure 2 and Figure 4 , the first region I of the substrate 100 may include third to fifth regions III, IV and V. Note that, Figure 2 Shows Figure 1 Detailed and enlarged plan view of region X (i.e., a single first region I surrounded by a portion of the second region II), and Figure 4 Shows Figure 1 Detailed and enlarged plan view of region Y (ie, portions of two adjacent first regions I separated by a portion of a second region II).

[0025] Reference Figure 2 and Figure 4, the third region III of the substrate 100 may be a cell region where a memory cell is formed. In example embodiments, a plurality of third regions III may be formed on the substrate 100 along each of the second direction and the third direction. For example, Figure 2 As shown in , two third regions III may be formed in one first region I to be adjacent to each other along the second direction.

[0026] In the following, it is shown Figure 1 In the plan view of the region X, the third region III formed at the left side may be referred to as the first unit region, and the third region III formed at the right side may be referred to as the second unit region. Figure 1 In the plan view of the region Y, the third region III formed at the left side may be referred to as a second unit region, and the third region III formed at the right side may be referred to as a third unit region.

[0027] The fourth region IV of the substrate 100 may be a through-via region in which a through-via connected to the lower circuit pattern is formed, and may be formed on both sides of the third region III in the second direction. In example embodiments, a plurality of fourth regions IV of the substrate 100 may be formed along the second direction, and each fourth region IV of the substrate 100 may extend in the third direction.

[0028] The fifth region V of the substrate 100 may be a region surrounded by the second region II while surrounding the third region III and the fourth region IV. The molding may remain after patterning the molding layer in the fifth region V of the substrate 100, and thus the fifth region V may be referred to as a molding region. The fifth region V of the substrate 100 may have a shape similar to a quadrilateral ring in a plan view. In example embodiments, the fifth region V of the substrate 100 may surround both sides of the third region III in the third direction, one side of the fourth region IV in the second direction, and both sides of the fourth region IV in the third direction.

[0029] Reference Figure 3 and Figure 5 , the gate electrode structure 360 ​​may be formed on the third region III of the substrate 100, and the first molding member 207 may be formed on the second region II and the fifth region V of the substrate 100. For example, Figure 3 As shown in , each gate electrode structure 360 ​​may be located between two trenches along the second direction (ie, between two fourth regions IV). Figure 3 As shown in , the first molding 207 may surround each gate electrode structure 360 ​​, for example, the first molding 207 may surround each gate electrode structure 360 ​​and the trenches adjacent thereto.

[0030] In example embodiments, a portion of the gate electrode structure 360 ​​surrounding the fourth region IV and a portion of the first molding 207 surrounding the fourth region IV may form a stepped structure together. Figure 3 and Figure 5 As shown in FIG. 1 , the sidewalls of the gate electrode structure 360 ​​and the first molding 207 facing the fourth region IV may include a step structure, for example, a step structure descending from the top of the gate electrode structure 360 ​​toward the bottom thereof. In example embodiments, the first molding 207 may be a step structure having a step shape toward the fourth region IV of the substrate 100, and an insulating layer 200 ( Fig.18 ) and a sacrificial layer 210 ( Fig.18 ) are sequentially stacked together as each step step layer, and the gate electrode structure 360 ​​can be a step structure with a step shape, and each gate electrode serves as each step step layer. In this specification, each layer of the step structure is defined as a "step step layer", and a portion formed on each of the two ends of the step step layer that does not overlap with the step step layer above in the first direction is defined as a "step step".

[0031] In example embodiments, the sacrificial layer 210 included in the step-step layer of the first mold 207 may be formed at the same level as the step-step layer of the gate electrode structure 360 ​​corresponding to the sacrificial layer 210, and the slope of the sacrificial layer 210 included in the step-step layer of the first mold 207 may be the same as the slope of the step-step layer of the gate electrode structure 360. In example embodiments, the sacrificial layer 210 included in the step-step layer of the first mold 207 may be connected to the step-step layer of the gate electrode structure 360 ​​corresponding to the sacrificial layer 210.

[0032] In example embodiments, the third molding 209 may be formed on a middle portion of the third region III of the substrate 100 in the third direction and may extend in the second direction between the gate electrode structures 360 adjacent to each other. The third molding 209 may include insulating patterns 205 ( Fig.13 ) and sacrificial pattern 215 ( Fig.13 ).

[0033] In example embodiments, similar to the first molding 207, the third molding 209 may also be in a stepped shape, and one insulating pattern 205 and one sacrificial pattern 215 are sequentially stacked together as each stepped layer. In example embodiments, the sacrificial pattern 215 included in the stepped layer of the third molding 209 may be connected to the stepped layer of the gate electrode structure 360 ​​corresponding to the sacrificial pattern 215.

[0034] The vertical memory device may include a first molding member 207 remaining on each of a fifth region V formed on an edge of the first region I of the substrate 100 and a second region II surrounding the first region I of the substrate 100. Therefore, in a method of manufacturing the vertical memory device described later, an insulating layer 200 and a sacrificial layer 210 having a compressive force and a tensile force, respectively, may be repeatedly stacked on the fifth region V and the second region II of the substrate 100, so that unilateral stress is not applied to the substrate 100.

[0035] Figures 6 to 25 are plan views and cross-sectional views showing stages in a method of manufacturing a vertical memory device according to an example embodiment. Specifically, Figures 7 and 8 , Fig.12 and Fig.17 For the plan view, Figure 6 , Figures 9 to 11 , Figures 13 to 16 and Figures 18 to 25 It is a cross-sectional view.

[0036] Figure 7 and Fig.12 yes Figure 1 The plane diagram of region X, Figure 8 and Fig.17 yes Figure 1 The plan view of area Y. Figure 6 , Figures 9 and 10 , Fig.13 , Fig.15 , Fig.18 and Fig. 22 is a cross-sectional view taken along the line AA' of the corresponding plan view, Fig.11 , Fig.19 and Fig.23 is a cross-sectional view taken along the line BB' of the corresponding plan view, Fig.14 , Fig.16 , Fig. 20 and Fig.24 is a cross-sectional view taken along the line CC' of the corresponding plan view, Fig.21 and Fig.25 It is a cross-sectional view taken along the line DD' of the corresponding plan view.

[0037] Reference Figure 6, a circuit pattern may be formed on the substrate 100, and a first lower insulating interlayer 130 and a second lower insulating interlayer 180 may be sequentially formed on the substrate 100 to cover the circuit pattern. The substrate 100 may include an active region and a field region (e.g., an isolation pattern 110) surrounding the active region. The isolation pattern 110 may be formed by an STI process and may include, for example, oxide. The circuit pattern may include a transistor, a lower contact plug 140, a first lower wiring 150 and a second lower wiring 170, a lower via 160, and the like.

[0038] For example, the transistor in the circuit pattern may include a lower gate structure 120 and a first impurity region 105 formed on an upper portion of the active region adjacent to the lower gate structure 120. In example embodiments, the lower gate structure 120 may include a lower gate insulating pattern, a lower gate electrode, and a lower gate mask sequentially stacked on the substrate 100.

[0039] A first lower insulating interlayer 130 may be formed on the substrate 100 to cover the transistor, and a lower contact plug 140 may extend through the first lower insulating interlayer 130 to contact the first impurity region 105 or the lower gate structure 120. A first lower wiring 150 may be formed on the first lower insulating interlayer 130 to contact an upper surface of the lower contact plug 140. A first lower via 160 and a second lower wiring 170 may be sequentially stacked on the first lower wiring 150. A second lower insulating interlayer 180 may be formed on the first lower insulating interlayer 130 to cover the first lower wiring 150, the second lower wiring 170, and the first lower via 160.

[0040] Figure 6 It is shown that the circuit pattern is formed only on the fourth region IV of the substrate 100. However, the embodiment is not limited thereto. That is, a plurality of circuit patterns may be formed on the first to fifth regions I, II, III, IV, and V of the substrate 100 along each of the second and third directions.

[0041] A base pattern 190 may be formed on the second lower insulating interlayer 180, and insulating layers 200 and sacrificial layers 210 may be alternately and repeatedly stacked on the base pattern 190 to form a mold layer. The base pattern 190 may include a semiconductor material (e.g., silicon), the insulating layer 200 may include an oxide (e.g., silicon oxide), and the sacrificial layer 210 may include a material having an etching selectivity with respect to the insulating layer 200, for example, a nitride such as silicon nitride.

[0042] Reference Figures 7 to 9, a first photoresist pattern covering the first region I and the second region II of the substrate but not covering the fourth region IV of the substrate 100 may be formed on the uppermost insulating layer 200 of the insulating layers 200. An etching process using the first photoresist pattern as an etching mask and a trimming process for reducing the area of ​​the first photoresist pattern may be alternately and repeatedly performed to etch the mold layer.

[0043] The first photoresist pattern may include a first opening that exposes only the fourth region IV of the substrate 100, and the first opening may be enlarged in size as the trimming process is repeatedly performed. Therefore, each time the trimming process is repeatedly performed, the first opening of the first photoresist pattern may be enlarged to gradually expose more portions of the third region III and the fifth region V that are adjacent to and surround the fourth region IV (e.g., to form a Figure 7 and Fig. 9 After the etching process and the trimming process, the first photoresist pattern may be removed by, for example, an ashing process and / or a stripping process.

[0044] After the etching process of the molding layer, the first molding member 207 may remain on the second region II and the fifth region V of the substrate 100 (ie, in Fig. 9 The second molding 208 may remain on the third region III of the substrate 100 (ie, on the right side of the molded part). Fig. 9 The first molding member 207 and the second molding member 208 may contact each other at a boundary between the third region III and the fifth region V of the substrate 100 to be connected to each other. For example, the first molding member 207 and the second molding member 208 may be formed at a step structure of a molding member on the left side of the substrate 100. Figure 7 The short sides of the grooves in the fourth region IV shown in FIG. 1 are connected to each other. The base pattern 190 may be exposed on the fourth region IV of the substrate through the first opening. For example, the base pattern 190 may be exposed on the first molding member 207 ( Fig. 9 ) and the second molded part 208 ( Fig. 9 ) are exposed on the fourth area IV.

[0045] In example embodiments, the second molding 208 may be a stepped structure having a stepped shape, with one insulating layer 200 and one sacrificial layer 210 sequentially stacked together as each stepped step layer, and a portion of the first molding 207 corresponding to the second molding 208 may also be a stepped structure having a stepped shape, with one insulating layer 200 and one sacrificial layer 210 sequentially stacked together as each stepped step layer. In addition, the first molding 207 and the second molding 208 formed on the portions of the third region III and the fifth region V adjacent to the fourth region IV of the substrate 100 may be a stepped structure having a stepped shape (e.g., completely) surrounding the fourth region IV (e.g., surrounding the circumference of the fourth region IV).

[0046] In example embodiments, the stepped structure formed together by the portions of the first molding 207 and the second molding 208 surrounding the fourth region IV may have a quadrilateral ring shape in a plan view in which a size gradually decreases toward the center of the fourth region IV. For example, the distance between the opposite sides of the quadrilateral ring shape may gradually decrease, for example, the distance between corresponding opposite steps in the first molding 207 and the second molding 208 may decrease as the distance from the base pattern 190 along the first direction decreases.

[0047] Reference Fig.10 and Fig.11 A first insulating interlayer 220 may be formed on the base pattern 190 to cover the sidewalls of the first molding 207 and the second molding 208. For example, the first insulating interlayer 220 may completely fill the first molding 207 and the second molding 208. Figure 7 and Fig. 9 A second insulating interlayer 230 may be formed on an upper surface of the uppermost insulating layer 200 of the insulating layers 200 and an upper surface of the first insulating interlayer 220. The first insulating interlayer 220 and the second insulating interlayer 230 may include an oxide (e.g., silicon oxide) and may be fused with the insulating layer 200 or fused with each other.

[0048] Reference Fig.12 and Fig.14 , a first mask may be formed on the second insulating interlayer 230, and the second insulating interlayer 230 and the insulating layer 200 and the sacrificial layer 210 of the substrate 100 on the third region III may be etched using the first mask as an etching mask. Thus, a channel hole extending through the second insulating interlayer 230, the insulating layer 200, and the sacrificial layer 210 may be formed to expose the upper surface of the base pattern 190.

[0049] A pillar structure filling the channel hole may be formed. That is, after removing the first mask, a selective epitaxial growth (SEG) process using the upper surface of the base pattern 190 exposed by the channel hole as a seed may be performed to form a semiconductor pattern 240 partially filling the channel hole. In an example embodiment, the upper surface of the semiconductor pattern 240 may be disposed between the upper surface and the lower surface of the insulating layer 200 at a second level from the upper surface of the base pattern 190 in the first direction in the insulating layer 200. In some cases, the process of forming the semiconductor pattern 240 may be omitted.

[0050] A first barrier layer, a charge storage layer, a tunnel insulating layer, and a first spacer layer may be sequentially formed on the sidewalls of the channel hole, the upper surface of the semiconductor pattern 240, and the upper surface of the second insulating interlayer 230. The first spacer layer may be anisotropically etched to form a first spacer remaining only on the sidewalls of the channel hole, and the first barrier layer, the charge storage layer, and the tunnel insulating layer may be etched using the first spacer as an etching mask to form a first barrier pattern 250, a charge storage pattern 260, and a tunnel insulating pattern 270 on the sidewalls of the channel hole and the semiconductor pattern 240, respectively. The upper portion of the semiconductor pattern 240 may also be removed together therewith. Each of the first barrier pattern 250, the charge storage pattern 260, and the tunnel insulating pattern 270 may have a cup shape with a central portion penetrated, and the first barrier pattern 250, the charge storage pattern 260, and the tunnel insulating pattern 270 together may form a charge storage structure 280. The first spacer layer may include nitride (eg, silicon nitride), the tunnel insulating pattern 270 and the first barrier pattern 250 may include oxide (eg, silicon oxide), and the charge storing pattern 260 may include nitride (eg, silicon nitride).

[0051] After removing the first spacer, a channel layer may be formed on the exposed semiconductor pattern 240, the tunnel insulating pattern 270, and the second insulating interlayer 230, and a filling layer may be formed on the channel layer to fill the remaining portion of the channel hole. The filling layer and the channel layer may be planarized until the upper surface of the second insulating interlayer 230 is exposed.

[0052] Filling pattern 300 may be formed to fill the remaining portion of the channel hole and may transform the channel layer into channel 290. In example embodiments, a plurality of channels 290 may be formed on the third region III of substrate 100 along each of the second and third directions and may together form a channel block and a channel array.

[0053] The filling pattern 300, the channel 290, and the upper portion of the charge storage structure 280 may be removed to form a trench, and a capping pattern 310 may be formed to fill the trench. Thus, a pillar structure including the semiconductor pattern 240, the channel 290, the charge storage structure 280, the filling pattern 300, and the capping pattern 310 may be formed in the channel hole. The channel 290 and the capping pattern 310 may include doped or undoped amorphous silicon or polycrystalline silicon.

[0054] like Fig.13 As shown in , a third insulating interlayer 320 may be formed on the second insulating interlayer 230 and the capping pattern 310, and a second mask may be formed on the third insulating interlayer 320. Fig.12 and Fig.14 As shown in , a second opening 330 extending through the second insulating interlayer 230, the third insulating interlayer 320, the insulating layer 200, and the sacrificial layer 210 and extending in the second direction on the third region III of the substrate 100 can be formed using the second mask as an etching mask to expose the upper surface of the base pattern 190. Therefore, the insulating layer 200 and the sacrificial layer 210 of the second mold 208 remaining on the third region III of the substrate 100 can be transformed into the insulating pattern 205 and the sacrificial pattern 215.

[0055] The second openings 330 formed on both edges in the third direction may be formed to be spaced apart from the fifth region V of the substrate 100 along the third direction. For example, the second opening 330 may not be formed on the middle portion of the third region III of the substrate 100 in the third direction.

[0056] Reference Fig.15 and Fig.16 , the second mask may be removed, the sacrificial pattern 215 exposed by the second opening 330 may be removed by, for example, a wet etching process to form a gap 340 between the insulating patterns 205 of each level, and a portion of the outer sidewall of the first barrier pattern 250 and the sidewall of the semiconductor pattern 240 may be exposed by the gap 340. Since the second opening 330 is formed only on the third region III of the substrate 100, only the sacrificial pattern 215 of the second molding 208 remaining on the third region III of the substrate 100 may be removed by the wet etching process ( Fig.16 ), while the sacrificial layer 210 of the first molding member 207 remaining on the second region II and the fifth region V of the substrate 100 may not be removed ( Fig.15 ).

[0057] In example embodiments, the first molding 207 may be formed on each portion of the fifth region V disposed on both sides of the third region III of the substrate 100 in the third direction. In other example embodiments, the first molding 207 may be formed only on a portion of the fifth region V disposed on one side of the third region III of the substrate 100 in the third direction.

[0058] Since the second opening 330 may not be formed on the middle portion of the third region III of the substrate 100 in the third direction, the sacrificial pattern 215 may not be removed but remain on the middle portion of the third region III of the substrate 100 to form the third molding 209 together with the insulating pattern 205. The third molding 209 may extend in the second direction on the third region III of the substrate 100.

[0059] In example embodiments, the first molding 207 may be a stepped structure having a stepped shape toward the fourth region IV of the substrate 100, and one insulating layer 200 and one sacrificial layer 210 are sequentially stacked together as each step layer. Similar to the first molding 207, the third molding 209 may also be a stepped shape, and one insulating pattern 205 and one sacrificial pattern 215 are sequentially stacked together as each step layer.

[0060] Reference Figures 17 to 21 , a second barrier layer 350 may be formed on the exposed outer sidewalls of the first barrier pattern 250, the exposed sidewalls of the semiconductor pattern 240, the inner sidewalls of the gap 340, the surface of the insulating pattern 205, the exposed upper surface of the base pattern 190, and the upper surface of the third insulating interlayer 320. A gate conductive layer may be formed on the second barrier layer 350 to fully fill the remaining portion of the gap 340. A gate barrier layer may be further formed between the second barrier layer 350 and the gate conductive layer. The second barrier layer 350 may include a metal oxide (e.g., aluminum oxide), the gate conductive layer may include a low resistance metal (e.g., tungsten, aluminum, etc.), and the gate barrier layer may include a metal nitride (e.g., titanium nitride, tantalum nitride, etc.).

[0061] The gate conductive layer may be partially removed to form a gate conductive pattern in the gap 340, and when forming the gate barrier layer, the gate barrier layer may also be removed to form a gate barrier pattern. The gate conductive pattern and the gate barrier pattern together may form a gate electrode. The gate electrodes may be stacked on a plurality of levels to be spaced apart from each other along the first direction to form a gate electrode structure 360, and each gate electrode may extend along the second direction on the third region III of the substrate 100.

[0062] In example embodiments, a plurality of gate electrode structures 360 may be formed along the third direction. That is, the gate electrode structures 360 may extend in the second direction and may be spaced apart from each other in the third direction by the second openings 330. In one embodiment, one of the gate electrode structures 360 formed on each of both ends in the third direction may contact the first molding 207.

[0063] In example embodiments, the gate electrode structure 360 ​​may contact the first molding 207 at a boundary between the third region III and the fifth region V of the substrate 100, and may contact the third molding 209 on a middle portion of the third region III of the substrate 100. In example embodiments, the gate electrode of the gate electrode structure 360 ​​may be formed at substantially the same height as the sacrificial layer 210 of the first molding 207 and the sacrificial pattern 215 of the third molding 209, respectively.

[0064] Since the gate electrode of the gate electrode structure 360 ​​is formed by replacing the sacrificial pattern 215 on the third region III of the substrate 100, and the second molding 208 including the sacrificial pattern 215 has a stepped shape, the gate electrode structure 360 ​​may also have a stepped shape, with each gate electrode as each stepped step layer. In example embodiments, the stepped step layers of the gate electrode structure 360 ​​may be formed at the same height as the sacrificial layer 210 included in the stepped step layers of the first molding 207 corresponding thereto, and the slope of the stepped step layers of the gate electrode structure 360 ​​may be the same as the slope of the sacrificial layer 210 included in the stepped step layers of the first molding 207.

[0065] The gate electrode may include first to third gate electrodes 362, 364, and 366 sequentially formed along the first direction. In example embodiments, the first gate electrode 362 may be formed on the lowest level, the third gate electrode 366 may be formed on the highest level and one level therebelow (i.e., the first level and the second level), and the second gate electrode 364 may be formed on a plurality of levels between the first gate electrode 362 and the third gate electrode 366, but the embodiment is not limited thereto.

[0066] Impurities may be implanted into an upper portion of the base pattern 190 exposed by the second opening 330 to form a second impurity region 195. A second spacer layer may be formed on an upper surface of the base pattern 190 exposed by the second opening 330, a sidewall of the second opening 330, and an upper surface of the third insulating interlayer 320, and the second spacer layer may be anisotropically etched to form a second spacer 370 on each sidewall of the second opening 330. A common source pattern (CSP) 380 may be formed on the second impurity region 195 to fill a remaining portion of the second opening 330.

[0067] In example embodiments, a first conductive layer filling the second opening 330 may be formed on the exposed upper surfaces of the second impurity region 195, the second spacer 370, and the third insulating interlayer 320, and the first conductive layer may be planarized until the upper surface of the third insulating interlayer 320 may be exposed to form a CSP 380. A portion of the second barrier layer 350 formed on the upper surface of the third insulating interlayer 320 may also be removed. The CSP 380 may be formed in the second opening 330 and may contact the upper surface of the second impurity region 195 thereunder. Each of the first to third gate electrodes 362, 364, and 366 on the same level may be separated from each other along the third direction by the CSP 380 and the second spacer 370 filling the second opening 330 extending in the second direction.

[0068] Reference Figure 22 to Figure 25 , a fourth insulating interlayer 390 may be formed on the third insulating interlayer 320, the CSP 380, the second spacer 370, and the second barrier layer 350. A first contact plug 402 may be formed extending through the third insulating interlayer 320 and the fourth insulating interlayer 390 and in contact with an upper surface of the capping pattern 310. Second to fourth contact plugs 404, 406, and 408 may be formed extending through the first to fourth insulating interlayers 220, 230, 320, and 390, the insulating pattern 205, and the second barrier layer 350 and in contact with corresponding upper surfaces of the first to third gate electrodes 362, 364, and 366.

[0069] A through via 410 may be formed extending through the first to fourth insulating interlayers 220, 230, 320, and 390, the base pattern 190, and the second lower insulating interlayer 180 and contacting the upper surface of the second lower wiring 170. After a fifth insulating interlayer is formed on the fourth insulating interlayer 390, the first to fourth contact plugs 402, 404, 406, and 408, and the through via 410, a bit line extending through the fifth insulating interlayer and contacting the upper surface of the first contact plug 402 and an upper wiring may be formed to complete the manufacture of a vertical memory device.

[0070] As described above, when the mold layer including the insulating layer 200 and the sacrificial layer 210 alternately and repeatedly stacked on the substrate 100 is patterned, the portion of the mold layer formed on the second region II and the fifth region V of the substrate 100 may not be removed, that is, may remain as the first mold 207. Therefore, since the insulating layer 200 and the sacrificial layer 210 of the first mold 207 may include oxide and nitride, respectively, the compressive force and the tensile force of each of the insulating layer 200 and the sacrificial layer 210 may offset each other, and thus the stress generated on the second region II of the substrate 100 may be reduced.

[0071] Fig.26 , Fig.27A and Fig.27B 1 is a plan view and a perspective view showing a vertical memory device according to an example embodiment. Specifically, Fig.26 yes Figure 1 The plane diagram of area Y, Fig.27A and Fig.27B yes Figure 1 A perspective view of area Y.

[0072] In addition to the alignment keys, the vertical memory device can be Figures 1 to 5 Therefore, the same reference numerals denote the same elements, and a detailed description thereof is omitted here.

[0073] Reference Fig.26 , before forming the second insulating interlayer 230, an alignment key 225 extending through the first molding 207 in the first direction may be further formed by partially removing the first molding 207 on the second region II of the substrate 100. In example embodiments, the alignment key 225 may be formed by removing the insulating layer 200 and the sacrificial layer 210 formed on all levels of the first molding 207, and the upper surface of the base pattern 190 may be exposed on the portion where the alignment key 225 is formed. Alternatively, the alignment key 225 may also be formed by removing the insulating layer 200 from the uppermost insulating layer to the insulating layer of a certain level.

[0074] Fig.26 The alignment key 225 is shown to have a rectangular shape in a plan view, however, the embodiment is not limited thereto. That is, in a plan view, the alignment key 225 may also have various shapes other than a rectangular shape.

[0075] also, Fig.26 It is shown that one alignment key 225 is formed on the second region II of the substrate 100 , however, the embodiment is not limited thereto. That is, a plurality of alignment keys 225 may be formed on the second region II of the substrate 100 , and may be formed on the first region I of the substrate 100 .

[0076] Reference Fig.27A , an etching process using a third mask may be performed to partially remove the first molding member 207 from the second region II. Thus, the alignment key 225 may have a sidewall substantially perpendicular to the upper surface of the substrate 100.

[0077] Reference Fig.27B, an etching process using the second photoresist pattern and a trimming process for reducing the area of ​​the second photoresist pattern may be alternately and repeatedly performed to partially remove the first molding member 207. Therefore, the alignment key 225 may be formed to have a stair shape with one insulating layer 200 and one sacrificial layer 210 sequentially stacked together as each stair step layer.

[0078] Figures 28 to 33 1 is a plan view and a perspective view showing a vertical memory device according to an example embodiment. Specifically, Fig.28 , Fig.30 and Fig.32 yes Figure 1 The plane diagram of region X, Fig.29 , Fig.31 and Fig.33 yes Figure 1 A perspective view of area X.

[0079] In addition to the shape of the first molding, the vertical memory device can be Figures 1 to 5 Therefore, the same reference numerals denote the same elements, and a detailed description thereof is omitted here.

[0080] Reference Fig.28 and Fig.29 , the first molding 207 may be formed on a portion of the fifth region V disposed on each of both sides of the first unit region in the third direction (wherein the first unit region is formed at the left side in the third region III of the substrate 100), and may be formed on a portion of the fifth region V disposed on one side of the second unit region in the third direction (wherein the second unit region is formed at the right side in the third region III of the substrate 100). Therefore, the first molding 207 may completely surround both sides of the first unit region in the third direction, but may partially surround only one side of the second unit region in the third direction.

[0081] In execution and Figures 6 to 9 After a process substantially the same as or similar to the process of the present invention, the first molding 207 may be formed by performing an etching process using a fourth mask, and an etching process using the fourth mask may be performed to remove a portion of the first molding 207 on one side of the second unit region. The portion of the first molding 207 removed from the second region II and the fifth region V of the substrate 100 may be used as an alignment key.

[0082] Reference Fig.30 and Fig.31, the first molding 207 may be formed on a portion of the fifth region V disposed on each of the two sides of the first unit area in the third direction, and may not be formed on a portion of the fifth region V disposed on each of the two sides of the second unit area in the third direction. Therefore, the first molding 207 may completely surround both sides of the first unit area in the third direction, but may not surround both sides of the second unit area in the third direction.

[0083] In execution and Figures 6 to 9 After a process substantially the same as or similar to the process of the first molding member 207, a trimming process and an etching process using a third photoresist pattern may be performed to form the first molding member 207, and a trimming process and an etching process using the third photoresist pattern may be performed to remove portions of the first molding member 207 from both sides of the second unit region.

[0084] In example embodiments, the remaining portion of the first molding 207 on each of both sides of the second cell region may have a stair shape, with one insulating layer 200 and one sacrificial layer 210 sequentially stacked together as each stair step layer.

[0085] In example embodiments, the sacrificial layer 210 included in the step-step layer of the remaining portion of the first molding 207 on each of both sides of the second cell region may be formed at the same height as the step-step layer of the gate electrode structure 360 ​​corresponding thereto and the sacrificial layer 210 included in the step-step layer of the first molding 207, and may have a slope substantially the same as that of the step-step layer of the gate electrode structure 360 ​​and the sacrificial layer 210 included in the step-step layer of the first molding 207. The removed portions of the first molding 207 on the second region II and the fifth region V of the substrate 100 may serve as an alignment key.

[0086] Reference Fig.32 and Fig.33 , the first molding 207 may not be formed on a portion of the fifth region V disposed on each of all sides of the first unit region in the second and third directions, and may be formed only on a portion of the fifth region V disposed on all sides of the second unit region except a side of the second unit region opposite to the first unit region. Therefore, the first molding 207 may not surround all sides of the first unit region, and may surround all sides of the second unit region except one side. In performing Figures 6 to 9 The first molding member 207 may be formed by performing a trimming process and an etching process using the fourth photoresist pattern after performing processes substantially the same as or similar to the processes of the first and second photoresist patterns, and the trimming process and the etching process using the fourth photoresist pattern may be performed only on the first cell region.

[0087] Fig.34 and Fig.35 is a cross-sectional view illustrating a vertical memory device according to example embodiments. Fig.34 and Fig.35 It is a cross-sectional view taken along the line AA' of the corresponding plan view.

[0088] Except for the shape of the portion of the first molding on the fifth region of the substrate, the vertical memory device may be similar to Figures 1 to 5 Therefore, the same reference numerals denote the same elements, and detailed descriptions thereof are omitted here.

[0089] Reference Fig.34 , among the portions of the stepped structure surrounding the fourth region IV of the substrate 100 , the portion on the fifth region V of the substrate 100 may have a steeper slope than that of the portion on the third region III of the substrate 100 .

[0090] Reference Fig.35 , among the portion of the step structure surrounding the fourth region IV of the substrate 100 , a portion on the fifth region V of the substrate 100 may not have a step shape.

[0091] In example embodiments, a portion of the first molding 207 extending in the third direction and formed on the fifth region V of the substrate 100 adjacent to the fourth region IV may have a sidewall substantially perpendicular to the upper surface of the substrate 100 .

[0092] By way of summary and review, when the insulating interlayer is made of a single material of an oxide having a compressive force or a nitride having a tensile force, the stress generated on the S / L region is increased. Therefore, a stress difference occurs between the S / L region and the chip region, and thus a test using a test element group (TEG) formed on the S / L region has limited accuracy.

[0093] In contrast, example embodiments provide a vertical memory device with improved characteristics. Example embodiments provide a method for manufacturing a vertical memory device with improved characteristics. That is, in the method for manufacturing a vertical memory device according to example embodiments, when an etching process is performed to pattern a mold layer including an insulating layer and a sacrificial layer alternately and repeatedly stacked on a substrate including a chip region and an S / L region, a portion of the mold layer formed on the S / L region may not be removed. Therefore, since a mold layer including an insulating layer and a sacrificial layer having a compressive force and a tensile force, respectively, may remain on the S / L region as in the chip region, the stress generated on the S / L region may be reduced, and since the S / L region has a stress similar to that of the chip region, a test using a test element group (TEG) formed on the S / L region may be accurately performed.

[0094] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a general and descriptive sense only, and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art from the time of filing this application, unless otherwise specifically stated, the features, characteristics, and / or elements described in conjunction with a specific embodiment may be used alone or in combination with the features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the claims.

Claims

1. A vertical memory device, the vertical memory device comprising: a substrate including a cell region, through-hole regions on two opposite sides of the cell region, and a molding region surrounding the cell region and the through-hole region; a gate electrode structure including gate electrodes on a substrate, the gate electrodes being stacked to be spaced apart from each other along a first direction substantially perpendicular to an upper surface of the substrate, and each gate electrode extending in a second direction substantially parallel to the upper surface of the substrate; A channel extending along a first direction on the cell region of the substrate and extending through at least a portion of the gate electrode structure; as well as A first molding part includes a first layer and a second layer alternately and repeatedly stacked along a first direction on a molding part region of a substrate, the first layer and the second layer include insulating materials different from each other, and each first layer of the first molding part is located at the same height and in contact with a corresponding gate electrode among gate electrodes included in the gate electrode structure and located on the substrate.

2. The vertical memory device of claim 1, wherein: The through via region is located on each of two opposite sides of the cell region in the second direction, and The molding area surrounds opposite sides of the through via area in a third direction substantially parallel to the upper surface of the substrate and intersecting the second direction, and surrounds at least one side of the through via area in the second direction.

3. The vertical memory device according to claim 2, wherein: The first molding is located on a portion of the molding region on each of two opposite sides of the cell region in the third direction.

4. The vertical memory device according to claim 2, wherein: The first molding is located on a portion of the molding region on one of two opposite sides of the cell region in the third direction.

5. The vertical memory device according to claim 2, wherein: The plurality of unit regions are spaced apart from each other along the second direction, and a through via region is located on each of two opposite sides of each of the plurality of unit regions in the second direction.

6. The vertical memory device according to claim 5, wherein: The first molding is located on a portion of the molding area on each of two opposite sides of a first cell area among the plurality of cell areas in the third direction and on a portion of the molding area on one side of a second cell area among the plurality of cell areas in the third direction.

7. The vertical memory device according to claim 5, wherein: The first molding is located on a portion of the molding area on at least one of both sides in the third direction of a first cell area among the plurality of cell areas, and is not located on a portion of the molding area on both sides in the third direction of a second cell area among the plurality of cell areas.

8. The vertical memory device according to claim 2, further comprising a second molding member located on a middle portion of the unit area of ​​the substrate in the third direction, the second molding member comprising first and second patterns alternately and repeatedly stacked along the first direction, and the first and second patterns respectively comprise substantially the same material as the first layer and the second layer.

9. The vertical memory device according to claim 8, wherein: The second molding has a stepped shape having a stepped step layer, one first pattern and one second pattern are sequentially stacked together as one of the stepped step layers, and the stepped shape of the second molding faces the through-hole region.

10. The vertical memory device according to claim 2, wherein: The plurality of gate electrode structures are spaced apart from each other along a third direction, and a gate electrode structure located at one end in the third direction among the plurality of gate electrode structures contacts the first molding member.

11. The vertical memory device according to claim 1, wherein: The gate electrode structure has a stepped shape having stepped step layers, each gate electrode is one of the stepped step layers, and the stepped shape of the gate electrode structure faces the through via region.

12. The vertical memory device according to claim 11, wherein: The first molding has a stepped shape having a stepped step layer, a first layer and a second layer are sequentially stacked together as one of the stepped step layers, and the stepped shape of the first molding faces the through-hole region.

13. The vertical memory device according to claim 12, wherein: The first layer in each of the step-step layers included in the first molding is located at the same height level as a corresponding step-step layer in the step-step layers of the gate electrode structure.

14. The vertical memory device of claim 13, wherein: The first layer included in each step-step layer of the first molding is connected to a corresponding step-step layer of the step-step layers of the gate electrode structure.

15. The vertical memory device of claim 12, wherein: The slope of the first layer included in the step-step layer of the first molding member is the same as the slope of the step-step layer of the gate electrode structure.

16. The vertical memory device of claim 12, wherein: The slope of the first layer included in the step-step layer of the first molding member is steeper than the slope of the step-step layer of the gate electrode structure.

17. The vertical memory device of claim 1, further comprising: a circuit pattern, located on a substrate; as well as The base pattern is located on the circuit pattern, and the gate electrode structure and the first molding member are located on the base pattern. 18 . The vertical memory device of claim 17 , further comprising a through via extending in the first direction on the through via region of the substrate, the through via being electrically connected to the circuit pattern.

19. The vertical memory device of claim 1, wherein: The first layer includes nitride and the second layer includes oxide.

20. A vertical memory device, the vertical memory device comprising: a gate electrode structure, comprising gate electrodes stacked on a substrate to be spaced apart from each other along a first direction substantially perpendicular to an upper surface of the substrate, each gate electrode extending in a second direction substantially parallel to the upper surface of the substrate, and the gate electrode structures being spaced apart from each other in a third direction substantially parallel to the upper surface of the substrate and intersecting the second direction; a channel extending in a first direction on the substrate and extending through at least a portion of at least one of the gate electrode structures; as well as a first molding including a first layer and a second layer alternately and repeatedly stacked along a first direction on a substrate and contacting at least one of the gate electrode structures at both ends in a third direction, Each gate electrode structure is in a stepped shape with stepped step layers, and each gate electrode is one of the stepped step layers in the stepped shape of the gate electrode structure. wherein a portion of the first molding member that is opposite to a corresponding gate electrode structure in the gate electrode structure is in a stepped shape having a stepped step layer, a first layer of the first layer and a second layer of the first layer and the second layer are sequentially stacked together in each stepped step layer of the stepped shape of the first molding member as a stepped step layer in the stepped step layer, and The first layer in each step-step layer in the step-step structure of the first molding and the step-step layer corresponding thereto in the step-step layer of the step-step structure of the gate electrode structure are located at the same height as each other.

21. The vertical memory device of claim 20, wherein: The first layer included in each step-step layer of the first molding and the step-step layer corresponding thereto among the step-step layers of the gate electrode structure are connected to each other.

22. The vertical memory device of claim 20, wherein: The slope of the first layer included in the step-step layer of the first molding member is the same as the slope of the step-step layer of the gate electrode structure.

23. The vertical memory device of claim 20, wherein: The slope of the first layer included in the step-step layer of the first molding member is steeper than the slope of the step-step layer of the gate electrode structure.

24. The vertical memory device of claim 20, wherein: The first molding member contacts each of the gate electrode structures at both ends in the third direction.

25. A vertical memory device, the vertical memory device comprising: a circuit pattern, located on a substrate; a substrate pattern, located on the circuit pattern; a gate electrode structure, comprising gate electrodes stacked on the base pattern to be spaced apart from each other along a first direction substantially perpendicular to an upper surface of the substrate, each gate electrode extending in a second direction substantially parallel to the upper surface of the substrate, and the gate electrode structures being spaced apart from each other in a third direction substantially parallel to the upper surface of the substrate and intersecting the second direction; a channel extending along a first direction on the base pattern and extending through at least a portion of the gate electrode structure; a charge storage structure located on the outer sidewall of each channel; a common source pattern located between gate electrode structures adjacent to each other in the third direction, each common source pattern extending in the second direction; a first molding including a first layer and a second layer alternately and repeatedly stacked along a first direction on the base pattern and contacting a sidewall of at least one of the gate electrode structures located at both ends in a third direction; a second molding member located between adjacent gate electrode structures on a central portion in the third direction among the gate electrode structures, extending in the second direction, and comprising first and second patterns alternately and repeatedly stacked along the first direction, the first and second patterns comprising substantially the same material as the first and second layers, respectively; as well as The through via extends along the first direction between the gate electrode structure and the first molding member and is electrically connected to the circuit pattern.

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