Optoelectronic semiconductor device

Abstract

An optoelectronic semiconductor device includes a semiconductor stack, an electrode, and a plurality of contacts. The semiconductor stack has a first-type semiconductor structure, an active structure on the first-type semiconductor structure, and a second-type semiconductor structure on the active structure. The first-type semiconductor structure has a first protrusion, a second protrusion, and a recess between the first protrusion and the second protrusion, and the semiconductor stack has a thickness. The electrode is on the second-type semiconductor structure and has a portion corresponding to the first protrusion. The plurality of contacts are under the first-type semiconductor structure and in contact with the first-type semiconductor structure. The electrode and one of the plurality of contacts closest to the electrode have a second distance in a horizontal direction, and a ratio of the second distance to the thickness is greater than 5.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device, and particularly to an optoelectronic semiconductor device. BACKGROUND

[0002] A semiconductor device includes a compound semiconductor composed of group III-V elements, such as gallium phosphide (GaP), gallium arsenide (GaAs), or gallium nitride (GaN), and can be a power device or an optoelectronic semiconductor device (e.g., a light emitting diode (LED), a laser diode, a photodetector, a solar cell). An LED includes a p-type semiconductor layer, an n-type semiconductor layer, and an active structure disposed between the p-type semiconductor layer and the n-type semiconductor layer, such that, under an applied electric field, electrons and holes provided by the n-type semiconductor layer and the p-type semiconductor layer, respectively, recombine in the active structure to convert electrical energy into light energy. Improving the photoelectric conversion efficiency of an optoelectronic semiconductor device is one of the focuses of research and development. SUMMARY

[0003] To solve the above problems, the present application provides an optoelectronic semiconductor device, which includes a semiconductor stack, an electrode, and a first contact structure. The semiconductor stack has a first-type semiconductor structure, an active structure on the first-type semiconductor structure, and a second-type semiconductor structure on the active structure. The first-type semiconductor structure has a first protrusion, a second protrusion, and a recess between the first protrusion and the second protrusion, and the semiconductor stack has a thickness. The electrode is on the second-type semiconductor structure and has a portion corresponding to the first protrusion. The first contact structure has a plurality of contact portions under and in contact with the first-type semiconductor structure. The electrode and one of the plurality of contact portions closest to the electrode have a second distance in a horizontal direction, and the ratio of the second distance to the thickness is greater than 5.

[0004] The present application provides another optoelectronic semiconductor device, which includes a semiconductor stack, an electrode, and a first contact structure. The semiconductor stack has a first-type semiconductor structure, an active structure on the first-type semiconductor structure, and a second-type semiconductor structure on the active structure. The first-type semiconductor structure has a first protrusion, a second protrusion, and a recess between the first protrusion and the second protrusion. The electrode is on the second-type semiconductor structure and has a portion corresponding to the first protrusion. The first contact structure has a plurality of contact portions under and in contact with the first-type semiconductor structure. The electrode and the second protrusion have a first distance in a horizontal direction, and the electrode and one of the plurality of contact portions closest to the electrode have a second distance in the horizontal direction, which is greater than the first distance. The difference between the first distance and the second distance is less than 20 μm and greater than 2 μm.

[0005] In one embodiment, the optoelectronic semiconductor device further comprises an insulating layer under the first-type semiconductor structure.

[0006] In one embodiment, the insulating layer has a plurality of openings, and each of the plurality of contact portions is located in each of the plurality of openings.

[0007] In one embodiment, the optoelectronic semiconductor device further comprises a recess formed in the first-type semiconductor structure, such that the first-type semiconductor structure comprises a first protrusion, a second protrusion, and a recessed portion, the recess has a first width and a first height, and a ratio of the first width to the first height is greater than 3 and less than 8.

[0008] In one embodiment, the optoelectronic semiconductor device comprises a plurality of protrusions and a plurality of recessed portions, and each of the plurality of recessed portions is located between two adjacent protrusions, and the plurality of recessed portions has a first total surface area, and the first-type semiconductor structure has an upper surface facing the active structure, and the first total surface area accounts for 15% to 40% of an upper surface area of the upper surface.

[0009] In one embodiment, the optoelectronic semiconductor device comprises a plurality of protrusions, and the plurality of protrusions has a second total surface area, and the plurality of contact portions has a third total surface area, and the third total surface area accounts for 15% to 30% of the second total surface area.

[0010] In one embodiment, the optoelectronic semiconductor device further comprises a first conductive oxide layer under the first-type semiconductor structure and covering the plurality of contact portions.

[0011] In one embodiment, the material of the plurality of contact portions is a III-V semiconductor compound.

[0012] In one embodiment, each of the contact portions has a thickness greater than a thickness of the insulating layer.

[0013] In one embodiment, each of the contact portions has a surface away from the first-type semiconductor structure and a sidewall connecting the surface, and the first conductive oxide layer covers the surface and a portion of the sidewall.

[0014] In one embodiment, each of the contact portions has a surface away from the first-type semiconductor structure and a sidewall connecting the surface, and the first conductive oxide layer covers the surface and the sidewall and contacts the second protrusion.

[0015] In one embodiment, the optoelectronic semiconductor device further comprises a second conductive oxide layer under the first conductive oxide layer and covering the first conductive oxide layer, and the material of the second conductive oxide layer is different from the material of the first conductive oxide layer.

[0016] In one embodiment, the optoelectronic semiconductor device further comprises a metal layer under the second conductive oxide layer and covering the second conductive oxide layer.

[0017] In one embodiment, the optoelectronic semiconductor device further comprises a first conductive oxide layer under the insulating layer and in contact with the insulating layer.

[0018] In one embodiment, the optoelectronic semiconductor device further comprises an insulating layer covering the first protrusion, the second protrusion, and the recess, the insulating layer having an opening over the second protrusion, a plurality of contact portions in the opening, and the insulating layer not in contact with the plurality of contact portions.

[0019] In one embodiment, the first protrusion has a thickness of 0.5 μm to 2 μm, and the recess has a thickness of 0.01 μm to 1 μm.

[0020] In one embodiment, the first thickness is 4.5 μm to 6.5 μm.

[0021] In one embodiment, the optoelectronic semiconductor device further comprises a second contact structure disposed on a window layer of the second type semiconductor structure.

[0022] In one embodiment, each of the contact portions has a second width, the recess has a third width, and a sum of the second widths is 5% to 50% of the fifth width. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 Partial cross-sectional view of an optoelectronic semiconductor device of one embodiment;

[0024] Figure 2 Top view of an optoelectronic semiconductor device of one embodiment;

[0025] Figures 3-4 Bottom view of a structure completed in a step of a fabrication process of an optoelectronic semiconductor device of one embodiment;

[0026] Figure 5 Partial cross-sectional view of an optoelectronic semiconductor device of one embodiment;

[0027] Figure 6 Partial cross-sectional view of an optoelectronic semiconductor device of one embodiment illustrating a partial cross-sectional view of an optoelectronic semiconductor device according to one embodiment;

[0028] Figure 7A Partial top view of an optoelectronic semiconductor device of one embodiment;

[0029] Figure 7B Partial top view of an optoelectronic semiconductor device of one embodiment;

[0030] Figure 8 Encapsulation structure of an optoelectronic semiconductor device of one embodiment.

[0031] REFERENCE NUMERALS

[0032] 100, 200, 300, 400, 500 optoelectronic semiconductor device

[0033] 1 semiconductor stack 11 first semiconductor structure

[0034] 111 first protrusion 112 second protrusion

[0035] 113 recess 114 protrusion

[0036] 115 recess structure 116 groove

[0037] 117 third protrusion 118 fourth protrusion

[0038] 1a first side 1b second side

[0039] 1c third side 1d fourth side

[0040] 12 active structure 13 second semiconductor structure

[0041] 14 window layer 141 light exit surface

[0042] 15 second contact structure 2 first contact structure

[0043] 21 contact 22 contact group

[0044] 3 upper electrode 31 electrode pad

[0045] 32 first extension electrode 33 second extension electrode

[0046] 4 substrate 5 reflection structure

[0047] 51 first insulating layer 511 opening

[0048] 52 first conductive oxide layer 53 second conductive oxide layer

[0049] 531 second plane 54 metal layer

[0050] 541 first plane 55 second insulating layer

[0051] 551 second opening

[0052] 6 conductive adhesive layer 7 lower electrode

[0053] 8 protective layer 900 encapsulation structure

[0054] 91 encapsulation substrate 92 via

[0055] 93 carrier 93a first portion

[0056] 93b second portion 95 bonding wire

[0057] 96 contact structure 96a, 96b contact pad

[0058] 98 encapsulation material T1 first thickness

[0059] T2 second thickness T3 third thickness

[0060] S lower surface S1 first bottom surface

[0061] S2 second bottom surface S3 third bottom surface

[0062] S4 first side surface S5 second side surface

[0063] S6 surface S7 sidewall

[0064] H height θ1 first included angle

[0065] θ2 second included angle W1 first width

[0066] W2 second width W3 third width

[0067] W4 fourth width W5 fifth width

[0068] W6 fourth width W7 fourth width

[0069] D1 first distance D2 second distance

[0070] P walkway DETAILED DESCRIPTION

[0071] In order to make the above object, features, and advantages of the present disclosure more comprehensible, below, preferred embodiments are specifically described, and the accompanying drawings are used for detailed description as follows:

[0072] Figure 1 Partially cross-sectional schematic view of a photoelectric semiconductor device 100 according to an embodiment of the present disclosure, Figure 2 Top view schematic view of a photoelectric semiconductor device 100 according to an embodiment of the present disclosure, Figure 2 The structure of the A-A' line section in Figure 1 The cross-sectional view of the photoelectric semiconductor device 100 is shown. As shown in Figure 1 and Figure 2 The photoelectric semiconductor device 100 includes a semiconductor stack 1, a first contact structure 2 located below the semiconductor stack 1, and an upper electrode 3 (refer to Figure 2 The upper electrode 3 includes an electrode pad 31, a first extension electrode 32, and a second extension electrode 33. Figure 1Only the second extension electrode 33 is drawn. The optoelectronic semiconductor device 100 can optionally be provided with a substrate 4 and a reflective structure 5. The reflective structure 5 is arranged between the substrate 4 and the semiconductor stack 1 to reflect light generated by the semiconductor stack 1 in the direction of the second extension electrode 33, thereby increasing the light emission efficiency.

[0073] The semiconductor stack 1 can be a p-n structure or a p-i-n structure. In one embodiment, the semiconductor stack 1 comprises a first-type semiconductor structure 11, an active structure 12 arranged on the first-type semiconductor structure 11, and a second-type semiconductor structure 13 arranged on the active structure 12, in other words, the active structure 12 and the second-type semiconductor structure 13 are arranged in sequence on the first-type semiconductor structure 11 in a stacking direction (i.e. the Y direction in the drawing, or a direction substantially perpendicular to the X axis). In one embodiment, the optoelectronic semiconductor device 100 is a light emitting device, the semiconductor stack 1 is a light emitting stack, and the first-type semiconductor structure 11 and the second-type semiconductor structure 13 are, for example, cladding layers and / or confinement layers, and have a larger energy gap than the active structure 12, thereby increasing the probability of the combination of electrons and holes in the active structure 12 to emit light. Depending on the material, the active structure 12 can emit a light having a peak wavelength of 200 nm to 1800 nm, for example, infrared light having a peak wavelength of 700 nm to 1700 nm, red light having a peak wavelength of 610 nm to 700 nm, yellow light having a peak wavelength of 530 nm to 570 nm, green light having a peak wavelength of 490 nm to 550 nm, blue or dark blue light having a peak wavelength of 400 nm to 490 nm, or ultraviolet light having a peak wavelength of 250 nm to 400 nm. In this embodiment, the active structure 12 emits red light having a peak wavelength of 610 nm to 700 nm.

[0074] The first-type semiconductor structure 11 and the second-type semiconductor structure 13 can be single-layered or multi-layered and have different first and second conductivities, respectively, to provide holes and electrons, respectively, or to provide electrons and holes, respectively. In an embodiment, the first-type semiconductor structure 11 and the second-type semiconductor structure 13 can selectively include a Bragg reflector (DBR). The semiconductor stack 1 can include a single heterostructure or a double heterostructure. The active structure 12 can include multiple quantum wells. The materials of the first-type semiconductor structure 11, the second-type semiconductor structure 13 and the active structure 12 are III-V compound semiconductors, such as GaAs, InGaAs, AlGaAs, AlInGaAs, GaP, InGaP, AlInP, AlGaInP, GaN, InGaN, AlGaN, AlInGaN, AlAsSb, InGaAsP, InGaAsN, AlGaAsP, etc. In embodiments of the present application, unless otherwise specified, the above chemical formulas include "chemically-dose-compliant compounds" and "non-chemically-dose-compliant compounds", wherein the "chemically-dose-compliant compounds" are, for example, compounds in which the total element dose of the group III elements is the same as the total element dose of the group V elements, and the "non-chemically-dose-compliant compounds" are, for example, compounds in which the total element dose of the group III elements is different from the total element dose of the group V elements. For example, the chemical formula AlGaAs represents a compound including the group III elements aluminum (Al) and gallium (Ga) and the group V element arsenic (As), wherein the total element dose of the group III elements (aluminum and gallium) can be the same as or different from the total element dose of the group V element (arsenic). In addition, when each of the above compounds represented by the chemical formula is a chemically-dose-compliant compound, AlGaAs represents Al x1 Ga 1-x1 As, wherein the aluminum content x can comply with 0 < x1 < 1; AlInP represents Al x2 In 1-x2 P, wherein the aluminum content x can comply with 0 < x2 < 1; AlGaInP represents (Al y1 Ga 1-y1 ) 1-x3 In x3 P, wherein 0 < x3 < 1, 0 < y1 < 1; AlGaN represents Al x4 Ga 1-x4 N, wherein the aluminum content x4 can comply with 0 < x4 < 1; AlAsSb represents AlAs x5 Sb 1-x5 , wherein 0 < x5 < 1; InGaP represents In x6 Ga 1-x6P, where 0 < x6 < 1; InGaAsP represents In x7 Ga 1-x7 As 1-y2 P y2 , where 0 < x7 < 1, 0 < y2 < 1; InGaAsN represents In x8 Ga 1-x8 As 1- y3 N y3 , where 0 < x8 < 1, 0 < y3 < 1; AlGaAsP represents Al x9 Ga 1-x9 As 1-y4 P y4 , where the aluminum content x can satisfy 0 < x9 < 1, 0 < y4 < 1; InGaAs represents In x10 Ga 1-x10 As, where 0 < x10 < 1.

[0075] As shown Figure 1 , a groove 116 is formed in the first-type semiconductor structure 11 and makes the first-type semiconductor structure 11 include a first convex portion 111, a second convex portion 112, and a concave portion 113. The first convex portion 111 has a first thickness T1 and the concave portion 113 has a second thickness T2 less than the first thickness T1. In this embodiment, the second convex portion 112 has a thickness approximately equal to the thickness of the first convex portion​​The second protrusion 112 has a third bottom surface S3 facing away from the second semiconductor structure 13. The first protrusion 111 has a first side surface S4 connecting the first bottom surface S1 and the second bottom surface S2, and the second protrusion 112 has a second side surface S5 connecting the second bottom surface S2 and the third bottom surface S3. The first side surface S4, the second side surface S5 and the second bottom surface S2 together define a groove 116, and the first side surface S4 faces the second side surface S5. The first side surface S4 is not perpendicular to the first bottom surface S1, and the second side surface S5 is not perpendicular to the third bottom surface S3. In detail, the first side surface S4 and the first bottom surface S1 have a first included angle θ1 between 100° and 165°, and the second side surface S5 and the third bottom surface S3 have a second included angle θ2 between 100° and 165°. The reflective structure 5 is disposed under the first protrusion 111, the second protrusion 112 and the recess 113 of the first semiconductor structure 11, and the first bottom surface S1, the second bottom surface S2, the third bottom surface S3, the first side surface S4 and the second side surface S5 are all covered by the reflective structure 5. Therefore, when the light emitted by the active structure 12 travels toward the reflective structure 5, the light is reflected by the reflective structure 5 and is emitted toward the photoelectric semiconductor device 100 in the direction of the second extended electrode 33. In detail, when the light emitted by the active structure 12 travels toward the reflective structure 5, the light is reflected by the side surfaces S4, S5 and the bottom surfaces S1, S2, S3 at different angles toward the light emitting surface 141, thereby reducing the probability of total reflection at the light emitting surface 141 and increasing the light extraction efficiency of the photoelectric semiconductor device 100.

[0077] Since the first side surface S4 and / or the second side surface S5 are not perpendicular to the second bottom surface S2, the groove 116 has a gradually increasing width, for example, in the present embodiment, the width of the groove 116 gradually increases in the direction away from the second semiconductor structure 13, or, in another embodiment, the width of the groove 116 gradually decreases in the direction away from the second semiconductor structure 13. The maximum width of the groove 116 is defined as a first width W1, and in addition, the groove 116 has a height H (H = T1-T2). In the present embodiment, the height H is 0.5 μm to 1.5 μm, so that the first side surface S4 and the second side surface S5 have a specific range to allow the light to be reflected at the first side surface S4 and the second side surface S5. The first width W1 and the height H have a ratio (W1 / H) greater than 3 and less than 8, for example: 3, 3.5, 4, 5, 6, 7.

[0078] As Figure 1As shown, the semiconductor stack 1 optionally further comprises a window layer 14 disposed on the second-type semiconductor structure 13, the window layer 14 being transparent to light generated by the active structure 12, for example, the window layer 14 has a bandgap greater than that of the active structure 12. In addition, the window layer 14 can increase the light extraction efficiency and / or the uniformity of current spreading of the optoelectronic semiconductor device 100. The thickness of the window layer 14 is greater than 1500 nm and less than 4000 nm, for example, 1500 nm, 2000 nm, 2500 nm, 3000 nm, 3500 nm, 4000 nm. In an embodiment, the window layer 14 has a doping concentration greater than 1 x 1016 / cm3and less than 1 x 1020 / cm3, for example, 1 x 1016 / cm3, 5 x 1016 / cm3, 1 x 1017 / cm3, 5 x 1017 / cm3, 1 x 1018 / cm3, 5 x 1018 / cm3, 1 x 1019 / cm3, 5 x 1019 / cm3, 1 x 1020 / cm3, or 5 x 1020 / cm3. 17 3 19 3 17 3 17 3 18 3 18 3 The window layer 14 comprises an outcoupling surface 141, light generated by the active structure 12 is emitted from the optoelectronic semiconductor device 100 through the outcoupling surface 141. The outcoupling surface 141 can be a rough surface to reduce the probability of total internal reflection and scatter light emitted by the semiconductor stack 1 to increase the light extraction efficiency of the optoelectronic semiconductor device 100.

[0079] The semiconductor stack 1 optionally further comprises a second contact structure 15 disposed on the window layer 14, a portion of the outcoupling surface 141 is provided with the second contact structure 15, and another portion of the outcoupling surface 141 is not provided with the second contact structure 15, and the second contact structure 15 is disposed between the window layer 14 and the second extension electrode 33. In this embodiment, the second contact structure 15 has a low resistance value with the window layer 14, for example, the resistance value between the second contact structure 15 and the window layer 14 is less than the resistance value between the second extension electrode 33 and the window layer 14. In this embodiment, the second extension electrode 33 covers the second contact structure 15, that is, the second extension electrode 33 has a third width W3 in the X-axis direction greater than the width of the second contact structure 15. The materials of the window layer 14 and the second contact structure 15 are III-V compound semiconductors, for example, GaAs, InGaAs, AlGaAs, AlInGaAs, GaP, InGaP, AlInP, AlGaInP, GaN, InGaN, AlGaN, AlInGaN, AlAsSb, InGaAsP, InGaAsN, AlGaAsP, etc.

[0080] ​​​​​​​​​​​The first contact structure 2 is disposed under the first type semiconductor structure 11, and the first contact structure 2 has a plurality of contact portions 21 separated from each other, and the plurality of contact portions 21 are located under the second protrusion 112. In this embodiment, the plurality of contact portions 21 are not disposed under the first protrusion 111 and the recess 113 (i.e., the plurality of contact portions 21 are only located under the second protrusion 112), so that most of the current flows to the plurality of contact portions 21 under the second protrusion 112 to the reflecting structure 5. In detail, the first contact structure 2 and the third bottom surface S3 of the second protrusion 112 are in contact with each other to form an electrical connection, and the material of the first contact structure 2 can be metal, alloy or semiconductor. The metal is gold (Au), silver (Ag), germanium (Ge), or beryllium (Be). The alloy is an alloy containing the above-mentioned metal. The semiconductor is a III-V semiconductor compound, such as gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), gallium phosphide (GaP), etc.

[0081] When the material of the first contact structure 2 is a III-V semiconductor compound, the first contact structure 2 can selectively contain an n-type dopant or a p-type dopant, and the doping concentration is 1 x 10 18 / cm 3 to 1 x 10 20 / cm 3 In another embodiment, the dopant concentration in each contact portion 21 increases from the direction close to the first type semiconductor structure 11 to the direction away from the first type semiconductor structure 11. In this embodiment, as viewed from the cross section of the optoelectronic semiconductor device 100, each of the plurality of contact portions 21 has a second width W2, and the third bottom surface S3 has a fifth width W5, and when the material of the first contact structure 2 is a semiconductor, the sum of the second widths W2 accounts for 5% to 50% of the fifth width W5; in another embodiment, when the material of the first contact structure 2 is metal or alloy, the sum of the second widths W2 accounts for 1% to 20% of the fifth width W5. In addition, the plurality of contact portions 21 can have the same shape and / or size, such as circular, triangular or irregular shape, and in other embodiments, the plurality of contact portions 21 have different shapes and / or sizes, and the present disclosure is not limited thereto.

[0082] Please continue Figure 1 , Figure 2As shown, a portion of the upper electrode 3 (i.e., the second extension electrode 33) corresponds to the first protrusion 111. In detail, a portion of the upper electrode 3 (i.e., the second extension electrode 33) overlaps the first protrusion 111 in the vertical direction (i.e., the Y-axis direction as shown). In the present embodiment, the projection of the second extension electrode 33 toward the first protrusion 111 is entirely within the range of the first protrusion 111, and the first side surface S4 does not overlap the second extension electrode 33 in the vertical direction. The second extension electrode 33 has a third width W3, and the first bottom surface S1 of the first protrusion 111 has a fourth width W4 greater than the third width W3, and the third bottom surface S3 of the second protrusion 112 has a fifth width W5 greater than the fourth width W4. The second extension electrode 33 and the second protrusion 112 have a first distance D1 in the horizontal direction (X-axis direction), and the second extension electrode 33 and the plurality of contact portions 21 (i.e., the contact portion closest to the second extension electrode 33) have a second distance D2 in the horizontal direction, which is greater than the first distance D1. The second distance D2 is greater than 3 μm and less than 20 μm, such as 5 μm, 8 μm, 10 μm, 12 μm, or 15 μm, so that current can be transmitted to a location away from the second extension electrode 33, and the probability of light emitted by the active structure 12 being reflected and then blocked by the second extension electrode 33 is reduced. In one embodiment, the difference (D2-D1) between the second distance D2 and the first distance D1 is less than 20 μm and greater than 2 μm, such as 15 μm, 10 μm, 8 μm, 5 μm, or 3 μm, so that light emitted by the active structure 12 can be reflected by the second side surface S5 to effectively emit light toward the light emission surface 141, thereby increasing the light extraction efficiency of the optoelectronic semiconductor device 100. In one embodiment, when the second distance D2 and the difference (D2-D1) satisfy the above descriptions, the optoelectronic semiconductor device 100 can simultaneously have the above benefits to further increase the light extraction efficiency.

[0083] In one embodiment, the second distance D2 is greater than the third thickness T3 of the semiconductor stack 1, and the ratio (D2 / T3) is greater than 5 and less than 20, such as 5, 6, 7, 8, 9, 10, 12, 14, 16, 18, or 20, so as to avoid the light emitted by the active structure 12 being blocked by the second extension electrode 33 to reduce the light emission efficiency. Similarly, when the ratio (D2 / T3) and the difference (D2-D1) satisfy the above descriptions, the optoelectronic semiconductor device 100 can simultaneously have the above benefits to further increase the light extraction efficiency. The first distance D1 described above is the absolute value (i.e., the projection onto the X-axis of the drawing) of the vector of the intersection point of the third bottom surface S3 and the second side surface S5 to the edge of the second extension electrode 33 in the horizontal direction, and the second distance D2 described above is the absolute value of the vector of the edge of the second extension electrode 33 to the edge of the closest contact portion 21 in the horizontal direction.

[0084] Figure 2Figure 1 is a top view of a light-electricity semiconductor device 100 according to an embodiment of the present disclosure. The light-electricity semiconductor device 100 includes a first contact structure 2, an upper electrode 3, and a lower electrode 4. The first contact structure 2 includes a plurality of first contact pads 21, a plurality of first contact extensions 22, and a plurality of second contact extensions 23. The upper electrode 3 includes a plurality of electrode pads 31, a plurality of first electrode extensions 32, and a plurality of second electrode extensions 33. The lower electrode 4 includes a plurality of lower electrode pads 41, a plurality of lower electrode extensions 42, and a plurality of lower electrode pads 43. The first contact pads 21 are electrically connected to the electrode pads 31, the first electrode extensions 32 are electrically connected to the second contact extensions 23, and the second electrode extensions 33 are electrically connected to the lower electrode extensions 42. The first contact pads 21, the first electrode extensions 32, the second contact extensions 23, the electrode pads 31, the first electrode extensions 32, the second electrode extensions 33, the lower electrode pads 41, the lower electrode extensions 42, and the lower electrode pads 43 are arranged in a staggered manner.

[0085] Reference is made to Figure 1 and Figure 2 , Figure 1 The third width W3 in FIG. 3 refers to the width of the second electrode extensions 33, which is merely an example of an embodiment. In another embodiment, the upper electrode can optionally not include any other extensions and the second electrode extensions 33 of FIG. 3 are the electrode pads 31. Thus, if the upper electrode 3 includes only the electrode pads 31, the third width W3 in FIG. 3 is the width of the electrode pads 31. Figure 1 Figure 1

[0086] ​​The substrate 4 can be used to support the semiconductor stack 1 and other layers or structures thereon. The semiconductor stack 1 can be grown on the substrate 4 or another growth substrate (not shown) by an epitaxial method such as metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or hydride vapor phase epitaxy (HVPE). If the semiconductor stack 1 is grown on a growth substrate, the semiconductor stack 1 can be transferred to the substrate 4 by a substrate transfer technique and the growth substrate can be optionally removed. In one embodiment, the semiconductor stack 1 is grown on a growth substrate and then transferred to the substrate 4 by a substrate transfer technique through an electrically conductive bonding layer 6. In particular, the substrate 4 can be transparent, semi-transparent, or opaque to light emitted by the active structure 12, and can be electrically conductive, semiconductive, or insulating. In the present embodiment, the optoelectronic semiconductor device 100 is of a vertical type, and thus the substrate 4 is an electrically conductive material and includes a metallic material, a metallic alloy material, a metal oxide material, a semiconductive material, or a carbon-containing material. The metallic material includes copper (Cu), aluminum (Al), chromium (Cr), tin (Sn), gold (Au), nickel (Ni), titanium (Ti), platinum (Pt), lead (Pb), zinc (Zn), cadmium (Cd), antimony (Sb), molybdenum (Mo), tungsten (W), or cobalt (Co); the metallic alloy material includes an alloy of the above-mentioned metallic materials; the metal oxide material can include, but is not limited to, indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO), indium zinc oxide (IZO), gallium oxide (Ga2O3), lithium gallate (LiGaO2), lithium aluminate (LiAlO2), or magnesium aluminate (MgAl2O4); the semiconductive material can include, but is not limited to, a group IV semiconductor or a group III-V semiconductor, such as silicon (Si), germanium (Ge), silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), gallium phosphide (GaP), gallium arsenide (GaAs), gallium arsenide phosphide (AsGaP), zinc selenide (ZnSe), zinc selenide (ZnSe), or indium phosphide (InP); and the carbon-containing material can include, but is not limited to, a diamond-like carbon (DLC) film or graphene.

[0087] The reflective structure 5 includes a first insulating layer 51 and a first conductive oxide layer 52 disposed under and covering the first insulating layer 51. The first insulating layer 51 conformally covers the first protrusions 111, the recesses 113, and the second protrusions 112. In the present embodiment, the first insulating layer 51 is in contact with the first bottom surface S1, the second bottom surface S2, the third bottom surface S3, the first side surface S4, and the second side surface S5. In the present embodiment, the first insulating layer 51 includes a plurality of openings 511 to expose the plurality of contact portions 21, and each opening 511 exposes each contact portion 21. Each contact portion 21 has a surface S6 facing away from the first semiconductor structure 11 and a sidewall S7 connected to the surface S6. The first insulating layer 51 physically contacts the sidewalls S7 of the plurality of contact portions 21. Each of the plurality of contact portions 21 has a thickness greater than a thickness of the first insulating layer 51, such that the plurality of contact portions 21 protrude out of the first insulating layer 51 at the third bottom surface S3. In the present embodiment, the thickness of the plurality of contact portions 21 is 0.05 μm to 0.5 μm, such as 0.08 μm, 0.12 μm, 0.15 μm, 0.18 μm, 0.2 μm, 0.22 μm, 0.25 μm, 0.28 μm, 0.3 μm, 0.4 μm, or 0.5 μm. In an embodiment, each of the plurality of contact portions 21 has a thickness less than the thickness of the first insulating layer 51. The thickness of the plurality of contact portions 21 can be designed according to a peak wavelength of the optoelectronic semiconductor device 100, such as 0.2 μm to 0.4 μm for red light with a peak wavelength between 610 nm and 700 nm, and 0.05 μm to 0.08 μm for infrared light with a peak wavelength between 700 nm and 1700 nm.

[0088] In the present embodiment, the reflective structure 5 can further include a second conductive oxide layer 53 covering the first conductive oxide layer 52, and the second conductive oxide layer 53 has a different material from the first conductive oxide layer 52. Specifically, in the present embodiment, the first conductive oxide layer 52 has a material of indium tin oxide, and the second conductive oxide layer 53 has a material of indium zinc oxide. The second conductive oxide layer 53 has a different thickness from the first conductive oxide layer 52, such as a thickness of the first conductive oxide layer 52 being much smaller than a thickness of the second conductive oxide layer 53 in an embodiment. In another embodiment, the first conductive oxide layer 53 is discontinuously distributed under the first semiconductor structure 11.

[0089] The first oxidized conductive layer 52 conformally covers the first insulating layer 51 and the plurality of contact portions 21 exposed by the plurality of openings 511, and the first oxidized conductive layer 52 is in contact with the plurality of contact portions 21. The first oxidized conductive layer 52 covers the surface S6 and / or the partial sidewall S7 of the contact portion 21. In another embodiment, the reflective structure 5 optionally does not include the first oxidized conductive layer 52, the second oxidized conductive layer 53 covers the first insulating layer 51 and conformally covers the first protrusion 111, the recess 113 and the second protrusion 112, and the second oxidized conductive layer 53 covers the surface S6 and / or the partial sidewall S7 of the contact portion 21.

[0090] The reflective structure 5 further includes a metal layer 54 located below and covering the second oxidized conductive layer 53, and the metal layer 54 has a first plane 541 in the Y-axis direction away from the second extension electrode 33, i.e., the distance from the first plane 541 to the first bottom surface S1 is less than the distance from the first plane 541 to the second bottom surface S2.

[0091] The optoelectronic semiconductor device 100 of the present disclosure further includes a lower electrode 7 located below the substrate 4, and the upper electrode 3 and the lower electrode 7 are respectively arranged on opposite sides of the semiconductor stack 1 to form a vertical optoelectronic semiconductor device 100. The materials of the upper electrode 3 and the lower electrode 7 can include metal materials or metal alloy materials, for example, the metal materials can include but are not limited to aluminum (Al), chromium (Cr), copper (Cu), tin (Sn), gold (Au), nickel (Ni), titanium (Ti), platinum (Pt), lead (Pb), zinc (Zn), cadmium (Cd), antimony (Sb) or cobalt (Co), and the metal alloy materials include alloys of the above-mentioned metals. In addition, the optoelectronic semiconductor device 100 can further include a protective layer 8 covering the light-emitting surface 141 to prevent external water vapor or contaminants from entering the semiconductor stack 1 to change the optoelectronic properties of the optoelectronic semiconductor device 100. In order to facilitate subsequent electrical connection, the protective layer 8 can optionally expose the electrode pads 31 and / or the extension electrodes 32, 33.

[0092] The material of the first insulating layer 51 described above includes a non-conductive material. The non-conductive material includes an organic material or an inorganic material. The organic material includes Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy, acrylic resin, cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide or fluorocarbon polymer. The inorganic material includes silicone or glass, aluminum oxide (Al2O3), silicon nitride (SiN x ), silicon oxide (SiOx ), titanium oxide (TiO x ), or magnesium fluoride (MgF x ). In one embodiment, the first insulating layer 51 comprises one or more sub-layers (e.g., a Bragg reflector (DBR) structure formed by alternately stacking two sub-layers, such as SiO x , TiO x , or MgF2.

[0093] The first and second conductive oxide layers 52 and 53 are transparent to the emitted light from the semiconductor stack 1, and can comprise a metal oxide material such as indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO), magnesium oxide (MgO), or indium zinc oxide (IZO).

[0094] The metal layer 54 can comprise, but is not limited to, a metal material or a metal alloy material, such as copper (Cu), aluminum (Al), tin (Sn), gold (Au), silver (Ag), lead (Pb), titanium (Ti), nickel (Ni), platinum (Pt), tungsten (W), or an alloy comprising any of the foregoing materials.

[0095] The material of the conductive bonding layer 6 can include a conductive material, such as a metal oxide material, a semiconductor material, a metal material, a metal alloy material, or a carbon-containing material. For example, the metal oxide material can include, but is not limited to, indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), zinc oxide (ZnO), indium cerium oxide (ICO), indium tungsten oxide (IWO), indium titanium oxide (ITiO), indium zinc oxide (IZO), indium gallium oxide (IGO), gallium and aluminum codoped zinc oxide (GAZO). The semiconductor material can include, but is not limited to, gallium phosphide (GaP). The metal material can include, but is not limited to, copper (Cu), aluminum (Al), tin (Sn), gold (Au), silver (Ag), lead (Pb), titanium (Ti), nickel (Ni), indium (In), platinum (Pt), or tungsten (W). The metal alloy material is an alloy including the above-mentioned metal materials. The carbon-containing material can include, but is not limited to, graphene. The conductive bonding layer 6 can connect the substrate 4 to the reflective structure 5, and can have a plurality of sub-layers (not shown).

[0096] Figure 3 and Figure 4 are bottom views of a step of manufacturing Figure 1 a photoelectric semiconductor device 100, respectively. In manufacturing the photoelectric semiconductor device 100, first, a semiconductor stack and a first contact structure 2 are formed on a growth substrate (not shown) in sequence. As shown in Figure 3 , the first contact structure 2 includes a plurality of contact groups 22 (such as the structures within the rectangular dashed lines in Figure 3 ) that are separated from each other, and each contact group 22 includes a plurality of contact portions 21 that are separated from each other. A walkway P is provided between two adjacent contact groups 22, corresponding to a position where a second extension electrode 33 is to be formed, and the width Wp of the walkway P is greater than the third width W3 of the second extension electrode 33. Any two of the plurality of contact groups 22 can have the same or different number and arrangement of the plurality of contact portions 21. In this embodiment, the plurality of contact portions 21 are formed on the semiconductor stack in a two-dimensional arrangement, and the plurality of contact groups 22 are parallel to each other. The first contact structure 2 can be formed by photolithography and etching.

[0097] After the step of Figure 3 , as shown in Figure 4As shown, multiple grooves 116 can be formed in the first-type semiconductor structure 11 by dry etching or wet etching, and multiple protrusions 114 and multiple recesses 113 can be defined, wherein the multiple recesses 113 can be defined as recess structure 115 (see also). Figure 1 Each recess 113 is located between two adjacent protrusions 114 and corresponds to the position of each groove 116. The plurality of protrusions 114 include a plurality of first protrusions 111, a plurality of second protrusions 112, a plurality of third protrusions 117, and a plurality of fourth protrusions 118. One of the plurality of recesses 113 is located between the first protrusion 111 and the second protrusion 112, and the first protrusion 111 corresponds to the position forming the passageway P, and the second protrusion 112 is offset from the passageway P. Viewed from above, the semiconductor stack 1 has a first side 1a, a second side 1b relative to the first side 1a, a third side 1c connecting the first side 1a and the second side 1b, and a fourth side 1d relative to the third side 1c. A plurality of third protrusions 117 are disposed near the first side 1a and the second side 1b, and a subsequent first extension electrode 32 is formed on the plurality of third protrusions 117. A plurality of fourth protrusions 118 are disposed near the third side 1c and the fourth side 1d, and are parallel to the first protrusions 111 and the second protrusions 112. The plurality of third protrusions 117 are perpendicular to the plurality of fourth protrusions 118. The plurality of third protrusions 117 are interconnected with the plurality of first protrusions 111 and the plurality of fourth protrusions 118.

[0098] In this embodiment, viewed from above, a portion of the plurality of recesses 113 may be a closed structure (e.g., an opening shape), while a portion of the plurality of recesses 113 may be an open structure (e.g., an elliptical shape or a straight line). When a recess 113 is a closed structure, this recess surrounds a second protrusion 112. A plurality of third protrusions 117 and a plurality of fourth protrusions 118 surround a plurality of recesses 113, a plurality of first protrusions 111, and a plurality of second protrusions 112.

[0099] Reference Figure 1 and Figure 4The first protrusions 111 have a fourth width W4, and the third bottom surfaces S3 of the second protrusions 112 have a fifth width W5 greater than the fourth width W4. Preferably, the ratio of the fifth width W5 to the fourth width W4 is greater than 2 and less than 15, such as 2.5, 3, 3.25, 3.5, 3.75, 4, 4.5, 5, 7, 9, 11, 13, or 15. Each third protrusion 117 has a sixth width W6 (in the direction of the Z-axis) between the fourth width W4 and the fifth width W5, and each fourth protrusion 118 has a seventh width W7 (in the direction of the X-axis) that, in this embodiment, is not equal to the sixth width W6, such as between the sixth width W6 and the fourth width W4. In other embodiments, the seventh width W7 is equal to the sixth width W6. The plurality of recesses 113 has a first total surface area (i.e., the sum of the areas of the second bottom surfaces S2 of the recesses), and the first-type semiconductor structure 11 has an upper surface facing the lower surface S of the active structure 12, the upper surface having an upper surface area, the first total surface area being 15% to 40% of the upper surface area, such as 15%, 20%, 25%, 30%, 35%, or 40%. The plurality of protrusions 114 has a second total surface area (i.e., the sum of the areas of the bottom surfaces of the protrusions, such as the areas of the first bottom surfaces S1 plus the areas of the third bottom surfaces S3 plus…), and the plurality of contacts 21 has a third total surface area that is 15% to 30% of the second total surface area, such as 15%, 18%, 21%, 24%, 27%, or 30%. In the embodiment shown in FIG. 6, the first total surface area is 18.6% of the upper surface area, and the third total surface area is 17.2% of the second total surface area. Figure 1

[0100] Next, as shown in FIG. 5, a first insulating layer 51 having a plurality of openings 511 is formed, the plurality of openings 511 being located on the second protrusions 112 and respectively exposing the plurality of contacts 21, and the width of each opening 511 being approximately equal to the width of each contact 21. Since the width of each opening 511 is approximately equal to the width of each contact 21, a first conductive oxide layer 52 covers each contact 21 and the first insulating layer 51 without directly covering the first-type semiconductor structure 11 (i.e., the first conductive oxide layer 52 is not in physical contact with the third bottom surfaces S3). Figure 1 Figure 4 After the step of FIG. 5, a first conductive oxide layer 52, a second conductive oxide layer 53, and a metal layer 54 are sequentially formed on the first insulating layer 51. The substrate 4 and the metal layer 54 are bonded by a conductive adhesive layer 6. The growth substrate is then removed, and a lower electrode 7 is formed on the substrate 4 and an upper electrode 3 is formed on the window layer 14, respectively, to complete the fabrication of the photoelectric semiconductor device 100 as shown in FIG. 6.

[0101] After the step of FIG. 5, a first conductive oxide layer 52, a second conductive oxide layer 53, and a metal layer 54 are sequentially formed on the first insulating layer 51. The substrate 4 and the metal layer 54 are bonded by a conductive adhesive layer 6. The growth substrate is then removed, and a lower electrode 7 is formed on the substrate 4 and an upper electrode 3 is formed on the window layer 14, respectively, to complete the fabrication of the photoelectric semiconductor device 100 as shown in FIG. 6. Figure 4 Figure 1 After the step of FIG. 5, a first conductive oxide layer 52, a second conductive oxide layer 53, and a metal layer 54 are sequentially formed on the first insulating layer 51. The substrate 4 and the metal layer 54 are bonded by a conductive adhesive layer 6. The growth substrate is then removed, and a lower electrode 7 is formed on the substrate 4 and an upper electrode 3 is formed on the window layer 14, respectively, to complete the fabrication of the photoelectric semiconductor device 100 as shown in FIG. 6.

[0102] ​​​Figure 5 This is a partial cross-sectional schematic diagram of a photoelectric semiconductor device 200 according to another embodiment of the present disclosure. The photoelectric semiconductor device 200 of this embodiment is similar to... Figure 1 The photoelectric semiconductor device 100 shown generally has the same components and their interconnections, the difference being that the distribution of the first insulating layer 51 is different from that of the aforementioned photoelectric semiconductor device 100. Specifically, the first insulating layer 51 conformally covers the first protrusion 111, the recess 113, and a portion of the second protrusion 112, and has an opening 511 to expose the plurality of contact portions 21 below the second protrusion 112, and the first type semiconductor structure 11 between the plurality of contact portions 21. The first insulating layer 51 and the plurality of contact portions 21 are separated from each other and do not have physical contact. A first conductive oxide layer 52 conformally covers the first insulating layer 51, the plurality of contact portions 21, and the third bottom surface S3 of the second protrusion 112, and fills the space between the contact portions 21 and the opening 511, and between the plurality of contact portions 21, allowing the first conductive oxide layer 52 to physically contact the third bottom surface S3 of the second protrusion 112. Alternatively, in embodiments without a first oxide conductive layer 52, a second oxide conductive layer 53 is filled between the contact portion 21 and the opening 511, and between the plurality of contact portions 21, so that the second oxide conductive layer 53 can physically contact the third bottom surface S3.

[0103] Figure 6 This is a partial cross-sectional schematic diagram of a photoelectric semiconductor device 300 according to another embodiment of the present disclosure. The photoelectric semiconductor device 300 of this embodiment is similar to... Figure 1The photoelectric semiconductor device 100 shown has substantially the same elements and connection relationship between elements, the difference is that the reflective structure 5 of the photoelectric semiconductor device 300 of the present embodiment further comprises a second insulating layer 55 between the first insulating layer 51 and the first conductive oxide layer 52. The first insulating layer 51 and the second insulating layer 55 help to improve the covering force on the first protrusion 111 and the recess 113. For example, when the covering of the first insulating layer 51 on the first side surface S4 and the second side surface S5 is not good, the second insulating layer 55 also covers the side surfaces S4 and S5, so that the light emitted by the active structure 12 can be reflected at the interface between the side surfaces S4 and S5 and the reflective structure 5, thereby increasing the light extraction efficiency. The material of the second insulating layer 55 can refer to the material of the first insulating layer 51. The material of the second insulating layer 55 can be the same as or different from the material of the first insulating layer 51. In an embodiment, the refractive index of the first insulating layer 51 is less than the refractive index of the second insulating layer 55. The refractive index of the first insulating layer 51 is 1-1.5, and the refractive index of the second insulating layer 55 is 1.4-2.2. For example, the material of the first insulating layer 51 is magnesium fluoride (MgF2), and the material of the second insulating layer 55 is silicon dioxide (SiO2). The second insulating layer 55 comprises a second opening 551 larger than the first opening 511 of the first insulating layer 51, and the second insulating layer 55 and the plurality of contact portions 21 are separated from each other without physical contact.

[0104] In addition, as Figure 6 shown, the thickness (i.e. along the Y-axis direction of the drawing) of the second conductive oxide layer 53 below the recess 113 is greater than the height H of the groove 116, in other words, the second conductive oxide layer 53 has a second plane 531 away from the second extension electrode 33, and the second plane 531 is a flat surface, that is, the distance from the second plane 531 to the first bottom surface S1 is less than the distance from the second plane 531 to the second bottom surface S2. The second conductive oxide layer 53 is connected with the metal layer 54 by the second plane 531, for improving the process yield of the subsequent formation of the metal layer 54.

[0105] Figure 7A and Figure 7B are partial top view schematic diagrams of photoelectric semiconductor devices according to other embodiments of the present disclosure. In order to clearly show the relative relationship of the structures, Figure 7A and Figure 7B show the relative relationship of some structures, but in fact, some structures cannot be directly observed by the naked eye or a microscope from the top view. Figure 7A the elements and the connection relationship between elements of the photoelectric semiconductor device 400 are substantially the same as those of the photoelectric semiconductor device 100 shown in Figure 1Similar to the photoelectric semiconductor device 100 shown, the difference lies in the distribution of the first protrusion 111, the second protrusion 112, and the recess 113, as well as the shape of the opening 511. In this embodiment, the first type semiconductor structure 11 has a plurality of mutually separated second protrusions 112, and the recess 113 surrounds the plurality of second protrusions 112; furthermore, the first insulating layer 51 has a plurality of openings, and unlike the photoelectric semiconductor device 100 where each opening 511 individually exposes a contact portion 21, in this embodiment, each opening 511 simultaneously exposes multiple contact portions 21. The openings 511 and the second protrusions 112 are pentagonal in shape. Furthermore, in this embodiment, the first total surface area accounts for 38.9% of the upper surface area, and the third total surface area accounts for 22.3% of the second total surface area.

[0106] Figure 7B The components of the optoelectronic semiconductor device 500 and the connections between the components are related to Figure 7A The device is similar to the photoelectric semiconductor device 400 shown, except that the distribution of the first protrusion 111, the second protrusion 112, and the recess 113, and the shape of the opening 511 are different. Figure 7A As shown. In this embodiment, the first type of semiconductor structure 11 includes a plurality of second protrusions 112 of different shapes and separated from each other, such as triangular and rhomboid shapes, and recesses 113 surround the plurality of second protrusions 112. Furthermore, the first insulating layer 51 has a plurality of openings 511, and each opening 511 simultaneously exposes a plurality of contact portions 21. The shapes of the plurality of openings 511 and the second protrusions 112 are triangular or rhomboid. In addition, the first total surface area accounts for 32.7% of the upper surface area, and the third total surface area accounts for 25.8% of the second total surface area.

[0107] Please refer to Table 1, which compares the luminous intensity of the experimental and comparative examples disclosed herein. Experimental Example 1 is as described above. Figure 1 The optoelectronic semiconductor device 100 and Experimental Example 2 are as described above. Figure 7A The optoelectronic semiconductor device 400, and Experimental Example 3 are as described above. Figure 7B The optoelectronic semiconductor device 500 and the comparative example are mainly optoelectronic semiconductor devices with a first-type semiconductor structure that does not have multiple protrusions and multiple recesses. In other words, the first-type semiconductor structure of the comparative example does not have a groove, and the surface of the first-type semiconductor structure away from the upper electrode is a plane. As can be seen from Table 1, the optoelectronic semiconductor devices of the present disclosure in Examples 1 to 3 all have higher luminous intensity than the optoelectronic semiconductor devices of the comparative example. Furthermore, compared with the comparative example, the brightness improvement ratio of the optoelectronic semiconductor devices of Examples 1 to 3 is 1.53% to 5.7%. The brightness improvement ratio is calculated as follows, for example: the luminous intensity of the optoelectronic semiconductor device of the comparative example is P0, the luminous intensity of the optoelectronic semiconductor device of Example 1 is P1, and the brightness improvement ratio of Example 1 is [(P1-P0) / P0]×100%.

[0108] Table 1

[0109] Comparative Example Experimental Example 1 Experimental Example 2 Experimental Example 3 Luminous brightness (mW) 287.26 303.71 296.2 291.66 Brightness improvement ratio —— 5.7％ 3.1％ 1.53％

[0110] Figure 8 FIG. 9 shows a schematic diagram of a package structure of an optoelectronic semiconductor device according to an embodiment. The package structure 900 includes an optoelectronic semiconductor device 100, a package substrate 91, a carrier 93, bonding wires 95, contact structures 96, and a package material 98. The package substrate 91 can include a ceramic or a glass material. The package substrate 91 has a plurality of through holes 92 therein. The through holes 92 can be filled with a conductive material such as a metal to facilitate conduction and / or heat dissipation. The carrier 93 is disposed on a surface of one side of the package substrate 91 and also includes a conductive material such as a metal. The contact structures 96 are disposed on a surface of another side of the package substrate 91. In this embodiment, the contact structures 96 include contact pads 96a, 96b, and the contact pads 96a, 96b can be electrically connected to the carrier 93 through the through holes 92. In an embodiment, the contact structures 96 can further include a thermal pad (not shown) disposed between the contact pad 96a and the contact pad 96b. The optoelectronic semiconductor device 100 is disposed on the carrier 93 and can be any of the optoelectronic semiconductor devices described in any of the embodiments. In this embodiment, the carrier 93 includes a first portion 93a and a second portion 93b, and the optoelectronic semiconductor device 100 is electrically connected to the second portion 93b of the carrier 93 through the bonding wires 95. The bonding wires 95 can include a metal such as gold, silver, copper, aluminum, or an alloy including at least one of the foregoing. The package material 98 covers the optoelectronic semiconductor device 100 and has a protective effect on the optoelectronic semiconductor device 100. Specifically, the package material 98 can include a resin material such as an epoxy, a silicone, or the like. The package material 98 can further include a plurality of wavelength conversion particles (not shown) to convert a first light emitted by the optoelectronic semiconductor device 100 into a second light. The second light has a wavelength greater than that of the first light. In other embodiments, the optoelectronic semiconductor device 100 in the package structure 900 described above can be the optoelectronic semiconductor devices 200, 300, 400, or 500, or, in some embodiments, the package structure 900 includes a plurality of optoelectronic semiconductor devices 100, 200, 300, 400, and / or 500, and the plurality of optoelectronic semiconductor devices 100, 200, 300, 400, and / or 500 can be connected in series, in parallel, or in series-parallel. The optoelectronic semiconductor devices 100, 200, 300, 400, 500, or the package structure 900 described above can be applied in the fields of lighting elements, backlight elements, automotive lighting elements, display modules, and / or plant lighting elements, etc.

[0111] In summary, although the present application is disclosed in connection with the above embodiments, it is not intended to limit the present application. Those skilled in the art to which the present application pertains can make various modifications and improvements without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application should be defined by the appended claims.

Claims

1. An optoelectronic semiconductor device, characterized by The semiconductor stack has a first-type semiconductor structure, an active structure on the first-type semiconductor structure, and a second-type semiconductor structure on the active structure, the first-type semiconductor structure has a first protrusion, a second protrusion, and a recess between the first protrusion and the second protrusion, and the semiconductor stack has a first thickness; an electrode on the second-type semiconductor structure and having a portion corresponding to the first protrusion; and a first contact structure having a plurality of contact portions under and in contact with the first-type semiconductor structure, the electrode and one of the plurality of contact portions closest to the electrode have a second distance in a horizontal direction; wherein a ratio of the second distance to the first thickness is greater than 5. The semiconductor stack has a first-type semiconductor structure, an active structure on the first-type semiconductor structure, and a second-type semiconductor structure on the active structure, the first-type semiconductor structure has a first protrusion, a second protrusion, and a recess between the first protrusion and the second protrusion; an electrode on the second-type semiconductor structure and having a portion corresponding to the first protrusion; and 2. An optoelectronic semiconductor device, characterized by a first contact structure having a plurality of contact portions under and in contact with the first-type semiconductor structure; wherein the electrode and the second protrusion have a first distance in a horizontal direction, the electrode and one of the plurality of contact portions closest to the electrode have a second distance in the horizontal direction greater than the first distance, and a difference between the first distance and the second distance is less than 20 mm and greater than 2 mm.

3. The optoelectronic semiconductor device of claim 1 or 2, further comprising an insulating layer under the first-type semiconductor structure. The insulating layer has a plurality of openings, each of the plurality of contact portions is in each of the plurality of openings.

5. The optoelectronic semiconductor device of claim 1 or 2, further comprising a recess formed in the first-type semiconductor structure, such that the first-type semiconductor structure comprises the first protrusion, the second protrusion, and the recess, the recess has a first width and a first height, a ratio of the first width to the first height is greater than 3 and less than 8. The optoelectronic semiconductor device comprises a plurality of protrusions and a plurality of recesses, each of the plurality of recesses is between two adjacent protrusions, from a top view, the plurality of recesses has a first total surface area, the first-type semiconductor structure has an upper surface facing the active structure, the first total surface area accounts for 15% to 40% of an upper surface area of the upper surface. The optoelectronic semiconductor device comprises a plurality of protrusions, from a top view, the plurality of protrusions has a second total surface area, the plurality of contact portions has a third total surface area, the third total surface area accounts for 15% to 30% of the second total surface area.

4. The optoelectronic semiconductor device of claim 3, wherein, 8. The optoelectronic semiconductor device of claim 1 or 2, further comprising a first oxide conductive layer under the first-type semiconductor structure and covering the plurality of contact portions. The plurality of contact portions is made of a III-V semiconductor compound.

6. The optoelectronic semiconductor device of claim 1 or 2, wherein, Each of the plurality of contact portions has a thickness greater than a thickness of the insulating layer.

7. The optoelectronic semiconductor device according to claim 1 or 2, wherein ​ ​ 9. The optoelectronic semiconductor device of claim 1 or 2, wherein, ​ 10. The optoelectronic semiconductor device of claim 3, wherein, ​ 11. The optoelectronic semiconductor device of claim 8, wherein, Each of the plurality of contact portions has a surface facing away from the first-type semiconductor structure and a sidewall connecting the surface, the first conductive-oxide layer covering the surface and a portion of the sidewall.

12. The optoelectronic semiconductor device of claim 8, wherein, Each of the plurality of contact portions has a surface facing away from the first-type semiconductor structure and a sidewall connecting the surface, the first conductive-oxide layer covering the surface and a portion of the sidewall.

13. The optoelectronic semiconductor device of claim 8, further comprising a second conductive-oxide layer under the first conductive-oxide layer and covering the first conductive-oxide layer, and a material of the second conductive-oxide layer is different from a material of the first conductive-oxide layer.

14. The optoelectronic semiconductor device of claim 13, further comprising a metal layer under the second conductive-oxide layer and covering the second conductive-oxide layer.

15. The optoelectronic semiconductor device of claim 3, further comprising a first conductive-oxide layer under the insulating layer and contacting the insulating layer.

16. The optoelectronic semiconductor device of claim 1 or 2, further comprising an insulating layer covering the first protrusion, the second protrusion, and the recess, the insulating layer having an opening over the second protrusion, the plurality of contact portions being in the opening, and the insulating layer not contacting the plurality of contact portions.

17. The optoelectronic semiconductor device of claim 1 or 2, wherein, The first protrusion has a thickness of 0.5 mm to 2 mm, and the recess has a thickness of 0.01 mm to 1 mm.

18. The optoelectronic semiconductor device of claim 1, wherein, The first thickness is 4.5 mm to 6.5 mm.

19. The optoelectronic semiconductor device of claim 1 or 2, further comprising a window layer provided on the second-type semiconductor structure and a second contact structure on the window layer.

20. The optoelectronic semiconductor device of claim 1 or 2, wherein, Each of the plurality of contact portions has a second width, the recess has a third width, and a sum of the second widths is 5% to 50% of the third width.

Images