Semiconductor device and method for manufacturing semiconductor device

Abstract

A semiconductor device according to an embodiment of the present invention is provided with: a first substrate having a first joint portion; and a second substrate having a second joint portion joined to the first joint portion. The first substrate further includes a first multilayer wiring layer electrically connected to the first joint portion via a first insulating layer, in which one surface of the first wiring faces the first insulating layer, the first wiring is formed on a side closest to a joint surface with the second substrate, and the other surface opposite to the one surface contacts the second insulating layer, and the relative dielectric constant of the second insulating layer is lower than the relative dielectric constant of the first insulating layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor device in which semiconductor substrates are bonded to each other and a method for manufacturing the semiconductor device. Background Art

[0002] In recent years, in order to reduce the size of semiconductor devices and increase the integration degree, people have developed semiconductor devices with three-dimensional structures. For example, Patent Document 1 discloses a semiconductor device with a three-dimensional structure, in which a sensor substrate including a photoelectric converter and a circuit substrate including a peripheral circuit portion are bonded by CuCu bonding.

[0003] Reference List

[0004] Patent Literature

[0005] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2014-187166 Summary of the invention

[0006] Incidentally, in a semiconductor device (image sensor) in which a substrate is bonded by CuCu bonding as described above, silicon oxide (SiO2) is generally used as a wiring interlayer material included in a wiring layer of a sensor substrate. The relative dielectric constant of SiO2 is higher than that of a Low-k material used in, for example, front-end logic products. SiO2 tends to increase the RC delay of wiring. Therefore, it is necessary to reduce the wiring delay of a semiconductor device having CuCu bonding.

[0007] It is desirable to provide a semiconductor device and a method for manufacturing the semiconductor device that can reduce wiring delay.

[0008] A semiconductor device according to an embodiment of the present invention includes: a first substrate, the first substrate includes a first joint portion; and a second substrate, the second substrate includes a second joint portion. The second joint portion is joined to the first joint portion. The first substrate further includes a first multilayer wiring layer, wherein a surface of the first wiring formed closest to the joint surface with the second substrate faces the first insulating layer, and the other surface of the first wiring opposite to the one surface contacts the second insulating layer. The first multilayer wiring layer is electrically connected to the first joint portion through the first insulating layer. The relative dielectric constant of the second insulating layer is lower than the relative dielectric constant of the first insulating layer.

[0009] A method for manufacturing a semiconductor device according to an embodiment of the present invention includes: sequentially forming a first multilayer wiring layer and a first joint portion to form a first substrate, in which the first multilayer wiring layer is formed such that one surface of the first wiring closest to the first joint portion faces the first insulating layer, and the other surface of the first wiring opposite to the one surface contacts the second insulating layer; and forming a second joint portion as a second substrate, and then joining the first joint portion and the second joint portion together. The first multilayer wiring layer includes a second insulating layer as an interlayer insulating layer. The first joint portion is surrounded by a first insulating layer. The relative dielectric constant of the second insulating layer is lower than the relative dielectric constant of the first insulating layer.

[0010] In a semiconductor device according to an embodiment of the present invention and a method for manufacturing a semiconductor device according to an embodiment, in a first substrate joined to a second substrate via respectively arranged joints (first joints and second joints), a surface of the first wiring layer formed to be closest to the joint surface with the second substrate faces the first insulating layer, and the other surface of the first wiring layer opposite to the one surface contacts the second insulating layer. The first multilayer wiring layer is electrically connected to the first joint, and a first insulating layer is inserted between the first multilayer wiring layer and the first joint. The relative dielectric constant of the second insulating layer is lower than the low relative dielectric constant of the first insulating layer. By this, all interlayer insulating layers of the multilayer wiring layer arranged on the first substrate are formed using an insulating layer with a low relative dielectric constant.

[0011] According to the semiconductor device of the embodiment of the present invention and the manufacturing method of the semiconductor device of the embodiment, the first multilayer wiring layer is formed so that one surface of the first wiring layer closest to the bonding surface with the second substrate faces the first insulating layer arranged around the first bonding portion, and the other surface of the first wiring opposite to the one surface is contacted with the second insulating layer, and the relative dielectric constant of the second insulating layer is lower than the relative dielectric constant of the first insulating layer. The first multilayer wiring layer is arranged on the first substrate. This makes it possible to use an insulating layer with a low relative dielectric constant to form all the interlayer insulating layers of the first multilayer wiring layer. Therefore, the wiring delay in the first multilayer wiring layer arranged on the first substrate can be reduced.

[0012] It should be noted that the effects described here are not necessarily restrictive, but may include any effects described in the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a schematic cross-sectional view showing the configuration of a semiconductor device according to a first embodiment of the present invention.

[0014] Figure 2A It is used to illustrate Figure 1 A schematic cross-sectional view of a method for manufacturing a semiconductor device shown.

[0015] Figure 2B It shows Figure 2A Schematic cross-section of the following steps.

[0016] Figure 2C It shows Figure 2B Schematic cross-section of the following steps.

[0017] Figure 2D It shows Figure 2C Schematic cross-section of the following steps.

[0018] Figure 2E It shows Figure 2D Schematic cross-section of the following steps.

[0019] Figure 3 is a schematic cross-sectional view showing the configuration of a semiconductor device according to a second embodiment of the present invention.

[0020] Figure 4A It is used to illustrate Figure 3 A schematic cross-sectional view of a method for manufacturing a semiconductor device shown.

[0021] Figure 4B It shows Figure 4A Schematic cross-section of the following steps.

[0022] Figure 4C It shows Figure 4B Schematic cross-section of the following steps.

[0023] Figure 4D It shows Figure 4C Schematic cross-section of the following steps.

[0024] Figure 4E It shows Figure 4D Schematic cross-section of the following steps.

[0025] Figure 5 1 is a schematic cross-sectional view showing the structure of a semiconductor device according to Modification 1 of the present invention.

[0026] Figure 6 : is a cross-sectional schematic diagram showing an example of the configuration of a semiconductor device according to Modification 2 of the present invention.

[0027] Figure 7 FIG. 1 is a schematic cross-sectional view showing another example of the configuration of the semiconductor device according to Modification 2 of the present invention.

[0028] Figure 8 FIG. 1 is a schematic cross-sectional view showing another example of the configuration of the semiconductor device according to Modification 2 of the present invention. DETAILED DESCRIPTION

[0029] The embodiments of the present invention are described in detail below with reference to the accompanying drawings. The following description is a specific example of the present invention, but the present invention is not limited to the following manner. In addition, the present invention is not limited to the configuration, size, and size ratio of each component shown in each drawing. It should be noted that the description is given in the following order.

[0030] 1. First Embodiment (Example of a Semiconductor Device Using Low-k Materials for All Interlayer Insulation Layers of Multilayer Wiring Layers)

[0031] 1-1. Structure of semiconductor device

[0032] 1-2. Method for manufacturing semiconductor device

[0033] 1-3. Actions and effects

[0034] 2. Second Embodiment (Example of a Semiconductor Device in Which a Joint Portion is Structured as a Single Damascene Structure)

[0035] 2-1. Structure of semiconductor device

[0036] 2-2. Method for manufacturing semiconductor device

[0037] 3. Modification 1 (Example of a semiconductor device in which gaps are provided in each interlayer insulating layer of a multilayer wiring layer)

[0038] 4. Modification 2 (Example of a semiconductor device further stacked with DRAM)

[0039] <1. First Embodiment>

[0040] Figure 1 The cross-sectional structure of a semiconductor device (semiconductor device 1) according to the first embodiment of the present invention is schematically shown. A plurality of substrates (two substrates in this case) are bonded by CuCu bonding, thereby obtaining the semiconductor device 1. Functional elements and various circuits are formed in the plurality of corresponding substrates. In the semiconductor device 1 according to the present embodiment, the sensor substrate 10 (first substrate) and the logic substrate 20 (second substrate) are bonded together at the pad portions 17 and 27 (first bonding portion and second bonding portion). For example, the sensor substrate 10 (first substrate) is provided with a photodiode as a light receiving element (sensor element). For example, in the logic substrate 20 (second substrate), a logic circuit of the light receiving element is formed. The pad portions 17 and 27 are provided on the surface S1 and the surface S2 as the bonding surfaces of the sensor substrate 10 (first substrate) and the logic substrate 20 (second substrate), respectively.

[0041] (1-1. Structure of Semiconductor Device)

[0042] The semiconductor device 1 according to the present embodiment is formed so that one surface (surface 14S1) of the wiring 14C (first wiring) faces the insulating layer 16A, and the other surface (surface 14S2) faces the interlayer insulating layer 13C. In the multilayer wiring layer 14 (first multilayer wiring layer) further provided on the sensor substrate 10, the wiring 14C (first wiring) is formed closest to the surface S1. The multilayer wiring layer 14 is electrically connected to the pad portion 17. The other surface (surface 14S2) is opposite to the one surface (surface 14S1).

[0043] The sensor substrate 10 is provided with a multilayer wiring layer 14 above the front surface (surface 11S1) of the semiconductor substrate 11 via an insulating layer 12. The semiconductor substrate 11 is provided with a photodiode as a light receiving portion in a predetermined area included in each pixel, for example. The photodiode has a pn junction. The multilayer wiring layer 14 is used as a transmission path for the charge generated by the photodiode, for example. Above the multilayer wiring layer 14, a pad portion 17 whose surface is bonded to the logic substrate 20 is provided. Above the rear surface (surface 11S2) of the semiconductor substrate 11, for example, a light shielding film 32, a color filter 33 and an on-chip lens 34 are provided via a protective layer 31.

[0044] The semiconductor substrate 11 includes, for example, an n-type silicon (Si) substrate and has a p-well 61 in a predetermined region. Although not shown, a surface 11S1 of the semiconductor substrate 11 is provided with, for example, a floating diffusion (floating diffusion layer) FD, various transistors such as an amplifier transistor, and the like.

[0045] The insulating layer 12 is provided on the surface 11S1 of the semiconductor substrate 11. The insulating layer 12 includes, for example, silicon oxide (SiO x ), silicon nitride (SiN x ) and silicon oxynitride (SiON), etc., or a stacked film containing two or more of these materials.

[0046] An interlayer insulating layer 13A, an interlayer insulating layer 13B and an interlayer insulating layer 13C are provided on the insulating layer 12. The interlayer insulating layer 13A, the interlayer insulating layer 13B and the interlayer insulating layer 13C are arranged in order from the one closer to the semiconductor substrate 11. The interlayer insulating layers 13A, 13B and 13C respectively have wirings 14A, 14B and 14C buried therein to form a multilayer wiring layer 14. The wirings 14A, 14B and 14C included in the multilayer wiring layer 14 are respectively formed with a wiring rule such as L / S (Line and Space) of 120 / 120 or less. In addition, the wirings 14A, 14B and 14C are respectively formed to have a thickness of, for example, 250nm or less. The interlayer insulating layers 13A, 13B and 13C are respectively formed using the following materials: the relative dielectric constant of the material is lower than the relative dielectric constant of each of the insulating layers 16A and 16B described below. Specifically, preferably, the interlayer insulating layers 13A, 13B, and 13C are formed using materials having a relative dielectric constant of 1.5 or more and 3.8 or less. Examples include Low-k materials. Specific examples of Low-k materials include SiOC, SiOCH, porous silicon dioxide, SiOF, inorganic SOG, organic SOG, and polyallylether. The interlayer insulating layers 13A, 13B, and 13C each include a single-layer film containing one of the above materials or a stacked film containing two or more of these materials.

[0047] The insulating layer 16A and the insulating layer 16B are arranged in this order above the interlayer insulating layer 13C and the wiring 14C exposed on the upper surface of the interlayer insulating layer 13C. The pad portion 17 is buried in the insulating layer 16B. The pad portion 17 is exposed on the surface of the insulating layer 16B. The pad portion 17 and the insulating layer 16B form a bonding surface (surface S1) with the logic substrate 20. The insulating layers 16A and 16B are respectively formed using, for example, a material with a relative dielectric constant of 4.0 or more and 8.0 or less. Examples of such materials include SiO x 、SiN x , SiON, SiC, SiCN, etc. The insulating layers 16A and 16B each include a single layer film containing one of the above materials or a stacked film containing two or more of these materials. Preferably, for example, the pad portion 17 is formed to have a total film thickness of 1 μm or more with the via hole V4 described below.

[0048] The photodiode provided on the semiconductor substrate 11 is connected to the wiring 14A via the via hole V1. The wiring 14A is connected to the wiring 14B via the via hole V2. The wiring 14B is connected to the wiring 14C via the via hole V3. The wiring 14C is connected to the pad portion 17 via the via hole V4. This electrically connects the front surface (surface 11S1) of the semiconductor substrate 11 to the pad portion 17. The wiring 14A, 14B and 14C, the pad portion 17 and the via holes V1, V2, V3 and V4 respectively include metal materials such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), cobalt (Co), hafnium (Hf) or tantalum (Ta).

[0049] In addition, diffusion prevention layers 15A, 15B, and 15C are provided between the interlayer insulating layer 13A and the interlayer insulating layer 13B, between the interlayer insulating layer 13B and the interlayer insulating layer 13C, and between the interlayer insulating layer 13C and the insulating layer 16A, respectively. The diffusion prevention layers 15A, 15B, and 15C prevent the diffusion of metal materials (for example, copper (Cu)) included in the wirings 14A, 14B, and 14C, the vias V1, V2, V3, and V4, and the pad portion 17. The diffusion prevention layers 15A, 15B, and 15C are made of, for example, SiOC, SiCN, SiC, AlNO, and AlO, respectively. x The interlayer insulating layer 15D is provided between the insulating layer 16A and the insulating layer 16B.

[0050] The protective layer 31 is provided on the rear surface (surface 11S2) of the semiconductor substrate 11. The protective layer 31 includes a material having light transmittance, and includes, for example, SiO x 、SiN x and SiON, etc., or a stacked film containing two or more of these materials.

[0051] A color filter 33 and an on-chip lens 34 are provided on the protective layer 31. The color filter 33 is provided on the protective layer 31. For example, any one of a red color filter (33R), a green color filter (33G) and a blue color filter (33B) is provided for each pixel. These color filters 33R, 33G and 33B are provided in a regular color arrangement (for example, a Bayer arrangement). By providing the color filter 33 in this way, the photodiode provided on the semiconductor substrate 11 can obtain respective light receiving data of the colors corresponding to the color arrangement. The light shielding film 32 is provided between the red color filter (33R), the green color filter (33G) and the blue color filter (33B). It should be noted that in addition to the red color filter (33R), the green color filter (33G) and the blue color filter (33B), a white color filter can also be provided as the color filter 33.

[0052] The on-chip lens 34 has a function of, for example, focusing light on a photodiode provided for each pixel. Examples of the lens material include organic materials, silicon oxide films (SiO2), and the like.

[0053] For example, a circuit (e.g., a logic circuit) including, for example, a plurality of transistors is formed on the front surface (surface 21S1) of the semiconductor substrate 21 of the logic substrate 20. As an example, a multilayer wiring layer 24 is provided above the semiconductor substrate 21 via an insulating layer 22. Above the multilayer wiring layer 24, a pad portion 27 whose surface is bonded to the sensor substrate 10 is provided.

[0054] The semiconductor substrate 21 includes, for example, a silicon (Si) substrate. Although not shown, the semiconductor substrate 21 is provided with a transistor having, for example, a Si planar structure or a transistor such as a Fin-FET transistor having a three-dimensional structure.

[0055] The insulating layer 22 is provided on the surface 21S1 of the semiconductor substrate 21. Similar to the insulating layer 12, the insulating layer 22 includes, for example, SiO x 、SiN x and SiON, etc., or a stacked film containing two or more of these materials.

[0056] An interlayer insulating layer 23A, an interlayer insulating layer 23B, an interlayer insulating layer 23C, an interlayer insulating layer 23D, and an interlayer insulating layer 23E are provided on the insulating layer 22. The interlayer insulating layer 23A, the interlayer insulating layer 23B, the interlayer insulating layer 23C, the interlayer insulating layer 23D, and the interlayer insulating layer 23E are provided in order from the one closer to the semiconductor substrate 21. The interlayer insulating layers 23A, 23B, 23C, 23D, and 23E have wirings 24A, 24B, 24C, 24D, and 24E buried therein, respectively. The interlayer insulating layers 23A, 23B, 23C, 23D, and 23E are formed using a material having a relative dielectric constant lower than that of each of the insulating layers 26A, 26B, and 26C described below, respectively. Specifically, preferably, the interlayer insulating layers 23A, 23B, 23C, 23D, and 23E are formed using materials having relative dielectric constants of 1.5 or more and 3.8 or less. Examples include the above-mentioned Low-k materials. The interlayer insulating layers 23A, 23B, 23C, 23D, and 23E each include a single-layer film containing one of the above-mentioned materials or a stacked film containing two or more of these materials.

[0057] The insulating layer 26A, the insulating layer 26B, and the insulating layer 26C are arranged in this order above the interlayer insulating layer 23E and the wiring 24E exposed on the upper surface of the interlayer insulating layer 23E. The insulating layer 26A has the wiring 24F buried therein. The insulating layer 26A forms the multilayer wiring layer 24 together with the above-mentioned wiring 24A, 24B, 24C, 24D, and 24E. The pad portion 27 is buried in the insulating layer 26C. The pad portion 27 is exposed on the surface of the insulating layer 26C. The pad portion 27 and the insulating layer 26C form a bonding surface (surface S2) with the sensor substrate 10. The insulating layers 26A, 26B, and 26C are respectively formed using, for example, a material with a relative dielectric constant of 4.0 or more and 8.0 or less. Examples of such materials include SiO x 、SiN x , SiON, SiC, SiCN, etc. The insulating layers 26A, 26B, and 26C each include a single layer film containing one of the above materials or a stacked film containing two or more of these materials. Preferably, for example, the pad portion 27 is formed to have a total film thickness of 1 μm or more with the via hole V11 described below.

[0058] Various transistors provided in the semiconductor substrate 21 are connected to the wiring 24A via vias V5, respectively. The wiring 24A is connected to the wiring 24B via vias V6. The wiring 24B is connected to the wiring 24C via vias V7. The wiring 24C is connected to the wiring 24D via vias V8. The wiring 24D is connected to the wiring 24E via vias V9. The wiring 24E is connected to the wiring 24F via vias V10. The wiring 24F is connected to the pad portion 27 via vias V11. This electrically connects the front surface (surface 21S1) of the semiconductor substrate 21 to the pad portion 27. Wiring 24A, 24B, 24C, 24D, 24E and 24F, pad portion 27 and vias V5, V6, V7, V8, V9, V10 and V11 respectively include, for example, metal materials such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), cobalt (Co), hafnium (Hf) or tantalum (Ta).

[0059] In addition, diffusion prevention layers 25A, 25B, 25C, 25D, 25E, and 25F are provided between the interlayer insulating layer 23A and the interlayer insulating layer 23B, between the interlayer insulating layer 23B and the interlayer insulating layer 23C, between the interlayer insulating layer 23C and the interlayer insulating layer 23D, between the interlayer insulating layer 23D and the interlayer insulating layer 23E, between the interlayer insulating layer 23E and the insulating layer 26A, and between the insulating layer 26A and the insulating layer 26B, respectively. The diffusion prevention layers 25A, 25B, 25C, 25D, 25E, and 25F prevent the diffusion of metal materials (e.g., copper (Cu)) included in the wirings 24A, 24B, 24C, 24D, 24E, and 24F, the vias V5, V6, V7, V8, V9, V10, and V11, and the pad portion 27. The diffusion prevention layers 25A, 25B, 25C, 25D, 25E, and 25F are made of, for example, SiOC, SiCN, SiC, AlNO, and AlO, respectively. x The interlayer insulating layer 25G is provided between the insulating layer 26B and the insulating layer 26C.

[0060] The sensor substrate 10 and the logic substrate 20 are bonded together via the pad portion 17 and the pad portion 27. The pad portion 17 and the pad portion 27 are respectively provided on the surface S1 and the surface S2 as the bonding surface. This electrically connects the front surface (surface 11S1) of the semiconductor substrate 11 and the front surface (surface 21S1) of the semiconductor substrate 21.

[0061] (1-2. Method for manufacturing semiconductor device)

[0062] The semiconductor device 1 according to the present embodiment can be manufactured in the following manner, for example.

[0063] FIG. 2A to FIG. 2E The method for manufacturing the semiconductor device 1 is shown in the order of steps. First, Figure 2A As shown, after the photodiode is formed on the semiconductor substrate 11 using a conventional process, for example, SiO x The film is formed as an insulating layer 12 on the semiconductor substrate 11. Subsequently, via V1, interlayer insulating layer 13A, wiring 14A, anti-diffusion layer 15A, via V2, interlayer insulating layer 13B, wiring 14B, anti-diffusion layer 15B, via V3, interlayer insulating layer 13C, wiring 14C and anti-diffusion layer 15C are sequentially formed using, for example, a Cu wiring process. Here, interlayer insulating layers 13A, 13B and 13C are formed using, for example, SiOC. Wiring 14A, 14B and 14C are respectively formed with a wiring rule of, for example, a thickness of 250nm or less and, for example, L / S (line and space) of 120 / 120 or less. Anti-diffusion layers 15A, 15B and 15C are respectively formed to have a thickness of 30nm using, for example, SiC.

[0064] Next, if Figure 2B As shown, the insulating layer 16A, the via hole V4, the interlayer insulating layer 15D, the insulating layer 16B and the pad portion 17 are formed on the diffusion prevention layer 15C using a general dual damascene method. x The insulating layer 16A is formed to have a thickness of 600 nm. For example, SiN x The interlayer insulating layer 15D is formed to have a thickness of 400 nm. For example, SiO x The insulating layer 16B is formed to have a thickness of 250 nm. The interlayer insulating layer 15D can be used as an etching stopper film when forming the pad portion 17. The via V4 is formed to have a thickness of, for example, 850 nm. The pad portion 17 is formed to have a thickness of, for example, 500 nm. This allows the pad portion 17 and the via V4 to have a total film thickness of more than 1 μm, thereby ensuring mechanical strength.

[0065] In addition, if Figure 2C As shown, after various transistors are formed on the semiconductor substrate 21 using a general process, for example, SiO x A film is formed as an insulating layer 22 on the semiconductor substrate 21. Subsequently, a via V5, an interlayer insulating layer 23A, a wiring 24A, an anti-diffusion layer 25A, a via V6, an interlayer insulating layer 23B, a wiring 24B, an anti-diffusion layer 25B, a via V7, an interlayer insulating layer 23C, a wiring 24C, an anti-diffusion layer 25C, a via V8, an interlayer insulating layer 23D, a wiring 24D, an anti-diffusion layer 25D, a via V9, an interlayer insulating layer 23E, a wiring 24E, an anti-diffusion layer 25E, a via V10, an insulating layer 26A, a wiring 24F, and an anti-diffusion layer 25F are sequentially formed using, for example, a W wiring process or a Cu wiring process. Here, the interlayer insulating layers 23A, 23B, 23C, 23D, and 23E are formed using, for example, SiOC. The wirings 24A, 24B, 24C, 24D, and 24E are respectively formed with a wiring rule of, for example, a thickness of 250 nm or less and, for example, L / S (line and space) of 120 / 120 mm or less. The diffusion prevention layers 25A, 25B, 25C, 25D, and 25E are formed to have a thickness of 30 nm using, for example, SiC. x The insulating layer 26A is formed to have a thickness of 1500 nm. For example, SiN x The diffusion prevention layer 25E is formed to have a thickness of 50 nm. The via hole V10 is formed to have a thickness of, for example, 600 nm.

[0066] Next, if Figure 2D As shown, the insulating layer 26B, the via hole V11, the interlayer insulating layer 25G, the insulating layer 26C and the pad portion 27 are formed on the diffusion prevention layer 25F using a general dual damascene method. xThe insulating layer 26B is formed to have a thickness of 600 nm. For example, SiN x The interlayer insulating layer 25G is formed to have a thickness of 400 nm. For example, SiO x The insulating layer 26C is formed to have a thickness of 250 nm. The interlayer insulating layer 25G can be used as an etching stopper film when forming the pad portion 27. The via V11 is formed to have a thickness of, for example, 850 nm. The pad portion 27 is formed to have a thickness of, for example, 500 nm. This allows the pad portion 27 and the via V11 to have a total film thickness of 1 μm or more, thereby ensuring mechanical strength.

[0067] Then, if Figure 2E As shown, plasma activation treatment is performed on the bonding surface (surface S1) of the sensor substrate 10 formed using the insulating layer 16B and the pad portion 17 and the bonding surface (surface S2) of the logic substrate 20 formed using the insulating layer 26C and the pad portion 27. Next, after the bonding surface (surface S1) of the sensor substrate 10 and the bonding surface (surface S2) of the logic substrate 20 are temporarily bonded together, the bonding surfaces are annealed at 380°C for about 2 hours to allow CuCu bonding to bond the sensor substrate 10 and the logic substrate 20 together. Thereafter, the thickness of the semiconductor substrate 11 is reduced to about 3μm by combining a general backgrinding process with chemical mechanical polishing (CMP: Chemical Mechanical Polishing). Finally, a protective layer 31, a light shielding film 32, a color filter 33, and an on-chip lens 34 are formed in sequence. This completes Figure 1 The semiconductor device 1 is shown.

[0068] (1-3. Actions and Effects)

[0069] As described above, in recent years, in order to reduce the size of semiconductor devices and increase the integration, semiconductor devices with three-dimensional structures have been developed. For example, an image sensor in which a sensor substrate and a circuit substrate are joined by CuCu bonding is reported. The sensor substrate includes a photoelectric conversion unit. The circuit substrate includes a peripheral circuit unit. Generally, in an image sensor with CuCu bonding, a SiO2 film is used to form a film located between wiring layers of the sensor substrate. The relative dielectric constant ratio of SiO2 is higher than the relative dielectric constant of a Low-k film used in, for example, front-end logic products. SiO2 tends to increase the RC delay of the wiring.

[0070] When the RC delay of the wiring in the image sensor becomes large, the photoelectric conversion efficiency and the settling characteristics may be reduced. As a method for improving the wiring delay, a method of forming a film between the wiring layers of the sensor substrate using a low-k film is considered. However, when all the films between the wiring layers of the sensor substrate are formed using a low-k film, while the thickness of the semiconductor substrate is reduced, the film may be peeled off from the CuCu junction due to insufficient mechanical strength.

[0071] In contrast, in the semiconductor device 1 according to the present embodiment, the upper surface (surface 14S1 on the bonding surface (surface S1) side) of the wiring 14C disposed closest to the bonding surface (surface S1) of the multilayer wiring layer 14 faces the SiN x The anti-diffusion layer 15C of the film and the insulating layer 16A including the SiO2 film. The lower surface of the wiring 14C (the surface 14S2 opposite to the surface 14S1) is in contact with the interlayer insulating layer 13C including the Low-k film. In other words, the interlayer insulating layers between the wirings 14A to 14C included in the multilayer wiring layer 14 provided on the sensor substrate 10 are respectively formed using Low-k materials. The pad portion 17 included in the CuCu bonding and the insulating layers 16A and 16B located between the pad portion 17 and the wiring 14C provided on the uppermost layer of the multilayer wiring layer 14 are respectively formed using, for example, SiO2 materials. This allows the interlayer insulating layers 13A to 13C included in the multilayer wiring layer 14 to be formed using all Low-k films with low relative dielectric constants. In addition, the insulating layers 16A and 16B included in the bonding surface (surface S1) respectively include, for example, SiO2 materials that provide high mechanical strength. This makes it possible to ensure the mechanical strength of the bonding surface.

[0072] As described above, in the semiconductor device 1 according to the present embodiment, the interlayer insulating layers 13A to 13C included in the multilayer wiring layer 14 are all formed using a Low-k film having a low relative dielectric constant. This reduces the wiring delay in the sensor substrate 10. In addition, the insulating layers 16A and 16B included in the bonding surface (surface S1) are respectively formed using an insulating material such as SiO2 material that can provide high mechanical strength. Therefore, the occurrence of film peeling and the like can be reduced.

[0073] It should be noted that in the present embodiment, the pad portions 17 and 27 are formed using a dual damascene wiring method, respectively. Therefore, a dummy pad portion can be formed on the bonding surface (surface S1 and surface S2) of the sensor substrate 10 and the logic substrate 20. Providing a dummy pad helps to form a Cu film with uniform density. The flattening performance of the bonding surface, such as by CMP, can be improved. This makes it possible to reduce the generation of voids at the bonding portion, thereby achieving a stable CuCu bonding.

[0074] Next, a second embodiment and modifications (modifications 1 and 2) are described. Note that components corresponding to those of the semiconductor device 1 according to the above-described first embodiment are denoted by the same reference numerals for explanation.

[0075] <2. Second Embodiment>

[0076] Figure 3 The cross-sectional structure of a semiconductor device (semiconductor device 2) according to a second embodiment of the present invention is schematically shown. As with the semiconductor device 1 according to the first embodiment described above, a plurality of substrates (two substrates in this case) are bonded by CuCu bonding, thereby obtaining the semiconductor device 2. Functional elements and various circuits are formed in the plurality of corresponding substrates. The semiconductor device 2 according to the present embodiment is different from the first embodiment in that the pad portions 47 and 57 included in the CuCu bonding are both formed using a single damascene wiring method. The pad portions 47 and 57 are provided on the sensor substrate 40 and the logic substrate 50, respectively.

[0077] (2-1. Structure of Semiconductor Device)

[0078] The semiconductor device 2 is obtained by bonding the sensor substrate 40 and the logic substrate 50 together at the pad portions 47 and 57. The sensor substrate 40 is provided with, for example, a photodiode as a light receiving element. In the logic substrate 50, for example, a logic circuit is formed. The pad portions 47 and 57 are provided on the surface S3 and the surface S4 as respective bonding surfaces.

[0079] The sensor substrate 40 is provided with a multilayer wiring layer 14 above the front surface (surface 11S1) of the semiconductor substrate 11 via an insulating layer 12. The semiconductor substrate 11 is provided with a photodiode as a light receiving portion in a predetermined area included in each pixel, for example. The photodiode has a pn junction. The multilayer wiring layer 14 is used as a transmission path for the charge generated by the photodiode, for example. Above the multilayer wiring layer 14, a pad portion 47 whose surface is bonded to the logic substrate 50 is provided. The pad portion 47 forms a bonding surface (surface S3) together with the insulating layer 16B provided around it. Above the rear surface (surface 11S2) of the semiconductor substrate 11, for example, a light shielding film 32, a color filter 33 and an on-chip lens 34 are provided via a protective layer 31.

[0080] The pad portion 47 is exposed on the surface of the insulating layer 16B. The pad portion 47 forms a bonding surface (surface S3) with the logic substrate 50 together with the insulating layer 16B. The pad portion 47 penetrates the anti-diffusion layer 15C, the insulating layer 16A, the interlayer insulating layer 15D and the insulating layer 16B provided on the wiring 14C and the interlayer insulating layer 13C included in the multilayer wiring layer 14, and is directly electrically connected to the wiring 14C. Like the wirings 14A, 14B and 14C and the vias V1, V2, V3 and V4, the pad portion 47 preferably includes, for example, a metal material such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), cobalt (Co), hafnium (Hf) or tantalum (Ta). Here, the pad portion 47 is formed using Cu. The pad portion 47 is preferably formed to be, for example, 1 μm or more.

[0081] For example, a circuit (e.g., a logic circuit) including, for example, a plurality of transistors is formed on the front surface (surface 21S1) of the semiconductor substrate 21 of the logic substrate 50. As an example, a multilayer wiring layer 24 is provided above the semiconductor substrate 21 via an insulating layer 22. Above the multilayer wiring layer 24, a pad portion 57 is provided whose surface is bonded to the sensor substrate 40. The pad portion 57 forms a bonding surface (surface S4) together with the insulating layer 26C provided around it.

[0082] The pad portion 57 is exposed on the surface of the insulating layer 26C. The pad portion 57 forms a bonding surface (surface S4) with the sensor substrate 40 together with the insulating layer 26C. The pad portion 57 penetrates the diffusion prevention layer 25F, the insulating layer 26B, the interlayer insulating layer 25G, and the insulating layer 26C provided on the wiring 24F and the insulating layer 26A included in the multilayer wiring layer 24, and is directly electrically connected to the wiring 24F. As with the wiring 24A, 24B, 24C, 24D, 24E, and 24F and the vias V5, V6, V7, V8, V9, and V10, the pad portion 57 preferably includes, for example, a metal material such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), cobalt (Co), hafnium (Hf), or tantalum (Ta). Here, the pad portion 57 is formed using Cu. The pad portion 57 is preferably formed to be, for example, 1 μm or more.

[0083] (2-2. Method for manufacturing semiconductor device)

[0084] The semiconductor device 2 according to the present embodiment can be manufactured in the following manner, for example.

[0085] FIG. 4A to FIG. 4E The method for manufacturing the semiconductor device 2 is shown in order of steps. First, Figure 4A As shown, after a photodiode is formed on a semiconductor substrate 11 by using a conventional process, a SiO xThe film is formed as an insulating layer 12 on the semiconductor substrate 11. Subsequently, via V1, interlayer insulating layer 13A, wiring 14A, anti-diffusion layer 15A, via V2, interlayer insulating layer 13B, wiring 14B, anti-diffusion layer 15B, via V3, interlayer insulating layer 13C, wiring 14C and diffusion prevention layer 15C are sequentially formed using, for example, a W wiring process or a Cu wiring process. Here, interlayer insulating layers 13A, 13B and 13C are formed using, for example, SiOC. Wiring 14A, 14B and 14C are respectively formed with a wiring rule of, for example, a thickness of 250nm or less and, for example, L / S (line and space) of 120 / 120nm or less. Anti-diffusion layers 15A, 15B and 15C are respectively formed to have a thickness of 30nm using, for example, SiC.

[0086] Next, if Figure 4B As shown in FIG. 1 , after the insulating layer 16A, the interlayer insulating layer 15D, and the insulating layer 16B are sequentially formed on the diffusion prevention layer 15C, a through hole reaching the wiring 14C is formed using a general single damascene wiring method. Subsequently, for example, the through hole is filled with Cu to form the pad portion 47. Here, for example, SiO x The insulating layer 16A is formed to have a thickness of 600 nm. For example, SiN x The interlayer insulating layer 15D is formed to have a thickness of 400 nm. For example, SiO x The insulating layer 16B is formed to have a thickness of 250 nm. The diffusion prevention layer 15C can be used as an etching stopper when forming the pad portion 47. The pad portion 47 is formed to have a thickness of, for example, 1 μm or more. This ensures the mechanical strength of the bonding surface with the logic substrate 50 and its surrounding area.

[0087] In addition, if Figure 4C As shown, after various transistors are formed on the semiconductor substrate 21 using a general process, for example, SiO xA film is formed as an insulating layer 22 on the semiconductor substrate 21. Subsequently, a via V5, an interlayer insulating layer 23A, a wiring 24A, an anti-diffusion layer 25A, a via V6, an interlayer insulating layer 23B, a wiring 24B, an anti-diffusion layer 25B, a via V7, an interlayer insulating layer 23C, a wiring 24C, an anti-diffusion layer 25C, a via V8, an interlayer insulating layer 23D, a wiring 24D, an anti-diffusion layer 25D, a via V9, an interlayer insulating layer 23E, a wiring 24E, an anti-diffusion layer 25E, a via V10, an insulating layer 26A, a wiring 24F, and an anti-diffusion layer 25F are sequentially formed using, for example, a W wiring process or a Cu wiring process. Here, the interlayer insulating layers 23A, 23B, 23C, 23D, and 23E are formed using, for example, SiOC. The wirings 24A, 24B, 24C, 24D, and 24E are respectively formed with a wiring rule of, for example, a thickness of 250 nm or less and, for example, L / S (line and space) of 120 / 120 nm or less. The diffusion prevention layers 25A, 25B, 25C, 25D, and 25E are formed to have a thickness of 30 nm using, for example, SiC. x The insulating layer 26A is formed to have a thickness of 1500 nm. For example, SiN x The diffusion prevention layer 25E is formed to have a thickness of 50 nm. The via hole V10 is formed to have a thickness of, for example, 600 nm.

[0088] Next, if Figure 4D As shown in FIG. 1 , after the insulating layer 26B, the interlayer insulating layer 25G, and the insulating layer 26C are sequentially formed on the diffusion prevention layer 25F, a through hole reaching the wiring 24F is formed using a general single damascene process. Thereafter, for example, the through hole is filled with Cu to form the pad portion 57. Here, for example, SiO x The insulating layer 26B is formed to have a thickness of 600 nm. For example, SiN x The interlayer insulating layer 25G is formed to have a thickness of 400 nm. For example, SiO x The insulating layer 26C is formed to have a thickness of 250 nm. The diffusion prevention layer 25F can be used as an etching stopper when forming the pad portion 57. The pad portion 57 is formed to have a thickness of, for example, 1 μm or more. This ensures the mechanical strength of the bonding surface with the sensor substrate 40 and its surrounding area.

[0089] Then, if Figure 4EAs shown, plasma activation treatment is performed on the bonding surface (surface S3) of the sensor substrate 40 formed using the insulating layer 16B and the pad portion 47 and the bonding surface (surface S4) of the logic substrate 50 formed using the insulating layer 26C and the pad portion 57. Next, after the bonding surface (surface S3) of the sensor substrate 40 and the bonding surface (surface S4) of the logic substrate 50 are temporarily bonded together, the bonding surfaces are annealed at 380°C for about 2 hours to allow CuCu bonding to bond the sensor substrate 40 and the logic substrate 50 together. Thereafter, the thickness of the semiconductor substrate 11 is reduced to about 3μm by combining a general backgrinding process and CMP. Finally, a protective layer 31, a light shielding film 32, a color filter 33, and an on-chip lens 34 are formed in sequence. This completes Figure 3 The semiconductor device 2 is shown.

[0090] As described above, in the semiconductor device 2 according to the present embodiment, the pad portions 47 and 57 included in the CuCu junction are formed using the single damascene wiring method. This can reduce the number of manufacturing steps compared to the manufacturing steps of the semiconductor device 1 according to the first embodiment.

[0091] <3. Modification 1>

[0092] Figure 5 The cross-sectional structure of a semiconductor device (semiconductor device 3) according to the first modification of the present invention is schematically shown. As with the semiconductor device 1 according to the first embodiment described above, a plurality of substrates (two substrates in this case) are bonded by CuCu bonding, thereby obtaining the semiconductor device 3. Functional elements and various circuits are formed in the plurality of corresponding substrates. The semiconductor device 3 according to this modification is different from the first embodiment described above in that the interlayer insulating layers 13A, 13B, and 13C around the wirings 14A, 14B, and 14C included in the multilayer wiring layer 14 provided on the sensor substrate 10 are provided with gaps G1, G2, and G3, respectively.

[0093] The gaps G1, G2, and G3 of the interlayer insulating layers 13A, 13B, and 13C are formed using the following methods, respectively. For example, a predetermined region of the interlayer insulating layer 13A is removed by etching and then pinched off by, for example, chemical vapor deposition (CVD) to form the gap G1 in the interlayer insulating layer 13A. Alternatively, for example, the gap G1 can be formed in the interlayer insulating layer 13A by providing a through hole in the interlayer insulating layer 13B higher than the gap G1 and removing the interlayer insulating layer 13A by etching from the through hole. The gap G2 of the interlayer insulating layer 13B and the gap G3 of the interlayer insulating layer 13C can be formed using a similar method.

[0094] As described above, in this modification, for example, gaps G1, G2, and G3 are formed in interlayer insulating layers 13A, 13B, and 13C respectively formed using Low-k. In addition to the effects of the first embodiment described above, an effect of further suppressing wiring delay is obtained by providing gaps having a relative dielectric constant lower than Low-k.

[0095] Note that although Figure 5 The example in which the pad portions 17 and 27 are both formed using the dual damascene wiring method is shown, but this is not restrictive. For example, this modification example can also be applied to a semiconductor device including pad portions 47 and 57 formed using a single damascene wiring method like the semiconductor device 2 according to the second embodiment.

[0096] <4. Modification 2>

[0097] Figure 6 An example of a cross-sectional configuration of a semiconductor device (semiconductor device 4) according to variant example 2 of the present invention is schematically shown. In the semiconductor device 4, a DRAM substrate 60 is stacked together with a sensor substrate 10 and a logic substrate 20. The semiconductor device 4 has a configuration in which a surface S1 of the sensor substrate 10 and a surface S5 of the DRAM substrate are bonded together by CuCu bonding, and the logic substrate 20 is bonded to a surface S6 side of the DRAM substrate 60 opposite to the surface S5. In this way, the substrate bonded to the sensor substrate 10 described in the first embodiment and the like described above is not limited to, for example, the logic substrate 20, but the sensor substrate 10 may be bonded to another substrate such as a DRAM substrate 60 and the like.

[0098] In addition, although Figure 6 The example in which the sensor substrate 10 and the DRAM substrate 60 are bonded together by CuCu bonding is shown, but for example Figure 7 In the semiconductor device 5 shown, the sensor substrate 10 and the logic substrate 20 can be bonded together using CuCu bonding and the DRAM substrate 60 can be bonded to the other surface of the logic substrate 20 .

[0099] In addition, if Figure 8 In the semiconductor device 6 shown, a DRAM substrate 60 can be bonded to the sensor substrate 10 and the logic substrate 20 bonded together using CuCu bonding, for example, using a bumping technique.

[0100] Although the present invention has been described above with reference to the first and second embodiments and Modifications 1 and 2, the present invention is not limited to the above embodiments and the like, and can be modified in various ways. For example, in the above embodiments and the like, although an example has been described in which a light receiving element including a photodiode is mounted as a functional element, this is not restrictive. A storage element or an antenna of a communication system may also be mounted.

[0101] Note that the effects described in this specification are merely illustrative and non-restrictive, and other effects may exist. In addition, the present technology may have the following configurations.

[0102] (1) A semiconductor device comprising:

[0103] a first substrate including a first bonding portion; and

[0104] a second substrate, the second substrate comprising a second bonding portion, the second bonding portion being bonded to the first bonding portion, wherein

[0105] The first substrate further includes a first multilayer wiring layer, in which a surface of a first wiring formed closest to a joining surface with the second substrate faces a first insulating layer, and another surface of the first wiring opposite to the one surface contacts a second insulating layer, the first multilayer wiring layer is electrically connected to the first joining portion via the first insulating layer, and a relative dielectric constant of the second insulating layer is lower than that of the first insulating layer.

[0106] (2) The semiconductor device according to (1), wherein the second insulating layer is formed using a material having a relative dielectric constant of 1.5 or more and 3.8 or less.

[0107] (3) The semiconductor device according to (1) or (2), wherein the second insulating layer is formed using a Low-k material.

[0108] (4) The semiconductor device according to any one of (1) to (3), wherein the second insulating layer includes at least one of SiOC, SiOCH, porous silicon dioxide, SiOF, inorganic SOG, organic SOG, and polyallyl ether.

[0109] (5) The semiconductor device according to any one of (1) to (4), wherein the first insulating layer is formed using a material having a relative dielectric constant of 4.0 or more and 8.0 or less.

[0110] (6) The semiconductor device according to any one of (1) to (5), wherein the first insulating layer includes at least one of SiO, SiN, SiON, SiC, and SiCN.

[0111] (7) The semiconductor device according to any one of (1) to (6), wherein the first multilayer wiring layer including the first wiring is formed with a wiring rule of L / S (line and space) of 120 / 120 mm or less.

[0112] (8) The semiconductor device according to any one of (1) to (7), wherein

[0113] The first bonding portion and the first wiring are connected via a via hole, and

[0114] The total thickness of the first bonding portion and the via hole is 1 μm or more.

[0115] (9) The semiconductor device according to (8), wherein the first bonding portion and the via hole each have a dual damascene structure.

[0116] (10) The semiconductor device according to (8), wherein the first bonding portion and the via hole each have a single damascene structure.

[0117] (11) The semiconductor device according to any one of (1) to (10), wherein the first substrate further includes a functional element.

[0118] (12) The semiconductor device according to (11), wherein the functional element is a sensor element.

[0119] (13) A method for manufacturing a semiconductor device, the method comprising:

[0120] A first multilayer wiring layer and a first junction are sequentially formed to form a first substrate, wherein the first multilayer wiring layer is formed such that one surface of a first wiring closest to the first junction faces a first insulating layer, and another surface of the first wiring opposite to the one surface contacts a second insulating layer, the first multilayer wiring layer includes the second insulating layer as an interlayer insulating layer, the first junction is surrounded by the first insulating layer, and the relative dielectric constant of the second insulating layer is lower than that of the first insulating layer; and

[0121] A second bonding portion is formed as a second substrate, and then the first bonding portion and the second bonding portion are bonded together.

[0122] (14) The method for manufacturing a semiconductor device according to (13), wherein a via hole connecting the first bonding portion and the first wiring of the first multilayer wiring layer is formed using a dual damascene wiring method.

[0123] (15) The method for manufacturing a semiconductor device according to (13), wherein a via hole connecting the first bonding portion and the first wiring of the first multilayer wiring layer is formed using a single damascene wiring method.

[0124] This application claims priority based on Japanese Patent Application No. 2018-123927 filed with the Japan Patent Office on June 19, 2018, the entire contents of which are incorporated herein by reference.

[0125] It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.

Claims

1. A semiconductor device comprising: a first substrate, the first substrate comprising a first bonding portion; and a second substrate, the second substrate comprising a second bonding portion, the second bonding portion being bonded to the first bonding portion, wherein The first substrate further includes a first multilayer wiring layer, in which one surface of a first wiring formed closest to a bonding surface with the second substrate faces a first insulating layer, and another surface of the first wiring opposite to the one surface contacts a second insulating layer, the first multilayer wiring layer is electrically connected to the first bonding portion via the first insulating layer, and a relative dielectric constant of the second insulating layer is lower than a relative dielectric constant of the first insulating layer, The first bonding portion and the first wiring are connected via a via hole, and The total thickness of the first bonding portion and the via hole is 1 μm or more.

2. The semiconductor device according to claim 1, wherein The second insulating layer is formed using a material having a relative dielectric constant of 1.5 or more and 3.8 or less.

3. The semiconductor device according to claim 1, wherein The second insulating layer is formed using a Low-k material.

4. The semiconductor device according to claim 1, wherein The second insulating layer includes at least one of SiOC, SiOCH, porous silicon dioxide, SiOF, inorganic SOG, organic SOG, and polyallyl ether.

5. The semiconductor device according to claim 1, wherein The first insulating layer is formed using a material having a relative dielectric constant of 4.0 or more and 8.0 or less.

6. The semiconductor device according to claim 1, wherein The first insulating layer includes at least one of SiO, SiN, SiON, SiC, and SiCN.

7. The semiconductor device according to claim 1, wherein The first multi-layer wiring layer including the first wiring is formed with a wiring rule of line and space of 120 / 120 nm or less.

8. The semiconductor device according to claim 1, wherein The first joint portion and the via hole each have a dual damascene structure.

9. The semiconductor device according to claim 1, wherein: The first joint portion and the via hole each have a single damascene structure.

10. The semiconductor device according to any one of claims 1 to 9, wherein: The first substrate further includes a functional element.

11. The semiconductor device according to claim 10, wherein The functional element is a sensor element.

12. A method for manufacturing a semiconductor device, the method comprising: A first multilayer wiring layer and a first junction are sequentially formed to form a first substrate, wherein the first multilayer wiring layer is formed such that one surface of a first wiring closest to the first junction faces a first insulating layer, and another surface of the first wiring opposite to the one surface contacts a second insulating layer, the first multilayer wiring layer includes the second insulating layer as an interlayer insulating layer, the first junction is surrounded by the first insulating layer, and the relative dielectric constant of the second insulating layer is lower than that of the first insulating layer; and forming a second bonding portion as a second substrate, and then bonding the first bonding portion and the second bonding portion together, The first bonding portion and the first wiring are connected via a via hole, and The total thickness of the first bonding portion and the via hole is 1 μm or more.

13. The method for manufacturing a semiconductor device according to claim 12, wherein: The vias are formed using a dual damascene wiring method.

14. The method for manufacturing a semiconductor device according to claim 12, wherein: The vias are formed using a single damascene wiring method.

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