Memory system and method of operating a memory system

Abstract

A memory system and a method of operating a memory system are provided. The memory system includes a memory device including a plurality of blocks, a buffer storing degradation information about at least one block of the plurality of blocks, and a memory controller configured to determine a degradation level of a block corresponding to a read request based on the degradation information in response to the read request from a host, infer a read level corresponding to the read request based on the degradation level, and read data from the memory device based on the read level.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2019-0100539, filed on August 16, 2019, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] One or more embodiments of the inventive concept relate to a memory system, and more specifically, to a memory system and a method of operating thereof that infers a read level based on degradation information about a block corresponding to a read request. Background Technology

[0003] A memory system may include a memory controller and memory devices. As a type of memory device, a non-volatile memory device may include multiple memory cells that store data in a non-volatile manner. As a non-volatile memory, flash memory can store data by modifying the threshold voltage of the memory cells and read data by using a predetermined read level. However, memory cells may degrade for various reasons, and read errors can occur because the threshold voltage changes due to the degradation of the memory cells. Summary of the Invention

[0004] One or more embodiments of the inventive concept provide a memory system and a method of operation thereof that have improved reliability and efficiency by reading data using a read level inferred from degradation information about the block corresponding to the read request.

[0005] According to one aspect of the inventive concept, a memory system includes: a memory device including at least one block; a buffer configured to store degradation information about the at least one block; and a memory controller configured to infer a read level based on the degradation information of the at least one block corresponding to a read request from a host for the at least one block, and to read data from the memory device based on the read level.

[0006] According to another aspect of the inventive concept, a memory system includes: a memory device comprising a plurality of blocks; a buffer storing degradation information about at least one of the plurality of blocks; and a memory controller configured to read data from the at least one block in response to a read request from a host, wherein the memory controller may include: a hardware accelerator executing an artificial intelligence model trained to infer read levels; and a processor configured to: control the buffer to provide degradation information about the at least one block corresponding to the read request to the hardware accelerator, obtain a read level corresponding to the read request through the artificial intelligence model, and read data based on the obtained read level.

[0007] According to another aspect of the inventive concept, a method for operating a memory system, the memory system including a memory device comprising a plurality of blocks, the method comprising: receiving a read request from a host; obtaining degradation information about a block among the plurality of blocks corresponding to the read request; determining a degradation level of the block corresponding to the read request based on the degradation information; inferring a read level corresponding to the read request based on the degradation level; and reading data from the memory device based on the read level. Attached Figure Description

[0008] Embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 This is a block diagram illustrating a memory system according to an embodiment of the inventive concept;

[0010] Figure 2 This illustrates an embodiment based on the inventive concept. Figure 1 A block diagram of an implementation of the memory device;

[0011] Figure 3A and Figure 3B This is a diagram illustrating an example of the change in threshold voltage distribution caused by the deterioration of memory cells;

[0012] Figure 4A and Figure 4B This is a diagram illustrating another example of the change in threshold voltage distribution caused by the deterioration of memory cells;

[0013] Figure 5 This illustrates an embodiment based on the inventive concept. Figure 1 A block diagram of the memory controller;

[0014] Figure 6 This illustrates another embodiment based on the inventive concept. Figure 1 A block diagram of the memory controller;

[0015] Figure 7 and Figure 8 This is a flowchart illustrating a method of operating a memory system according to an embodiment of the inventive concept;

[0016] Figure 9 This is a flowchart illustrating a method for generating degradation information according to an embodiment of the inventive concept;

[0017] Figure 10 It shows the basis Figure 9 An example diagram illustrating the method for generating degradation information;

[0018] Figure 11 It shows the use Figure 10A flowchart of a method for inferring the read level from degradation information;

[0019] Figure 12 This is a flowchart illustrating a method for generating degradation information and degradation level information according to an embodiment of the inventive concept;

[0020] Figure 13 It shows the basis Figure 12 The diagram illustrates an example of the method for generating degradation information and degradation level information.

[0021] Figure 14 It shows the use Figure 13 A flowchart illustrating an example of a method for inferring read levels from degradation information and degradation level information;

[0022] Figure 15 It is a diagram illustrating an artificial intelligence model according to an embodiment of the inventive concept; and

[0023] Figure 16 This is a block diagram illustrating a solid-state drive (SSD) system according to an embodiment of the inventive concept. Detailed Implementation

[0024] Figure 1 This is a block diagram illustrating a memory system according to an embodiment of the inventive concept.

[0025] Reference Figure 1 The memory system 10 may include a memory controller 100 and a memory device 200. The memory controller 100 may include an artificial intelligence model 110, and the memory device 200 may include a memory cell array 210, a voltage generator 220, and control logic 230.

[0026] The host can communicate with the memory system 10 through various interfaces. For example, the host can send read requests, write requests, etc., to the memory system 10. The host can be implemented using an application processor (AP), a system-on-a-chip (SoC), etc.

[0027] The storage system 10 can be implemented using a personal computer (PC), data server, network-attached storage (NAS), Internet of Things (IoT) device, portable electronic device, etc. Examples of portable electronic devices may include laptops, mobile phones, smartphones, tablet PCs, personal digital assistants (PDAs), enterprise digital assistants (EDAs), digital cameras, digital video cameras, audio devices, portable multimedia players (PMPs), personal navigation devices (PNDs), MPEG-1 audio layer 3 (MP3) players, handheld game consoles, e-readers, wearable devices, etc.

[0028] Alternatively, the memory system 10 can be implemented using internal memory embedded in the electronic device. For example, the memory system 10 can be Universal Flash Memory (UFS), an embedded multimedia card (eMMC), or a solid-state drive (SSD). Alternatively, the memory system 10 can be implemented using external memory that is removably attached to the electronic device. For example, the memory system 10 can be a UFS memory card, a Compact Flash Memory (CF) card, a Secure Digital (SD) card, a Micro-SD card, a Mini-SD card, an xD card, or a Memory Stick.

[0029] The memory controller 100 can control the memory device 200 to write (or program) data to the memory device 200, or read or erase data stored in the memory device 200 in response to a read / write request from the host.

[0030] In detail, the memory controller 100 can control write, read, or erase operations of the memory device 200 by providing the memory device 200 with an address ADDR, a command CMD, or a control signal CTRL. Furthermore, the memory controller 100 can send and receive data DATA to be written to the memory device 200 and data DATA to be read from the memory device 200 between itself and the memory device 200.

[0031] Memory device 200 may include a non-volatile memory device. Memory cell array 210 may include a plurality of memory cells, wherein the plurality of memory cells may include flash memory cells. However, embodiments of the inventive concept are not limited thereto. The plurality of memory cells included in memory cell array 210 may include resistive memory cells (e.g., resistive random access memory (ReRAM)), phase-change random access memory (PRAM), or magnetic random access memory (MRAM).

[0032] The memory cell array 210 may include multiple blocks. Each of the multiple blocks may include multiple pages, and each page may include multiple memory cells. In the memory cell array 210, data erase operations can be performed on a block-by-block basis, and data read operations and data write operations can be performed on a page-by-page basis. For example, the memory device 200 may perform erase operations on a block-by-block basis and read and write operations on a page-by-page basis, referring to address ADDR from the memory controller 100.

[0033] Voltage generator 220 can generate various types of voltages for performing read / write / erase operations. For example, a data write operation can be performed using Incremental Step Pulse Programming (ISPP), and voltage generator 220 can generate multiple voltages for ISPP and provide the generated multiple voltages to memory cell array 210. Furthermore, voltage generator 220 can generate a read voltage used in read operations and provide the generated read voltage to memory cell array 210. Additionally, voltage generator 220 can generate an erase voltage with a high voltage level used in erase operations and provide the generated erase voltage to memory cell array 210.

[0034] Control logic 230 can control the overall operation associated with memory operations of memory device 200. For example, control logic 230 can control voltage generator 220, which can modify the levels of various types of voltages generated under the control of control logic 230. The threshold voltage distribution of memory cells in memory cell array 210 can be adjusted according to the voltage generated by voltage generator 220.

[0035] However, degradation (e.g., threshold voltage change) may occur in the multiple memory cells of the memory cell array 210. Degradation may occur due to retention, floating gate coupling, charge loss due to elapsed time, etc.

[0036] If the threshold voltage has changed due to the degradation of multiple memory cells, a read error may occur when memory system 10 uses the default read level and attempts to read data that was previously at the threshold voltage. A read error can refer to a situation where the number of erroneous bits in the read data is equal to or greater than a reference number of errors that can be corrected by error-correcting codes (ECC). A read error can be referred to as uncorrectable ECC (UECC).

[0037] To eliminate read errors, it may be necessary to modify the read level through read retry operations. To perform a read retry operation, the memory system 10 can execute recovery codes, which may take a considerable amount of time. If data is read using the default read level when the memory cell has already deteriorated, the memory system 10 may suffer from reduced data reliability due to read errors and performance degradation due to read retry operations.

[0038] According to an example embodiment of the inventive concept, the memory controller 100 may, in response to a read request from a host, infer a read level based on degradation information regarding multiple blocks of the memory device 200, and read data from the memory device 200 based on the inferred read level, to prevent data reliability and the performance of the memory controller 100 from being compromised due to degradation. The degradation information may include various information relating to the degradation state of the multiple blocks included in the memory cell array 210.

[0039] In an exemplary embodiment of the inventive concept, the memory controller 100 can anticipate the degradation state of the block corresponding to the read request based on degradation information about multiple blocks, and infer a read level that allows data to be read without causing any read errors even in the anticipated degradation state. Furthermore, the memory controller 100 can read data by providing information about the inferred read level to the memory device 200 via command CMD and / or control signal CTRL. Therefore, the memory system 10 according to the exemplary embodiment of the inventive concept can reduce read errors caused in reading data, improve data reliability, and improve the performance of the memory system 10 without incurring any overhead involving read retries.

[0040] According to an example embodiment of the inventive concept, the memory controller 100 may include an artificial intelligence model 110 trained to infer read levels. The memory controller 100 may use the artificial intelligence model 110 to perform the aforementioned operation of inferring read levels. Specifically, the memory controller 100 may obtain the read level corresponding to a read request by providing degradation information to the artificial intelligence model 110.

[0041] Artificial intelligence model 110 can be implemented in software or hardware and can be a model based on at least one of the following: artificial neural network (ANN) model, multilayer perceptron (MLP) model, convolutional neural network (CNN) model, deconvolutional neural network, decision tree model, random forest model, AdaBoost (adaptive boosting) model, multiple regression analysis model, logistic regression model, recurrent neural network (RNN) selectively including long short-term memory (LSTM) units and / or gated recurrent units (GRU), stacked neural network (SNN), state-space dynamic neural network (SSDNN), deep belief network (DBN), generative adversarial network (GAN), and / or restricted Boltzmann machine (RBM). Optionally or additionally, artificial intelligence model 110 may include other forms of artificial intelligence models, such as linear regression and / or logistic regression, statistical clustering, Bayesian classification, decision trees, dimensionality reduction (such as principal component analysis), expert systems, random sampling consensus (RANSAC) models, and / or combinations thereof. Examples of artificial intelligence model 110 are not limited thereto.

[0042] Furthermore, according to an example embodiment of the inventive concept, the memory controller 100 can selectively perform an operation to infer the read level based on the degradation level of the block corresponding to the read request. Specifically, the memory controller 100 can determine a degradation level indicating the extent of degradation that has occurred based on degradation information about the block corresponding to the read request, and determine whether to infer the read level based on the determined degradation level.

[0043] For example, when the degradation level of the block corresponding to the read request is equal to or greater than a predefined threshold, the memory controller 100 anticipates a significant change in the threshold voltage distribution due to degradation, and therefore, the read level corresponding to the read request can be inferred. Conversely, when the degradation level of the block corresponding to the read request is less than the threshold, the memory controller 100 anticipates a slight change in the threshold voltage distribution due to degradation. In that case, the memory controller 100 can read data based on a default read level without inferring the read level. Optionally, separate firmware or software executed by a processing unit stored in the memory controller 100 can perform the aforementioned operations of determining the degradation level and whether to infer the read level based on the determined degradation level.

[0044] In an example embodiment of the inventive concept, by inferring the read level only when the expected change in the threshold voltage distribution would be significant, the memory controller 100 can reduce the computational overhead involved in the inference operation while improving data reliability and reducing data retry operations.

[0045] Figure 2This illustrates an embodiment based on the inventive concept. Figure 1 A block diagram illustrating an implementation of the memory device.

[0046] Reference Figure 2 The memory device 200 may include a memory cell array 210, a voltage generator 220, control logic 230, a row decoder 240, and a page buffer 250. Although in Figure 2 Although not shown, the memory device 200 may also include various other components related to memory operation (e.g., data input / output circuitry, input / output interfaces, etc.).

[0047] The memory cell array 210 includes multiple blocks BLK1 to BLKz, wherein the memory cells of blocks BLK1 to BLKz can be connected to word line WL, serial select line SSL, ground select line GSL, and bit line BL. The memory cell array 210 is connected to the row decoder 240 via word line WL, serial select line SSL, and ground select line GSL, and can be connected to the page buffer 250 via bit line BL. Each memory cell can store one or more bits. For example, each memory cell can include a multi-level cell (MLC), a three-level cell (TLC), or a four-level cell (QLC).

[0048] The memory cell array 210 may include a two-dimensional memory cell array, wherein the two-dimensional memory cell array may include multiple cell strings arranged in the row and column directions. Furthermore, according to embodiments of the inventive concept, the memory cell array 210 may include a three-dimensional memory cell array, wherein the three-dimensional memory cell array may include multiple cell strings, wherein each cell string may include memory cells vertically stacked on a substrate connected to each of multiple word lines. For example, U.S. Patents 7,679,133, 8,553,466, 8,654,587, and 8,559,235, and U.S. Patent Publication No. 2011 / 0233648 disclose possible configurations of three-dimensional memory cell arrays formed by multiple layers, wherein word lines and / or bit lines are shared between layers. U.S. Patent Nos. 7,679,133, 8,553,466, 8,654,587, and 8,559,235, as well as U.S. Patent Publication No. 2011 / 0233648, are incorporated herein by reference.

[0049] Based on commands CMD, addresses ADDR, or control signals CTRL received from the memory controller 100, control logic 230 can output various types of internal control signals for programming data into or reading data from the memory cell array 210. For example, control logic 230 can output a voltage control signal CTRL_vol to control the levels of various types of voltages generated in voltage generator 220, providing row address X-ADDR to row decoder 240 and column address Y-ADDR to page buffer 250. Voltage generator 220 can generate various types of voltages used in memory device 200. As an example, voltage generator 220 can generate programming and verification voltages used in write operations and read voltages used in read operations.

[0050] According to an example embodiment of the inventive concept, regarding the operation of inferring a read level, the memory controller 100 can send information about the inferred read level via a command CMD and / or a control signal CTRL. Control logic 230 can generate a voltage control signal CTRL_vol based on the information about the read level verified by the received command CMD and / or control signal CTRL. Voltage generator 220 can generate a read voltage corresponding to the inferred read level in response to the voltage control signal CTRL_vol.

[0051] Figure 3A and Figure 3B This is a diagram illustrating an example of the change in threshold voltage distribution caused by the deterioration of memory cells.

[0052] Reference Figure 3A and Figure 3B The horizontal axis represents the threshold voltage Vth, and the vertical axis represents the number of memory cells. (Refer to...) Figure 3A When a memory cell is a single-level cell programmed with 1 bit, the memory cell can have either an erase state E or a programmable state P. Furthermore, the memory cell can have a threshold voltage distribution corresponding to either the erase state E or the programmable state P. The memory system 10 can use the default read level DRL to determine whether the memory cell is in the erase state E or the programmable state P.

[0053] On the other hand, the threshold voltage distribution may change when memory cells deteriorate. (Refer to...) Figure 3BIt can be confirmed that the threshold voltage distribution corresponding to the erase state E or the programming state P of the memory cell has changed. The threshold voltage distribution of a memory cell changes when the threshold voltage decreases due to charge leakage from the charge storage layer of the memory cell to the substrate, or when the threshold voltage increases due to read interference caused by read operations performed on adjacent memory cells. Furthermore, the threshold voltage distribution of a memory cell may change due to an increase in the frequency of programming / erasing operations on the memory cell or a change in the operating temperature of the memory cell.

[0054] If the threshold voltage distribution has changed, and the memory system 10 uses the default read level DRL to read data in order to determine the erase state E or the programming state P of a memory cell, read errors may occur in some memory cells programmed in the programming state P. In that case, it may be necessary to modify the read level through a read retry operation.

[0055] However, according to an example embodiment of the inventive concept, the memory system 10 can anticipate the degradation state of the block corresponding to the read request based on degradation information in response to a read request from the host, and infer a read level that will not cause a read error based on the anticipated degradation state. Furthermore, the memory system 10 can use the inferred read level IRL to determine the erase state E or programming state P of the memory cell. Therefore, the memory system 10 can improve the reliability of read data and improve the performance of the memory system 10 without incurring any overhead involving read retries.

[0056] Figure 4A and Figure 4B This is a diagram illustrating another example of the change in threshold voltage distribution caused by the deterioration of memory cells.

[0057] Reference Figure 4A and Figure 4B The horizontal axis represents the threshold voltage Vth, and the vertical axis represents the number of memory cells. (Refer to...) Figure 4A When the memory cell is a multi-level cell programmed with 2 bits, the memory cell can have one of the following states: erase state E, first programming state P1, second programming state P2, and third programming state P3. The memory cell can have a threshold voltage distribution corresponding to either erase state E, first programming state P1, second programming state P2, or third programming state P3. The memory system 10 can use each of the first default read level DRL1 to the third default read level DRL3 to determine the first programming state P1 to the third programming state P3 of the memory cell.

[0058] On the other hand, when memory cells deteriorate, the threshold voltage distribution of the memory cells may change. (Refer to...) Figure 4B It can be confirmed that the threshold voltage distribution corresponding to the erase state E, the first programming state P1, the second programming state P2, or the third programming state P3 of the memory cell has changed. In that case, if the memory system 10 reads data as is using the default read levels DRL1 to DRL3 to determine the erase state E, the first programming state P1, the second programming state P2, or the third programming state P3 of the memory cell, read errors may occur in some memory cells programmed under the first programming state P1 to the third programming state P3. In that case, it may be necessary to modify the read level through a read retry operation.

[0059] However, according to an example embodiment of the inventive concept, the memory system 10 can anticipate the degradation state of the block corresponding to the read request based on degradation information in response to a read request from the host, and infer a read level that will not cause a read error based on the anticipated degradation state. Furthermore, the memory system 10 can use the inferred read levels IRL1 to IRL3 to determine the erase state E, the first programming state P1, the second programming state P2, or the third programming state P3 of the memory cell. Therefore, the memory system 10 can improve the reliability of read data and improve the performance of the memory system 10 without incurring any overhead involving read retries.

[0060] Despite Figures 3A to 4B It is not shown in the figure, but the same principle can be applied to cases where the memory cells are multi-layered cells (e.g., three-layered or four-layered cells).

[0061] Figure 5 This illustrates an embodiment based on the inventive concept. Figure 1 Block diagram of the memory controller.

[0062] Reference Figure 5 The memory controller 100 may include a host interface 120, a processor 130, a tightly coupled memory (TCM) 140, a memory 150, an error correction code (ECC) module 160, and a memory interface 170, and these components may communicate with each other via a bus 180.

[0063] The host interface 120 can provide a physical connection between the host and the storage system 10. As an example, the host interface 120 may include various interface methods such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), IEEE 1394, Universal Serial Bus (USB), Secure Digital (SD) card interface, Multimedia Card (MMC) interface, Embedded Multimedia Card (eMMC) interface, Compact Flash (CF) card interface, etc.

[0064] The host interface 120 can receive read requests from the host and transfer data read from the memory device 200 to the host.

[0065] Processor 130 may be processing circuitry (such as hardware including logic circuitry; hardware / software combination executing software; or a combination thereof). For example, processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc. Processor 130 can control the overall operation of memory controller 100 by executing instructions stored in memory 150. For example, processor 130 may use degradation information about the block corresponding to a read request to determine the degradation level and execute firmware or software that performs an operation to determine whether to infer a read level based on the determined degradation level. Furthermore, processor 130 may include TCM 140, in which an artificial intelligence model trained to infer read levels is stored. Moreover, because processor 130 can access TCM 140 for a relatively short period of time, processor 130 can quickly perform read level inference operations using artificial intelligence model 110 when a read request is received from the host.

[0066] The memory 150 may be a data buffer, which can operate under the control of the processor 130, and may be volatile memory (e.g., DRAM and SRAM) or non-volatile memory (e.g., PRAM and flash memory). The memory 150 may be a memory block dedicated to serving as a data buffer for the processor 130, or it may be a block dedicated to serving as a buffer, such as a memory device.

[0067] A background read controller (BRC) included in memory 150 can be executed by processor 130 to control background read operations on a plurality of blocks BLK1 to BLKn included in memory device 200. A background read operation can refer to an operation performed by the background read controller BRC, which issues a read command CMD and address ADDR to itself without receiving a read request from the host, and reads data DATA from memory device 200 in response to the read command CMD and address ADDR. The background read controller BRC can be implemented in firmware or software and can be loaded into memory 150. However, embodiments of the inventive concept are not limited thereto. Alternatively, the background read controller BRC can be implemented in hardware.

[0068] The memory controller 100 can collect degradation information DI for each of a plurality of blocks after a background read operation. Afterward, the memory controller 100 can store the collected degradation information DI in the memory 150. The degradation information DI may include at least one of the following: program / erase cycle (P / E cycle), read count, hold time, operating temperature, and the number of erroneous bits in the read data.

[0069] In addition, degradation information (DI) may include the aforementioned information about each word line or each memory cell included in each block.

[0070] Furthermore, degradation information DI may include a count of active cells (e.g., the number of memory cells active when a default read level is applied to each word line of the block) and / or a count of deactivated cells (e.g., the number of memory cells deactivated when a default read level is applied to each word line of the block under the control of the background read controller BRC). However, the type of degradation information DI is not limited to this.

[0071] The memory controller 100 can perform background read operations and degradation information DI collection operations at preset cycles. However, embodiments of the inventive concept are not limited thereto. Optionally, the memory controller 100 can perform background read operations and degradation information DI collection operations according to a variable cycle.

[0072] The collected degradation information DI can be provided to the artificial intelligence model 110 under the control of the processor 130, thus enabling the read level inference operation to be performed. The read level inference operation will be described in more detail below.

[0073] When a read request is received from the host, the processor 130 can obtain degradation information about the block corresponding to the read request from the degradation information DI stored in the memory 150. Once the processor 130 has received the read request and logical address from the host, the processor 130 can obtain the physical address corresponding to the logical address and obtain degradation information about the block corresponding to that physical address among multiple blocks of the memory device 200. On the other hand, the memory 150 can store a mapping table (not shown) that maps logical addresses and physical addresses.

[0074] Furthermore, the processor 130 can determine the degradation level of the block corresponding to the read request based on the obtained degradation information. When the determined degradation level is equal to or greater than a threshold, the processor 130 can control the memory 150 to provide verified degradation information to the TCM 140. Depending on the degree of degradation, the degradation level can consist of three or more different levels. The higher the degradation level, the greater the degree of degradation. However, embodiments of the inventive concept are not limited to this. There are two degradation levels: degradation level "0" indicates that degradation has not occurred or is slight, and degradation level "1" indicates that degradation exists.

[0075] The degradation level determination operation can be performed based on a combination of various information sets included in the degradation information. For example, the degradation level may correspond to the value of the on-cell count or off-cell count in the degradation information, and the processor 130 can determine the degradation level of the block by verifying the on-cell count or off-cell count in the degradation information. Optionally, the degradation level can be determined based on a combination of at least one or more of the following included in the degradation information: P / E cycle, read count, hold time, operating temperature, number of error bits in read data, etc. Optionally, the degradation level determination operation can be performed by a separate configuration other than the processor 130.

[0076] Processor 130 can execute artificial intelligence model 110 included in TCM 140 and obtain read levels inferred from artificial intelligence model 110. Furthermore, processor 130 can control memory interface 170 to provide information about the inferred read levels to memory device 200 via command CMD and / or control signal CTRL.

[0077] On the other hand, when the determined degradation level is less than a threshold, the processor 130 can determine the default read level as the read level corresponding to the read request without inferring the read level corresponding to the read request. Furthermore, the processor 130 can control the memory interface 170 to provide information about the default read level to the memory device 200 via the command CMD and / or the control signal CTRL.

[0078] ECC module 160 detects error bits in the data received from memory device 200 and can perform ECC operations to correct the detected error bits. ECC module 160 can determine whether the number of error bits detected from the received data exceeds the correction capability of ECC module 160.

[0079] For example, ECC module 160 detects error bits from the read data in response to a read request from the host, and can determine whether the number of detected error bits exceeds the error correction capability of ECC module 160. If the number of detected error bits exceeds the error correction capability of ECC module 160, ECC module 160 can notify processor 130 of the result, whereby processor 130 can execute recovery codes to perform a read retry operation.

[0080] ECC module 160 can be implemented in hardware. However, embodiments of the inventive concept are not limited thereto. Alternatively, ECC module 160 can be implemented in firmware or software and can be loaded into memory 150.

[0081] Memory interface 170 provides a channel between memory controller 100 and memory device 200. For example, commands CMD, addresses ADDR, data DATA, degradation information DI, etc., can be sent and received between memory controller 100 and memory device 200 via memory interface 170. Requested data to be written from host and data to be read from memory device 200 can be temporarily stored in memory 150.

[0082] Despite Figure 5 The memory controller is shown and described in the illustrations and descriptions as including one TCM, but the memory controller can be implemented with multiple TCMs.

[0083] Furthermore, despite Figure 5 In the illustrations and descriptions, the memory controller is shown and described as including one memory, but the memory controller may include multiple memories. In that case, the background read controller (BRC) can be stored in one memory, and degradation information can be stored in the remaining memories.

[0084] Figure 6 This illustrates another embodiment based on the inventive concept. Figure 1 Block diagram of the memory controller.

[0085] Reference Figure 6 The memory controller 100' is Figure 5 A modified embodiment of the memory controller 100 shown is described. Therefore, details related to it will be omitted in the following text. Figure 5The description is the same as the previous one. Hardware accelerator 190 can implement an artificial intelligence model 110 trained to infer read levels. Hardware accelerator 190 may include a dedicated accelerator for artificial intelligence computing.

[0086] Examples of hardware accelerator 190 may include various types of accelerators, such as field-programmable gate arrays (FPGAs), massively parallel processor arrays (MPPAs), graphics processing units (GPUs), application-specific integrated circuits (ASICs), neural processors (NPUs), tensor processors (TPUs), multiprocessor system-on-a-chip (MPSoCs), etc. Processor 130 can use hardware accelerator 190 to perform read-level inference operations.

[0087] Once processor 130' has received a read request from the host, processor 130' can confirm the degradation information about the block corresponding to the read request from the degradation information DI stored in memory 150. Afterward, processor 130' can determine the degradation level of the block corresponding to the read request based on the confirmed degradation information. When the determined degradation level is equal to or greater than a threshold, processor 130' can control memory 150 to provide the confirmed degradation information to the hardware accelerator 190 implementing the artificial intelligence model 110.

[0088] Furthermore, processor 130' can control hardware accelerator 190 to execute artificial intelligence model 110 and can obtain read levels inferred from artificial intelligence model 110. Additionally, processor 130' can control memory interface 170 to provide information about the inferred read levels to memory device 200 via command CMD and / or control signal CTRL.

[0089] On the other hand, when the determined degradation level is less than a threshold, the processor 130' can determine the default read level as the read level corresponding to the read request without inferring the read level. Furthermore, the processor 130 can control the memory interface 170 to provide information about the default read level to the memory device 200 via the command CMD and / or the control signal CTRL.

[0090] When using an artificial intelligence model 110 executed by dedicated artificial intelligence computing hardware (e.g., hardware accelerator 190), read level inference operations can be performed rapidly in parallel. In such a case, read levels can be inferred over a time period that is almost the same as the time period when using a read path that does not require inference processing, and therefore the resulting read levels can be sent to the memory device 200.

[0091] Figure 7 and Figure 8 This is a flowchart illustrating a method of operating a memory system according to an embodiment of the inventive concept.

[0092] Figure 7 This is a flowchart illustrating a read level inference operation based on deterioration information about the block corresponding to the read request, according to this embodiment. For example, it can include... Figure 5 The memory controller 100 of the memory system 10 or including Figure 6 The operation method according to this embodiment is executed in the memory system 10 of the memory controller 100'. (Refer to...) Figures 1 to 6 The description provided can be applied to this embodiment.

[0093] Reference Figure 7 In operation S11, a read request can be received from the host. Memory controllers 100 and 100' can receive read requests from the host via host interface 120. The memory system 10 can also receive the logical address associated with the read request from the host.

[0094] In operation S12, degradation information about the block can be obtained. Memory controllers 100 and 100' can obtain physical addresses corresponding to received logical addresses from multiple blocks of the memory device 200, and can obtain degradation information about the block corresponding to the physical address among the multiple blocks. The degradation information may include at least one of the following: on-cell count, off-cell count, P / E cycle, read count, hold time, operating temperature, and the number of erroneous bits in the read data.

[0095] In operation S13, the degradation level of the block can be determined. Memory controllers 100 and 100' can determine the degradation level based on the obtained degradation information. Specifically, memory controllers 100 and 100' can determine the degradation level of the block corresponding to the read request by verifying the degradation level corresponding to the value of the on-cell count or off-cell count included in the degradation information. Optionally, memory controllers 100 and 100' can determine the degradation level based on a combination of at least one or more of the following included in the degradation information: P / E cycle, read count, hold time, operating temperature, number of erroneous bits of read data, etc.

[0096] In operation S14, the read level can be inferred based on the degradation level. Memory controllers 100 and 100' can infer the read level corresponding to the read request based on a determined degradation level. For example, depending on whether the degradation level is equal to or greater than a threshold, memory controllers 100 and 100' may or may not perform the read level inference operation. In the following text, Figure 8 A detailed description of it is provided in the description and illustrations.

[0097] The read level inference operation based on the degradation level can be performed using an inference method selected according to the determined degradation level. For example, if there are a first method and a second method for inferring the read level, the read level can be inferred using either the first method or the second method based on the degradation level.

[0098] Memory controllers 100 and 100' can use an artificial intelligence model 110 trained to infer read levels to infer read levels. Specifically, memory controllers 100 and 100' can input degradation information about the block corresponding to the read request into the artificial intelligence model 110 and obtain the read level inferred from the artificial intelligence model 110.

[0099] Artificial intelligence model 110 can be implemented in software or hardware, and can be based on at least one or a combination of decision tree models, random forest models, AdaBoost models, multiple regression analysis models, logistic regression models, and random sampling consensus (RANSAC) models discussed above. Examples of artificial intelligence model 110 are not limited thereto.

[0100] Alternatively, the artificial intelligence model 110 can be executed in the TCM 140 included in the processor 130 of the memory controller 100. Furthermore, the artificial intelligence model 110 can be implemented via a hardware accelerator 190 included in the memory controller 100' of the memory system 10.

[0101] In operation S15, data can be read based on the read level. Memory controllers 100 and 100' can send information about the inferred read level to memory device 200 via command CMD and / or control signal CTRL, and receive data read from memory device 200.

[0102] Figure 8 It shows in detail the basis Figure 7 A flowchart illustrating the read level inference operation based on the degradation level of the block corresponding to the read request. (Refer to...) Figure 8 The operations performed in S21 to S23, namely receiving a read request from the host, obtaining degradation information about the block, and determining the read level of the block, can be compared with those in reference. Figure 7 The operations S11 to S13 are essentially the same as those described above. Therefore, they will be omitted in the following text. Figure 7 The description is the same as the description.

[0103] In operation S24, the degradation level of the block corresponding to the read request can be compared with a threshold. If the degradation level is equal to or greater than the threshold, memory controllers 100 and 100' can perform operation S25. Conversely, if the degradation level is less than the threshold, memory controllers 100 and 100' can perform operation S27.

[0104] In operation S25, the read level corresponding to the read request can be inferred using degradation information about the block corresponding to the read request. In operation S26, data can be read using the inferred read level. Memory controllers 100 and 100' can send information about the inferred read level to memory device 200 via command CMD and / or control signal CTRL. Memory device 200 verifies the information about the inferred read level using the received command CMD and / or control signal CTRL, thereby allowing memory device 200 to read data using the read voltage corresponding to the inferred read level.

[0105] In operation S27, the default read level can be determined as the read level corresponding to the read request. Specifically, memory controllers 100 and 100' can determine the default read level as the read level corresponding to the read request without performing a read level inference operation. In operation S28, data can be read using the default read level. Memory controllers 100 and 100' can send information about the default read level to memory device 200 via command CMD and / or control signal CTRL. Memory device 200 verifies the information about the default read level using the received command CMD and / or control signal CTRL, thereby allowing memory device 200 to read data using the read voltage corresponding to the default read level.

[0106] Figure 9 This is a flowchart illustrating a method for generating degradation information according to an embodiment of the inventive concept.

[0107] Reference Figure 9 The method for generating degradation information according to this embodiment is executed through a background read operation. For example, it can include... Figure 5 The memory controller 100 is in the memory system 10 or includes Figure 6 The memory system 10 of the memory controller 100' executes a method for generating degradation information according to this embodiment. (Refer to...) Figures 1 to 6 The foregoing description can be applied to this embodiment.

[0108] In operation S31, degradation information about each of the multiple blocks can be collected (or obtained) by monitoring the memory device 200. Memory controllers 100 and 100' can perform background read operations via the background read controller BRC during background operation. Furthermore, memory controllers 100 and 100' can collect degradation information about each of the multiple blocks after the background read operation.

[0109] In operation S32, the degradation level of each of the multiple blocks can be determined based on the collected degradation information. Detailed methods for determining the degradation level can be combined with... Figure 5 The preceding description is essentially the same. Therefore, the following text will omit the similarities. Figure 5 The description is the same as the description.

[0110] In operation S33, the degradation level of each of the multiple blocks can be compared with a threshold. Memory controllers 100 and 100' can perform operation S34 on blocks whose degradation level is equal to or greater than the threshold. On the other hand, memory controllers 100 and 100' can perform operation S35 on blocks whose degradation level is less than the threshold. Memory controllers 100 and 100' can execute operations S34 and S35 in parallel.

[0111] In operation S34, degradation information about blocks among multiple blocks whose degradation level is equal to or greater than a threshold can be stored. In other words, memory controllers 100 and 100' can store only degradation information about blocks whose degradation level is equal to or greater than the threshold in memory 150.

[0112] On the other hand, in operation S35, the operation of storing degradation information about blocks among the multiple blocks whose degradation level is less than a threshold can be omitted. In other words, memory controllers 100 and 100' can omit the operation of storing degradation information about blocks whose degradation level is less than a threshold in memory 150.

[0113] Figure 10 It shows the basis Figure 9 An example diagram illustrating the method for generating degradation information.

[0114] Reference Figure 10 The degradation information stored in memory 150 may include degradation information described in a vector format using the numbering of each block in a plurality of blocks. The degradation information described in vector format (e.g., Figure 10V1 to Vn in the diagram may include at least one of the following: on-cell count (e.g., OCC1), off-cell count (e.g., OCC2), P / E cycle, read count, hold time, operating temperature, and the number of erroneous bits in the read data. Alternatively, information about degradation described in vector format may include two or more on-cell counts obtained by using different read levels or two or more off-cell counts obtained by using different read levels. Although shown and described... Figure 10 Information about degradation is described in vector format, but it will be understood that this approach is given by way of example rather than constraint. Degradation information can be generated using other descriptive methods.

[0115] like Figure 9 As described above, degradation information for blocks whose degradation level is equal to or greater than a threshold can be stored in memory 150. Therefore, degradation information for blocks BLK1 and BLKn whose degradation level is equal to or greater than the threshold can be stored, while degradation information for block BLK2 whose degradation level is less than the threshold can be empty.

[0116] Figure 11 It shows the use Figure 10 A flowchart illustrating an example of a method for inferring read levels from degradation information.

[0117] Reference Figure 11 In operation S41, a read request can be received from the host. Memory controllers 100 and 100' can receive read requests and logical addresses from the host via host interface 120.

[0118] In operation S42, it can be verified whether degradation information regarding the block corresponding to the read request exists. Specifically, memory controllers 100 and 100' can obtain the physical address corresponding to the received logical address from multiple blocks of memory device 200, and verify whether degradation information regarding the block corresponding to the physical address is stored in memory 150. If the verified degradation information regarding the block is stored in memory 150, memory controllers 100 and 100' can perform operation S43. Conversely, if the verified degradation information regarding the block is not stored in memory 150, memory controllers 100 and 100' can perform operation S45.

[0119] In operation S43, the read level corresponding to the read request can be inferred using verified degradation information about the block. Since the existence of verified degradation information about the block indicates that the block has undergone verified degradation, memory controllers 100 and 100' can perform a read level inference operation. Specifically, memory controllers 100 and 100' provide the verified degradation information about the block to the artificial intelligence model 110 and can obtain the read level inferred from the artificial intelligence model 110. In operation S44, data can be read using the inferred read level. Memory controllers 100 and 100' can send information about the inferred read level to memory device 200 via command CMD and / or control signal CTRL. Memory device 200 verifies the information about the inferred read level using the received command CMD and / or control signal CTRL, thereby allowing memory device 200 to read data using a read voltage corresponding to the inferred read level.

[0120] In operation S45, the default read level can be determined as the read level corresponding to the read request. Since there is no verified degradation information regarding the block indicating that the block has experienced slight verified degradation or no verified degradation, memory controllers 100 and 100' can determine the default read level as the read level corresponding to the read request. In operation S46, data can be read using the default read level. Memory controllers 100 and 100' can send information about the default read level to memory device 200 via command CMD and / or control signal CTRL. Memory device 200 verifies the information about the default read level using the received command CMD and / or control signal CTRL, thereby allowing memory device 200 to read data using the read voltage corresponding to the default read level.

[0121] therefore, Figures 9 to 11 The memory controllers 100 and 100' can reduce storage capacity by pre-selecting the blocks for which read level inference operations are required (i.e., the blocks that have deteriorated) and storing only the deterioration information about those blocks.

[0122] Figure 12 This is a flowchart illustrating a method for generating degradation information and degradation level information according to an embodiment of the inventive concept.

[0123] Reference Figure 12 The method for generating degradation information and degradation level information according to this embodiment is executed through a background read operation. For example, it can be implemented in a manner including... Figure 5 The memory controller 100 is in the memory system 10 or includes Figure 6The memory system 10 of the memory controller 100' executes a method for generating degradation information and degradation level information according to this embodiment. (Refer to...) Figures 1 to 6 The above description can be applied to this embodiment.

[0124] In operation S51, degradation information about each of the multiple blocks can be collected by monitoring the memory device 200. Memory controllers 100 and 100' can perform background read operations via the background read controller BRC during background operation. Furthermore, after the background read operation, memory controllers 100 and 100' can collect degradation information about each of the multiple blocks and store the collected information in the memory 150. In other words, memory controllers 100 and 100' can store all the collected degradation information about each of the multiple blocks.

[0125] In operation S52, the degradation level (i.e., degradation level information) of each of multiple blocks can be determined based on the collected degradation information. Detailed methods for determining the degradation level can be discussed in conjunction with... Figure 5 The related descriptions above are essentially the same. Therefore, they will be omitted in the following text. Figure 5 The description is the same as the description.

[0126] In operation S53, memory 150 can store determined degradation level information for each of the plurality of blocks. Memory system 10 can store all of the determined degradation level information for each of the plurality of blocks.

[0127] Figure 13 It shows the basis Figure 12 The diagram illustrates an example of the method for generating degradation information and degradation level information.

[0128] Reference Figure 13 The degradation information stored in memory 150 may include degradation-related information described in a numbered and vector format for each of the multiple blocks, and the degradation level information may include the degradation level for each of the multiple blocks.

[0129] Information related to degradation described in vector format (e.g., Figure 13The V1 to Vn values ​​may include at least one of the following: on-cell count (e.g., OCC1), off-cell count (e.g., OCC2), P / E cycle, read count, hold time, operating temperature, and the number of erroneous bits in the read data. Furthermore, information about degradation described in vector format may include two or more on-cell counts obtained by using different read levels or two or more off-cell counts obtained by using different read levels. Alternatively, information about degradation may be generated in different formats besides vector format.

[0130] As in Figure 12 As mentioned in the description, since degradation information about all multiple blocks can be stored in memory 150 regardless of the degradation level, degradation information about block BLK2, whose degradation level is less than the threshold, can also be stored in memory 150.

[0131] Degradation information and degradation level information in Figure 13 The description and illustrations depict simultaneous generation. However, degradation information and degradation level information can be generated and stored separately in the implementation.

[0132] Figure 14 It shows the use Figure 13 A flowchart illustrating an example of a method for inferring the read level from degradation information and degradation level information.

[0133] Reference Figure 14 In operation S61, read requests can be received from the host. Memory controllers 100 and 100' can receive read requests and logical addresses from the host via host interface 120.

[0134] In operation S62, degradation level information about the block corresponding to the read request can be obtained. Memory controllers 100 and 100' obtain physical addresses corresponding to the received logical addresses from multiple blocks of memory device 200, and can obtain degradation level information about the block among the multiple blocks corresponding to the physical address from memory 150.

[0135] In operation S63, the degradation level of the block corresponding to the read request can be compared with a threshold. In other words, memory controllers 100 and 100' can compare the degradation level of the block corresponding to the read request with a preset threshold. If the degradation level is equal to or greater than the threshold, memory controllers 100 and 100' can execute operation S64. Conversely, if the degradation level is less than the threshold, memory controllers 100 and 100' can execute operation S66.

[0136] In operation S64, the read level can be inferred using degradation information about the block corresponding to the read request. Specifically, memory controllers 100 and 100' provide verified degradation information about the block to the artificial intelligence model 110, and the read level inferred from the artificial intelligence model 110 can be obtained. In operation S65, data can be read using the inferred read level. Memory controllers 100 and 100' can send information about the inferred read level to memory device 200 via command CMD and / or control signal CTRL. Memory device 200 verifies the information about the inferred read level via command CMD and / or control signal CTRL, thereby allowing memory device 200 to read data using a read voltage corresponding to the inferred read level.

[0137] In operation S66, the default read level can be determined as the read level corresponding to the read request. In other words, memory controllers 100 and 100' can determine the default read level as the read level corresponding to the read request without inferring the read level. In operation S67, data can be read using the default read level. Memory controllers 100 and 100' can send information about the default read level to memory device 200 via command CMD and / or control signal CTRL. Memory device 200 verifies the information about the default read level via command CMD and / or control signal CTRL, thereby allowing memory device 200 to read data using the read voltage corresponding to the default read level.

[0138] according to Figures 12 to 14 As described and illustrated, memory controllers 100 and 100' pre-generate degradation level information and can determine whether to perform a read level inference operation by verifying the pre-generated degradation level information upon receiving a read request. Therefore, the time spent reading memory in response to read requests can be reduced.

[0139] Figure 15 This is a diagram illustrating an artificial intelligence model according to an embodiment of the inventive concept.

[0140] Reference Figure 15 The artificial intelligence model 110 can infer the read level corresponding to the read request by using degradation information about the block corresponding to the read request as input data, and can output the inferred read level.

[0141] The input data of the artificial intelligence model 110 can consist of various types of information included in the degradation information. For example, the input data of the artificial intelligence model 110 can be a conduction cell count, which represents the number of memory cells that are turned on when a default read level is applied to the block corresponding to the read request. Optionally, according to an embodiment, the input data of the artificial intelligence model 110 can be a first conduction cell count and a second conduction cell count, the first conduction cell count being related to when a first read level is applied to the block corresponding to the read request, and the second conduction cell count being related to when a second read level different from the first read level is applied to the block corresponding to the read request. However, examples of the input data of the artificial intelligence model 110 are not limited thereto. The input data of the artificial intelligence model 110 can be implemented using at least one or more combinations of P / E cycles, read counts, hold time, operating temperature, the number of error bits in the read data, etc. According to an embodiment, the artificial intelligence model 110 can also infer other operating conditions (e.g., programming level, erase level, etc.).

[0142] Furthermore, the artificial intelligence model 110 can be trained based on degradation information about blocks used as input data and read levels that do not produce read errors used as output data. Additionally, the artificial intelligence model 110 can be pre-trained by its manufacturer and included during the manufacture of the memory system 10. In other words, the artificial intelligence model 110, trained based on degradation information collected by its manufacturer from multiple memory systems and information on read levels that do not produce read errors, can be included during the manufacture of the memory system 10. However, embodiments of the inventive concept are not limited thereto. According to embodiments, the artificial intelligence model 110 can be trained or updated based on degradation information collected by the memory system 10 during actual operation as its input data and read levels that do not produce read errors as its output data.

[0143] Optionally, in addition to degradation information about the block, the AI ​​model 110 can be trained based on the word line number of the block corresponding to the read request, which can be further used as input data for the AI ​​model 110. The AI ​​model 110 trained in this way can output a read level corresponding to the read request by using the word line number of the block corresponding to the read request received from the host as its additional input data. Optionally, the AI ​​model 110 can use various types of information other than those described above as its input or output data.

[0144] Figure 16 This is a block diagram illustrating a solid-state drive (SSD) system according to an embodiment of the inventive concept.

[0145] Reference Figure 16 The SSD system 300 may include a host 310 and an SSD 320. The SSD 320 exchanges signals SIG with the host 310 via a signal connector and can receive power PWR via a power connector. The SSD 320 may include an SSD controller 321, an auxiliary power supply 322, and memory devices 323_1 to 323_n (e.g., flash memory 1 to flash memory n). The above references can be used... Figures 1 to 15 The described embodiments implement SSD 320. According to embodiments of the inventive concept, SSD controller 321 may include artificial intelligence model 321_1, and each of memory devices 323_1 to 323_n may include multiple blocks.

[0146] The foregoing embodiments can be applied to SSD system 300. When a read request is received from host 310, SSD controller 321 can determine the degradation level of the block corresponding to the read request based on degradation information about the block in memory devices 323_1 to 323_n corresponding to the read request, infer the read level corresponding to the read request based on the determined degradation level, and use the inferred read level to read data from memory devices 323_1 to 323_n through channels 1 to 3 (e.g., Ch1 to Ch3).

[0147] According to the foregoing embodiments, if degradation information is used to infer the read level, the reliability of the read data can be improved, and performance can be improved without incurring any overhead related to read retries. Furthermore, because the read level inference operation is performed based on the degradation level of the block corresponding to the read request, the computational overhead of the inference operation can be reduced while improving data reliability, and the frequency of read retries can be decreased.

[0148] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the claims.

Claims

1. A memory system comprising: a memory device including at least one block; a buffer configured to store degradation information about the at least one block; and a memory controller configured to, when a read request is received from a host, obtain degradation information about the at least one block corresponding to the read request from the buffer before reading data from the memory device; obtain a read level of the at least one block corresponding to the read request based on the obtained degradation information; and read data from the memory device based on the obtained read level.

2. The memory system of claim 1, wherein, The memory controller is configured to: determine a degradation level of the at least one block corresponding to the read request; inference the read level when the degradation level is equal to or greater than a threshold value, and read data based on the inferred read level; and read data based on a default read level when the degradation level is less than the threshold value.

3. The memory system of claim 1, wherein, The memory controller is configured to: include an artificial intelligence model trained to infer the read level; and obtain the read level of the at least one block corresponding to the read request by providing the degradation information to the artificial intelligence model. The artificial intelligence model is based on at least one of: an artificial neural network model, a multi-layer perceptron model, a convolutional neural network model, a decision tree model, a random forest model, an AdaBoost model, a multivariate regression analysis model, a logistic regression model, and a bootstrap aggregating model.

4. The memory system of claim 3, wherein, The memory controller includes:

5. The memory system of claim 3, wherein, a hardware accelerator configured to implement the artificial intelligence model, and the memory controller is configured to control the buffer to provide the degradation information to the hardware accelerator. 6.The memory system of claim 3, wherein, the memory controller includes: a processor including a tightly coupled memory storing the artificial intelligence model; and the memory controller is configured to control the buffer to provide the degradation information to the tightly coupled memory. 7.The memory system of claim 1, wherein, the degradation information includes at least one of a pass cell count, a fail cell count, an operating temperature, a number of error bits of read data, a program / erase cycle, a read count, and a retention time of the at least one block. 8.A memory system comprising: a memory device including a plurality of blocks; a buffer storing degradation information about at least one block of the plurality of blocks; and a memory controller configured to read data from the memory device in response to a read request from a host, wherein the memory controller includes: a hardware accelerator configured to execute an artificial intelligence model trained to infer a read level; and a processor configured to, when the read request is received from the host, control the buffer to provide the degradation information about the at least one block corresponding to the read request to the hardware accelerator before reading data from the memory device, obtain the read level of the at least one block corresponding to the read request by the artificial intelligence model based on the provided degradation information, and read data based on the obtained read level. The processor is configured to read data based on a default read level when there is no degradation information about the block corresponding to the read request.

9. The memory system of claim 8, wherein, The processor is configured to:

10. The memory system of claim 8, wherein, ​ collecting deterioration information about each of the plurality of blocks by monitoring the memory device, determining a deterioration level of each of the plurality of blocks based on the collected deterioration information about each of the plurality of blocks, and storing the deterioration information of the at least one block among the collected deterioration information about each of the plurality of blocks based on the deterioration level of each of the plurality of blocks.

11. The memory system of claim 10, wherein, the processor is configured to: store the deterioration information of a block having a deterioration level equal to or greater than a threshold value among the collected deterioration information about each of the plurality of blocks, and omit storage of the deterioration information of a block having a deterioration level less than the threshold value among the collected deterioration information about each of the plurality of blocks.

12. The memory system of claim 10, wherein, the processor is configured to collect the deterioration information about each of the plurality of blocks by monitoring the memory device at a predetermined period. 13.A method of operating a memory system including a memory device including a plurality of blocks, the method comprising: receiving a read request from a host; when the read request is received from the host, obtaining deterioration information about a block corresponding to the read request among the plurality of blocks from a buffer included in the memory system before reading data from the memory device; obtaining a read level of the block corresponding to the read request based on the obtained deterioration information; and reading data from the memory device based on the obtained read level. 14.The method of claim 13, further comprising: determining a deterioration level of the block corresponding to the read request based on the deterioration information, wherein the obtaining of the read level comprises inferring the read level based on the deterioration information when the deterioration level is equal to or greater than a threshold value, and determining a default read level as the read level when the deterioration level is less than the threshold value. the obtaining of the read level comprises:

15. The method of claim 13, wherein, providing the deterioration information to an artificial intelligence model trained to infer the read level; and obtaining the read level corresponding to the read request from the artificial intelligence model. the artificial intelligence model is based on at least one of: an artificial neural network model, a multi-layer perceptron model, a convolutional neural network model, a decision tree model, a random forest model, an AdaBoost model, a multivariate regression analysis model, a logistic regression model, and a bootstrap aggregating model.

16. The method of claim 15, wherein, the artificial intelligence model is implemented by a hardware accelerator included in the memory system.

17. The method of claim 15, wherein, the deterioration information includes at least one of a pass cell count, a cut cell count, an operating temperature, a number of error bits of read data, a program / erase cycle, a read count, and a retention time of the block.

18. The method of claim 13, wherein, 19.The method of claim 13, further comprising: storing the deterioration information about at least one block among the plurality of blocks in the buffer, wherein the storing of the deterioration information comprises: collecting the deterioration information about each of the plurality of blocks by monitoring the memory device; determining a deterioration level of each of the plurality of blocks based on the collected deterioration information about each of the plurality of blocks; and ​ The collected deterioration information about each of the plurality of blocks is stored based on a deterioration level of each of the plurality of blocks, and The step of obtaining deterioration information includes: The deterioration information about the block corresponding to the read request is obtained from the deterioration information stored in the buffer.

20. The method of claim 19, wherein, The step of storing the collected deterioration information about the at least one block among the collected deterioration information about each of the plurality of blocks includes storing the collected deterioration information about a block having a deterioration level equal to or greater than a threshold value among the collected deterioration information about each of the plurality of blocks.

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