Method, apparatus, device, and computer-readable storage medium for storage management

Abstract

According to an example embodiment of the present disclosure, a method, apparatus, device, and computer-readable storage medium for storage management are provided. A method for storage management includes: obtaining an available channel mode for multiple channels of a memory of a data processing system, the available channel mode indicating the availability of multiple channels, each of the multiple channels being associated with a set of addresses in the memory; obtaining channel data granularity, the channel data granularity indicating the size of a data block that each channel can carry; obtaining a target address of data to be transmitted on the memory; and determining a conversion address corresponding to the target address based on the available channel mode and the channel data granularity. Thus, this solution can improve the yield, service life, flexibility, and adaptability of a data processing system by dynamically mapping the target address to the conversion address.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to the field of storage, and more particularly, to methods, apparatuses, devices, and computer-readable storage media for storage management. Background Art

[0002] Currently, the use of data processing systems (e.g., chips) is becoming increasingly popular. However, as the size of the manufacturing process of the data processing system becomes smaller and smaller, the yield of the data processing system decreases rapidly. For example, the yield of a data processing system with a 7nm manufacturing process is generally between 60% and 70%. In addition, with the development of artificial intelligence (AI) technology, the processing power of data processing systems (e.g., graphics processing units (GPUs) or AI chips) continues to increase. This not only leads to larger and larger data processing systems, but also leads to higher and higher bandwidth requirements for access to the memory associated with the data processing system. For example, the current AI chip area is generally 500mm 2 , even up to 800mm 2 However, the larger the data processing system area, the lower the yield. Summary of the Invention

[0003] According to an example embodiment of the present disclosure, a solution for storage management is provided.

[0004] In a first aspect of the present disclosure, a method for storage management is provided, comprising: obtaining an available channel mode for multiple channels of a memory of a data processing system, the available channel mode indicating availability of the multiple channels, each of the multiple channels being associated with a set of addresses in the memory; obtaining a channel data granularity, the channel data granularity indicating a size of a data block that can be carried by each channel; obtaining a target address of data to be transmitted on the memory; and determining a conversion address corresponding to the target address based on the available channel mode.

[0005] In a second aspect of the present disclosure, a device for storage management is provided, comprising: an available channel mode acquisition module configured to acquire available channel modes for multiple channels of a memory of a data processing system, the available channel modes indicating the availability of the multiple channels, each of the multiple channels being associated with a set of addresses in the memory; a channel data granularity acquisition module configured to acquire channel data granularity, the channel data granularity indicating the size of a data block that can be carried by each channel; a target address acquisition module configured to acquire a target address of data to be transmitted on the memory; and a determination module configured to determine a conversion address corresponding to the target address based on the available channel mode.

[0006] In a third aspect of the present disclosure, an electronic device is provided, comprising one or more processors; and a storage device for storing one or more programs, which, when executed by the one or more processors, enables the one or more processors to implement the method according to the first aspect of the present disclosure.

[0007] In a fourth aspect of the present disclosure, a computer-readable medium is provided, on which a computer program is stored. When the program is executed by a processor, the method according to the first aspect of the present disclosure is implemented.

[0008] In a fifth aspect of the present disclosure, a computer program product is provided, comprising computer program instructions, which are used by a processor to implement the method according to the first aspect of the present disclosure.

[0009] It should be understood that the contents described in the Summary of the Invention section are not intended to limit the key or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. In the accompanying drawings, the same or similar reference numerals represent the same or similar elements, wherein:

[0011] Figure 1 shows a schematic diagram of a conventional memory;

[0012] Figure 2 A schematic diagram of a memory according to an embodiment of the present disclosure is shown;

[0013] Figure 3 A flowchart illustrating a process for storage management according to some embodiments of the present disclosure is shown;

[0014] Figure 4 shows a flowchart of another process for storage management according to some embodiments of the present disclosure;

[0015] Figure 5 A schematic diagram illustrating dynamic address mapping according to some embodiments of the present disclosure is shown;

[0016] Figure 6 A schematic diagram illustrating an address within a channel according to some embodiments of the present disclosure is shown;

[0017] Figure 7 A schematic block diagram illustrating an apparatus for storage management according to some embodiments of the present disclosure is shown; and

[0018] Figure 8A block diagram of a computing device capable of implementing some embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0019] The following describes embodiments of the present disclosure in more detail with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustrative purposes only and are not intended to limit the scope of protection of the present disclosure.

[0020] In the description of the embodiments of the present disclosure, the term "including" and similar terms should be understood as open inclusion, that is, "including but not limited to." The term "based on" should be understood as "based at least in part on." The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment." The terms "first," "second," etc. may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0021] The term "data processing system" may refer to a chip such as a central processing unit (CPU), a GPU, or an AI chip. However, the data processing system is not limited thereto and may be any device that uses a channel to transmit data.

[0022] As mentioned above, the processing power of data processing systems continues to increase, resulting in higher and higher bandwidth requirements for access to memories associated with data processing systems. Single-channel memories cannot provide the bandwidth required by certain applications (such as AI applications), so data processing systems use multi-channel interleaving technology to increase the bandwidth of memories. The more interleaved channels, the higher the bandwidth. This also means that the area of ​​the memory controller (including the physical layer) is larger. Taking the 8-channel sixth edition graphics double data rate memory (GDDR6 memory) as an example, it provides a bandwidth of about 384GB / s. For about 300mm 2 For AI chips, such GDDR6 memory occupies about 20% of the area of ​​the AI ​​chip.

[0023] Traditionally, data to be transmitted is statically mapped to channels for data transmission. When this static mapping method is used, if one or more channels cannot pass the automated test equipment (ATE) test due to process reasons (such as, a channel scan fails), the data processing system is considered to be faulty and unavailable. In addition, even for data processing systems that pass the ATE test, due to the high power consumption and high temperature of certain applications (such as AI applications) during use, the data processing system ages faster, which may cause one or more channels to become unstable or even damaged. For example, the GPU on the computing equipment used to obtain Bitcoin usually becomes unstable and needs to be replaced in about a year, which is far less than the average service life of a data center server.

[0024] Such a conventional memory 100 structure will be combined with Figure 1 As described above, a data processing system can use multi-channel interleaving technology to improve memory bandwidth. For N-channel memory interleaving, the memory network on chip (NoC_Mem) can use, for example, an M*N crossbar switch matrix to connect input interfaces and memory controllers, where M and N are positive integers.

[0025] like Figure 1 As shown, the memory 100 includes M input interfaces 1100-110 M-1 (hereinafter collectively referred to as “input interface 110 ”), memory on-chip network 120 , N memory controllers 1300 - 130 N-1 (hereinafter collectively referred to as “memory controller 130 ”), and corresponding to N memory controllers 1300 - 130 N-1 The number M of input interfaces 110 is generally greater than the number N of channels to ensure that the total input bandwidth of the memory network on chip 120 is not less than the total output bandwidth. Furthermore, the number M of input interfaces 110 is set to a larger value to facilitate quality of service (QoS) control.

[0026] The input interface 110 is used to receive data to be transmitted and provide the data to be transmitted to the memory network on chip 120. The data to be transmitted is distributed to one or more channels among N channels through the memory network on chip 120 and transmitted to the corresponding memory controller 130 via the distributed one or more channels.

[0027] Specifically, in multi-channel interleaving technology, interleaving granularity (interchangeably referred to as channel data granularity) is used to control the size of the data block that each channel can carry. For example, the channel data granularity can be in bytes and can be, for example, 64B, 128B, 256B, etc. Assume that the number of channels is 8, the channel data granularity is 128B, and the input interface 110 receives 1KB of data to be transmitted. When a static mapping method is adopted, the data to be transmitted is allocated to each of the 8 channels for transmission. In other words, 1KB of data to be transmitted will be split into 8 128B data blocks to be allocated to the 8 channels for transmission. It can be seen that since each channel needs to transmit data, any channel damage will make data transmission impossible, thereby causing the data processing system to malfunction. For this reason, a dynamic mapping solution is proposed here.

[0028] In general, according to an embodiment of the present disclosure, an available channel pattern and channel data granularity for multiple channels of a memory of a data processing system are obtained. The available channel pattern indicates the availability of multiple channels. For example, the available channel pattern can be represented in binary, decimal, hexadecimal, or the like. When the available channel pattern is represented in binary form, a bit with a value of 1 indicates that the corresponding channel is available, while a bit with a value of 0 indicates that the corresponding channel is unavailable. Assuming that the number of channels is 8 and the available channel pattern is "10110111", it means that channels 0, 1, 2, 4, 5, and 7 are available, and channels 3 and 6 are unavailable.

[0029] As described above, the channel data granularity can control the size of the data block that each channel can carry. For example, the channel data granularity can be in bytes and can be, for example, 64B, 128B, 256B, etc.

[0030] Each of the multiple channels is associated with a set of addresses in the memory. Specifically, the target address of the data to be transmitted in the memory can be used to determine which of the multiple channels to use for transmission. Thus, the principle of dynamic mapping is to determine the translation address corresponding to the target address based on the available channel pattern and the channel data granularity, so that the data to be transmitted will be transmitted on the available channels and not on unavailable channels according to the translation address.

[0031] Taking eight channels as an example, if one channel is detected as unavailable, data is interleaved as 7 channels, distributing the data across the seven available channels for transmission. If two channels are detected as damaged, data is interleaved as 6 channels, distributing the data across the six available channels for transmission. In this article, the term "interleaving" refers to the method of distributing data across channels for transmission. In contrast, with static mapping, any unavailable channel renders the entire data processing system unavailable.

[0032] When dynamic mapping is used, assuming the data processing system yield is 60% and the memory occupies 20% of the data processing system area, the yield can be improved by 8% (= (1-60%) * 20%). When the memory occupies a larger area of ​​the data processing system (such as for high-bandwidth memory (HBM)), the yield and service life of the data processing system can be further improved.

[0033] Dynamic mapping can also improve the flexibility of data processing systems. For example, in Internet of Things (IoT) applications, where bandwidth requirements are low, a subset of multiple channels can be interleaved to reduce costs.

[0034] Furthermore, in different application scenarios, the channel data granularity may lead to different performances. Dynamic mapping can support dynamic changes in the channel data granularity to adapt to different application scenarios.

[0035] In the following, we will combine Figure 2-Figure 8 A specific example of this solution is described in more detail. Note that although this solution is described using multi-channel interleaving technology as an example, this solution can be used to manage any memory involving transmission modes such as channels, pipes, etc.

[0036] Figure 2 FIG. 1 shows a schematic diagram of a memory 200 according to an embodiment of the present disclosure. Figure 1 Similar to the memory 100 shown, the memory 200 includes M input interfaces 1100-110 M-1 (hereinafter collectively referred to as “input interface 110 ”), memory on-chip network 120 , N memory controllers 1300 - 130 N-1 (hereinafter collectively referred to as “memory controller 130 ”), and corresponding to N memory controllers 1300 - 130 N-1 N channels (channel 0 - channel N-1).

[0037] The difference between the memory 200 and the memory 100 is that the memory 200 further includes address mappers 2301-230 M-1 (Hereinafter collectively referred to as "address mapper 230"). Address mapper 230 maps the target address of the data to be transferred on the memory into a translation address based on the available channel pattern of the N channels and the channel data granularity. Based on the translation address, the data is transferred on the available channels and not on unavailable channels. For example, if channels 0, 1, 2, 4, 5, and 7 are available, but channels 3 and 6 are unavailable, the data is transferred only on the available channels 0, 1, 2, 4, 5, and 7, and not on the unavailable channels 3 and 6.

[0038] Note that although Figure 2The address mapper 230 is shown as being disposed between the input interface 110 and the memory on-chip network 120, but the address mapper 230 may be implemented at any location, for example, the address mapper 230 may be implemented inside the memory, outside the memory, or even outside the data processing system.

[0039] When using the address mapper 230, the input interface 110 receives the data to be transmitted and provides the data to the address mapper 230. The address mapper 230 maps the target address of the data to be transmitted on the memory into a translation address. The memory on-chip network 120 allocates the data to one or more available channels among the N channels based on the translation address. The data to be transmitted is then transmitted to the memory controller 130 via the allocated available channels.

[0040] For example, assume the number of channels is 8, the channel data granularity is 128B, the available channel pattern is "10110111", and input interface 110 receives 1KB of data to be transmitted. Using dynamic mapping, the data to be transmitted is allocated to each of the six available channels for transmission. Specifically, the 1KB of data to be transmitted is split into eight 128B data blocks, which are then allocated to the six available channels for transmission.

[0041] In this way, even if unavailable channels exist in the data processing system, data can still be transmitted through available channels, thereby improving the yield and service life of the data processing system. Furthermore, this solution can dynamically adapt to different applications or scenarios by setting the channel data granularity and available channel mode, thereby increasing the flexibility and adaptability of the data processing system.

[0042] Figure 3 A flowchart of a process 300 for storage management according to some embodiments of the present disclosure is shown. For example, the method 300 may be performed in a Figure 2 The method 300 may include additional steps not shown and / or may omit steps shown, and the scope of the present disclosure is not limited in this respect.

[0043] At 310, the address mapper 230 obtains an available channel pattern for a plurality of channels of a memory of the data processing system. As described above, each of the plurality of channels is associated with a set of addresses in the memory. Furthermore, the available channel pattern indicates the availability of the plurality of channels and may be represented in binary, decimal, hexadecimal, or any other suitable format. In some embodiments, the address mapper 230 may obtain information regarding unavailable channels among the plurality of channels and determine the available channel pattern by analyzing the information regarding the unavailable channels. For example, the information may indicate that channels 3 and 6 are damaged and unavailable, and thus the available channel pattern may be determined to be "10110111."

[0044] At 320, the address mapper 230 obtains the channel data granularity. The channel data granularity indicates the size of the data block that each channel can carry. For example, the channel data granularity can be in bytes and can be, for example, 64B, 128B, 256B, etc. Furthermore, at 330, the address mapper 230 obtains the target address of the data to be transmitted on the memory. For example, the target address is the address at which the data to be transmitted is to be written to the memory.

[0045] Thus, at 340, the address mapper 230 determines a translation address corresponding to the target address based on the available channel pattern and the channel data granularity, so that according to the translation address, the data will be transmitted on the available channel and not on the unavailable channel. In this way, the yield, service life, flexibility, and adaptability of the data processing system can be improved.

[0046] The following will be combined Figure 4 A flowchart depicting a more detailed example process 400 for storage management according to some embodiments of the present disclosure. For example, the method 400 may be implemented in a manner such as Figure 2 The method 400 may include additional steps not shown and / or may omit steps shown, and the scope of the present disclosure is not limited in this respect.

[0047] At 410, the address mapper 230 divides the target address into a high-order portion and a low-order portion based on the channel data granularity. The high-order portion of the target address corresponds to a data block in a data block set associated with the data to be transmitted, while the low-order portion corresponds to a portion of a data block.

[0048] For example, assuming that the target address is addr[AW-1:0], where AW represents the address bit width, for example, the address bit width can be 32 bits (AW=32). In addition, assuming that the channel data granularity K is 256B, it can be represented by 8 bits, that is, the channel data granularity bit width KW is 8. Thus, based on the target address addr[AW-1:0] and the channel data granularity, the high-order part addr[AW-1:KW] and the low-order part addr[KW-1:0] can be generated. It can be understood that the high-order part addr[AW-1:KW] can indicate a data block that can be carried by a channel, and the low-order part addr[KW-1:0] can indicate a specific address within the data block.

[0049] At 420, the address mapper 230 determines the number of available channels based on the available channel pattern. For example, if the available channel pattern is "10110111," the address mapper 230 may determine that six channels are available, i.e., the number of available channels is six. Alternatively, the address mapper 230 may obtain information regarding unavailable channels among the plurality of channels and determine the number of available channels by analyzing the information regarding the unavailable channels. For example, the information may indicate that channels 3 and 6 are damaged and unavailable, thereby determining the number of available channels to be six.

[0050] At 430, the address mapper 230 determines an available channel for transmitting the data block to be transmitted from the plurality of channels based on the high-order portion and the number of available channels. In some embodiments, a modulo operation can be performed on the high-order portion and the number of available channels to determine the available channel. For example, the modulo obtained by dividing the high-order portion addr[AW-1:KW] by the number of available channels N can be used to select the available channel. For ease of understanding, this will be combined with Figure 5 Describe, where Figure 5 A schematic diagram 500 illustrating dynamic address mapping according to some embodiments of the present disclosure is shown.

[0051] Figure 5 In this example, the number of channels is 8, the available channel pattern is "10110111", the number of available channels is 6, and the channel data granularity is 256 bytes. For example, the target address "0X05_XX" is used as an example, where "0X" represents the address in hexadecimal, "05" represents the high-order address, and "XX" represents the low-order address. Since the low-order address is not involved in determining the available channels or the address within a channel, "XX" is used as a general reference.

[0052] In this case, the modulo division of the high-order portion "05" by the number of available channels (6) yields modulo 5. An available channel can then be selected based on the modulo. For example, a bit with a value of 1 can be added to the modulo from the lowest to the highest bit in the available channel pattern, and the channel indicated by the bit with a value of 1 can be determined as the available channel for the data block associated with the high-order portion "05." In the case of a modulo of 5, the channel indicated by the sixth bit with a value of 1 in the available channel pattern (i.e., channel 7) is determined as the available channel. For comparison, the original channel of this data block is channel 5.

[0053] Return Reference Figure 4 At 440, the address mapper 230 determines the intra-channel address of the data block to be transmitted on the available channel based on the high-order portion and the number of available channels. The intra-channel address represents the address of the data block within each channel. In some embodiments, it can be used to indicate the order in which the data blocks are transmitted via the channels.

[0054] The following will be combined Figure 6 Describes the address within the channel, where Figure 6 Schematic diagram 600 of an intra-channel address according to some embodiments of the present disclosure is shown. Figure 6 As shown, the leftmost column represents the channel address, such as 0-N, and each of the remaining columns represents a channel, such as channels 0-7. The number in each box represents the sequence number of the data block. In some embodiments, the sequence number can be indicated by the high-order address. Since the channel address can indicate the order in which the data blocks are transmitted via the channel, data block 0 with channel address 0 will be transmitted via the channel before data block 8 with channel address 1, and data block 8 with channel address 1 will be transmitted via the channel before data block 16 with channel address 2, and so on.

[0055] In some embodiments, the intra-channel address can be determined by taking the quotient of the high-order portion and the number of available channels. Figure 6 As shown in the figure, assuming that the available channel pattern is "10110111" and the number of available channels is 6, the quotients obtained by dividing the upper-order addresses "00" and "06" by the number of available channels, 6, are "0" and "1" respectively, that is, the intra-channel addresses are "0" and "1" respectively. Furthermore, since the data blocks associated with the upper-order addresses "00" and "06" are both determined to be transmitted using channel 0, and the intra-channel addresses of these two data blocks in channel 0 are "0" and "1" respectively, the data block associated with the upper-order address "00" will be transmitted via channel 0 before the data block associated with the upper-order address "06".

[0056] Return Reference Figure 4At 450, the address mapper 230 generates a translation address based on the available channels, the intra-channel address, and the low-order portion. In some embodiments, the high-order portion of the translation address can be determined based on the available channels and the intra-channel address, and the low-order portion of the translation address can be determined based on the low-order portion. For example, assume that the intra-channel address is represented as 1 bit in binary, and the available channels are represented as 3 bits in binary. In this case, Figure 6 As shown in FIG. 1 , the intra-channel address for the target address “0X05_XX” is “0” and the available channels are “7” (i.e., “111”), so the upper portion of the conversion address can be determined as “07” (i.e., “0111”). In addition, the lower portion of the target address “0X05_XX” is “XX”, so the lower portion of the conversion address can be determined as “XX”.

[0057] Therefore, by dynamically mapping the target address in combination with information of available channels, data can be transmitted on available channels instead of unavailable channels according to the converted address, thereby improving the yield and service life of the data processing system.

[0058] Dynamic mapping also improves the flexibility of data processing systems. In low-bandwidth applications, only a portion of the predefined bandwidth may be required. For example, only four of the eight channels may be needed. In this case, by alternating the available channel patterns to "11110000" and "00001111," different four channels can be used alternately. This balances channel usage, thereby increasing service life compared to fixed use of channels 0-3.

[0059] Furthermore, in different application scenarios, the channel data granularity may lead to different performances. Dynamic mapping can support dynamic changes in the channel data granularity to adapt to different application scenarios.

[0060] Figure 7 FIG. 7 is a schematic block diagram of an apparatus 700 for storage management according to some embodiments of the present disclosure. Figure 7 As shown, the apparatus 700 includes: an available channel mode acquisition module 710, configured to be configured to acquire available channel modes of multiple channels of a memory of a data processing system, the available channel mode indicating the availability of multiple channels, each of the multiple channels being associated with a set of addresses in the memory; a channel data granularity acquisition module 720, configured to acquire channel data granularity, the channel data granularity indicating the size of a data block that can be carried by each channel; a target address acquisition module 730, configured to acquire a target address of data to be transmitted on the memory; and a determination module 740, configured to determine a conversion address corresponding to the target address based on the available channel mode.

[0061] In some embodiments, the available channel mode acquisition module 710 includes: an unavailable channel information acquisition module configured to acquire information related to unavailable channels among multiple channels; and an available channel mode determination module configured to determine the available channel mode based on the information related to the unavailable channels.

[0062] In some embodiments, the determination module 740 includes: an address division module, configured to divide the target address into a high-order part and a low-order part based on the channel data granularity, the high-order part corresponds to a data block in a set of data blocks associated with the data to be transmitted, and the low-order part corresponds to a part of a data block; an available channel number determination module, configured to determine the number of available channels based on the available channel mode; an available channel determination module, configured to determine an available channel for transmitting the data block to be transmitted from multiple channels based on the high-order part and the number of available channels; an intra-channel address determination module, configured to determine the intra-channel address of the data block to be transmitted on the available channel; and a generation module, configured to generate a conversion address based on the available channels, the intra-channel address and the low-order part.

[0063] In some embodiments, the available channel determination module includes: a modulo module configured to perform a modulo operation on the high-order portion and the number of available channels to determine the available channels.

[0064] In some embodiments, the intra-channel address determination module includes: a quotient module configured to perform a quotient operation on the high-order portion and the number of available channels to determine the intra-channel address.

[0065] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium, and a computer program product for storage management.

[0066] Figure 8 Schematic block diagram of an example device 800 that can be used to implement embodiments of the present disclosure. Figure 2 As shown in the figure, the device 800 includes a central processing unit (CPU) 801, which can perform various appropriate actions and processes according to computer program instructions stored in a read-only memory (ROM) 802 or loaded from a storage unit 808 into a random access memory (RAM) 803. Various programs and data required for the operation of the device 800 can also be stored in the RAM 803. The CPU 801, ROM 802, and RAM 803 are connected to each other via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0067] Various components in device 800 are connected to I / O interface 805, including an input unit 806, such as a keyboard, mouse, etc.; an output unit 807, such as various types of displays, speakers, etc.; a storage unit 808, such as a magnetic disk, optical disk, etc.; and a communication unit 809, such as a network card, modem, wireless communication transceiver, etc. The communication unit 809 allows device 800 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0068] The processing unit 801 performs the various methods and processes described above, such as processes 300 and 400. For example, in some embodiments, processes 300 and 400 may be implemented as computer software programs that are tangibly contained in a machine-readable medium, such as a storage unit 808. In some embodiments, part or all of the computer program may be loaded and / or installed onto the device 800 via the ROM 802 and / or the communication unit 809. When the computer program is loaded into the RAM 803 and executed by the CPU 801, one or more steps of the processes 300 and 400 described above may be performed. Alternatively, in other embodiments, the CPU 801 may be configured to perform processes 300 and 400 in any other suitable manner (e.g., by means of firmware).

[0069] The functions described above herein may be performed, at least in part, by one or more hardware logic components. For example, and without limitation, exemplary types of hardware logic components that may be used include: field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), and the like.

[0070] The program code for implementing the method of the present disclosure can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device so that when the program code is executed by the processor or controller, the functions / operations specified in the flow chart and / or block diagram are implemented. The program code can be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0071] In the context of the present disclosure, a machine-readable medium can be a tangible medium that can contain or store a program for use by or in conjunction with an instruction execution system, device or equipment. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium can include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0072] In addition, although adopting specific order to describe each operation, this should be understood as requiring such operation to be carried out in the specific order shown or in sequential order, or requiring that all illustrated operations should be carried out to obtain desired results. Under certain circumstances, multitasking and parallel processing may be advantageous. Similarly, although comprising some specific implementation details in the above discussion, these should not be interpreted as limiting the scope of the present disclosure. Some features described in the context of separate embodiment can also be implemented in a single implementation in combination. On the contrary, the various features described in the context of a single implementation also can be implemented in a plurality of implementations individually or in the mode of any suitable subcombination.

[0073] Although the subject matter has been described in language specific to structural features and / or methodological logical acts, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are merely example forms of implementing the claims.

Claims

1. A method for storage management, comprising: obtaining an available channel pattern for a plurality of channels of a memory of a data processing system, the available channel pattern indicating availability of the plurality of channels, each channel of the plurality of channels being associated with a set of addresses in the memory; Acquire channel data granularity, where the channel data granularity indicates the size of a data block that can be carried by each channel; Obtaining a target address of the data to be transmitted on the memory; Based on the channel data granularity, the target address is divided into a high-order portion and a low-order portion, wherein the high-order portion corresponds to a data block in a data block set associated with the data to be transmitted, and the low-order portion corresponds to a portion of the data block; Determining the number of available channels based on the available channel pattern; Determining, from the plurality of channels, an available channel for transmitting the to-be-transmitted data block based on the high-order portion and the number of available channels; Determining, based on the high-order portion and the number of available channels, an intra-channel address of the data block to be transmitted on the available channel; as well as A translation address is generated based on the available channels, the intra-channel address, and the lower portion.

2. The method according to claim 1, wherein obtaining the available channel mode comprises: obtaining information about unavailable channels among the plurality of channels; as well as The available channel mode is determined based on the information related to the unavailable channels.

3. The method of claim 1 , wherein determining the available channels comprises: A modulo operation is performed on the high-order portion and the number of available channels to determine the available channels.

4. The method of claim 1 , wherein determining the intra-channel address comprises: A quotient operation is performed on the high-order portion and the number of available channels to determine the intra-channel address.

5. A device for storage management, comprising: an available channel pattern acquisition module configured to acquire an available channel pattern for a plurality of channels of a memory of a data processing system, the available channel pattern indicating availability of the plurality of channels, each channel of the plurality of channels being associated with a set of addresses in the memory; a channel data granularity acquisition module configured to acquire channel data granularity, where the channel data granularity indicates the size of a data block that can be carried by each channel; A target address acquisition module is configured to acquire a target address of the data to be transmitted on the memory; as well as a determining module configured to divide the target address into a high-order portion and a low-order portion based on the channel data granularity, wherein the high-order portion corresponds to a data block in a data block set associated with the data to be transmitted, and the low-order portion corresponds to a portion of the data block; Determining the number of available channels based on the available channel pattern; Determining, from the plurality of channels, an available channel for transmitting the to-be-transmitted data block based on the high-order portion and the number of available channels; Determining, based on the high-order portion and the number of available channels, an intra-channel address of the data block to be transmitted on the available channel; as well as A translation address is generated based on the available channels, the intra-channel address, and the lower portion.

6. The apparatus according to claim 5, wherein acquiring the available channel mode comprises: obtaining information about unavailable channels among the plurality of channels; as well as The available channel mode is determined based on the information related to the unavailable channels.

7. The apparatus of claim 5, wherein determining the available channel comprises: A modulo operation is performed on the high-order portion and the number of available channels to determine the available channels.

8. The apparatus of claim 5, wherein determining the intra-channel address comprises: A quotient operation is performed on the high-order portion and the number of available channels to determine the intra-channel address.

9. An electronic device, comprising: one or more processors; as well as A storage device for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the method according to any one of claims 1 to 4.

10. A computer-readable storage medium having a computer program stored thereon, wherein when the program is executed by a processor, the method according to any one of claims 1 to 4 is implemented.

11. A computer program product comprising a computer program, which, when executed by a processor, implements the method according to any one of claims 1 to 4.

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