A method and system for managing tracks in a storage device

Abstract

A computer program product, system, and method for managing the addition of an accessed track to the most recently used end of a cache list in a cache. The cache list for the cache has a least recently used (LRU) end and a most recently used (MRU) end. Tracks in the cache are indicated in the cache list. The track in the cache indicated in the cache list is accessed. It is determined whether the track cache residency time since the accessed track was last accessed while in the cache list is within a minimum track cache residency time range. In response to determining that the track cache residency time of the accessed track is within the minimum track cache residency time range, a flag indicating that the track is at the MRU end is set for the accessed track. After setting the flag, the accessed track remains in its current position in the cache list before being accessed.

Description

Technical Field

[0001] The present invention relates to a computer program product, system, and method for managing the addition of accessed tracks to the most recently used end of a cache list in a cache. Background Art

[0002] As a result of read and write operations in an access storage device (e.g., a memory) that is faster than the storage device storing the requested track, a cache management system buffers tracks in the most recently accessed storage device. Compared to returning the requested track from the slower access storage device, subsequent read requests for tracks in the faster access cache memory are returned at a faster speed, thereby reducing read latency. When writing a modified track pointing to the storage device to the cache memory, and before writing the modified track out to a storage device such as a hard disk drive, the cache management system may also return to complete the write request. Generally, the write latency of a storage device is much longer than the latency of writing to the cache memory. Therefore, using a cache also reduces write latency.

[0003] A cache management system may maintain a linked list with one entry for each track stored in the cache, and the track may include write data or read data buffered in the cache before being written to the storage device. In a general least recently used (LRU) cache technique, if a track in the cache is accessed, i.e., the cache "hits", the entry for the accessed track in the LRU cache list is moved to the most recently used (MRU) end of the list. If the requested track is not in the cache, i.e., the cache misses, the track whose entry is at the LRU end of the list in the cache may be removed and demoted, and an entry for the track data entering the cache from the storage device is added to the MRU end of the LRU list. Using this LRU cache technique, tracks that are accessed more frequently are likely to remain in the cache, while data that is accessed less frequently is more likely to be removed from the LRU end of the list, thus making room for newly accessed tracks in the cache.

[0004] To move a track to the MRU end when the track is accessed, the process managing the cache needs to obtain a lock on the LRU cache list. Since many processes strongly seek this lock, there may be a large amount of lock contention to obtain the lock.

[0005] One technique for resolving lock contention is to batch the tracks that need to be moved to the MRU end into the MRU array. When the MRU array is full, all the tracks in the MRU array are moved to the MRU end of the cache list. Another technique for resolving lock contention is cache partitioning, where multiple LRU lists are maintained for different track partitions, and each partition has its own LRU lock.

[0006] There is a need in the art for improved techniques for moving tracks towards the MRU end of the cache when the tracks are accessed. SUMMARY OF THE INVENTION

[0007] A computer program product, system, and method for managing the addition of accessed tracks to the most recently used (MRU) end of a cache list in a cache. The cache list for the cache has a least recently used (LRU) end and a most recently used (MRU) end. Tracks in the cache are indicated in the cache list. A track indicated in the cache list in the cache is accessed. It is determined whether the track cache residency time of the accessed track since the last time it was accessed while in the cache list is within a minimum track cache residency time range. In response to determining that the track cache residency time of the accessed track is within the minimum track cache residency time range, a flag indicating that the track is at the MRU end is set for the accessed track. After setting the flag, the accessed track remains in its current position in the cache list before being accessed. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 An embodiment of a computing environment is shown.

[0009] Figure 2 An embodiment of a least recently used (LRU) list is shown.

[0010] Figure 3 An embodiment of a cache control block is shown.

[0011] Figure 4 An embodiment of an operation for processing an access request to a track is shown.

[0012] Figure 5 An embodiment of an operation for initiating a downgrade scan to downgrade a track from the LRU end of a cache list is shown.

[0013] Figure 6 An embodiment of an operation for processing tracks in an MRU array is shown.

[0014] Figure 7 Shows Figure 1 the computing environment in which the components of DETAILED DESCRIPTION

[0015] In the prior art, accessed tracks can be batch - processed and then re - positioned at the MRU end of the cache list. Operations for moving the indication of tracks into and out of the cache list result in latency when processing read / write requests to obtain the locks required to move tracks into and out of the cache list. The described embodiments provide an improvement to computer cache technology by providing enhanced decision - making to determine whether a track (e.g., at the least recently used (LRU) end of the cache list) being considered for demotion should be added back to the MRU end. In the described embodiments, before moving an accessed track in the cache back to the MRU end, it is considered whether the track cache residency time of the accessed track is within the range of the lowest track cache residency time of the tracks indicated in the cache list. If the accessed track is within the lowest track cache residency time range, in response to determining that the track cache residency time of the accessed track is within the lowest track cache residency time range, a flag indicating that the accessed track is at the MRU end is set for the accessed track. After setting the flag, the accessed track remains at its current position in the cache list before being accessed.

[0016] Using the described embodiments, cache latency is reduced because accessed tracks that may have a high cache hit rate do not move to the MRU array or are not immediately remade MRU (which requires resources to complete). Instead, accessed tracks with a high probability of having a high cache hit rate are still indicated at the same position in the cache list, and a flag is set to ensure that they are moved back to the MRU end when they reach the LRU end of the cache list.

[0017] Figure 1 An embodiment of a computing environment is shown. Multiple hosts 1021, 1022... 102 n can submit input / output (I / O) requests via network 106 to storage controller 104 to access data at volume 108 in storage device 110 (e.g., logical unit number, logical device, logical subsystem, etc.). Storage controller 104 includes one or more processors 112 and a memory 114, and the memory 114 includes a cache 116 for caching data for storage device 110. Processor 112 can include a separate central processing unit (CPU), one core on a single CPU, or a group of multiple cores, or a set of processing resources on one or more CPUs. Data transferred between hosts 1021, 1022... 102 n and volume 108 of storage device 110 is buffered in cache 116.

[0018] Memory 114 further includes: a storage manager 118 for managing between hosts 1021, 1022... 102n Transfer of tracks transferred between the storage device 110; and a cache manager 120, which manages the transfer of data in the cache 116 between the host 1021, 1022... 102 n Data in the cache 116 transferred between the storage device 110. A track can include any data unit configured in the storage device 110, such as a track, a logical block address (LBA), a storage cell, a group of cells (e.g., a column, row, or array of cells), a sector, a field, etc., which may be part of a larger track grouping (e.g., a volume, a logical device, etc.).

[0019] The cache manager 120 maintains cache management information 122 in the memory 114 to manage read (unmodified) and write (modified) tracks in the cache 116. The cache management information 122 can include: a least recently used (LRU) cache list 200, which indicates the tracks in the cache 116; a track index 124, which provides an index of the tracks in the cache 116 to the cache control blocks in the control block directory 300, where there is a cache control block for each track in the cache 116, which provides metadata on the tracks in the cache 116, and the cache list 200 can indicate the cache control blocks 300 in the directory 300 i ; a most recently used (MRU) array 126, also referred to as an MRU list, which has tracks added to the cache 116 that are not yet indicated in the cache list 200, to allow a batch of tracks to be added to the cache list 200 at one time to improve cache processing efficiency, because multiple newly added tracks can be added to the cache 116 in the cache list 200 using a single lock request; and a demotion ready list 128, which indicates the tracks that are removed from the LRU end 204 of the cache list 200 and are ready to be demoted from the cache 116.

[0020] The processor 112 executes a demotion scan task 130 for scanning the cache list 200 to determine the unmodified tracks to be added to the demotion ready list 128.

[0021] As the program code is loaded into the memory 114 and executed by one or more processors 112, the storage manager 118, the cache manager 120, and the demotion scan task 130 are shown in Figure 1 . Optionally, some or all of the functions can be implemented as microcode or firmware in a hardware device in the storage controller 104, such as in an application-specific integrated circuit (ASIC).

[0022] The storage device 110 may include one or more storage devices known in the art, such as solid-state storage devices (SSDs) composed of solid-state electronic devices, NAND storage cells, EEPROM (electrically erasable programmable read-only memory), flash memory, flash drives, random access memory (RAM) drives, storage class memory (SCM), phase change memory (PCM), resistive random access memory (RRAM), spin transfer torque memory (STM-RAM), conductive bridge RAM (CBRAM), magnetic hard disk drives, optical discs, magnetic tapes, etc. The storage device may be further configured as an array of devices, such as, for example, a Just a Bunch of Disks (JBOD), a direct access storage device (DASD), a redundant array of independent disks (RAID) array, a virtualized device, etc. Additionally, the storage device may include heterogeneous storage devices from different vendors or from the same vendor.

[0023] The memory 114 may include suitable volatile or non-volatile storage devices, including those described above.

[0024] The network 106 may include a storage area network (SAN), a local area network (LAN), a wide area network (WAN), the Internet, and an intranet, etc. Alternatively, the hosts 1021, 1022... 102 n may be connected to the storage controller 104 through a bus interface (e.g., a Peripheral Component Interconnect (PCI) bus interface and other interfaces known in the art).

[0025] Figure 2 An embodiment of the cache list 200 as the Least Recently Used (LRU) list 200 is shown, which has the Most Recently Used (MRU) end 202 and the Least Recently Used (LRU) end 204. The Most Recently Used (MRU) end 202 identifies the track that was most recently added to the cache 116 or most recently accessed in the cache 116. The tracks identified at the LRU end starting from the Least Recently Used (LRU) end 204 are selected to be demoted from the cache 116. When a track is added to the MRU end 202, the other tracks move down towards the LRU end 204. If there is not enough space to add a track to the MRU end 202, a track may be demoted from the LRU end 204 to make room for the new track to be added to the cache list 200.

[0026] Figure 3 An embodiment of an instance of the cache control block 300 for one track in the cache 116 is shown i of the cache control block 300 i includes but is not limited to: a cache control block identifier 302, such as the cache control block 300 iThe index value; the cache list 304, which indicates the cache control block 300 associated with the track i ; the position of the track indicated in the LRU cache list 306; the last access timestamp 308, which indicates the time when the track was last accessed (e.g., read) in the cache 116; the re-MRU flag 310, which indicates whether the track needs to be indicated at the MRU end 202 of the cache list 200 if the track is accessed when indicated in the cache list 200; the downgrade status 312, which indicates whether the track identified by the cache control block 300 i should be downgraded from the cache 116 and whether it is indicated in the downgrade preparation list 128. The cache control block 300 i may include additional information for managing the tracks in the cache 116 not mentioned herein.

[0027] In some embodiments, the timestamp 308 can be set to a sequence number that increments periodically, for example, every clock cycle or every few milliseconds.

[0028] Figure 4 An embodiment of the operation performed by the cache manager 120 for processing an access request (such as a read or write) to a track is shown. (At block 400) When an access request is received, if (at block 402) the track is in the cache 116, then (at block 404) the last access timestamp 308 for the accessed track in the cache control block 300 i is set to the current system timestamp. If (at block 406) the cache 116 size is less than the threshold case size, then (at block 408) the indication of the accessed track in the cache list 200 is removed from the cache list 200, and when a condition is met (such as the MRU array 126 is full), (at block 410) the accessed track is indicated to be bulk added to the MRU end 202 in the MRU array 126. If (at block 406) the cache 116 size is greater than (or greater than or equal to) the threshold cache size, then (at block 412) the minimum cache residency time range of the tracks in the cache list 200 (the track with the least amount of time resident in the cache since the track was last accessed), which also includes the range of the most recently and most frequently accessed track in the cache 200, is determined. (At block 414) The track cache residency time of the processed track is also determined along with the current timestamp and the last access timestamp 308 of the processed track.

[0029] The minimum track cache residency time range may include a percentage of the entire cache residency time. Tracks with a track cache residency time within or less than the percentage of the entire cache residency time will be within the minimum track cache residency time range. Tracks with a track cache residency time greater than the percentage of the entire cache residency time will be outside the minimum cache residency time range. The minimum track cache residency time range may also include the range of the track when the most recently accessed track is in the cache list 200.

[0030] The track cache residency time may include the difference between the current timestamp and the last access time 308 of the accessed track. The entire cache residency time may be calculated as the difference between the current timestamp and the last access timestamp 308 of the track at the LRU end 204 of the cache list 200. Alternatively, the entire cache residency time may be calculated as the difference between the last access timestamp 308 of the track at the MRU end 202 and the last access timestamp 308 of the track at the LRU end 204. The predetermined percentage applied to the entire cache residency time to determine the minimum track cache residency time range may include: a value less than 50% (e.g., 25%), which includes the most recently and frequently accessed tracks above, and caching these tracks is most likely to help improve the cache hit rate.

[0031] If (at block 416) the track cache residency time of the processed track is within the minimum track cache residency time range, i.e., it has a shorter time in the cache 116 compared to tracks not in this range, then (at block 418) the re-MRU flag 310 is set for the accessed track in the cache control block 300 i to indicate re-MRU of the track, and the track is left at its current position in the cache list 200. However, because the last access timestamp 308 of the accessed track is updated, the track is now at the top of the upper part of the cache residency, i.e., the time period in the cache is the shortest among all tracks. If (at block 416) the track is not within the minimum track cache residency time range of the tracks in the cache list 200, the control proceeds to block 408 to remove the indication of the track from the cache list 200 for addition to the MRU array 126.

[0032] If (at block 402) the accessed track is not in the cache 116, then (at block 420) the track is staged from the volume 108 to the cache 116. (At block 422) the cache control block 300 for the track used for staging iIt is added to the cache control block directory 300, the last access timestamp 308 is set to the current timestamp, and the re-MRU flag 310 is set to indicate no re-MRU. Then, in the MRU array 126, the accessed track is indicated to be batch-added to the MRU end 202 together with the other tracks indicated in the MRU array 126.

[0033] In the embodiment Figure 4 adopted, the requested track having a track cache residency time within the lowest track cache residency time range of the tracks indicated in the cache list 200 (which means that it has been in the cache for less time than other tracks not in this range relative to its last access timestamp 308) remains in its current position in the cache list 200 without being added to the MRU array 126. This reduces cache access latency because the more recently accessed tracks with a lower track cache residency time due to their continuously updated access timestamps 308 do not continuously move to the MRU array 126 and are not batch-indicated at the MRU end 202, but instead remain in their current positions in the cache list 200, where their last access timestamps are updated 308. Only setting the re-MRU flag 310 at box 418 and not adding the track to the MRU array 126 avoids the latency required to add the track to the MRU array 126 and process the MRU array 126 to batch-add the track to the MRU end 202, because removing a track from the cache list 200 or adding it to the MRU end 202 requires locking. However, the accessed tracks having a longer track cache residency time (longer than the residency time within the lowest track cache residency time range of the tracks in the cache list 200) are removed from the cache list 200 and added to the MRU array 126 because they are less likely to be accessed again compared to the more recently accessed tracks in the upper range. By keeping more recently accessed tracks in the cache list 200 while moving the tracks that have been in the cache for a relatively longer time and are less likely to be accessed to the MRU array 126, the cache hit rate is further improved.

[0034] Figure 5An embodiment of the operations performed by the demotion scan task 130 is shown. The demotion scan task 130 is periodically invoked to process tracks starting from the LRU end 204 of the cache list 200 for demotion from the cache. When (at block 500) a track is being processed at the LRU end 204 for demotion, if (at block 502) the re-MRU flag 310 is not set, which indicates that the track has not been recently accessed since it was last added to the cache 116, then (at block 504) the track being processed is removed from the cache list 200 and demoted, for example, added to the demotion ready list 128, and tracks from this demotion ready list 128 are removed from the cache list. If (at block 502) the re-MRU flag 310 indicates re-MRU or moving the track towards the MRU end 202, then (at block 506) the minimum track cache residency time range of the tracks in the cache list 200 is determined, for example, a predetermined percentage of the cache residency time, where the predetermined percentage is greater than 50%. For example, this minimum track cache residency time range can include more than 50% of the cache residency, such as 75% of the tracks have been more recently accessed, that is, they have spent less time in the cache since the last access. In this way, for Figure 4 the determination at block 416, the minimum track cache residency time range of the tracks in the cache list 200 can be different. In Figure 4 it is less than 50% (e.g., 25%), and in Figure 5 at block 510, it is greater than 50% (e.g., 75%).

[0035] As described above, (at block 508) the track cache residency time is determined. If (at block 510) the track cache residency time is greater than the minimum track cache residency time range, then the track has spent more time in the cache 116 than the tracks in that range, and control proceeds to block 504 to remove the track being processed from the cache list 200 and demote it, for example, add it to the demotion ready list 128.

[0036] If (at block 510) the track residency time is less than the minimum track cache residency time range of the tracks in the cache list 200, then (at block 512) an indication to remove the track from the cache list 200 is given, and (at block 514) the track is indicated in the MRU array 126.

[0037] Adopt Figure 5In an embodiment, if the re-MRU flag is set to indicate that the track has been accessed while in the cache list 200 and if the track cache residency time indicates that it has been in cache 116 for a period of time within the minimum track cache residency time of tracks in the cache list 200, then the track is not demoted. In this case, the track is accessed while in the cache because it is identified as most recently more accessed, so it is added to the MRU array 126 for re-MRU. Re-MRUing the most recently more accessed tracks improves the cache hit rate.

[0038] Figure 6 An embodiment of the operation performed by the cache manager 120 and / or the demotion scan task 130 to process the MRU array 126 to add tracks to the MRU end 202 of the cache list 200 is shown. The MRU array 126 can be processed when the number of tracks equals a threshold or when the MRU array 126 is full. (At block 600) When starting the processing of the tracks in the MRU array 126, control continues to execute Figure 5 the operation until the demotion scan task 130 demotes an equal number of tracks as the number of tracks in the MRU array 126 that are to be added to the cache list 200. Then control continues to (at block 604) obtain a lock on the cache list 200 and add the tracks in the MRU array 126 to the MRU end 202 of the cache list 200.

[0039] employs Figure 6 In an embodiment, tracks added to cache 116 or determined to be re-MRU are not immediately indicated to the MRU end 202, which would cause a delay in obtaining a lock on the cache list 200 to be postponed. Instead, the tracks added to cache 116 are indicated in the MRU array 126 and batched to be moved to the MRU end 202, i.e., added to the MRU end 202 while holding a lock on the cache list 200, to avoid lock contention for indicating tracks at the MRU end 202.

[0040] The present invention can be a system, method, and / or computer program product. The computer program product can include a computer-readable storage medium having computer-readable program instructions thereon for causing a processor to implement various aspects of the present invention.

[0041] A computer-readable storage medium can be a tangible device that can hold and store instructions for use by an instruction execution device. A computer-readable storage medium may be, for example—but not limited to—an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disc (DVD), a memory stick, a floppy disk, a mechanically encoded device such as a punched card or raised structures in grooves having instructions stored thereon, and any suitable combination of the foregoing. The computer-readable storage medium as used herein is not construed as being a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., an optical pulse through an optical fiber cable), or an electrical signal transmitted through a wire.

[0042] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to various computing / processing devices, or can be downloaded to an external computer or external storage device through a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network may include a copper transmission cable, an optical fiber transmission, a wireless transmission, a router, a firewall, a switch, a gateway computer, and / or an edge server. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium in each computing / processing device.

[0043] The computer program instructions for carrying out the operations of the present invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine - related instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object - oriented programming languages such as Java, Smalltalk, C++, etc., and procedural programming languages such as the "C" language or similar programming languages. The computer - readable program instructions may be executed entirely on the user's computer, partially on the user's computer, executed as a stand - alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or, alternatively, may be connected to an external computer (e.g., through the Internet using an Internet service provider). In some embodiments, by using the state information of the computer - readable program instructions to customize an electronic circuit, such as a programmable logic circuit, a field - programmable gate array (FPGA), or a programmable logic array (PLA), the electronic circuit can execute the computer - readable program instructions to implement various aspects of the present invention.

[0044] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer - readable program instructions.

[0045] These computer - readable program instructions can be provided to a processor of a general - purpose computer, a special - purpose computer, or other programmable data - processing apparatus to produce a machine such that the instructions, when executed by the processor of the computer or other programmable data - processing apparatus, create a means for implementing the functions / acts specified in one or more blocks of the flowchart and / or block diagram. These computer - readable program instructions can also be stored in a computer - readable storage medium, which, when executed, causes a computer, a programmable data - processing apparatus, and / or other devices to function in a particular manner, such that the computer - readable medium storing the instructions comprises a manufacture, including instructions for implementing various aspects of the functions / acts specified in one or more blocks of the flowchart and / or block diagram.

[0046] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices, causing a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other devices to generate a computer-implemented process, such that the instructions executed on the computer, other programmable data processing apparatus, or other devices implement the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0047] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, a segment of a program, or a portion of an instruction, which contains one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two consecutive blocks may in fact be executed substantially in parallel, or they may sometimes be executed in the reverse order, depending on the functionality involved. It should also be noted that each block of the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented by special-purpose hardware-based systems that perform the specified functions or actions, or by combinations of special-purpose hardware and computer instructions.

[0048] Figure 1 The computing components (including hosts 1021, 1022... 102 n and storage controller 104) may be implemented in one or more computer systems, such as Figure 7 the computer system 702 shown. The computer system / server 702 may be described in the general context of computer system-executable instructions, such as program modules, executed by a computer system. Generally, program modules may include routines, programs, objects, components, logic, data structures, etc. that perform particular tasks or implement particular abstract data types. The computer system / server 702 may be practiced in a distributed cloud computing environment where tasks are performed by remote processing devices linked through a communications network. In a distributed cloud computing environment, program modules may be located in both local and remote computer system storage media including memory storage devices.

[0049] As Figure 7As shown, computer system / server 702 is shown in the form of a general-purpose computing device. The components of computer system / server 702 may include, but are not limited to: one or more processors or processing units 704, a system memory 706, and a bus 708 that couples various system components including the system memory 706 to the processor 704. The bus 708 represents any one or more of a variety of bus structures, including a memory bus or memory controller using any one of a variety of bus architectures, a peripheral bus, a graphics acceleration port, and a processor or local bus. By way of example and not limitation, such architectures include Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MCA) bus, Enhanced ISA (EISA) bus, Video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnect (PCI) bus.

[0050] Computer system / server 702 typically includes a variety of computer system readable media. Such media can be any available media accessible by computer system / server 702, and it includes both volatile and non-volatile media, removable and non-removable media.

[0051] System memory 706 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 710 and / or cache memory 712. Computer system / server 702 may further include other removable / non-removable volatile / non-volatile computer system storage media. By way of example only, a storage system 713 may be provided for reading from and writing to non-removable non-volatile magnetic media (not shown and typically referred to as a "hard disk drive"). Although not shown, a disk drive for reading from and writing to removable non-volatile disks (such as a "floppy disk"), and an optical disk drive for reading from or writing to removable non-volatile optical disks (CD-ROM, DVD-ROM or other optical media) may be provided. In such cases, each may be connected to the bus 708 via one or more data media interfaces. As will be further depicted and described below, memory 706 may include at least one program product having a set (e.g., at least one) of program modules configured to execute the functions of embodiments of the present invention.

[0052] A program / utilities 714 having a set (at least one) of program modules 716 may be stored in memory 706, by way of example and not limitation, along with an operating system, one or more application programs, other program modules, and program data. Each of the operating system, one or more application programs, other program modules, and program data, or some combination thereof, may include an implementation of a networking environment. The components of computer 702 may be implemented as program modules 716 that typically execute the functions and / or methods of embodiments of the present invention described herein.Figure 1 The system can be implemented in one or more computer systems 702, and if they are implemented in multiple computer systems 702, the computer systems can communicate via a network.

[0053] The computer system / server 702 can also communicate with one or more external devices 718, such as a keyboard, a pointing device, a display 720, etc.; communicate with one or more devices that enable users to interact with the computer system / server 702; and / or communicate with any device that enables the computer system / server 702 to communicate with one or more other computing devices (e.g., a network card, a modem, etc.). Such communication can occur via an input / output (I / O) interface 722. However, the computer system / server 702 can still communicate with one or more networks (such as a local area network (LAN), a general wide area network (WAN), and / or a public network (e.g., the Internet)) via a network adapter 724. As shown in the figure, the network adapter 724 communicates with other components of the computer system / server 702 via a bus 708. It should be understood that although not shown, other hardware and / or software components can be used in conjunction with the computer system / server 702. Examples include, but are not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, etc.

[0054] Unless otherwise explicitly stated, the terms "embodiment", "multiple embodiments", "the embodiment", "the multiple embodiments", "one or more embodiments", "some embodiments", and "an embodiment" mean "one or more (but not all) of the embodiments of the present invention".

[0055] Unless otherwise explicitly stated, the terms "comprise", "include", "have" and their variants mean "including but not limited to".

[0056] Unless otherwise explicitly stated, the list of items enumerated does not mean that any or all of the items are mutually exclusive.

[0057] Unless otherwise explicitly stated, the terms "a", "an", and "the" mean "one or more".

[0058] Unless otherwise explicitly stated, devices that communicate with each other do not need to communicate with each other continuously. Additionally, devices that communicate with each other can communicate directly or indirectly through one or more intermediate devices.

[0059] The description of an embodiment having multiple components that communicate with each other does not imply that all such components are required. Instead, various optional components are described to illustrate the wide range of various possible embodiments of the present invention.

[0060] When a single device or article is described herein, it will be apparent that more than one device / article (whether they cooperate or not) may be used instead of a single device / article. Similarly, where more than one device or article is described herein (whether they cooperate or not), it will be apparent that a single device / article may be used instead of the more than one device / article, or different quantities of devices / articles may be used in place of the shown quantities of devices or procedures. The functions and / or features of a device may alternatively be embodied by one or more other devices not explicitly described as having such functions / features. Accordingly, other embodiments of the present invention need not include the device itself.

[0061] For purposes of illustration and description, the foregoing description of various embodiments of the invention has been given. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teachings. The scope of the invention is not intended to be limited by this detailed description, but rather by the appended claims. The above description, examples and data provide a complete description of the manufacture and use of the composition of the invention. Since many embodiments of the invention can be made without departing from the spirit and scope of the invention, the invention is embodied in the appended claims.

Claims

1. A computer program product for managing tracks in a storage device in a cache, the computer program product including a computer-readable storage medium having embodied therein computer-readable program code, the computer-readable program code, when executed, performing operations, the operations including: Maintaining a cache list for the cache, the cache list having a least recently used (LRU) end and a most recently used (MRU) end, wherein tracks in the cache are indicated in the cache list; Accessing a track indicated in the cache list in the cache; Determining whether a track cache residency time since the accessed track was last accessed when it was in the cache list is within a minimum track cache residency time range; and In response to determining that the track cache residency time of the accessed track is within the minimum track cache residency time range, setting a flag for the accessed track to indicate that the track is at the MRU end, the flag ensuring that the accessed track is moved back to the MRU end when it reaches the LRU end of the cache list, wherein, after setting the flag, the accessed track remains at its current position in the cache list before being accessed.

2. The computer program product according to claim 1, wherein, The operations further include: In response to determining that the track cache residency time is not within the minimum track cache residency time range, removing an indication of the accessed track from the cache list and adding the indication of the accessed track to an MRU array, wherein tracks indicated in the MRU array are batch-added to the MRU end of the cache list.

3. The computer program product according to claim 1, wherein The operations further include: Processing a track at the LRU end of the cache list; Determining whether the flag for the processed track is set to indicate that the track is at the MRU end; In response to determining that the flag for the processed track is not set to indicate that the track is at the MRU end, demoting the processed track; In response to determining that the flag is set to indicate that the track is at the MRU end, determining whether the processed track is indicated at the MRU end of the cache list; In response to determining that the processed track is indicated at the MRU end of the cache list, indicating that the processed track is at the MRU end of the cache list; and In response to determining that the processed track is not indicated at the MRU end of the cache list, demoting the processed track.

4. The computer program product according to claim 1, wherein, The minimum track cache residency time range includes a first range, wherein the operations further include: Processing a track at the LRU end of the cache list; Determining whether the flag for the processed track is set to indicate that the track is at the MRU end; In response to determining that the flag is set to indicate that the track is at the MRU end of the cache list, determine whether the track cache residency time since the processed track was last accessed is within the second lowest track cache residency time range of the tracks in the cache list, wherein the first range is less than the second range in percentage of the entire cache residency time; In response to determining that the track cache residency time is within the second lowest track cache residency time range, initiate an indication of the processed track at the MRU end of the cache list; and Demote the processed track in response to determining one of the following: the flag is not set to indicate that the processed track is at the MRU end of the cache list, and the track cache residency time is not within the lowest track cache residency time range.

5. The computer program product according to claim 4, wherein, The first range includes less than fifty percent of the entire cache residency time, and the second range includes more than fifty percent of the entire cache residency time.

6. The computer program product according to claim 5, wherein, The track cache residency time includes the difference between the current timestamp and the last access timestamp, and the last access timestamp indicates the time when the processed track was last accessed in the cache, wherein the entire cache residency time includes the difference between the last access timestamp when the track at the MRU end was last accessed and the last access timestamp of the track at the LRU end.

7. The computer program product according to claim 1, wherein, The operations further include: Determine whether the cache size of the cache is less than a threshold cache size; and In response to determining that the cache size is less than the threshold cache size, remove the indication of the accessed track from the cache list to add to the MRU array, wherein the tracks indicated in the MRU array are batch added to the MRU end of the cache list, and wherein determining whether the accessed track is within the lowest track cache residency time range is performed in response to determining that the cache size is greater than the threshold cache size.

8. A system for managing tracks in a storage device, comprising: A processor; A cache in a memory device; A computer program product, which includes a computer-readable storage medium, and computer-readable program code is embodied in the computer-readable storage medium, and the computer-readable program code, when executed, performs operations, and the operations include: Maintain a cache list for the cache, the cache list having a least recently used (LRU) end and a most recently used (MRU) end, wherein the tracks in the cache are indicated in the cache list; Access the tracks indicated in the cache list in the cache; Determine whether the track cache residency time since the accessed track was last accessed when it was in the cache list is within the lowest track cache residency time range; and In response to determining that the track cache residency time of the accessed track is within the lowest track cache residency time range, set a flag for the accessed track indicating that the track is at the MRU end, the flag ensuring that the accessed track is moved back to the MRU end when it reaches the LRU end of the cache list, wherein after setting the flag, the accessed track remains at its current position in the cache list before being accessed.

9. The system according to claim 8, wherein The operation further includes: In response to determining that the track cache residency time is not within the lowest track cache residency time range, remove the indication of the accessed track from the cache list and add the indication of the accessed track to the MRU array, wherein the tracks indicated in the MRU array are batch-added to the MRU end of the cache list.

10. The system according to claim 8, wherein, The operation further includes: Process the track at the LRU end of the cache list; Determine whether the flag for the processed track is set to indicate that the track is at the MRU end; In response to determining that the flag for the processed track is not set to indicate that the track is at the MRU end, demote the processed track; In response to determining that the flag is set to indicate that the track is at the MRU end, determine whether the processed track is indicated to be at the MRU end of the cache list; In response to determining that the processed track is indicated to be at the MRU end of the cache list, indicate that the processed track is at the MRU end of the cache list; and In response to determining that the processed track is not indicated to be at the MRU end of the cache list, demote the processed track.

11. The system according to claim 8, wherein, The lowest track cache residency time range includes a first range, wherein the operation further includes: Process the track at the LRU end of the cache list; Determine whether the flag for the processed track is set to indicate that the track is at the MRU end; In response to determining that the flag is set to indicate that the track is at the MRU end of the cache list, determine whether the track cache residency time since the processed track was last accessed is within a second lowest track cache residency time range of the tracks in the cache list, wherein the first range is a smaller percentage of the overall cache residency time than the second range; In response to determining that the track cache residency time is within the second lowest track cache residency time range, initiate an indication that the processed track is at the MRU end of the cache list; and Demote the processed track in response to determining one of the following: the flag is not set to indicate that the processed track is at the MRU end of the cache list, and the track cache residency time is not within the lowest track cache residency time range.

12. The system according to claim 11, wherein, The first range includes less than fifty percent of the entire cache residency time, and the second range includes greater than fifty percent of the entire cache residency time.

13. The system according to claim 12, wherein The track cache residency time includes the difference between the current timestamp and the last access timestamp, where the last access timestamp indicates the time when the processed track was last accessed in the cache. Wherein, the entire cache residency time includes the difference between the last access timestamp when the track at the MRU end was last accessed and the last access timestamp of the track at the LRU end.

14. The system according to claim 8, wherein The operation further includes: Determining whether the cache size of the cache is less than a threshold cache size; and In response to determining that the cache size is less than the threshold cache size, removing the indication of the accessed track from the cache list for addition to the MRU array, where the tracks indicated in the MRU array are batch-added to the MRU end of the cache list, and determining whether the accessed track is within the lowest track cache residency time range is performed in response to determining that the cache size is greater than the threshold cache size.

15. A method for managing tracks in a storage device in a cache, comprising: Maintaining a cache list for the cache, the cache list having a least recently used (LRU) end and a most recently used (MRU) end, where the tracks in the cache are indicated in the cache list; Accessing a track indicated in the cache list in the cache; Determining whether the track cache residency time since the accessed track was last accessed while in the cache list is within a lowest track cache residency time range; and In response to determining that the track cache residency time of the accessed track is within the lowest track cache residency time range, setting a flag for the accessed track indicating that the track is at the MRU end, the flag ensuring that the accessed track is moved back to the MRU end when it reaches the LRU end of the cache list, where after setting the flag, the accessed track remains at its current position in the cache list before being accessed.

16. The method according to claim 15, further comprising: In response to determining that the track cache residency time is not within the lowest track cache residency time range, removing the indication of the accessed track from the cache list and adding the indication of the accessed track to the MRU array, where the tracks indicated in the MRU array are batch-added to the MRU end of the cache list.

17. The method according to claim 15, further comprising: Processing a track at the LRU end of the cache list; Determining whether the flag for the processed track is set to indicate that the track is at the MRU end; In response to determining that the flag for the processed track is not set to indicate that the track is at the MRU end, demote the processed track; In response to determining that the flag is set to indicate that the track is at the MRU end, determine whether it is indicated that the processed track is at the MRU end of the cache list; In response to determining that it is indicated that the processed track is at the MRU end of the cache list, indicate that the processed track is at the MRU end of the cache list; And In response to determining that it is not indicated that the processed track is at the MRU end of the cache list, demote the processed track.

18. The method according to claim 15, wherein, The lowest track cache residency time range includes a first range, wherein the operation further includes: Processing the track at the LRU end of the cache list; Determining whether the flag for the processed track is set to indicate that the track is at the MRU end; In response to determining that the flag is set to indicate that the track is at the MRU end of the cache list, determining whether the track cache residency time since the processed track was last accessed is within a second lowest track cache residency time range of the tracks in the cache list, wherein the percentage of the first range in the entire cache residency time is less than that of the second range; In response to determining that the track cache residency time is within the second lowest track cache residency time range, initiate an indication that the processed track is at the MRU end of the cache list; and Demote the processed track in response to determining one of the following: the flag is not set to indicate that the processed track is at the MRU end of the cache list, and the track cache residency time is not within the lowest track cache residency time range.

19. The method according to claim 18, wherein, The first range includes less than fifty percent of the entire cache residency time, and the second range includes more than fifty percent of the entire cache residency time.

20. The method according to claim 19, wherein the track cache residency time includes the difference between the current timestamp and the last access timestamp, and the last access timestamp indicates the time when the processed track was last accessed in the cache, Among them, The entire cache residency time includes the difference between the last access timestamp when the track at the MRU end was last accessed and the last access timestamp of the track at the LRU end.

21. The method according to claim 15, further comprising: Determining whether the cache size of the cache is less than a threshold cache size; And In response to determining that the cache size is less than the threshold cache size, an indication of the accessed track is removed from the cache list for addition to the MRU array, wherein the tracks indicated in the MRU array are added in a batch to the MRU end of the cache list, and wherein determining whether the accessed track is within the lowest track cache residency time range is performed in response to determining that the cache size is greater than the threshold cache size.

22. A computer system, the system including modules respectively for performing the steps of the method according to any one of claims 15 to 21.

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