High-throughput DRAM with distributed column access

Abstract

The present invention relates to a high throughput DRAM with distributed column access. A device has a memory die having a memory cell array divided into a plurality of data segments. A misalignment circuit selects a common command signal and sets a column access signal to select a data segment to be accessed based on the common command signal and / or an individual command signal to perform a memory operation corresponding to the selected common command signal on the selected data segment. A data bus connects the memory cell array to form data cells, wherein each data cell includes a data segment from each memory cell array and is configured so that the data segments are connected in parallel to the data bus and use the same line of the data bus. The misalignment circuit is configured so that the data segments identified for activation in the plurality of memory dies are not part of the same data cell.

Description

Technical Field

[0001] The present invention relates to systems for column access in dynamic random access memory, and more particularly to high throughput data transfer by distributing the column access selections over command signal cycles. Background Art

[0002] Devices classified as "Internet-of-things" (IoT) may include data collection devices such as, for example, temperature sensors, tracking sensors (e.g., for tracking pets, vehicles, etc. using, for example, GPS sensors), metering sensors (water, gas, etc.), environmental monitoring sensors (e.g., gas, fire, smoke, carbon monoxide, etc.), devices that monitor remote machines (vending machines, industrial equipment, etc.), proximity sensors, etc. One or more IoT sensors may be connected (e.g., wirelessly and / or wired) to one or more IoT nodes, which may be cloud or Internet connected. An IoT node may include a processor for writing received sensor data to a memory device and for reading stored sensor data from the memory device in order to transmit the data to the cloud or Internet.

[0003] In addition to being used in IoT devices, memory devices can also be used to store information in various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like. Memory devices are often provided as internal semiconductor integrated circuits and / or external removable devices in computers or other electronic devices. There are many different types of memory, including volatile and non-volatile memory. Volatile memory, including random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), as well as other memories, may require an external power source to maintain its data. In contrast, non-volatile memory can maintain its stored data even without external power supply. Non-volatile memory can be used in a variety of technologies, including flash memory (such as NAND and NOR), phase change memory (PCM), ferroelectric random access memory (FeRAM), resistive random access memory (RRAM), and magnetic random access memory (MRAM), as well as other memories.

[0004] The memory in the IoT device may be a DRAM with one or more memory dies. In some IoT devices that receive sensor data from one or more sensors, the sensor data corresponding to each sensor may be stored separately in the corresponding memory die. For example, the data from each memory sensor may be stored separately in a separate memory die ("single die configuration"). However, when the processor of the IoT device writes sensor data to such a single die configuration and / or reads sensor data from such a single die configuration, peak power consumption due to simultaneous switching of several bits during memory column access may become a problem. To accommodate the IR voltage drop in these single die configurations, the voltage level used for memory operation may be increased, which causes peak power consumption problems. To alleviate the peak power consumption problem, some IoT devices use a stacked memory die arrangement in which the sensor data from each memory sensor is divided into multiple data portions and each data portion is stored on a separate memory die. However, in order to access the appropriate memory location on the memory die, the through silicon via (TSV) connection in such a stacked memory DRAM is arranged so that there is a shift in the connection path between the memory dies. To create a shift in the TSV connection, a TSV mask change may be required during the manufacture of the DRAM. Mask changes may result in a more complex and / or more expensive manufacturing process. In addition, the layout and use of the write amplifier / driver and the read amplifier may cause noise on the power bus in a single die and conventional stacked memory configuration. Furthermore, in prior art DRAMs, the transfer of data to / from the memory cell is completed in a single step after the command signal is initiated, which may cause a limitation on the amount of data transferred during each clock cycle period. That is, only one column access selection operation is performed within each time period tCCD of the command signal (column access to column access delay), which limits the amount of data transferred during each tCCD clock cycle. Summary of the invention

[0005] In one aspect, the present invention provides an apparatus comprising: a plurality of memory dies, each memory die having at least one memory cell array divided into a plurality of data segments that can be selectively accessed, and a misalignment circuit configured to select a common command signal from a plurality of common command signals and configured to set at least one of a column access signal or an individual command signal, the column access signal selecting a data segment to be accessed based on the common command signal and the individual command signal to perform a memory operation corresponding to the selected common command signal on the selected data segment; a data bus connecting each of the at least one memory cell array to form a plurality of data cells, each data cell including data segments from each memory cell array, wherein the data segments in each data cell are connected to the data bus in parallel and use the same line of the data bus; and a command signal circuit connected to each misalignment circuit in the plurality of memory dies and configured to generate the plurality of common command signals, wherein the misalignment circuit is further configured so that the selected data segments are not part of the same data cell.

[0006] In another aspect, the present invention provides a device comprising: a first memory die comprising a first memory cell array at least partially divided into a first data segment and a second data segment; a second memory die stacked with the first memory die, the second memory die comprising a second memory cell array at least partially divided into a third data segment and a fourth data segment; a first data bus commonly coupled to the first data segment of the first memory die and the third data segment of the second memory die; and a second data bus commonly coupled to the second data segment of the first memory die and the fourth data segment of the second memory die; wherein the first memory die is configured to transfer memory data from the first data segment to the first data bus when the second memory die transfers memory data from the fourth data segment to the second data bus. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 A block diagram illustrating an Internet of Things system with a memory component in accordance with an embodiment of the present technology.

[0008] Figure 2 Instructions include the following: Figure 1 Block diagram of a system on a chip of memory components in a system.

[0009] Figure 3 Description Available for Figure 2 Block diagram of a memory die in a memory component of FIG.

[0010] Figure 4 illustrate Figure 3 Block diagram of a memory cell array in a memory die.

[0011] Figure 5 Description for Figure 2 00140] An exemplary timing diagram of phased command signals and distributed column access signals for a memory element of FIG.

[0012] Fig. 6A Description Used to generate Figure 5 A phase command signal circuit for a phase-controlled command signal.

[0013] Figure 6B Description Used to generate Figure 5 A distributed column access signal circuit for a distributed column access signal in the embodiment of the present invention.

[0014] Fig. 7A and 7B A common command signal circuit and a misalignment circuit for generating a phase command signal / column access signal according to an embodiment of the present technology are respectively described.

[0015] Fig. 8A A block diagram illustrating data storage devices in a memory component.

[0016] Figure 8B A block diagram illustrating data transfer from a memory component.

[0017] Fig.9A and 9B illustrate Figure 3 An exemplary block layout diagram of a memory cell array in a memory die of FIG.

[0018] Fig. 10A and 10B Block diagrams illustrating exemplary circuits for read and write operations, respectively.

[0019] Fig.11 Description Used to write data to Figure 2 Write timing diagram of the memory component. DETAILED DESCRIPTION

[0020] As discussed in more detail below, the techniques disclosed herein relate to data transfer in a memory component (such as, for example, a DRAM device) by distributing column access selections within clock cycles (periods) of command signals. However, it should be understood by those skilled in the art that the techniques may have additional embodiments and may not require the following reference to Figures 1 to 11The present invention relates to a method for implementing the present invention in accordance with some of the details of the embodiments described herein. In the embodiments described below, memory devices and systems are primarily described in the context of devices incorporating DRAM storage media. However, memory devices configured according to other embodiments of the present technology may include other types of memory devices and systems incorporating other types of storage media, including PCM, SRAM, FRAM, RRAM, MRAM, read-only memory (ROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEROM), ferroelectric, magnetoresistive, and other storage media, including non-volatile flash (e.g., NAND and / or NOR) storage media.

[0021] Figure 1 A system having a memory device according to an embodiment of the present invention is described. Figure 1 A block diagram of an IoT system 100 is shown that may include one or more IoT sensors, such as, for example, sensors 110a-f. IoT sensors 110a-f may be configured as a pet tracker, a smoke alarm, a water meter, a trash can monitor, a vending machine monitor, and a gas monitor, respectively. Of course, other types of sensors may be used in the IoT system 100, and one or more of the illustrated sensors need not be included in the IoT system 100. The IoT system 100 may include one or more IoT nodes, such as, for example, IoT nodes 120a-c. Each of the sensors 110a-f may be configured to transmit monitored data to one or more of the IoT nodes 120a-c wirelessly and / or through a wired connection. The IoT nodes 120a-c may be connected to a network, such as, for example, a cloud 130 and / or the Internet and / or another type of network, so that remote devices and / or users receive the monitored data. In some embodiments, the IoT nodes 120a to c may include controllers 122a to c, respectively, to handle the reception and transmission of monitored data. The controllers 122a to c may include processors 124a to c, respectively, connected to memory components 126a to c. The memory components 126a to c may include, for example, one or more DRAM devices. Of course, in some embodiments, the IoT nodes 120a to c also include non-volatile memory, such as, for example, flash memory, etc. As part of the monitoring operation and / or based on an external request, the data monitored from one or more sensors 110A to f is written to and / or read from the DRAM devices of the IoT nodes 120a to c.

[0022] Figure 22 is a simplified block diagram of a system on chip (SoC) system 200 configured using stacked memory dies. The SoC system 200 may be, for example, a controller 122a to c for the IoT node 120a to c discussed above. The SoC system 200 may include a memory component 202 and a processor component 204. The memory component 202 may be a high bandwidth memory (HBM) or wide I / O memory having a stacked arrangement of one or more memory dies. For example, the memory component 202 may include four memory dies 210a to d stacked on top of each other. Of course, the memory component 202 may have more than four memory dies or less than four memory dies. In some embodiments, the memory die 210 may be a DRAM chip. The memory dies 210a to d may be electrically connected to each other using through silicon vias (TSVs) 220. Of course, for the sake of clarity and brevity, only a few of the TSVs are described. The TSVs 220 between the memory dies 210a to d may be connected to each other using microbumps 222. Memory component 202 may also include a logic die 230 that includes common circuitry for controlling memory operations in memory component 202 and may include an interposer 235 that connects logic die 230 to package substrate 240. Additionally, processor component 204 may include a SoC die 250 that is connected to logic die 230 via interposer 235 using logic die 230 and a corresponding PHY connection on SoC die 250. In some embodiments, die 250 may be a graphics processor unit (GPU), a computer processing unit (CPU), or some other type of processor.

[0023] In HBM and wide I / O memory, one or more memory arrays in each of the memory dies can be configured to simultaneously activate column select lines to transfer data from the memory array and / or transfer data to the memory array without conflict on the data bus. That is, data transferred from different memory dies and / or transferred to different memory dies should not use the same main I / O bus. In related art systems, to prevent data conflicts, memory cells can be accessed one die at a time (single die configuration), which can lead to peak power problems on the power bus. In other related art systems, data can be transferred from different memory dies and / or transferred to different memory dies at the same time to reduce the peak power requirements for the power bus. However, the TSV connection between the memory dies in such memory components is shifted so that the simultaneous read / write operation in the memory dies will result in the use of different parts of the data bus to transfer data from different dies and / or transfer data to different dies. For example, the TSV in the first column of the memory die can be connected to the TSV in different columns in the adjacent memory die. Therefore, the shift of the TSV sequence can avoid data conflicts. However, in order to shift the TSV sequence, different TSV masks are used in the fabrication of the memory component 202 between the memory die layers. Using different masks can increase the complexity and expense of the memory component fabrication process. In addition to the above problems, prior art systems have peak power and / or noise issues with read amplifiers and / or write drivers when adjacent amplifiers / drivers are used in succession.

[0024] In an exemplary embodiment of the present technology, simultaneous transmission of data is achievable without shifting the TSV sequence. Figure 2 As can be seen in FIG. 1 , the connection order of the TSVs 220 between the memory dies 210 a to d is the same as in the related art system. That is, the first column of TSVs 220 of the memory dies 210 a to d are connected to each other. Similarly, the second, third, and fourth columns of TSVs 220 of the memory dies 210 a to d are connected to each other, respectively. For clarity, in FIG. Figure 2 Only four data TSVs are depicted in FIG. However, it should be understood by those skilled in the art that a data bus may have any number of TSV connections. As discussed further below, in order to avoid data conflicts on the data bus without having to shift the TSV connections, an exemplary embodiment of the present technology divides the memory cell array of the memory die into multiple data segments. The number of data segments depends on the structure of the memory die and is not limiting. In some embodiments, the number of data segments may be in the range of 2 to 8, and in some embodiments, the number of data segments may be 4. Each data segment may be selectively accessed by activating the corresponding column select line ("CSL") and staggering the activation of the CSL between the memory dies.

[0025] Figure 3 2 is a block diagram schematically illustrating an exemplary embodiment of a memory die (which may be, for example, a memory die 210a, 210b, 210c, or 210d connected to a common logic die 230) according to an embodiment of the present technology. The memory die 210 may include one or more banks MB (e.g., Figure 3 , and each bank may include one or more memory cell arrays, such as memory cell array 350 (also referred to herein as a "memory array"). For purposes of clarity and brevity, the exemplary embodiments of the present specification will be described in conjunction with bank MB0 having one memory array. However, those skilled in the art should recognize that each of banks MB0 to MB7 may have more than one memory array. Memory array 350 may include a plurality of word lines (WL), one or more bit lines (BL), and one or more memory cells arranged at the intersection of the word lines and the bit lines. The selection of word lines WL and the introduction of signal voltages on word lines WL may be performed by row decoder 340 in conjunction with word line drivers (not shown). The selection of bit lines BL may be performed by column decoder 345, which may use global column select lines and / or local column select lines ( Figure 3 Sense amplifiers (SA) may be provided for respective bit lines BL, and each SA may be connected to a local I / O bus pair (LIO(T / B)), which in turn may be coupled to a main I / O bus pair (MIO(T / B)) via a transmission gate (TG) (which may be used as a switch).

[0026] The logic die 230 may employ a plurality of external terminals to communicate with a memory controller and / or a host processor such as, for example, the processor component 204. The external terminals may include a command terminal and an address terminal coupled to a command bus and an address bus. The command bus and the address bus may receive a command signal ("CMD signal") and an address signal ADDR, respectively. The logic die 230 may further include a chip select terminal receiving a chip select signal CS, a clock terminal receiving clock signals CK and CKF, a data clock terminal receiving data clock signals WCK and WCKF, data terminals DQ, RDQS, DBI, and DMI, power supply terminals VDD, VSS, VDDQ, and VSSQ.

[0027] The command terminals and address terminals may be supplied with address signals and bank address signals from a memory controller and / or a host processor, such as, for example, the processor component 204. The address signals and bank address signals supplied to the address terminals may be transmitted to, for example, the memory dies 210a-d via the command / address input circuit 305. For example, the address signals and bank address signals may be supplied to an address decoder 310 in the appropriate memory die 210a, b, c, d. The address decoder 310 may receive the address signals and supply a decoded row address signal (XADD) to a row decoder 340, and a decoded column address signal (YADD) to a column decoder 345. The address decoder 310 may also receive a bank address signal (BADD) and supply the bank address signal to both the row decoder 340 and the column decoder 345.

[0028] The command and address terminals of the logic die 230 may be supplied with a CMD signal, an address signal ADDR, and a chip select signal CS from a memory controller and / or a host processor (e.g., processor component 204). The CMD signal may represent various memory commands from the memory controller, including, for example, access commands, which may include read commands and write commands. The selection signal CS may be used to select the memory component 202 in response to the command and address provided to the command and address terminals. When a valid CS signal is provided to the memory component 202, the command and address may be decoded, and a memory operation may be performed. The CMD signal may be provided to a command decoder 315 via the command / address input circuit 305 of the logic die 230. The command decoder 315 may include a processor 316 (and / or other circuits) that decodes the CMD signal to generate various internal signals and commands for performing memory operations. In some embodiments, the CMD signal may be provided as an internal command signal ICMD to various circuits in the memory die 210a, b, c, d. Processor 316 may execute instructions to (and / or other circuits may be configured to) generate row and column command signals and / or associated timing signals (e.g., in conjunction with timing generator 335) to select word lines and / or bit lines to perform a desired memory operation (e.g., read, write). Of course, the processor / circuitry that generates the command and / or timing signals may be located in another component of memory component 202, such as, for example, address command input circuit 305 and / or an external controller / processor.

[0029] When a read command is issued and the row address and the column address are supplied in time, data may be read from the appropriate memory cells in the memory array 350 based on the row address and the column address. The read command may be received by a command decoder 315, which may provide an internal command to an input / output (I / O) circuit 360 so that the read data may be output from the data terminals DQ, RDQS, DBI, and DMI via a read / write amplifier module (WA / DA) 355, the I / O circuit 360, and a read / write circuit 380 (discussed below).

[0030] When a write command is issued and the write command is supplied in time to the row address and the column address, data may be supplied to the data terminals DQ, DBI, and DMI according to the WCK and WCKF clock signals. The write command may be received by the command decoder 315, which may provide an internal command to the I / O circuit 360 so that the write data may be received by a data receiver in the I / O circuit 360 via a read / write circuit 380 (discussed below) and supplied to the memory array 350 via an amplifier module 355. The write data may be written to the appropriate memory cells in the memory array 350 based on the row address and the column address. The write data may be provided to the data terminals at a time defined by the write delay WL information. The operation of the I / O circuit 360 is known to those skilled in the art, and therefore, for the sake of brevity, will not be discussed again.

[0031] The power supply terminals may be supplied with power supply potentials VDD and VSS. These power supply potentials VDD and VSS may be supplied to the internal voltage generator circuit 370. The internal voltage generator circuit 370 may generate various internal potentials VPP, VOD, VARY, VPERI, VCC, VCCP, VCCP2, and the like based on the power supply potentials VDD, VNWL, and VSS. The internal potential VPP may be used in the row decoder 340, the internal potentials VOD and VARY may be used in the sense amplifiers included in the memory array 350, and the internal potential VPERI may be used in many other circuit blocks.

[0032] The clock input circuit 320 of the logic die 230 can receive an external clock signal and generate various internal clock signals for use in the memory component 202. For example, the clock input circuit 320 can receive an external clock signal to generate an internal clock signal pair ICLK_T and ICLK_B. The internal clock signal ICLK(T / B) can be supplied to the internal clock circuit 330. The internal clock circuit 330 can provide various phase and frequency controllable internal clock signals based on the internal clock signal ICLK and the clock enable signal CKE received from the command / address input circuit 305. For example, the internal clock circuit 330 can include: a clock path ( Figure 32 (not shown), which receives the internal clock signal ICLK(T / B) and provides various clock signals to various circuits, such as (for example) providing the complementary even phase clock signal PCLKE and the odd phase clock signal PCLKO (collectively referred to as "phase clock signal PCLK(E / O)" or "PCLK(E / O) signal") to the command decoder 315, the timing generator 335 and / or the column decoder 345. The internal clock circuit 330 may further provide an input / output (IO) clock signal. The IO clock signal may be supplied to the input / output circuit 360 and may be used as a timing signal for determining the output timing of read data and the input timing of write data. The IO clock signal may be provided at multiple clock frequencies so that data can be output from and input to the memory component 202 at different data rates. When high memory speed is desired, a higher clock frequency may be desirable. When low power consumption is desired, a lower clock frequency may be desirable. In some embodiments, the internal clock signal ICLK(T / B) may be supplied to the timing generator 335 to generate a PCLK(E / O) signal and / or other various internal clock signals.

[0033] Typically, a memory array (e.g., memory array 350) may have multiple column select lines, and the number of column select lines may be based on the bandwidth of a data bus (e.g., an MIO bus) and the number of bits in a word line WL. For example, a 128-bit data bus connected to a memory array with 1024-bit word lines may have 8 CSLs, which are selectively activated by column access signals to allow access to memory cells for transferring data between the memory cells and the data bus. The corresponding memory arrays on other dies will have similar CSL configurations. As discussed above, in related art systems, one way to avoid data conflicts on a data bus is to shift TSV connection paths or use a single die configuration. However, in an exemplary embodiment of the present technology, each of the memory arrays 350 in the memory dies 210a to d may be divided into multiple data fragments, and access to each of the multiple data fragments may be selectively controlled by activating a corresponding column select line so as not to generate data conflicts on the MIO (T / B) bus. Therefore, while the CSLs of the related art system activate the entire memory array, the CSLs of the present technology activate data fragments in the memory array.

[0034] For example, in some embodiments, each memory array 350 may include multiple CSLs that control access to appropriate data segments of multiple data segments of the memory array 350 based on column access signals. In an exemplary embodiment, activation of CSLs within a memory die and between memory dies may be controlled so that two data segments of a data unit cannot be accessed simultaneously. As used herein, "data unit" refers to data segments of different memory dies whose memory cells are connected to the same data line of a data bus (e.g., a LIO (T / B) bus and / or a MIO (T / B) bus). Figure 4 , the memory array 150 in each of the memory dies 210a-d can be divided into four data segments A-D. For example, data from the sensor 110a can be divided and stored in the data segments in one or more memory dies 210a-d. As discussed below, data to be transferred during a specified memory operation can be stored using a pattern that does not include data segments that are part of the same data unit.

[0035] In some embodiments, each data segment A to D may be accessed based on activation of a column select line corresponding to the data segment. Figure 4 In an exemplary embodiment of , CSLs may be used to access corresponding data segments A to D. For example, one or more memory arrays may be divided into data segments A to D, and each data segment A to D may be accessed by activating CSL 410a, 410b, 410c, or 410d, respectively. For clarity, only one memory array in one memory die is shown. Each CSL 410a to d represents 8 Sub-CSLs (e.g., SCSL0 to 7). Appropriate SCSL0 to 7 of CSL 410a to d may be individually activated based on the desired memory cells to be accessed. For clarity and brevity, the present invention will refer to the activation of CSL 410a to d, but those skilled in the art will recognize that the activation of CSL 410a to d means that the appropriate individual SCSL0 to 7 is activated for the corresponding CSL 410a to d depending on the memory cells to be accessed. Depending on the structure of the memory component 202, CSL 410a to d may be a global column select line or a local column select line or a combination of both.

[0036] like Figure 4As seen in FIG. 4 , CSL 410a to d are connected to sense amplifiers and, when activated, turn on the corresponding SA of the bit line BL of the memory cell to be accessed. If the memory operation is a write operation, the value of the LIO (T / B) line corresponding to the activated CSL and the activated WL is written to the desired memory cell. If the memory operation is a read operation, the value of the memory cell corresponding to the memory cell activated by the CSL and the activated word line WL is transferred to LIO (T / B) and then to MIO (T / B) via switch TG. Figure 4 As seen in FIG. 4 , bus pairs MIO(T / B)-A, MIO(T / B)-B, MIO(T / B)-C, and MIO(T / B)-D are connected to CSLs 410a to d, respectively.

[0037] In some embodiments, the configuration of the memory component 202 is such that the MIO (T / B) buses of the memory dies 210a to d are connected to each other. For example, the memory cells corresponding to the CSL 410a in each memory die 210a to d can be connected in parallel to the MIO (T / B)-A data bus. That is, the data segments A of the memory dies 210a to d belong to a data unit and share the same portion of the data bus, which in this case is the MIO (T / B)-A bus. Similarly, the data segments B to D of the memory dies 210a to d are respectively connected to each other (e.g., connected in parallel to the corresponding MIO (T / B)-B to D buses) to form a data unit. For clarity, Figure 4 The exemplary illustration in shows only two MIO (T / B) pairs for each data segment A to D. However, each data segment A to D may have 32 MIO (T / B) pairs.

[0038] In an exemplary embodiment, CSLs from different memory dies may be activated simultaneously to access memory cells of data segments in different memory dies that are not part of the same data unit. The CSLs are activated simultaneously using an activation pattern that ensures that data from a given data segment is transferred to / through a portion of the MIO bus (and / or LIO bus) that is different from the portion used by other data segments. For example, the activation pattern of the CSLs may include selection of at least one CSL 410a-d in each memory die 210a-d to allow data to be transferred to / from different memory dies 210a-d simultaneously, and the activation pattern also ensures that data is not transferred to / from data segments that are part of the same data unit. That is, the activation pattern of the CSLs ensures that two data segments A, two data segments B, two data segments C, and two data segments D of the memory die 210a-d are not accessed simultaneously for data transfer. In some embodiments, to transfer all data to / from data segments A to D, multiple activation modes may be used to activate the CSL while ensuring that data is not transferred from data segments that are part of the same data unit. The multiple activation modes may be implemented in multiple phases distributed (interspersed) within at least a portion of a CMD signal cycle. For example, one of the multiple activation modes may be implemented at a time (e.g., one activation mode per phase) to transfer all data to / from the corresponding memory arrays 350 of the memory dies 210a to d during a single cycle of the CMD signal, for example. The number of activation modes may correspond to the number of data segments into which the memory array 350 is divided. In some embodiments, one or more of the multiple activation modes may be predetermined and may be programmed into the memory component 202. The multiple activation modes may also be collectively referred to herein as "mis-tuned activation modes". The mis-tuned activation modes may be implemented during a single CMD signal phase. Exemplary mis-tuned activation modes are provided in Table 1.

[0039] Table 1

[0040]

[0041] As seen in Table 1, the first column lists the memory die, and columns 2-5 list the data segments (e.g., A, B, C, or D) to which the data set (e.g., Data 1-4) is transferred from / to. Columns 2-5 also list the column select lines (CSLs 410a-d) activated in the appropriate memory die 210a-d when the transfer is performed. Each column 2-5 represents an activation pattern for activating the CSL used during a corresponding phase (e.g., Phases 1-4) of a CMD signal cycle, and the activation patterns collectively represent staggered activation patterns implemented during a single CMD signal cycle. The activation pattern used when activating the CSL can be changed in order to access data in different memory dies simultaneously without causing data conflicts on the data bus (e.g., LIO (T / B) and / or MIO (T / B)). That is, the activation pattern of each stage (e.g., stages 1 to 4) is such that data segments that are part of the same data unit are not selected, and then the activation pattern of the next stage is shifted or misaligned to ensure that all data sets (e.g., Data1 to 4) are transmitted without conflict on the data bus. As discussed above, Data1, Data2, Data3, and Data4 may represent four data sets to be transmitted during a single CMD signal clock cycle period. Each data set Data1 to 4 may represent data from a separate sensor, or the four data sets Data1 to 4 may represent data from a single sensor (or some combination thereof).

[0042] To transfer a data set (e.g., Data1 to 4), the column access signal for activating the CSL is distributed within the CMD signal cycle (also referred to herein as a "distributed column access signal"). For example, in some embodiments, the distributed column access signal may be set (e.g., set to a high state) during a specific phase (e.g., phases 1 to 4) of the CMD signal cycle. In addition, a separate command signal based on the CMD signal (referred to herein as a "phase command signal") may be set at each phase (e.g., phases 1 to 4) to initiate a memory operation (e.g., read or write). In some embodiments, the phase command signal may correspond to the distributed column access signal. As seen in Table 1, the data set Data1 may be transferred to / from the appropriate data segment of the memory die 210a during the first transfer phase of the CMD signal cycle. In the first transfer phase, appropriate distributed column access signals are set to activate the CSLs 410a, d, b, c of the memory dies 210a-d, and appropriate phase command signals are set (e.g., set to a high state) in each memory die 210a-d to transfer the data set Data1 stored in the data segments A, D, B, C of the memory dies 210a-d, respectively. During phases 2-4, data sets Data2-4 are similarly transferred by initiating appropriate distributed column access signals, appropriate phase command signals as shown in Table 1. The timing and generation of phase command signals and distributed column access signals are discussed in more detail below.

[0043] Figure 5 5 is an exemplary timing diagram 500 showing a phase command signal sequence and a distributed column access signal sequence according to the present technology. Figure 5 As seen in FIG. 5 , CMD signal 510 (also referred to herein as “CMD signal 510”) corresponds to a memory operation (e.g., write or read) and has a period tCCD. CMD signal 510 may be a master command signal for a read / write memory operation, which is generated, for example, by processor component 204 (or an external host processor). CMD signal 510 may be an external command signal received by memory component 202. In some embodiments, address command input circuit 305 may generate an internal ICMD signal based on CMD signal 510, and the ICMD signal may be used to generate a phase command signal and a distributed column access signal discussed below. For example, after the ICMD signal is generated, then, address command input circuit 305 may transmit the ICMD signal to each of memory dies 210a-d for generating a phase command signal and a distributed column access signal in each memory die 210a-d. However, for clarity, the generation of the phase command signal and the distributed column access signal will be described below with reference to CMD signal 510.

[0044] As discussed further below, in some embodiments, memory operations on the memory array 350 may be distributed (interspersed) within the CMD signal period by using multiple phase command signals to perform memory operations at different times within the period tCCD. For example, the phase command signals CMDa to d may be based on the CMD signal 510, and the phase command signals CMDa to d may be used for memory operations in corresponding data segments A to D. The phase command signal sequence (e.g., the order of phase command signals CMDa, CMDb, CMDc, CMDd) may be based on the memory dies 210a to d, and / or may be different for each memory die 210a to d. In some embodiments, the phase command signal sequence is based on an activation pattern, such as (for example) the activation pattern in each column of Table 1. For example, Figure 5 The phase command signal sequence of Table 1 is shown for memory die 210a: CMDa signal for phase 1, CMDc signal for phase 2, CMDb signal for phase 3, and CMDd signal for phase 4. For clarity, Figure 5 Only the sequence of memory die 210a is shown. However, the sequence of other memory die 210b-d may similarly follow the activation pattern shown in Table 1. For each memory die 210a-d, the phase command signal CMDa-d may be generated during the period tCCD of the CMD signal 510 based on the rising and / or falling edges of the phase clock signal PCLK(E / O). The phase clock signal PCLK(E / O) may be generated based on the internal clock signal ICLK(T / B). The internal clock signal ICLK(T / B) may be based on an external clock signal received by the memory component 202.

[0045] Distributed column access signals CASa, CASb, CASc, CASd for activating CSLs 410a-d, respectively, may be generated based on CMD signal 510. In some embodiments, the distributed column access signal sequence is based on an activation pattern, such as, for example, the activation pattern in each column of Table 1. For example, Figure 5 The distributed column access signal activation sequence of Table 1 for memory die 210a is shown: CASa signal is used to activate CSL 410a in phase 1, CMDc signal is used to activate CSL 410c in phase 2, CMDb signal is used to activate CSL 410b in phase 3, and CMDd signal is used to activate CSL 410d in phase 4. For clarity, Figure 5Only the sequence of memory die 210a is shown. However, the sequences of other memory die 210b to d may similarly follow the activation pattern shown in Table 1. Similar to the phase command signals CMDa to d, the distributed column access signals CASa to d may be generated at different times during the period tCCD of the CMD signal 510 based on the rising and / or falling edges of the phase clock signal PCLK(E / O). In some embodiments, the generation of the column access signals CASa to d may correspond to the generation of the phase command signals CMDa to d. In some embodiments, for example, Figure 5 , each distributed column access signal CASa-d may be in phase with a corresponding phase command signal CMDa-d. In some embodiments, each distributed column access signal CASa-d and the corresponding phase command signal CMDa-d may be the same signal.

[0046] As discussed above, the phase clock signal PCLK(E / O) may be generated in each of the memory dies 210a-d based on the internal clock signal ICLK(T / B). For example, the phase clock signal PCLK(E / O) may be generated in the internal clock circuit 330, the timing generator 335, and / or another circuit. In other embodiments, the phase clock signal PCLK(E / O) may be generated in the logic die 230 (and / or in some other external device) and may be transmitted to each of the memory dies 210a-d. For example, the phase clock signal PCLK(E / O) may be generated in the CLK input circuit 320 based on the external clock signals CK and CKF. Figure 5 As seen in FIG. 1 , two cycles of the clock signal ICLK(T / B) may represent one cycle of the phase clock signal PCLK(E / O). However, in other embodiments, the ratio of the clock signal ICLK(T / B) to the phase clock signal PCLK(E / O) may be greater than 2 or less than 2. In some embodiments, external clock signals CK and CKF may be used to generate the PCLK(E / O) signal.

[0047] like Figure 5As seen in , the frequency of the PCLK(E / O) signal may be greater than the frequency of the CMD signal 510. Based on the CMD signal 510 and the PCLK(E / O) signal, multiple phase command signals may be generated within a period tCCD. For example, the generation of the phase command signal CMDa to d (also referred to herein as the "CMDa to d signal") and the distributed column access signal CASa to d (also referred to herein as the "CASa to d signal") may be based on the rising and / or falling edges of the PCLK(E / O) signal. In some embodiments, the frequency of the PCLK(E / O) signal may depend on the number of memory dies in the memory component 202. In some embodiments, the setting of the CMDa to d signal and / or the CASa to d signal (e.g., a change to a high state) may be triggered from the PCLK(E / O) signal. For example, the setting of the CMDa to d signal and / or the CASa to d signal may be triggered from the rising edge and / or the falling edge of the PCLK(E / O) signal. Figure 5 In an exemplary embodiment of the present invention, the setting of the CMDa to d signals and the CASa to d signals is triggered by the rising edge of the PCLKE signal or the rising edge of the PCLKO signal. By using the PCLK(E / O) signal to trigger the setting (e.g., becoming a high state) of the CASa to d signals and the CMDa to b signals at different times during the period tCCD of the CMD signal 510, access and memory operations to the data segments A to D can be distributed throughout the period tCCD rather than data set transfers occurring simultaneously.

[0048] The PCLK(E / O) signal may be synchronized to the CMD signal 510 such that when the CMD signal 510 is set (e.g., rises to a high state), the rising edge of the CMD signal 510 triggers the even phase clock signal PCLKE to also rise to a high state and the complementary odd phase clock signal PCLKO to fall to a low value. The PCLK(E / O) signal may be used to trigger each phase (e.g., phases 1 to 4 in Table 1) during a period tCCD of the CMD signal 510. For example, the generation of the first phase command signal and the first distributed column access signal may correspond to an initial rise of the PCLKE signal in synchronization with or after a rise of the CMD signal 510. Referring to Table 1, the first phase command signal may involve transferring data (e.g., data set Data1, for example) to / from appropriate data segments A to D of the memory dies 210a to d, as shown in the Phase 1 column. Similarly, the first distributed column access signals of the memory dies 210a-d may involve selecting the column access lines corresponding to the appropriate data segments A-D in phase 1. With the appropriate CMD and CAS signals for phase 1 set, the data set Data1 may be simultaneously transferred to / from the data segments A, D, B, C in the respective memory dies 210a-d. The phase command signals and distributed column access signals corresponding to the second, third, and fourth phases (e.g., phases 2-4 in Table 1) may be generated in a similar manner, but the generation of these signals is distributed within the period tCCD. The phase command signals and distributed column access signals of phases 2-4 may involve transferring, for example, Data2, Data3, and Data4, respectively, to / from the appropriate data segments A-D (e.g., the data segments identified in Table 1) in each of the memory dies 210a-d.

[0049] In some embodiments, the data set to be transmitted may be segmented into data portions, and each data portion may be stored in a different memory die. For example, the data set Data1 may be segmented into portions stored in data segments A, D, B, C in the respective memory dies 210a to d. The activation pattern of phase 1 ensures that the Data1 portion is transmitted without conflict on the data bus because the data segments A, D, B, C in the respective memory dies 210a to d are not portions of the same data unit. Similarly, the data sets Data2 to 4 may be segmented into portions and stored in data segments in different memory dies in a manner consistent with the activation pattern shown in Table 1. As Figure 5As seen in FIG. 1 , the phase command signal and the distributed column access signal may be set (e.g., set to a high state) within two system clock cycles to ensure data transfer. However, the number of system clock cycles in which the phase command signal and the distributed column access signal are set high may be less than two cycles or greater than two cycles as desired.

[0050] In some embodiments, the command decoder 315 in each memory die 210a-d can be configured to generate phase command signals and distributed column access signals. The command decoder 315 can receive the PCLK(E / O) signal and generate each of the phase command signals and distributed column access signals for the memory die 210a-d in the appropriate sequence. Figure 5 ), the phase command signal and the distributed column access signal sequence may correspond to, for example, CMDa / CSAa→CMDc / CASc→CMDb / CASb→CMDd / CASd. Memory die 210b to d ( Figure 5 The generation of the phase command signals and distributed column access signal sequences in FIG. 2 (not shown) may correspond to, for example: for memory die 210 b, CMDd / CASd→CMDa / CASa→CMDc / CASc→CMDb / CASb; for memory die 210 c, CMDb / CASb→CMDd / CASd→CMDa / CASa→CMDc / CASc; and for memory die 210 d, CMDc / CASc→CMDb / CASb→CMDd / CASd→CMDa / CASa.

[0051] The generation of the phase command signal and the distributed column access signal sequence will be presented with respect to the memory die 210a. Figure 5 As seen in FIG. 1 , at time t0 (e.g., phase 1), the rise of the PCLKE signal may set (e.g., in a high state) the CMDa and CASa signals. When the CMDa and CASa signals are set, data may be transferred to / from data segment A. For example, a portion of the data set Data1 may be transferred to / from data segment A of the memory die 210a. Of course, along with the data being transferred to / from data segment A of the memory die 210a, other portions of the data set Data1 (and / or some other data) may be simultaneously transferred to / from appropriate data segments B, C, D of other memory dies 210b to d (e.g., see Table 1).

[0052] At time t1 (e.g., phase 2), the CMDc and CASc signals may be set (e.g., set to a high state) on the next rising edge of the PCLKO signal after the CMDa and CASa signals are set. When the CMDc and CASc signals are set, data may be transferred to / from data segment C. For example, a portion of the data set Data2 may be transferred to / from data segment C of the memory die 210a. Of course, along with the data being transferred to / from data segment C of the memory die 210a, other portions of the data set Data2 (and / or some other data) may be simultaneously transferred to / from appropriate data segments A, B, D of other memory dies 210b to d (e.g., see Table 1).

[0053] At time t2 (e.g., stage 3), the CMDb and CASb signals may be set (e.g., set to a high state) on the next rising edge of the PCLKE signal after the CMDc and CASc signals are set. When the CMDb and CASc signals are set, data may be transferred to / from data segment B. For example, a portion of the data set Data3 may be transferred to / from data segment B of the memory die 210a. Of course, along with the data being transferred to / from data segment B of the memory die 210a, other portions of the data set Data3 (and / or some other data) may be simultaneously transferred to / from appropriate data segments A, C, D in other memory dies 210b to d (e.g., see Table 1).

[0054] At time t3 (e.g., stage 4), the CMDd and CASd signals may be set (e.g., set to a high state) on the next rising edge of the PCLKO signal after the CMDb and CASb signals are set. When the CMDd and CASd signals are set, data may be transferred to / from data segment D. For example, a portion of data set Data4 may be transferred to / from data segment D of memory die 210a. Of course, along with data being transferred to / from data segment D of memory die 210a, other portions of data set Data4 (and / or some other data) may be simultaneously transferred to / from appropriate data segments A, B, C of other memory dies 210b to d (e.g., see Table 1). In timing diagram 500, the phase shift between each of the phase command signals and between each of the distributed column access signals is 12.5% ​​of tCCD. However, in other embodiments, the phase shift between each of the phase command signal and / or column access signal may be different. For example, the phase command signal and / or column access signal may be set so that phases 1 to 4 correspond to 0%, 25%, 50%, and 75% of tCCD.

[0055] Fig. 6A Description Used to generate Figure 5 210a-d. In some embodiments, the phase command signal circuit 600 may be disposed in each of the memory dies 210a-d. For example, the phase command signal circuit 600 may be disposed in the command decoder 315 and / or another circuit in each of the memory dies 210a-d. For clarity, the phase command signal circuit 600 is described with respect to the memory die 210a. However, it should be understood by those skilled in the art that the phase command signal circuits in the memory dies 210b-d will be similar.

[0056] Fig. 6A A phase command signal circuit 600 is illustrated that can generate a phase command signal, such as, for example, the CMDa to d signal discussed above. In some embodiments, the initial phase command signal can correspond to the CMD signal 510. In this case, the phase command signal circuit 600 does not generate an initial phase command signal, but only receives the first phase command signal, such as Fig. 6A. For example, for memory die 210a, a first phase command signal CMDa may be generated together with CMD signal 510. In some embodiments, the CMDa signal and the CMD signal 510 may be in phase with each other, and in some embodiments, the CMDa signal and the CMD signal 510 may be the same signal. Similarly, for other memory dies 210b to d, an initial phase command signal may be generated together with CMD signal 510 or may be the same as CMD signal 510. Phase command signal circuit 600 may provide a sequence of phase command signals corresponding to the activation mode of the memory die. For example, as Fig. 6A , memory die 210a may have a phase command signal sequence as follows: CMDa→CMDc→CMDb→CMDd. Similarly, phase command signal circuits in memory dice 210b-d (not shown) may provide phase command signals corresponding to respective activation patterns of memory dice 210b-d as follows: CMDd→CMDa→CMDc→CMDb; CMDb→CMDd→CMDa→CMDc; and CMDc→CMDb→CMDd→CMDa. Of course, the phase command sequence may differ from that discussed above, as long as data is not transferred to / from data segments that are simultaneously part of the same data unit.

[0057] like Fig. 6A As seen in FIG. 6 , the phase command signal circuit 600 includes flip-flop (FF) circuits 610, 620, and 630. An initial phase command signal CMDa may be generated in another circuit, and together with initializing a memory operation in data segment A at stage 1, the CMDa signal may be an input to the phase command signal circuit 600 for generation of CMDc, b, d signals. For example, the CMDa signal may be sent to the data input of the FF circuit 610. The clock input of the FF circuit 610 may receive the PLCKO signal, and the output of the FF circuit 610 may be the CMDc signal for initiating a memory operation in data segment C at stage 2. The data input of the FF circuit 620 may receive the CMDc signal. The clock input of the FF circuit 620 may receive the PLCKE signal, and the output of the FF circuit 620 may be the CMDb signal for initiating a memory operation in data segment B at stage 3. The data input of the FF circuit 630 may receive the CMDb signal. The clock input of FF circuit 630 may receive the PLCKO signal, and the output of FF circuit 630 may be the CMDd signal used to initiate a memory operation in data segment D at stage 4 .

[0058] Figure 6B Description Used to generate Figure 5d. In some embodiments, the distributed column access signal circuit 650 may be disposed in each of the memory dies 210a-d. For example, the distributed column access signal circuit 650 may be disposed in the column decoder 345 and / or another circuit in each of the memory dies 210a-d. For clarity, the distributed column access signal circuit 650 is described with respect to the memory die 210a. However, it should be understood by those skilled in the art that the distributed column access signal circuits in the memory dies 210b-d will be similar.

[0059] In some embodiments, similar to the phase command signal circuit 600, the initial distributed column access signal may correspond to the CMD signal 510. In this case, the distributed column access signal circuit 650 does not generate the initial distributed column access signal, but only receives the first distributed column access signal. For example, for the memory die 210a, the first distributed column access signal CASa may be generated together with the CMD signal 510 and received by the distributed column access signal circuit 650. In some embodiments, the CASa signal and the CMD signal 510 may be in phase with each other, and in some embodiments, the CASa signal and the CMD signal 510 may be the same signal. In some embodiments, the CMDa signal and the CASa signal may be the same signal. Similarly, for other memory dies 210b to d, the initial distributed column access signal may be generated synchronously with the CMD signal 510 or may be the same as the CMD signal 510 or may be the same signal as the corresponding phase command signal of the memory die 210b to d.

[0060] The distributed column access signal circuit 650 can provide a distributed column access signal sequence corresponding to the activation mode of the memory die. Figure 6B , memory die 210a may have a distributed column access signal sequence as follows: CASa→CASc→CASb→CASd. Similarly, distributed column access signal circuits in memory dies 210b-d (not shown) may provide distributed column access signals corresponding to respective activation patterns of memory dies 210b-d as follows: CASd→CASa→CASc→CASb; CASb→CASd→CASa→CASc; and CASc→CASb→CASd→CASa. Of course, the distributed column access sequence may differ from that discussed above, as long as data is not transferred to / from data segments that are simultaneously part of the same data unit.

[0061] like Figure 6B, the distributed column access signal circuit 650 includes FF circuits 660, 670, and 680. As discussed above, the initial distributed column access signal CASa may be generated in another circuit, and along with selecting CSL 410a in data segment A at stage 1, the CASa signal may be an input to the distributed column access signal circuit 650. For example, the CASa signal may be sent to the data input of the FF circuit 660. The clock input of the FF circuit 660 may receive the PLCKO signal, and the output of the FF circuit 660 may be the CASc signal for selecting CSL 410c for data segment C at stage 2. The data input of the FF circuit 670 may receive the CASc signal. The clock input of the FF circuit 670 may receive the PLCKE signal, and the output of the FF circuit 670 may be the CASb signal for selecting CSL 410b for data segment B at stage 3. The data input of the FF circuit 680 may receive the CASb signal. The clock input of FF circuit 680 may receive the PLCKO signal, and the output of FF circuit 680 may be the CASd signal of CSL 410d for selecting data segment D at stage 4 .

[0062] refer to Figure 5 , 6A 6B, at point t0 (phase 1), the first phase command signal CMDa and the corresponding CASa signal are set (e.g., in a high state) to transfer the first portion of the data set Data1 from / to data segment A. The CMDa and CASa signals are input to the FF circuits 610 and 660, respectively, and the PLCKO signal is a clock input to the FF circuits 610 and 660. At point t1 (phase 2), with the PLCKO signal on its rising edge, the FF circuit 610 sets the CMDc signal (e.g., to a high state) and the FF circuit 660 sets the CASc signal (e.g., to a high state). With the CMDc and CASc signals set, the first portion of the data set Data2 is transferred from / to data segment C. The CMDc and CASc signals are input to the FF circuits 620 and 670, respectively, and the PLCKE signal is a clock input to the FF circuits 620 and 670.

[0063] At point t2 (stage 3), with the PLCKE signal on its rising edge, the FF circuit 620 sets the CMDb signal (e.g., to a high state) and the FF circuit 670 sets the CASb signal (e.g., to a high state). With the CMDb and CASc signals set, the first portion of the data set Data3 is transferred from / to data segment B. The CMDb and CASb signals are input to the FF circuits 630 and 680, respectively, and the PLCKO signal is a clock input to the FF circuits 630 and 680. At point t3, the PLCKO signal is again on its rising edge, but this time the CMDa and CASa signals are reset (e.g., to a low state). Therefore, the FF circuits 610 and 660 reset the CMDc and CASc signals, respectively (e.g., to a low state). Still at point t3 (stage 4), with the PLCKO signal on its rising edge, the FF circuit 630 sets the CMDd signal (e.g., to a high state) and the FF circuit 680 sets the CASd signal (e.g., to a high state). In case the CMDd and CASd signals are set, the first part of the data set Data4 is transferred from / to the data segment D.

[0064] At point t4, the PLCKE signal is again on its rising edge, and the CMDc and CASc signals are reset (e.g., reset to a low state). Thus, FF circuits 620 and 670 reset the CMDb and CASb signals, respectively (e.g., reset to a low state). At point t5, the PLCKO signal is again on its rising edge, and the CMDb and CASb signals are reset (e.g., reset to a low state). Thus, FF circuits 630 and 680 reset the CMDd and CASd signals, respectively (e.g., reset to a low state). Similar misalignment sequences may be performed simultaneously in other memory dies 210b-d, as long as the remaining data portions of data sets Data1-4 are not transferred from data segments that are also parts of the same data unit.

[0065] In the above exemplary embodiments, the phase command signal circuit 600 and the distributed column access circuit 650 may be disposed in each memory die and configured to have different CMD / CAS signal sequences (e.g., CMD / CAS signal sequences corresponding to the respective activation modes of each memory die). However, the different sequences may require different hard circuit configurations between the memory dies 210a-d, which may complicate manufacturing. Therefore, in some exemplary embodiments of the present technology, a common phase command signal generation circuit may be used by multiple memory dies, and each memory die may use the same signal generation circuit to generate individual CMD signals and / or corresponding CAS signals.

[0066] Fig. 7AA common phase command signal circuit 700 is described that generates a common phase command signal (such as, for example, common phase command signals CMD1, CMD2, CMD3, and CMD4) that can be transmitted to each memory die 210a-d to generate individual phase command signals (such as, for example, phase command signals CMDa-d) and, in some embodiments, generates distributed column access signals CASa-d in the appropriate activation mode of each memory die 210a-d. The operation of the common phase command signal circuit 700 is similar to the phase command signal circuit 600 discussed above, and therefore, for the sake of brevity, the operation of the common phase command signal circuit 700 will not be repeated. Similar to the generation of the phase command signal CMDa discussed above, the first phase command signal CMD1 can be in phase with or the same as the main command signal (such as, for example, CMD signal 510). The generation of the phase command signals CMD2-CMD4 can be similar to what is described above with respect to the phase command signals CMDb-d. In an exemplary embodiment, the common phase command signal circuit 700 and the phase clock generation circuit (not shown) for generating the PCLK(E / O) signal may be in the logic die 230. For example, the common phase command signal circuit 700 and the phase clock generation circuit may be part of the address command input circuit 305 and / or some other circuit in the logic die 230. The common phase command signals CMD1-4 output from the common phase command signal circuit 700 may be transmitted to the stagger circuit in each of the memory dies 210a-d. The stagger circuit sets the individual phase command signals and / or distributed column access signals according to the above for transferring data (e.g., data sets Data1-4) from / to each of the memory dies 210a-d based on the staggered activation pattern (e.g., Table 1).

[0067] Figure 7BExemplary embodiments of misalignment circuits according to the present technology are described. In some embodiments, each memory die may include a misalignment circuit 710 connected to the output of a common phase command signal circuit 700 (e.g., using TSVs and / or some other connection). The misalignment circuit 710 may include a plurality of phase command signal selector circuits 720 (also referred to herein as "selector circuits 720") corresponding to a number of data segments in the memory array. Each selector circuit 720 may include one or more signal inputs 722 configured to accept a common phase command signal (e.g., CMD1-4 signal) from the common phase command signal circuit 700. Each selector circuit 720 may include an output 724 configured to output the selected input signal as an individual phase command signal to the appropriate data segment in the memory array 350. The output of each signal selector circuit 720 in the memory die may be configured to connect to a different data segment so that no two selector circuits 720 are connected to the same data segment. Each selector circuit 720 may also include a program input 726 configured to accept program code for configuring the selector circuit 720. The program code configures the selector circuit 720 to select one of the common phase command signals at the input 722 as the signal transmitted to the output 724 .

[0068] like Figure 7B As seen in , the misalignment circuit 710 in each of the memory dies 210a to d may include four signal selector circuits 720a to d. Each selector circuit 720a to d may correspond to data segments A to D in the respective memory dies 210a to d. For example, the output 724 of the selector circuit 720a may be an individual phase command signal CMDa connected to data segment A. Similarly, the outputs of the selector circuits 720b to d may be individual phase command signals CMDb to d connected to data segments B to D, respectively. Each selector circuit 720a to d may receive a common phase command signal CMD1 to 4 at an input 722 (e.g., at inputs 1 to 4). Based on the program code, each selector circuit 720a to d may select one of the common phase command signals CMD1 to 4 and output the common phase command signal as one of the individual phase command signals CMDa to d. As shown Figure 7B, the order of the common phase command signals CMD1-4 at the input 722 may vary between the selector circuits 720a-d such that no two selector circuits 720a-d in the same memory die have the same order. However, the order of the common phase command signals at the selector circuits 720 of the misalignment circuit 710 may be the same between the memory dies 210a-d. That is, the misalignment circuit 710 may be the same in each memory die 210a-d. The change in the order of the common phase command signals CMD1-4 at the input 722 of each selector circuit 720a-d in the memory die may correspond to a misaligned activation pattern, such as, for example, the misaligned activation pattern shown in Table 1.

[0069] In some embodiments, based on a program code received at program input 726, each selector circuit 720a-d may be configured to select an appropriate common phase command signal CMD1-4. The programming of the selector circuits 720a-d and / or the order of the common phase command signals CMD1-4 at input 722 may be set so that data segments from memory dies 210a-d that are part of the same data unit are not selected when data is transferred from / to memory component 202. By having the selector circuits 720a-d have a programmable configuration rather than having a fixed configuration such as, for example, Fig. 6A and 6B In some embodiments, the programming of the selector circuits 720a to d may be completed at the factory. The programming may be fused so that once programmed the selector circuits 720a to d cannot be reprogrammed. In other embodiments, the selector circuits 720a to d may be reprogrammable.

[0070] In some embodiments, the program code used to configure the selector circuits 720a-d may be based on a memory die. For example, in some embodiments, each selector circuit 720a-d of a memory die may be programmed to select a particular input, such as, for example, an input <1> arrive <4> d and outputs the incoming signal on the selected input as an individual phase command signal to the appropriate data segment. For example, for memory die 210a, selector circuits 720a-d may be programmed to select input <1> Thus, selector circuit 720a may output the input CMD1 signal as the phase command signal CMDa, selector circuit 720b may output the input CMD2 signal as the phase command signal CMDb, selector circuit 720c may output the input CMD3 signal as the phase command signal CMDc, and selector circuit 720d may output the input CMD4 signal as the phase command signal CMDd. Similarly, each selector circuit 720a-d in memory die 210b may be programmed to select, for example, the input <2> , each selector circuit 720a-d in the memory die 210c can be programmed to select, for example, an input <3> , and each selector circuit 720a-d in memory die 210d can be programmed to select, for example, input <4> Table 2 for Figure 7B The embodiments provide exemplary selection modes.

[0071] Table 2

[0072]

[0073] As seen in Table 2, the selector circuit 720a-d of each memory die 210a-d can be configured to select an input (e.g., input <1> arrive <4> ). In phase 1, when the CMD1 signal is set (e.g., in a high state), the appropriate selector circuits 720a-d in each of the memory dies 210a-d output the appropriate individual phase command signals CMDa-d based on how the selector circuits 720a-d in each of the misalignment circuits 710 are programmed. For example, referring to Table 2, in the memory die 210a, the selector circuits 720a-d may be programmed to select the input <1> Thus, once programmed, the inputs to selector circuits 720a through d are <2> arrive <4> is not activated and is not used. Because the outputs of selector circuits 720a-d follow the selected inputs in memory die 210a <1> , so the CMDa signal will be set (e.g., in a high state) when the CMD1 signal is set, and the CMDb, c, d signals will be reset (e.g., in a low state) because the common phase command signals CMD2 to 4 will be reset (e.g., in a low state). In which the selector circuits 720a to d are programmed to select the input <2> In the memory die 210b of FIG. 1, when the CMD1 signal is set and CMD2 to 4 are reset, the CMDd signal will be set and the CMDa, b, c signals will be reset. Similarly, in the memory die 210b of FIG. 1, when the CMD1 signal is set and CMD2 to 4 are reset, the CMDd signal will be set and the CMDa, b, c signals will be reset. <3> In the memory die 210c in which the selector circuits 720a to d are programmed to select the input, when the CMD1 signal is set and CMD2 to 4 are reset, the CMDb signal will be set and the CMDa, c, d signals will be reset. Finally, in the memory die 210d in which the selector circuits 720a to d are programmed to select the input, when the CMD1 signal is set and CMD2 to 4 are reset, the CMDd signal will be set and the CMDa, b, c signals will be reset. Therefore, when the CMD1 signal is set, data from different data segments A to D in the memory die 210a to d are transmitted simultaneously. As shown in Table 2 and Fig. 7A and 7B As seen in FIG. 1 , data from other data segments A to D in the memory dies 210a to d may be transferred in a manner similar to that in which other common phase command signals CMD2 to 4 are sequentially set (eg, set to a high state).

[0074] As discussed above, when the individual phase command signals for a given data segment A to D are set, the corresponding distributed column access signals that select the appropriate CSL are also set (e.g., set to a high state) at the same time. Therefore, to provide the corresponding CAS signals, the memory component 202 may have a misalignment circuit for the CAS signal, which is similar to the content of the misalignment circuit 710. For example, if Figure 7BAs seen in , the corresponding CAS signals, CASa, CASb, CASc, and CASd signals are shown within parentheses. Because the mistuning circuit for the CAS signals will be similar to the content of the mistuning circuit for the CMD signal, the description of the CAS mistuning circuit is omitted for the sake of brevity. In some embodiments, the CMDa to d signal and the CASa to d signal may be generated by the same mistuning circuit. In some embodiments, the CMDa to d signal and the CASa to d signal may be the same signal, and in such cases, a separate CAS mistuning circuit may not be required. An exemplary mistuning pattern for the CASa to d signal that is compatible with the CMDa to d signal is shown in Table 3.

[0075] Table 3

[0076]

[0077] Fig. 8A An exemplary data arrangement in a memory component 202 of, for example, an IoT node 120 is illustrated. For example, the memory component 202 may be a memory component of the IoT node 120 and may store data sets Data1 to 4 from, for example, sensors 110a to d, respectively (see Figure 1 ). In an exemplary embodiment, as discussed above, each data set Data1-4 may be divided into multiple data portions, and the respective data portions may be stored in data segments (e.g., data segments A-D) of one or more memory dies such that the stored portions are not in data segments that are portions of the same data unit. For example, Fig. 8A As seen in FIG. 1 , data set Data1 may be divided into four portions D1a, D1b, D1c, and D1d, and each portion may be stored in a data segment in memory dies 210a, c, d, b, respectively. For example, data portions D1a-d may be stored in data segments A-D of memory dies 210a, c, d, b using a pattern that ensures that data portions D1a-d are not stored in data segments that are part of the same data unit. That is, data portions D1a-d may be stored such that no two data portions in D1a-d are in the same data unit. As discussed above, each data unit may include a shared data bus (connected by Fig. 8A ) are represented by dotted lines in the memory dies 210a to 210d. For example, all data segments A in the memory dies 210a to 210d may represent the first corresponding data segment. Similarly, all data segments B may represent the second data unit, all data segments C may represent the third data unit, and all data segments D may represent the fourth data unit.

[0078] In some embodiments, for example, Fig. 8AAs seen in FIG. 1 , data portions D1a-d and other data portions (e.g., data portions of data sets Data2-4) may be stored in data segments A-D of memory dies 210a-d in a pattern corresponding to the staggered activation pattern of Table 1. In some embodiments, each set of data portions Data1-4 may be transferred separately during corresponding phases 1-4 of a CMD signal cycle tCCD corresponding to, for example, CMD1-4. For example, data portions D1a-d are shown with square symbols to indicate that data is transferred to / from the corresponding data segments during the CMD1 signal phase. Fig. 8A , data portion D1a may be stored in data segment A of memory die 210a, data portion D1b may be stored in data segment B of memory die 210c, data portion D1c may be stored in data segment C of memory die 210d, and data portion D1d may be stored in data segment D of memory die 210b. During the CMD1 signal, data portions D1a, D1b, D1c, and D1d are simultaneously transferred to logic die 230 via TSVs A to D, respectively, and to, for example, processor component 204. Similarly, data sets Data2 to 4, which may be data from, for example, sensors 110b to d, may be divided into multiple portions, such as, for example, D2a to d, D3a to d, and D4a to d. Similar to data portions D1a-d, data portions D2a-d, D3a-d, and D4a-d may be stored in data segments A-D of memory dies 210a-d using activation patterns corresponding to the staggered activation patterns of Table 1. Data portions D2a-d are shown with circular symbols to indicate that data is transferred to / from the respective data segments during the CMD2 signal phase. During the CMD2 signal, data portions D2a, D2b, D2c, and D2d are simultaneously transferred via TSVs A-D, respectively. Similarly, D3a-d and D4a-d are shown with triangle and diamond symbols, respectively, to indicate that data is transferred during the CMD3 and CMD4 signal phases. During the CMD3 and CMD4 signals, respective data portions of data sets Data3 and Data4 are simultaneously transferred via TSVs A-D. Of course, data portions may be stored in data segments using other patterns, as long as the data portions are not simultaneously transferred from / to the same data unit.

[0079] As discussed above, data sets Data1-4 may be transferred from / to logic die 230 via LIO (T / B) and / or MIO (T / B) buses (represented by dotted lines) using TSVs A-D. For example, data portions D1a-d may be transferred simultaneously via TSVs A-D during CMD1 (Phase 1). Because data portions D1a-d are transferred simultaneously, each data portion D1a-d is transferred via a different TSV, such as (for example) TSVs A-D, respectively. Similarly, each set of data portions D2a-d, D3a-d, and D4a-d may be transferred simultaneously using TSVs A-D during respective CMD2-4 (Phase 2-4). Figure 8B As can be seen in FIG. 5 , four data sets Data1, Data2, Data3, and Data4 can be transmitted in each cycle tCCD of the CMD signal 510. In contrast, a related art system using a single die type configuration or using a TSV shift configuration can only transmit one data set, such as Data1, Data2, Data3, or Data4, in each cycle tCCD of the CMD signal 510.

[0080] Fig.9A A block layout diagram of a memory array with corresponding amplifiers / drivers is shown. Fig.9A A section of a memory die 210 having multiple memory arrays 350 is illustrated. In some embodiments, the memory arrays 350 may be disposed on the same bank and / or different banks MB0-7. The memory arrays 350 labeled "active area" correspond to rows accessed by a row decoder 340. As discussed above, instead of one column select line as in related art systems, the column select lines are divided into (for example) four portions CSL 410a-d. Based on an address signal ADDR, one of the CSLs 410a-d is activated by a column decoder 345 to allow access to a desired data segment A-D in the active area. Data to / from the selected data segment A-D is transmitted using a corresponding MIO (T / B) bus. As Fig.9A As seen in FIG. 1 , the read / write amplifier module 355 may include one or more amplifier modules connected to the MIO (T / B) bus. For example, the read / write amplifier module 355 may include four amplifier modules 355a to d. Each amplifier module 355a to d may be connected to 32 MIO (T / B) buses, which correspond to data segments A to D. For example, for data segment A, amplifier module 355a may be connected to 32 MIO (T / B) buses. Amplifier module 355a may receive a CMDa signal to transmit a data portion Dxa (where x corresponds to a data set, and the data layout in the memory die may be, for example) Fig. 8ASimilarly, for data segments B to D, amplifier modules 355b to d may be connected to 32 MIO (T / B) buses, respectively. Amplifier modules 355b to d may receive CMDb to d signals to transmit data portions Dxb to Dxd (see, for example, Fig. 8A For read operations, amplifier modules 355a-d may include a read amplifier that further amplifies the data signal from sense amplifier SA. For write operations, amplifier modules 355a-d may include a write amplifier / driver to set the MIO (T / B) bus voltage at an appropriate level for writing data to the appropriate memory cells. Each of amplifier modules 355a-d may be connected to a power bus 356 that supplies the voltage / current required to operate amplifier modules 355a-d.

[0081] As discussed above, amplifier modules 355a to d receive CMDa to d signals and corresponding data portions Dxa to d designated for respective data segments A to D. When the CMDa to d signals for data segments A to D are set to active, appropriate read or write circuits in amplifier modules 355a to d are turned on based on whether the CMDa to d signals are used to write data to a memory cell or to read data from a memory cell. In related art systems that include only one column select line for a memory array, the number of data bits switched on a given command signal can lead to peak power issues. However, by dividing the column access line into multiple column select lines (e.g., CSL 410a to d) and distributing the activation of the CSLs within a period tCCD of the CMD signal, as discussed above, the power drawn by the amplifier modules is spread over a period tCCD, which reduces the peak power drawn on any given amplifier module. Additionally, the staggered activation pattern of the CAS signals that activate the CSLs 410a to d can be varied to reduce noise on the power bus. Using an activation pattern in which adjacent amplifier modules 355 are turned on sequentially between phases (e.g., phase 1 to phase 2) can cause noise on the power bus. To mitigate noise, a staggered activation pattern for activating the CSLs may cause amplifier modules adjacent to each other, such as (for example) amplifier modules 355a and 355b or amplifier modules 355c and 355d, to not be turned on sequentially between phases. An exemplary activation sequence of the CSLs that may help reduce noise on the power bus may correspond to the staggered activation pattern of Table 1. For example, amplifier module 355 may be turned on as follows: amplifier module 355a (CSL 410a), amplifier module 355a (CSL 410c), amplifier module 355a (CSL 410b), and amplifier module 355a (CSL 410d). Of course, other sequences may be used to ensure that adjacent amplifier modules 355a to d are not turned on sequentially.

[0082] Fig. 9B Another layout diagram of a memory array with corresponding amplifiers / drivers is shown. Fig. 9B The layout of the memory array in Fig.9A The layout of the memory array of FIG. 350 is different in that the memory array 350′ uses a 512-bit data bus instead of Fig.9A The 256-bit data bus of the memory array 350 in FIG. Fig. 9B , each CSL corresponds to two sets of 32-bit MIO (T / B) buses connected to amplifier modules 355, respectively. For example, CSL 410a includes two 32-bit MIO (T / B) buses connected to amplifier modules 355a and 355a', respectively. Similarly, CSLs 410b-d each include two 32-bit MIO (T / B) buses connected to 355b, b', 355c, c', and 355d, d', respectively. Thus, although each data segment A-D has two amplifier modules, the two amplifier modules will work together when the phase command signal (e.g., CMDa-d signal) is set to transmit the corresponding data portion Dxa-d designated for the corresponding data segment A-D.

[0083] Fig. 10A and 10B Simplified block diagrams illustrating circuits for read and write operations, respectively. Fig. 10A A read circuit 1000 is described for reading data stored in a memory die using appropriate TSV connections. For example, the read circuit 1000 may use TSV A to D connections (see Fig. 8A ) reads Data 1 to 4 stored in memory dies 210a to d (which may correspond to data from IoT 110a to d). TSV A to D connections may correspond to, for example, a MIO (T / B) data bus connected to the IO circuitry 360 of each memory die 210a to d. Read circuitry 1000 may be part of the read / write circuitry 380 in logic die 230 and may be connected to the IO circuitry 360 of each memory die 210a to d (see Figure 3 ). When the read CMD signal is issued, data portions of one or more data sets (e.g., Data1-4) are read and transferred to the TSVs. For example, as discussed above, data portions D1a-d, which correspond to Data1, can be simultaneously read from respective memory dies 210a-d and transferred to TSVs A-D during phase 1. Similarly, data portions D2a-d, D3a-d, and D4a-d can be read during phases 2-4, respectively, as discussed above.

[0084] As discussed above, read circuit 1000 may be configured to read data present on TSVs A-D and transfer the data to, for example, DQ data terminals. Fig. 10A As seen in FIG. 1 , the read circuit 1000 may have multiple data latch circuits 1010, 1012, 1014, 1016, each of which has multiple FF circuits corresponding to each bit line of the MIO (T / B) bus (e.g., the MIO (T / B) may be a 128-bit bus or another bit size bus). As discussed below, the data latch circuit 1016 may have additional FF circuits corresponding to the output data from the data latch circuits 1010, 1012, and 1014. For clarity, the data latch circuits 1010, 1012, 1014, and 1016 are shown with only one FF circuit. However, those skilled in the art will recognize that the number of FF circuits in the data latch circuit will depend on the number of input data lines.

[0085] The data input to the data latch circuit 1010 may receive the data set Data1, and the clock input to the data latch circuit 1010 may receive the clock signal RD1, which may correspond to the CMD1 signal generated during the phase 1 cycle as discussed above. The clock signal RD1 may be synchronized with the CMD1 signal (in some embodiments, the same signal as the CMD1 signal), or the RD1 signal may be delayed based on the read latency when reading Data1 from the data segment. Similarly, the data inputs to the data latch circuits 1012 and 1014 may receive the data sets Data2 and Data3, respectively. The clock inputs to the data latch circuits 1012 and 1014 may receive the clock signals RD2 and RD3, respectively. Similar to the RD1 signal, the RD2 and RD3 signals may correspond to the CMD2 and CMD3 signals generated during the phase 2 and phase 3 cycles, respectively, as discussed above. The clock signals RD2 and RD3 may be synchronized with the CMD2 and CMD3 signals, respectively (in some embodiments, the same signals as the CMD2 or CMD3 signals, as appropriate), or the RD2 and RD3 signals may be delayed based on read latency when reading from the data segments.

[0086] like Fig. 10AAs seen in FIG. 1 , the data input to data latch circuit 1016 may receive data set Data4 and the outputs of data latch circuits 1010, 1012, and 1014. The clock input to data latch circuit 1016 may be RD4, which may correspond to the CMD4 signal generated during the phase 4 cycle as discussed above. The clock signal RD4 may be synchronized with the CMD4 signal (e.g., in some embodiments, may be the same signal as the CMD4 signal), or the RD4 signal may be delayed from the CMD4 signal to account for the read latency when reading Data4 from the data segment. In some embodiments, data latch circuit 1016 is identical to data latch circuits 1010, 1012, and 1014 and a separate data latch circuit may receive the outputs of data latch circuits 1010, 1012, 1014, and 1016.

[0087] As discussed above, the phase command signals CMDa to d and the distributed column access signals CASa to d may read the appropriate data set (e.g., Data1 to 4) during each phase (e.g., phases 1 to 4) of the CMD signal 510 and transfer the data set to the TSV connection. During each phase (e.g., phases 1 to 4), the data present on the TSV connection is read by the read circuit 1000 in a timely manner and transferred to the DQ terminal. For example, on the rising edge (or falling edge) of the RD1 signal, the data latch circuit 1010 may read the data set Data1 value from TSV A to D during phase 1 and output a latched value Data1_lat corresponding to the data set Data1. Similarly, on the rising edge (or falling edge) of RD2, the data latch circuit 1012 may read the data set Data2 value from TSV A to D during phase 2 and output a latched value Data2_lat corresponding to the data set Data2. On the rising edge (or falling edge) of the RD3 signal, the data latch circuit 1014 may read the data set Data3 value from TSV A to D during phase 3 and output a latched value Data3_lat corresponding to the data set Data3. Finally, on the rising edge (or falling edge) of RD4, the data latch circuit 1016 may read the data set Data4 value from TSV A to D during phase 4 and read the latched data from the output of the data latch circuits 1010, 1012, 1014. The output of the data latch circuit 1016 is Dout, which corresponds to the value of the data sets Data1, Data2, Data3, and Data4. Dout may be transmitted to the DQ data terminal of the logic die 230 for use by, for example, the processor component 204 and / or another device.

[0088] Fig. 10BA write circuit 1050 is illustrated for transmitting data Din to the TSV connection of the MIO (T / B) data bus. Data from the DQ data terminal is provided to the input of the write circuit 1050 as data Din. The clock input to the write circuit 1050 may be a WR clock signal. The clock signal WR may be synchronized with the CMD1 signal, and in some embodiments, may be the same as the CMD1 signal. The write circuit 1050 may be a data latch circuit having multiple FF circuits depending on the number of data lines. However, for clarity, the write circuit 1050 shows only one FF circuit. The write circuit 1050 may be part of the read / write circuit 380 in the logic die 230 and may be connected to the IO circuit 360 of each memory die 210a to d (see Figure 3 ).

[0089] As discussed above, the phase command signals CMDa-d and the distributed column access signals CASa-d may write the data sets (e.g., Data1-4) available on the TSV connections to the appropriate data segments (e.g., data segments A-D) in each of the memory dies (e.g., memory dies 210a-d) during each phase (e.g., phases 1-4) of the CMD signal 510. During each phase (e.g., phases 1-4), the data Din at the DQ terminals may be written to the TSVs in a timely manner by the write circuit 1050. For example, on the rising edge (or falling edge) of the WR clock cycle, the write circuit 1050 may read the Din value from the DQ terminals received at the input of the write circuit 1050 during, for example, phase 1 and output latched values ​​Data1_lat, Data2_lat, Data3_lat, and Data4_lat. In some embodiments, each latched value Data1_lat, Data2_lat, Data3_lat, and Data4_lat may be divided into data portions (e.g., D1a to d, D2a to d, D3a to d, and D4a to d) and multiplexed (not shown) so that an appropriate set of data portions (e.g., D1a to d, D2a to d, D3a to d, and D4a to d) may be used for write operations at TSVs A to D during appropriate phases 1 to 4 of the CMD signal 510. For example, Data1 may be divided into data portions D1a, D1b, D1c, and D1d and made available for write operations at TSVs A to D, respectively, during phase 1. Similarly, Data2 to 4 may be divided and made available for write operations at TSVs A to D during phases 2 to 4.

[0090] Fig.11 An exemplary timing diagram 1100 illustrates a write operation of data sets Data1, Data2, Data3, and Data4 to memory dies 210a-d. Fig.11As seen in FIG. 1 , data sets are transmitted during phases 1 to 4 based on common phase command signals CMD1, CMD2, CMD3, and CMD4 (discussed above). The phase shift between each of the phase command signals in this exemplary embodiment may be 25% of tCCD. For example, the CMD1 signal of phase 1 may be aligned with CMD signal 510 (see FIG. 1 ). Figure 5 ) in phase (e.g., 0% phase shift, e.g., at t=0), the CMD2 signal of phase 2 may be phase shifted 25% from the CMD signal (e.g., at t=1 / 4tCCD), the CMD3 signal of phase 3 may be phase shifted 50% from the CMD signal (e.g., at t=1 / 2tCCD), and the CMD4 signal of phase 4 may be phase shifted 75% from the CMD signal (e.g., at t=3 / 4tCCD). In some embodiments, each CMD1-4 may correspond to individual phase command signals CMDa-d and distributed column access select signals CASa-d in memory dies 210a-d, as shown in Tables 2 and 3 and as discussed above. For clarity, individual phase command signals and distributed column access signals are not shown in timing diagram 1100.

[0091] As seen in timing diagram 1100, at or before t0, a data set Data1 (data portions D1a, D1b, D1c, D1d) may be made available on TSVs A-D (which may be part of a MIO (T / B) and / or LIO (T / B) bus) for a write operation to a desired memory cell. At time t0 (e.g., phase 1), a CMD1 signal may be set (e.g., set to a high state) to activate the appropriate CSL, as discussed above. For example, referring to Figure 4 1, at t0, CSL 410a in memory die 210a may be activated, CSL 410d in memory die 210b may be activated, CSL 410b in memory die 210c may be activated, and CSL 410c in memory die 210d may be activated. As discussed above, activating the CSLs provides access to the desired memory cells in the appropriate data segments A to D, and the values ​​of the appropriate data portions D1a, D1b, D1c, D1d on the TSV A to D connections may be written to the data segments A to D. For example, referring to Fig. 8A As shown in Table 1, during Phase 1, D1a may be written to data segment A of memory die 210a, D1b may be written to data segment B of memory die 210c, D1c may be written to data segment C of memory die 210d, and D1d may be written to data segment D of die 210b.

[0092] At or before t1 (e.g., phase 2), data set Data2 (data portions D2a, D2b, D2c, D2d) may be made available on TSVs A through D for a write operation to a desired memory cell. At time t1, the CMD2 signal may be set (e.g., to a high state) to activate the appropriate CSL, as discussed above. For example, referring to Figure 4 As shown in Table 1, at t1, CSL 410c in memory die 210a may be activated, CSL 410a in memory die 210b may be activated, CSL 410d in memory die 210c may be activated, and CSL 410b in memory die 210d may be activated. Fig. 8A As shown in Table 1, during phase 2, D2a may be written to data segment A of memory die 210b, D2b may be written to data segment B of memory die 210d, D2c may be written to data segment C of memory die 210a, and D2d may be written to data segment D of memory die 210d.

[0093] At or before t2 (e.g., stage 3), data set Data3 (data portions D3a, D3b, D3c, D3d) may be made available on TSVs A through D for a write operation to the desired memory cell. At time t2, the CMD3 signal may be set (e.g., to a high state) to activate the appropriate CSL, as discussed above. For example, referring to Figure 4 As shown in Table 1, at t2, CSL 410b in memory die 210a may be activated, CSL 410c in memory die 210b may be activated, CSL 410a in memory die 210c may be activated, and CSL 410d in memory die 210d may be activated. Fig. 8A As shown in Table 1, during phase 3, D3a may be written to data segment A of memory die 210c, D3b may be written to data segment B of memory die 210a, D3c may be written to data segment C of memory die 210b, and D3d may be written to data segment D of memory die 210d.

[0094] At or before t3 (e.g., stage 4), Data4 (data portions D4a, D4b, D4c, D4d) may be made available on TSVs A through D for a write operation to the desired memory cell. At time t3, the CMD4 signal may be set (e.g., set to a high state) to activate the appropriate CSL, as discussed above. For example, referring to Figure 4As shown in Table 1, at t3, CSL 410d in memory die 210a may be activated, CSL 410b in memory die 210b may be activated, CSL 410c in memory die 210c may be activated, and CSL 410a in memory die 210d may be activated. Fig. 8A As shown in Table 1, during phase 4, D4a may be written to data segment A of memory die 210d, D4b may be written to data segment B of memory die 210b, D4c may be written to data segment C of memory die 210c, and D4d may be written to data segment D of memory die 210a.

[0095] At time tCCD, the process repeats until all desired data is written to the appropriate memory cells. For clarity, the read timing diagram is not shown, but one skilled in the art will understand that the timing will be similar, but where data is read from the memory cells and transferred to the appropriate TSV A to D connections. As seen in timing diagram 1100, for each cycle tCCD, four data transfers are performed compared to one data transfer in a related art memory device. Thus, exemplary embodiments of the present invention can achieve higher throughput than related art memory devices (e.g., four times the throughput). Additionally, the amplifier module does not require higher voltages to limit IR voltage drops and reduces noise on the power bus as compared to related art systems.

[0096] Although the present invention has been described with reference to the disclosed embodiments, it will be appreciated by those skilled in the art that changes may be made in form and detail without departing from the present invention. That is, the above detailed description of the embodiments of the present invention is not intended to be exhaustive or to limit the present technology to the precise form disclosed above. Although specific embodiments and examples of the present technology are described above for illustrative purposes, it will be appreciated by those skilled in the relevant art that various equivalent modifications are possible within the scope of the present technology. For example, the various embodiments described herein may be combined to provide additional embodiments. Such modifications are fully within the technical scope of those skilled in the art. Therefore, the present invention is limited only by the appended claims.

[0097] From the foregoing, it should be understood that the specific embodiments of the present technology are described herein for illustrative purposes, but well-known structures and functions are not shown or described in detail to avoid unnecessarily obscuring the description of the embodiments of the present technology. Where context permits, singular or plural terms may also include plural or singular terms, respectively. In addition, unless the word "or" is clearly limited to a single item that represents a list with reference to two or more items that is excluded from other items, the use of "or" in this list should be interpreted as any combination of items in any single item in the list (a), all items in the list (b) or the list (c). In addition, the use of the terms "including", "comprising" and "having / with" throughout the text means including at least the feature so as not to exclude any larger number of identical features and / or other features of additional types.

[0098] The processing device (e.g., processor 116 and / or another processor / controller) represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets or multiple processors that implement a combination of instruction sets. The processing device (e.g., processor component 204 and / or another controller) may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a system on a chip, a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device (e.g., processor component 204 and / or another controller) is configured to execute instructions for performing the operations and steps discussed herein.

[0099] A machine-readable storage medium (also referred to as a computer-readable medium) on which is stored one or more sets of instructions or software embodying any one or more of the methodologies or functions described herein. The machine-readable storage medium may be, for example, the memory component 202 or another memory device. The term "machine-readable storage medium" should be understood to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be understood to include any medium capable of storing or encoding a set of instructions executed by a machine and causing the machine to perform any one or more of the methodologies of the present invention. The term "machine-readable storage medium" should accordingly be understood to include, but not limited to, solid-state memory, optical media, and magnetic media.

[0100] Some portions of the foregoing detailed description have been presented in terms of algorithms and / or symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is herein, and generally, conceived to be a self-consistent sequence of operations leading to a desired result. Operations are those requiring physical manipulation of physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0101] It should be remembered, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present invention may be directed to the actions and processes of computer systems or similar electronic computing devices that manipulate data represented as physical (electronic) quantities within the computer system's registers and memories and transform that data into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0102] The present invention also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0103] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used in conjunction with programs according to the teachings herein, or it may prove convenient to construct more specialized equipment to perform the methods. The structures for various of these systems will appear as set forth in the description below. In addition, the present invention is not described with reference to any particular programming language. It should be appreciated that a variety of programming languages ​​may be used to implement the teachings of the present invention described herein.

[0104] The present invention may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which can be used to program a computer system (or other electronic device) to perform a process according to the present invention. A machine-readable medium includes any mechanism for storing information in a form that can be read by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory device, etc.

[0105] It should also be understood that various modifications may be made without departing from the present invention. For example, it should be understood by those skilled in the art that the various components of the present technology may be further divided into subcomponents, or the various components and functions of the present technology may be combined and integrated. In addition, certain aspects of the present technology described in the context of a particular embodiment may also be combined in other embodiments or eliminated in other embodiments. In addition, although the advantages associated with those embodiments have been described in the context of certain embodiments of the new technology, other embodiments may also exhibit such advantages, and not all embodiments necessarily need to exhibit such advantages to fall within the scope of the present technology. Therefore, the present invention and associated technology may encompass other embodiments that are not explicitly shown or described.

Claims

1. A semiconductor device comprising: A plurality of memory dies, each memory die having: at least one memory cell array divided into a plurality of data segments configured to be selectively accessed, and a detuning circuit configured to select a common command signal from a plurality of common command signals and configured to set at least one of a column access signal or an individual command signal, the column access signal selecting a data segment to be accessed based on the common command signal and the individual command signal to perform a memory operation corresponding to the selected common command signal on the selected data segment; a data bus connecting each of the at least one memory cell array to form a plurality of data cells, each data cell including data segments from each memory cell array, wherein the data segments in each data cell are connected in parallel to the data bus and use the same line of the data bus; and a command signal circuit connected to each misalignment circuit in the plurality of memory dies and configured to generate the plurality of common command signals, The misalignment circuit is further configured such that the selected data segments are not part of the same data unit. 2 . The semiconductor device according to claim 1 , further comprising an input-output circuit that simultaneously transfers data to or from the selected data segments. 3 .

3. The semiconductor device according to claim 1 , wherein the command signal circuit receives a main command signal and generates the plurality of common command signals based on the main command signal, each common command signal being arranged at a different phase of the main command signal, and Wherein a different data segment in each of the plurality of memory dies is selected for each phase of the master command signal.

4. The semiconductor device of claim 1 , wherein each mismatch circuit comprises a plurality of selector circuits corresponding to the plurality of data segments, each selector circuit having a plurality of input connections for respectively receiving one of the plurality of common command signals and an output for selecting a corresponding data segment for access, Wherein each selector circuit is configured to select a signal received at a predetermined input connection, and wherein an order of the plurality of common command signals for the input connections at each of the selector circuits in the misalignment circuit is different. 5 . The semiconductor device of claim 4 , wherein the common command signal sequence at the selector circuit of each of the mismatch circuits is the same between memory dies.

6. The semiconductor device of claim 4, wherein the predetermined input connections are specified for each selector circuit based on program code, and Wherein the predetermined input connections are the same for each selector circuit in the misalignment circuit.

7. The semiconductor device of claim 6, wherein the predetermined input connection is different between misaligned circuits.

8. The semiconductor device of claim 3, wherein each memory die further comprises a plurality of amplifier modules corresponding to the plurality of data segments, each amplifier module having a write driver, a read amplifier, or both, and Wherein each misalignment circuit is configured to select data segments whose amplifier modules are not disposed adjacent to each other on the power bus between consecutive phases of the master command signal.

9. The semiconductor device of claim 3, wherein a data set to be transmitted is divided into data portions and each data portion of the data set is stored in a separate memory die, and Wherein the data portions of the data set are transmitted simultaneously during a single phase of the master command signal.

10. The semiconductor device of claim 1, wherein each memory die is configured such that each data segment of the plurality of data segments has a corresponding column select line, and Wherein selecting the data segment to be accessed includes activating the corresponding column select line using the column access signal. 11 . The semiconductor device according to claim 1 , wherein the column access signal and the individual command signal are generated simultaneously. 12 . The semiconductor device according to claim 3 , wherein the main command signal corresponds to one of a read request or a write request generated outside the semiconductor device. 13 . The semiconductor device according to claim 3 , wherein the number of the common command signals generated by the command signal circuit is equal in number to the data segments. 14 . The semiconductor device according to claim 11 , wherein the number of the data fragments is in the range of 2 to 8.

15. The semiconductor device of claim 1, wherein the mismatch circuit is configured to output the column access signal and the individual command signal.

16. The semiconductor device of claim 1, wherein the plurality of memory dies are arranged in a stacked configuration.

17. The semiconductor device of claim 16, wherein the semiconductor device comprises at least four memory dies stacked on top of each other.

18. A semiconductor device comprising: a first memory die comprising a first array of memory cells at least partially divided into a first data segment and a second data segment; a second memory die stacked with the first memory die, the second memory die comprising a second memory cell array at least partially divided into a third data segment and a fourth data segment; a first data bus commonly coupled to the first data segment of the first memory die and the third data segment of the second memory die; and a second data bus commonly coupled to the second data segment of the first memory die and the fourth data segment of the second memory die; wherein the first memory die is configured to simultaneously transfer memory data from the first data segment to the first data bus when the second memory die transfers memory data from the fourth data segment to the second data bus, and The first data bus is different from the second data bus, the first data segment is different from the second data segment, and the third data segment is different from the fourth data segment.

19. The semiconductor device of claim 18, wherein the second memory die is configured to transfer memory data from the third data segment to the first data bus when the first memory die is configured to transfer memory data from the second data segment to the second data bus.

20. The semiconductor device of claim 19, wherein the first and second memory dies are configured such that the transfer of the memory data from the second data segment is completed after the transfer of the memory data from the first data segment.

21. The semiconductor device of claim 20, wherein the first and second memory dies are configured such that the transferring of the first and second data segments are performed at different phases of a single command signal cycle.

22. The semiconductor device of claim 18, wherein the first memory die comprises a first amplifier module disposed on a power bus corresponding to the first data segment and a second amplifier module disposed on the power bus corresponding to the second data segment, and The first amplifier module is not disposed adjacent to the second amplifier module on the power bus.

23. The semiconductor device of claim 18, wherein the semiconductor device comprises a plurality of memory dies stacked with the first memory die and the second memory die.

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