Memory, memory chip, and memory data access method

Abstract

The present invention provides a memory, a memory chip and a memory data access method. The memory of the present invention includes a plurality of memory chips. Each of the plurality of memory chips includes a first body group, a second body group, a read amplifier and a write amplifier. The first body group includes a plurality of first memory bodies. The second body group includes a plurality of second memory bodies. The read amplifier and the write amplifier are coupled to the first body group and the second body group, respectively. The read amplifier and the write amplifier are configured to independently access different body groups.

Description

Technical Field

[0001] The present invention generally relates to memory data access technology, and in particular, to a memory, a memory chip, and a memory data access method.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims the priority benefit of U.S. Provisional Application Serial No. 62 / 886,973 filed on August 15, 2019. The entire contents of the above-mentioned patent application are hereby incorporated by reference herein and become part of this specification. Background Art

[0004] In a general memory architecture, each of the multiple memory chips of the memory only includes a memory bank group having multiple memory banks, wherein each of the memory chips also includes a read amplifier and a write amplifier. That is, each of the memory chips must perform a read operation and a write operation at different times. In other words, if one of the memory chips has a read demand and a write demand at the same time, one of the memory chips must perform one of the read operation and the write operation, and then perform the other of the read operation and the write operation after completing the previous operation. Therefore, the memory data access efficiency of the memory of the general memory architecture is low, and memory data access conflicts are prone to occur. Therefore, regarding how to achieve good data access efficiency for the memory and reduce memory data access conflicts, the following provides solutions of several embodiments. Summary of the invention

[0005] The present invention is directed to a memory, a memory chip and a memory data access method, and can provide better memory data access efficiency.

[0006] The memory of the present invention comprises a plurality of memory chips. Each of the plurality of memory chips comprises a first bank, a second bank, a read amplifier and a write amplifier. The first bank comprises a plurality of first memory banks. The second bank comprises a plurality of second memory banks. The read amplifier and the write amplifier are respectively coupled to the first bank and the second bank, and are configured to independently access different bank groups.

[0007] In one embodiment of the present invention, the read amplifiers of each of the plurality of memory chips are coupled to the first input / output bus via the first sub-input / output bus. The bandwidth of the first input / output bus is greater than the bandwidth of the first sub-input / output bus, so that at least some of the read amplifiers of the plurality of memory chips transmit data via the first input / output bus at the same time.

[0008] In one embodiment of the present invention, the bandwidth of the first input / output bus is equal to the sum of the bandwidths of the first sub-input / output buses coupled to the read amplifiers of the plurality of memory chips.

[0009] In one embodiment of the present invention, the write amplifiers of each of the plurality of memory chips are coupled to the second input / output bus via the second sub-input / output bus. The bandwidth of the second input / output bus is greater than the bandwidth of the second sub-input / output bus, so that at least some of the write amplifiers of the plurality of memory chips receive data via the second input / output bus at the same time.

[0010] In one embodiment of the present invention, the bandwidth of the second input / output bus is equal to the sum of the bandwidths of the second sub-input / output buses coupled to the write amplifiers of the plurality of memory chips.

[0011] In one embodiment of the present invention, one of the memory chips receives a read start command to start a read operation, and a read amplifier of one of the memory chips reads first data from one of the first bank group and the second bank group during a read period of the read operation. One of the memory chips continuously receives a write start command during the read period to start a write operation, and a write amplifier of one of the memory chips writes second data to one of the first bank group and the second bank group during a write period of the write operation, wherein the read period and the write period partially overlap.

[0012] In one embodiment of the present invention, each of the plurality of first memory banks and the plurality of second memory banks is a memory array. The memory array includes a plurality of sub-memory arrays. The plurality of sub-memory arrays are coupled to a read amplifier and a write amplifier via a global data line. When the read amplifier reads the first data of one of the plurality of sub-memory arrays from the global data line according to a read start command during a read period, the write amplifier receives the second data in advance to start a write period. After the read amplifier completes receiving the first data from the global data line during the read period, the write amplifier continuously transmits the second data to the global data line for writing into the same or different sub-memory array during a write period.

[0013] In one embodiment of the present invention, each of the plurality of memory chips includes a selector. The selector is coupled to a read amplifier via a first internal input / output bus, coupled to a write amplifier via a second internal input / output bus, and coupled to a shared input / output bus via a sub-shared input / output bus. The selector is configured to select to access the first bank group or the second bank group via the read amplifier and the write amplifier.

[0014] In one embodiment of the present invention, the bandwidth of the sub-shared I / O bus is greater than or equal to the sum of the bandwidths of the first internal I / O bus and the second internal I / O bus, so that the read amplifier and the write amplifier can access different memory banks simultaneously.

[0015] In one embodiment of the present invention, the bandwidth of the shared I / O bus is equal to the sum of the bandwidths of the two sub-shared I / O buses.

[0016] The memory chip of the present invention comprises a first bank group, a second bank group, a read amplifier and a write amplifier. The first bank group comprises a plurality of first memory banks. The second bank group comprises a plurality of second memory banks. The read amplifier and the write amplifier are respectively coupled to the first bank group and the second bank group and are configured to independently access different bank groups.

[0017] The memory data access method is applicable to the memory chip of the present invention. The memory chip includes a first body group, a second body group, a read amplifier and a write amplifier. The read amplifier and the write amplifier are configured to independently access different body groups. The data access method includes the following steps. A read start command is received by the memory chip to start a read operation. The first data is read from one of the first body group and the second body group by the read amplifier during a read period of the read operation. During the read period, a write start command is continuously received by the memory chip to start a write operation. The second data is written to one of the first body group and the second body group by the write amplifier during a write period of the write operation, wherein the read period partially overlaps with the write period.

[0018] Based on the above, according to the memory, memory chip and memory data access method of the present invention, the memory chip of the memory can simultaneously perform read operations and write operations on different memory bank groups, so the memory chip and the memory can provide better memory data access efficiency.

[0019] In order to make the aforementioned features and advantages of the present invention more easily understood, embodiments of the present invention are described in detail below with accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present invention and together with the description serve to explain the principles of the present invention.

[0021] Figure 1 is a schematic architecture diagram of a memory according to an embodiment of the present invention.

[0022] Figure 2 is a schematic structural diagram of a memory chip according to an embodiment of the present invention.

[0023] Figure 3 FIG. 4 is a timing diagram of operations of accessing the same memory bank group according to an embodiment of the present invention.

[0024] Figure 4 FIG. 4 is a timing diagram of operations of accessing the same memory bank group according to another embodiment of the present invention.

[0025] Figure 5 FIG. 4 is a timing diagram of accessing different memory bank groups according to an embodiment of the present invention.

[0026] Figure 6 FIG. 4 is a timing diagram of operations of accessing different memory bank groups according to another embodiment of the present invention.

[0027] Figure 7 is a schematic architecture diagram of a memory according to another embodiment of the present invention.

[0028] Figure 8 FIG. 4 is a flow chart of a memory data access method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0029] For making content of the present invention easier to understand, list following embodiment as example of the present invention, and described example can be implemented accordingly completely.In addition, if possible, then in the drawings, the same or similar parts are represented by elements / assemblies / steps and implementation modes marked with the same identification numbers.

[0030] Figure 1 FIG. 1 is a schematic diagram of a memory according to an embodiment of the present invention. Figure 1, the memory 100 includes a memory chip 110, a memory chip 120, a memory chip 130 and a memory chip 140, and the plurality of memory chips 110, the memory chip 120, the memory chip 130 and the memory chip 140 are coupled to other circuits or modules outside the memory 100 via two input / output buses 101 and an input / output bus 102, such as a central processor unit (CPU), an image signal processor (ISP) core, a digital signal processor (DSP) core, a graphics processing unit (GPU) core, a convolutional neural network (CNN) accelerator or other modules with a large amount of data memory access requirements. In an embodiment of the present invention, the memory 100 may be a dynamic random-access memory (DRAM), but the present invention is not limited thereto. In an embodiment of the present invention, the memory chip 110, the memory chip 120, the memory chip 130, and the memory chip 140 include a first memory bank group 111, a first memory bank group 121, a first memory bank group 131, and a first memory bank group 141, and a second memory bank group 112, a second memory bank group 122, a second memory bank group 132, and a second memory bank group 142, wherein each of the memory chip 110, the memory chip 120, the memory chip 130, and the memory chip 140 includes a first memory bank group and a second memory bank group. In other words, a memory array of each of the memory chip 110, the memory chip 120, the memory chip 130, and the memory chip 140 can be divided to form two different memory bank groups, and each of the two different memory bank groups further includes one or more memory banks.

[0031] In an embodiment of the present invention, the first memory body group 111, the first memory body group 121, the first memory body group 131, the first memory body group 141 and the second memory body group 112, the second memory body group 122, the second memory body group 132 and the second memory body group 142 include the first memory body 111_1, the first memory body 112_1, the first memory body 121_1, the first memory body 122_1, the first memory body 131_1, the first memory body 132_1, the first memory body 141_1 and the first memory body 142_1 and the second memory body 111_2, the second memory body 112_2, the second memory body 121_2, the second memory body 122_2, the second memory body 131_2, the second memory body 132_2, the second memory body 141_2 and the second memory body 142_2, wherein one memory body group includes one first memory body and one second memory body. For example, the storage capacity of each of the memory chips 110, 120, 130, and 140 is 1 Gigabyte (Gb), the storage width of one memory bank is 128 kilobytes (Kb), and the storage depth of one memory bank is 2 kilobytes. In an embodiment of the present invention, the memory chips 110, 120, 130, and 140 further include read amplifiers 113, 123, 133, and 143, and write amplifiers 114, 124, 134, and 144, wherein each of the memory chips 110, 120, 130, and 140 includes one read amplifier and one write amplifier. Each of the read amplifier 113, the read amplifier 123, the read amplifier 133, and the read amplifier 143 is coupled to two memory bank groups in each of the memory chips 110, 120, 130, and 140, and each of the write amplifier 114, the write amplifier 124, the write amplifier 134, and the write amplifier 144 is also coupled to two memory bank groups in each of the memory chips 110, 120, 130, and 140. The read amplifier 113, the read amplifier 123, the read amplifier 133, and the read amplifier 143 are coupled to the input / output bus 101 via the sub-input / output bus 115, the sub-input / output bus 125, the sub-input / output bus 135, and the sub-input / output bus 145, respectively.Write amplifier 114, write amplifier 124, write amplifier 134, and write amplifier 144 are respectively coupled to input / output bus 102 via sub-input / output bus 116, sub-input / output bus 126, sub-input / output bus 136, and sub-input / output bus 146. However, the number of memory chips and the number of memory banks of memory 100 of the present invention are not limited thereto.

[0032] In an embodiment of the present invention, the bandwidth of the I / O bus 101 may be greater than or equal to the sum of the bandwidths of the sub-I / O bus 115, the sub-I / O bus 125, the sub-I / O bus 135, and the sub-I / O bus 145. For example, the bandwidth of the I / O bus 101 may be 2 kilobytes, and each of the bandwidths of the sub-I / O bus 115, the sub-I / O bus 125, the sub-I / O bus 135, and the sub-I / O bus 145 may be 512 bytes. Therefore, the memory chips 110, 120, 130, and 140 share the input / output bus 101, so that at least part of the read operations of the memory chips 110, 120, 130, and 140 can be performed simultaneously and independently, wherein at least part of the memory chips 110, 120, 130, and 140 can simultaneously transmit data via the sub-input / output bus 115, the sub-input / output bus 125, the sub-input / output bus 135, and the sub-input / output bus 145 of the input / output bus 101. In an embodiment of the present invention, the bandwidth of the input / output bus 102 can be greater than or equal to the sum of the bandwidths of the sub-input / output bus 116, the sub-input / output bus 126, the sub-input / output bus 136, and the sub-input / output bus 146. For example, the bandwidth of the input / output bus 102 may be 2 kilobytes, and each of the bandwidths of the sub-input / output bus 116, the sub-input / output bus 126, the sub-input / output bus 136, and the sub-input / output bus 146 may be 512 bytes. Therefore, the memory chip 110, the memory chip 120, the memory chip 130, and the memory chip 140 share the input / output bus 102, so that at least part of the write operations of the memory chip 110, the memory chip 120, the memory chip 130, and the memory chip 140 can be performed independently at the same time, wherein the memory chip 110, the memory chip 120, the memory chip 130, and the memory chip 140 can simultaneously receive data via the sub-input / output bus 116, the sub-input / output bus 126, the sub-input / output bus 136, and the sub-input / output bus 146 of the input / output bus 102.

[0033] In the embodiment of the present invention, the memory chip 110 is used as an example. Since the read amplifier 113 and the write amplifier 114 are coupled to the bank group 111 and the bank group 112 respectively, the read amplifier 113 and the write amplifier 114 can independently access different bank groups 111 and the bank group 112. That is, the read amplifier 113 can read data from one of the bank group 111 and the bank group 112, and the write amplifier 114 can simultaneously write data to the other of the bank group 111 and the bank group 112. In other words, the memory chip 110, the memory chip 120, the memory chip 130 and the memory chip 140 of the memory 100 can simultaneously perform at least one of a read operation and a write operation on different bank groups. The memory chip 110, the memory chip 120, the memory chip 130 and the memory chip 140 do not need to wait for each other's access operation, thereby saving the time of waiting for access. Therefore, the memory 100 of the present invention can provide fast and efficient memory data access efficiency to meet the memory access requirements of a large amount of data.

[0034] Figure 2 FIG. 1 is a schematic diagram of a memory chip according to an embodiment of the present invention. Figure 2, the memory chip 200 can be applied to the memory chips of various embodiments of the present invention. The memory chip 200 includes a plurality of sub-memory arrays 210_1 to 210_N, wherein N is a positive integer greater than 1, and the sub-memory arrays 210_1 to 210_N belong to a memory bank group. In addition, the sub-memory arrays 210_1 to 210_N may correspond to two memory banks, such as the first memory bank above and the second memory bank above. The memory chip 200 also includes a plurality of sense amplifiers 220_1 to 220_N corresponding to the sub-memory arrays 210_1 to 210_N. In the embodiment of the present invention, the read amplifier 207 and the write amplifier 208 of the memory chip 200 are respectively coupled to the global data line 203 via the global data line amplifier 205 and the global data line amplifier 206, and the global data line 203 is further coupled to the sense amplifiers 220_1 to 220_N. The read amplifier 207 and the write amplifier 208 are first input first output (FIFO) channels. The sense amplifiers 220_1 to 220_N access the sub-memory arrays 210_1 to 210_N, respectively, and transmit the data to the global data line 203 via a plurality of local data lines 204_1 to 204_N. In the embodiment of the present invention, the read amplifier 207 is further coupled to the input / output bus 201 to transmit the data read from any one of the sub-memory arrays 210_1 to 210_N to the outside, and the write amplifier 208 is further coupled to the input / output bus 202 to receive data from the outside for writing into any one of the sub-memory arrays 210_1 to 210_N.

[0035] Figure 3 FIG. 1 is a timing diagram of accessing the same memory bank group according to an embodiment of the present invention. Figure 2 and Figure 3 , Figure 3 The operation timing diagram of can be applied to the memory chip 200, and this embodiment uses the access sub-memory array 210_1 (the same memory bank group) as an example. In the embodiment of the present invention, as shown by Figure 3As shown in the time sequence CMD in FIG. 3 , the memory chip 200 receives a read start command (RD) during a period 311 to start a read operation, and then the memory chip 200 receives a write start command (WR) during a period 321 to start a write operation, wherein the read period of the read operation partially overlaps with the write period of the write operation. The read period is between time point t10 and time point t12. The write period is between time point t11 ​​and time point t13. In an embodiment of the present invention, after the memory chip 200 receives the read start command (RD) during the period 311 and starts the read operation, as shown by Figure 3 As shown in the time sequence SA in FIG. 1 , the sense amplifier 220_1 reads data (Q) from the sub-memory array 210_1 during the period 312. Subsequently, as shown by Figure 3 As shown in the time sequence LD in FIG. 1 , data (Q) is transmitted by the local data line 204_1 during the period 313. Subsequently, similarly, as shown by Figure 3 As shown in the time sequence GD in FIG. 3 , data (Q) is transmitted by the global data line 203 during the period 314. Finally, as shown by Figure 3 As shown in the time sequence I / O in FIG. 1 , the global data line amplifier 205 and the read amplifier 207 receive data (Q) from the global data line 203 and provide the data (Q) to the input / output bus 201 .

[0036] In an embodiment of the present invention, the memory chip 200 may receive a write start command (WR) during the period 321 (after the read start command (RD)). For example, when the sense amplifier 220_1 reads data (Q) from the sub-memory array 210_1, the memory chip 200 receives the write start command (WR). Figure 3 As shown in the time sequence I / O in FIG. 3 , the global data line amplifier 206 and the write amplifier 208 receive data (D) from the input / output bus 202 during period 322 and provide the data (D) to the global data line 203. Subsequently, as shown by Figure 3 As shown in the time sequence GD in FIG. 3 , data (D) is transmitted by the global data line 203 during the period 323. It should be noted that, as shown by Figure 3 As shown in the time sequence GD in FIG. 1 , since the global data line 203 first outputs data (D) and then inputs data (Q), the global data line 203 does not have a memory data access conflict. Figure 3 As shown in the time sequence LD in FIG. 1 , data (D) is transmitted by the local data line 204_1 during the period 324. Finally, as shown by Figure 3As shown in the time sequence SA in FIG. 3 , the sense amplifier 220_1 writes the data (D) into the sub-memory array 210_1 via the sub-memory array 210_1 during the period 325. Therefore, there is no memory data access conflict in the local data line 204_1 and the sense amplifier 220_1. In addition, since the read period of the read operation partially overlaps with the write period of the write operation, the memory chip 200 can provide fast and efficient data access efficiency. In addition, in other embodiments of the present invention, Figure 3 The operation timing diagram of FIG. 2 may also be applied to another access situation in which a read operation and a write operation are performed on different sub-memory arrays in the same memory bank group of the memory chip 200 .

[0037] Figure 4 FIG. 4 is a timing diagram of operations of accessing the same memory bank group according to another embodiment of the present invention. Figure 4 FIG. 1 is a timing diagram of accessing the same memory bank group according to an embodiment of the present invention. Figure 2 and Figure 4 , Figure 4 The operation timing diagram of can be applied to the memory chip 200, and this embodiment uses the access sub-memory array 210_1 (the same memory bank group) as an example. In the embodiment of the present invention, as shown by Figure 4 As shown in the time sequence CMD in FIG. 4 , the memory chip 200 receives a write start command (WR) during a period 411 to start a write operation, and then the memory chip 200 receives a read start command (RD) during a period 421 to start a read operation, wherein the read period of the read operation does not overlap with the write period of the write operation. The write period is between time point t20 and time point t21. The read period is between time point t22 and time point t23. In an embodiment of the present invention, after the memory chip 200 receives a write start command (WR) during period 411 and starts a write operation, as shown by Figure 4 As shown in the time sequence I / O in FIG. 4 , the global data line amplifier 206 and the write amplifier 208 receive data (D) from the input / output bus 202 during period 412 and provide the data (D) to the global data line 203. Subsequently, as shown by Figure 4 As shown in the time sequence GD in FIG. 4 , data (D) is transmitted by the global data line 203 during the period 413. Subsequently, similarly, as shown by Figure 4 As shown in the time sequence LD in FIG. 4 , data (D) is transmitted by the local data line 204_1 during the period 414. Finally, as shown by Figure 4 As shown in the time sequence SA in FIG. 4 , the sense amplifier 220_1 writes data (D) into the sub-memory array 210_1 during the period 415 .

[0038] In the embodiment of the present invention, to avoid data access conflicts between the sense amplifier 220_1, the local data line 204_1 and the global data line amplifier 205, if a write operation is performed before a read operation, the read operation should wait for the read operation to be completed before being performed. Figure 4 As shown in the time sequence SA in FIG. 4 , the sense amplifier 220_1 reads data (Q) from the sub-memory array 210_1 via the sub-memory array 210_1 during the period 422. Subsequently, as shown by Figure 4 As shown in the time sequence LD in FIG. 4 , data (Q) is transmitted by the local data line 204_1 during the period 423. Subsequently, similarly, as shown by Figure 4 As shown in the time sequence GD in FIG. 4 , data (Q) is transmitted by the global data line 203 during the period 424. Finally, as shown by Figure 4 As shown in the time sequence I / O in FIG. 4 , the global data line amplifier 205 and the read amplifier 207 receive data (Q) from the global data line 203 during the period 425 and provide the data (Q) to the input / output bus 201. In addition, in other embodiments of the present invention, Figure 4 The operation timing diagram of FIG. 2 may also be applied to another access situation in which a read operation and a write operation are performed on different sub-memory arrays in the same memory bank group of the memory chip 200 .

[0039] Figure 5 FIG. 1 is a timing diagram of access operations of different memory bank groups according to an embodiment of the present invention. Figure 2 and Figure 5 , Figure 5 The operation timing diagram of can be applied to the memory chip 200, and this embodiment uses different sub-memory arrays of accessing different memory bank groups as an example. In an embodiment of the present invention, Figure 2 The memory chip 200 may further include another memory bank group (not shown), and the read amplifier 207 and the write amplifier 208 may be additionally coupled to another sub-memory array of the other memory bank group.

[0040] In the embodiment of the present invention, the memory chip 200 accesses the sub-memory array 210_1 and another sub-memory array belonging to a different memory bank group. Figure 5As shown in the time sequence CMD in FIG. 5 , the memory chip 200 receives a read start command (RD0) during a period 511 to start a read operation, and then the memory chip 200 receives a write start command (WR1) during a period 521 to start a write operation, wherein the read period of the read operation partially overlaps with the write period of the write operation. The read period is between time point t30 and time point t32. The write period is between time point t31 and time point t33. In an embodiment of the present invention, after the memory chip 200 receives a read start command (RD) during period 511 and starts a read operation, as shown by Figure 5 As shown in the time sequence SA0 in FIG. 5 , the sense amplifier 220_1 reads data (Q0) from the sub-memory array 210_1 via the sub-memory array 210_1 during the period 512. Subsequently, as shown by Figure 5 As shown in the time sequence LD0 in FIG. 5 , data (Q0) is transmitted by the local data line 204_1 during the period 513. Subsequently, similarly, as shown by Figure 5 As shown in the time sequence GD0 in FIG. 5 , data (Q0) is transmitted by the global data line 203 during the period 514. Finally, as shown by Figure 5 As shown in the time sequence OUT in FIG. 1 , the global data line amplifier 205 and the read amplifier 207 receive data ( Q0 ) from the global data line 203 and provide the data ( Q0 ) to the input / output bus 201 .

[0041] In an embodiment of the present invention, the memory chip 200 may receive a write start command (WR1) during the period 521 (after the read start command (RD0)). For example, when the sense amplifier 220_1 reads data (Q0) from the sub-memory array 210_1, the memory chip 200 receives the write start command (WR1). Figure 5 As shown in the time sequence IN in FIG. 5 , another global data line amplifier and write amplifier 208 receives data (D1) from the input / output bus 202 during period 522 and provides the data (D1) to another global data line (not shown). Subsequently, as shown by Figure 5 As shown in the time sequence GD1 in FIG. 5 , data (D1) is transmitted by another global data line during period 523. Subsequently, similarly, as shown by Figure 5 As shown in the time sequence LD1 in FIG. 5 , data (D1) is transmitted by another local data line (not shown) during the period 524. Finally, as shown by Figure 5As shown in the time sequence SA1 in FIG. 3 , another sense amplifier (not shown) writes data (D1) into another sub-memory array belonging to a different memory bank group during period 325. It should be noted that since the read amplifier 207 and the write amplifier 208 are configured to access two different sub-memory arrays belonging to two different memory bank groups through different global data line amplifiers, different global data lines, different local data lines, and different sense amplifiers, the memory chip 200 does not have memory data access conflicts in this data access situation of the embodiment, and is able to provide fast and efficient data access efficiency.

[0042] Figure 6 FIG. 1 is a timing diagram of accessing different memory bank groups according to another embodiment of the present invention. Figure 2 and Figure 6 , Figure 6 The operation timing diagram of can be applied to the memory chip 200, and this embodiment uses different sub-memory arrays of accessing different memory bank groups as an example. In an embodiment of the present invention, Figure 2 The memory chip 200 may further include another memory bank group (not shown), and the read amplifier 207 and the write amplifier 208 may be additionally coupled to another sub-memory array of the other memory bank group.

[0043] In the embodiment of the present invention, the memory chip 200 accesses the sub-memory array 210_1 and another sub-memory array belonging to a different memory bank group. Figure 6 As shown in the time sequence CMD in FIG. 6 , the memory chip 200 receives a write start command (WR0) during a period 611 to start a write operation, and then the memory chip 200 receives a read start command (RD1) during a period 621 to start a read operation, wherein the read period of the read operation partially overlaps with the write period of the write operation. The write period is between time point t40 and time point t42. The read period is between time point t41 and time point t43. In an embodiment of the present invention, after the memory chip 200 receives a write start command (WR0) during period 611 and starts a write operation, as shown by Figure 6 As shown in the time sequence IN in FIG. 6 , the global data line amplifier 206 and the write amplifier 208 receive data (D0) from the input / output bus 202 during period 612 and provide the data (D0) to the global data line 203. Subsequently, as shown by Figure 6 As shown in the time sequence GD0 in FIG. 6 , data (D0) is transmitted by the global data line 203 during the period 613. Subsequently, similarly, as shown by Figure 6 As shown in the time sequence LD0 in FIG. 1 , data (D0) is transmitted by the local data line 204_1 during the period 614. Finally, as shown by Figure 6As shown in the time sequence SA0 in FIG. 6 , the sense amplifier 220_1 writes data ( D0 ) into the sub-memory array 210_1 via the sub-memory array 210_1 during the period 615 .

[0044] In an embodiment of the present invention, the memory chip 200 may receive a read start command (RD1) during the period 621 (after the write start command (WR0)). For example, when the global data line amplifier 206 and the write amplifier 208 receive data (D0) from the input / output bus 202, the memory chip 200 receives the read start command (RD1). Figure 6 As shown in the time sequence SA1 in FIG. 6 , another sense amplifier (not shown) reads data (Q1) from another sub-memory array belonging to a different memory bank group during period 622. Subsequently, as shown by Figure 6 As shown in the time sequence LD1 in FIG. 1 , data (Q1) is transmitted by another local data line (not shown) during period 623. Subsequently, similarly, as shown by Figure 6 As shown in the time sequence GD1 in FIG. 6 , data (Q1) is transmitted by another global data line (not shown) during period 624. Finally, as shown by Figure 6 As shown in the time sequence OUT in FIG. 6 , another global data line amplifier and read amplifier 207 receive data (Q1) from another global data line during period 625, and provide the data (Q1) to the input / output bus 201. It should be noted that since the read amplifier 207 and the write amplifier 208 are configured to access two different sub-memory arrays belonging to two different memory bank groups through different global data line amplifiers, different global data lines, different local data lines, and different sense amplifiers, the memory chip 200 does not have memory data access conflicts in this data access situation of the embodiment, and is able to provide fast and efficient data access efficiency.

[0045] Figure 77 is a schematic diagram of a memory according to another embodiment of the present invention. The memory 700 includes a memory chip 710, a memory chip 720, a memory chip 730, and a memory chip 740, and the plurality of memory chips 710, the memory chip 720, the memory chip 730, and the memory chip 740 are coupled to other circuits or modules outside the memory 700. In an embodiment of the present invention, the memory chip 710, the memory chip 720, the memory chip 730, and the memory chip 740 include a first memory bank group 711, a first memory bank group 721, a first memory bank group 731, and a first memory bank group 741, and a second memory bank group 712, a second memory bank group 722, a second memory bank group 732, and a second memory bank group 742, wherein each of the memory chip 710, the memory chip 720, the memory chip 730, and the memory chip 740 includes a first memory bank group and a second memory bank group. In an embodiment of the present invention, the first storage body group 711, the first storage body group 721, the first storage body group 731, the first storage body group 741 and the second storage body group 712, the second storage body group 722, the second storage body group 732 and the second storage body group 742 include the first storage body 711_1, the first storage body 712_1, the first storage body 721_1, the first storage body 722_1, the first storage body 731_1, the first storage body 732_1, the first storage body 741_1 and the first storage body 742_1 and the second storage body 711_2, the second storage body 712_2, the second storage body 721_2, the second storage body 722_2, the second storage body 731_2, the second storage body 732_2, the second storage body 741_2 and the second storage body 742_2, wherein one storage body group includes one first storage body and one second storage body. Memory chips 710, 720, 730, and 740 further include read amplifiers 713, 723, 733, and 743, and write amplifiers 714, 724, 734, and 744, wherein each of memory chips 710, 720, 730, and 740 includes one read amplifier and one write amplifier. Figure 1Compared with the above embodiments, the memory chip 710, the memory chip 720, the memory chip 730 and the memory chip 740 further include selectors 717, 727, 737 and 747, wherein each of the memory chip 710, the memory chip 720, the memory chip 730 and the memory chip 740 includes one selector. In the embodiment of the present invention, each of the read amplifier 713, the read amplifier 723, the read amplifier 733 and the read amplifier 743 is coupled to two respective memory bank groups in each of the memory chip 710, the memory chip 720, the memory chip 730 and the memory chip 740, and each of the write amplifier 714, the write amplifier 724, the write amplifier 734 and the write amplifier 744 is also coupled to two respective memory bank groups in each of the memory chip 710, the memory chip 720, the memory chip 730 and the memory chip 740.

[0046] In the embodiment of the present invention, the read amplifier 713, the read amplifier 723, the read amplifier 733 and the read amplifier 743 are respectively coupled to the selector 717, the selector 727, the selector 737 and the selector 747 via the internal input / output bus 715, the internal input / output bus 725, the internal input / output bus 735 and the internal input / output bus 745. The write amplifier 714, the write amplifier 724, the write amplifier 734 and the write amplifier 744 are respectively coupled to the selector 717, the selector 727, the selector 737 and the selector 747 via the internal input / output bus 716, the internal input / output bus 726, the internal input / output bus 736 and the internal input / output bus 746. The selectors 717, 727, 737, and 747 are coupled to the shared input / output bus 701 via the sub-shared input / output bus 718, the sub-shared input / output bus 728, the sub-shared input / output bus 738, and the sub-shared input / output bus 748. In an embodiment of the present invention, the selectors 717, 727, 737, and 747 are configured to respectively select to access the respective first bank group or the respective second bank group via the respective read amplifier or the respective write amplifier according to the respective memory address. However, the number of memory chips and the number of memory banks of the memory of the present invention are not limited thereto.

[0047] In an embodiment of the present invention, the bandwidth of the shared input / output bus 701 may be greater than or equal to the sum of the bandwidths of any two of the sub-shared input / output bus 718, the sub-shared input / output bus 728, the sub-shared input / output bus 738, and the sub-shared input / output bus 748. The sub-shared input / output bus 718 may be greater than or equal to the sum of the bandwidths of the internal input / output bus 715 and the internal input / output bus 716. The sub-shared input / output bus 728 may be greater than or equal to the sum of the bandwidths of the internal input / output bus 725 and the internal input / output bus 726. The sub-shared input / output bus 738 may be greater than or equal to the sum of the bandwidths of the internal input / output bus 735 and the internal input / output bus 736. The sub-shared input / output bus 748 may be greater than or equal to the sum of the bandwidths of the internal input / output bus 745 and the internal input / output bus 746. For example, the bandwidth of the shared I / O bus 701 may be 2 kilobytes, and each of the bandwidths of the sub-shared I / O bus 718, the sub-shared I / O bus 728, the sub-shared I / O bus 738, and the sub-shared I / O bus 748 may be 1 kilobyte. Each of the bandwidths of the internal I / O bus 715, the internal I / O bus 725, the internal I / O bus 735, and the internal I / O bus 745 and the internal I / O bus 716, the internal I / O bus 726, the internal I / O bus 736, and the internal I / O bus 746 may be 512 bytes. Therefore, at least one of the read operations or write operations of at least part of the memory chip 710, the memory chip 720, the memory chip 730 and the memory chip 740 can be executed independently and simultaneously, wherein the memory chip 710, the memory chip 720, the memory chip 730 and at least part of the memory chip 740 can simultaneously transmit data to the shared input / output bus 701 via the sub-shared input / output bus 718, the sub-shared input / output bus 728, the sub-shared input / output bus 738 and the sub-shared input / output bus 748, and simultaneously receive data from the shared input / output bus 701 via the sub-shared input / output bus 718, the sub-shared input / output bus 728, the sub-shared input / output bus 738 and the sub-shared input / output bus 748.

[0048] In the embodiment of the present invention, the memory chip 710 is taken as an example. Since the read amplifier 713 and the write amplifier 714 are coupled to the bank group 711 and the bank group 712, respectively, the read amplifier 713 and the write amplifier 714 can independently access different bank groups 711 and 712. That is, the read amplifier 713 can be selected by the selector 717 to read data from one of the bank group 711 and the bank group 712 according to the memory address, and at the same time, the write amplifier 714 can be selected by the selector 717 to write data to the other of the bank group 711 and the bank group 712 according to another memory address. In other words, the memory chips 710, 720, 730, and 740 of the memory 700 can perform at least one of a read operation and a write operation on different bank groups at the same time. The memory chips 710, 720, 730, and 740 do not need to wait for each other's access operations to save waiting time for access. Therefore, the memory 700 of the present invention can provide fast and efficient memory data access efficiency to meet the memory access requirements of a large amount of data, and further reduce the number of input / output buses coupled to the outside. It should be noted that Figures 3 to 6 The operation timing diagram of the memory chip 730 can also be applied to the memory chip 730, and corresponds to the operation timing diagram of the memory chip 730. Figures 3 to 6 Sufficient teaching and suggestions on the implementation scheme content and technical features of the operation timing diagram can be obtained from Figures 1 to 6 The relevant description of the embodiments of the present invention is obtained, and the details thereof are not repeated.

[0049] Figure 8 FIG. 1 is a flow chart of a memory data access method according to an embodiment of the present invention. Figure 1 and Figure 8 , Figure 8 The memory data access method can be applied to at least Figure 1 Any one of the memory chips 110, 120, 130 and 140 of the memory 100, and the following description uses the memory chip 110 as an example. In step S810, the memory chip 110 receives a read start command to start a read operation. In step S820, the read amplifier 113 reads the first data from one of the first body group 111 and the second body group 112 during a read period of the read operation. In step S830, the memory chip 110 continuously receives a write start command during the read period to start a write operation. In step S840, the write amplifier 114 writes the second data to one of the first body group 111 and the second body group 112 during a write period of the write operation, wherein the read period partially overlaps with the write period. Therefore, since the read period of the read operation partially overlaps with the write period of the write operation, Figure 8The memory data access method can manufacture any one of the memory chips 110 , 120 , 130 , and 140 in the memory 100 to provide fast and efficient data access efficiency.

[0050] In addition, you can Figures 1 to 7 The related description of the embodiment provides sufficient teaching and suggestions for other memory features, implementation details and technical features of the memory 100 of the embodiment, and the details thereof are not repeated.

[0051] In summary, in a memory, according to the memory chip and the memory data access method thereof of the present invention, the memory chip of the memory can simultaneously perform a read operation and a write operation on different memory bank groups. In addition, if a read operation is performed on the same memory bank group in advance before a write operation, the read period of the read operation and the write period of the write operation can partially overlap. Therefore, the memory chip and the memory of the present invention can provide better memory data access efficiency and avoid memory data access conflicts.

[0052] It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the invention. In view of the foregoing, the present invention is intended to cover modifications and variations, provided that the modifications and variations fall within the scope of the following claims and their equivalents.

[0053]

Explanation of symbols

[0054] 100, 700: Memory

[0055] 101, 102, 201, 202: Input / output bus

[0056] 110, 120, 130, 140, 200, 710, 720, 730, 740: memory chips

[0057] 111, 121, 131, 141, 711, 721, 731, 741: first memory bank group

[0058] 111_1, 112_1, 121_1, 122_1, 131_1, 132_1, 141_1, 142_1, 711_1, 712_1, 721_1, 722_1, 731_1, 732_1, 741_1, 742_1: first memory bank

[0059] 111_2, 112_2, 121_2, 122_2, 131_2, 132_2, 141_2, 142_2, 711_2, 712_2, 721_2, 722_2, 731_2, 732_2, 741_2, 742_2: second memory bank

[0060] 112, 122, 132, 142, 712, 722, 732, 742: second memory bank group

[0061] 113, 123, 133, 143, 207, 713, 723, 733, 743: Read amplifier

[0062] 114, 124, 134, 144, 208, 714, 724, 734, 744: Write amplifier

[0063] 115, 116, 125, 126, 135, 136, 145, 146: Sub-input / output bus

[0064] 203: Global data line

[0065] 204_1, 204_N: local data line

[0066] 205, 206: Global data line amplifier

[0067] 210_1, 210_N: sub-memory array

[0068] 220_1, 220_N: Sense amplifier

[0069] 311、312、313、314、315、321、322、323、324、325、411、412、413、414、415、421、422、423、424、425、511、512、513、514、515、521、522、523、524、525、611、612、613、614、615、621、622、623、624、625: Time

[0070] 701: Shared input / output bus

[0071] 715, 716, 725, 726, 735, 736, 745, 746: Internal input / output bus

[0072] 717, 727, 737, 747 selectors

[0073] 718, 728, 738, 748: Sub-shared input / output bus

[0074] CMD, SA, SA0, SA1, LD, LD0, LD1, GD, GD0, GD1, OUT, IN, I / O: Time sequence

[0075] S810, S820, S830, S840: Steps

[0076] t10, t11, t12, t13, t20, t21, t22, t23, t30, t31, t32, t33, t40, t41, t42, t43: time points

Claims

1. A memory comprising a plurality of memory chips, wherein each of the plurality of memory chips comprises: A first bank group, comprising a plurality of first storage banks; A second bank group, including a plurality of second storage banks; as well as a read amplifier and a write amplifier, coupled to the first bank group via a first global data line and coupled to the second bank group via a second global data line, and configured to independently select access to different bank groups, wherein the first global data line is different from the second global data line, and any one of the read amplifier and the write amplifier is configured to select any one of the first bank group and the second bank group; Among them, the read period and the write period of the memory chip partially overlap, when the first body group is read and written at the same time, the first global data line does not input and output data at the same time, when the second body group is read and written at the same time, the second global data line does not input and output data at the same time, and when the first body group is read and the second body group is written at the same time, data is output to the read amplifier through the first global data line and data is input from the write amplifier through the second global data line at the same time.

2. A memory as described in claim 1, wherein the read amplifier of each of the multiple memory chips is coupled to a first input / output bus via a first sub-input / output bus, and the bandwidth of the first input / output bus is greater than the bandwidth of the first sub-input / output bus, so that at least part of the read amplifiers of the multiple memory chips transmit data via the first input / output bus at the same time.

3. The memory as claimed in claim 2, wherein the bandwidth of the first input / output bus is equal to the sum of the bandwidths of the first sub-input / output buses coupling the read amplifiers of the plurality of memory chips.

4. The memory as claimed in claim 1, wherein the write amplifier of each of the multiple memory chips is coupled to a second input / output bus via a second sub-input / output bus, and a bandwidth of the second input / output bus is greater than a bandwidth of the second sub-input / output bus, so that at least part of the write amplifiers of the multiple memory chips receive data simultaneously via the second input / output bus.

5. The memory as claimed in claim 4, wherein the bandwidth of the second input / output bus is equal to the sum of the bandwidths of the second sub-input / output buses coupling the write amplifiers of the plurality of memory chips.

6. The memory of claim 1 , wherein one of the memory chips receives a read start command to start a read operation, and the sense amplifier of one of the memory chips reads first data from one of the first bank group and the second bank group during a read period of the read operation, One of the memory chips continuously receives a write start command during the read period to start a write operation, and the write amplifier of one of the memory chips writes second data to one of the first body group and the second body group during the write period of the write operation, wherein the read period partially overlaps with the write period.

7. The memory of claim 6, wherein each of the plurality of first memory banks is a memory array, and the memory array comprises: A plurality of sub-memory arrays are coupled to the read amplifier and the write amplifier via the first global data line, wherein when the read amplifier reads the first data of one of the plurality of sub-memory arrays from the first global data line according to the read start command during the read period, the write amplifier receives the second data in advance to start the write period, After the read amplifier completes receiving the first data from the first global data line during the read period, the write amplifier continuously transmits the second data to the first global data line for writing into the same or different sub-memory array during the write period.

8. The memory of claim 6, wherein each of the plurality of second memory banks is a memory array, and the memory array comprises: A plurality of sub-memory arrays are coupled to the read amplifier and the write amplifier via the second global data line, wherein when the read amplifier reads the first data of one of the plurality of sub-memory arrays from the second global data line according to the read start command during the read period, the write amplifier receives the second data in advance to start the write period, After the read amplifier completes receiving the first data from the second global data line during the read period, the write amplifier continuously transmits the second data to the second global data line for writing into the same or different sub-memory array during the write period.

9. The memory of claim 1, wherein each of the plurality of memory chips comprises: A selector is coupled to the read amplifier via a first internal input / output bus, coupled to the write amplifier via a second internal input / output bus, coupled to a shared input / output bus via a sub-shared input / output bus, and is configured to select to access the first body group or the second body group via the read amplifier and the write amplifier.

10. The memory of claim 9, wherein a bandwidth of the sub-shared I / O bus is greater than or equal to a sum of bandwidths of the first internal I / O bus and the second internal I / O bus, so that the read amplifier and the write amplifier access different memory banks simultaneously.

11. The memory of claim 9, wherein a bandwidth of the shared input / output bus is equal to a sum of bandwidths of two sub-shared input / output buses.

12. A memory chip, comprising: A first bank group, comprising a plurality of first storage banks; A second bank group, including a plurality of second storage banks; as well as a read amplifier and a write amplifier, coupled to the first bank group via a first global data line and coupled to the second bank group via a second global data line, and configured to independently select access to different bank groups, wherein the first global data line is different from the second global data line, and any one of the read amplifier and the write amplifier is configured to select any one of the first bank group and the second bank group; Among them, the read period and the write period of each of the multiple memory chips partially overlap, and when the first body group is read and written at the same time, the first global data line does not input and output data at the same time, and when the second body group is read and written at the same time, the second global data line does not input and output data at the same time, and when the first body group is read and the second body group is written at the same time, data is output to the read amplifier through the first global data line and data is input from the write amplifier through the second global data line at the same time.

13. The memory chip of claim 12 , wherein the memory chip receives a read start command to start a read operation, and the sense amplifier reads first data from one of the first bank group and the second bank group during a read period of the read operation, The memory chip continuously receives a write start command during the read period to start a write operation, and the write amplifier of the memory chip writes second data to one of the first body group and the second body group during the write period of the write operation, wherein the read period partially overlaps with the write period.

14. The memory chip of claim 13, wherein each of the plurality of first memory banks is a memory array, and the memory array comprises: A plurality of sub-memory arrays are coupled to the read amplifier and the write amplifier via the first global data line, wherein when the read amplifier reads the first data of one of the plurality of sub-memory arrays from the first global data line according to the read start command during the read period, the write amplifier receives the second data in advance to start the write period, After the read amplifier completes receiving the first data from the first global data line during the read period, the write amplifier continuously transmits the second data to the first global data line for writing into the same or different sub-memory array during the write period.

15. The memory chip of claim 13, wherein each of the plurality of second memory banks is a memory array, and the memory array comprises: A plurality of sub-memory arrays are coupled to the read amplifier and the write amplifier via the second global data line, wherein when the read amplifier reads the first data of one of the plurality of sub-memory arrays from the second global data line according to the read start command during the read period, the write amplifier receives the second data in advance to start the write period, After the read amplifier completes receiving the first data from the second global data line during the read period, the write amplifier continuously transmits the second data to the second global data line for writing into the same or different sub-memory array during the write period.

16. The memory chip according to claim 12, further comprising: A selector is coupled to the read amplifier via a first internal input / output bus, coupled to the write amplifier via a second internal input / output bus, coupled to a shared input / output bus via a sub-shared input / output bus, and is configured to select to access the first body group or the second body group via the read amplifier and the write amplifier.

17. The memory chip of claim 16, wherein a bandwidth of the sub-shared I / O bus is greater than or equal to a sum of bandwidths of the first internal I / O bus and the second internal I / O bus, so that the read amplifier and the write amplifier access different memory banks simultaneously.

18. The memory chip of claim 16, wherein a bandwidth of the shared input / output bus is equal to a sum of bandwidths of two sub-shared input / output buses.

19. A memory data access method applicable to a memory chip, wherein the memory chip comprises a first bank group, a second bank group, a read amplifier and a write amplifier, and the read amplifier and the write amplifier are coupled to the first bank group via a first global data line, coupled to the second bank group via a second global data line, and are configured to independently select access to different bank groups, wherein: The first global data line is different from the second global data line, and any one of the read amplifier and the write amplifier is configured to select any one of the first bank group and the second bank group, and the data access method includes: Receiving a read start command by the memory chip to start a read operation; reading first data from one of the first bank group and the second bank group by the read amplifier during a read period of the read operation; The memory chip continuously receives a write start command during the read period to start a write operation; and During a write period of the write operation, second data is written by the write amplifier to one of the first body group and the second body group, wherein the read period partially overlaps with the write period, wherein, in the case of simultaneous read and write operations on the first body group, the first global data line does not input and output data at the same time, and in the case of simultaneous read and write operations on the second body group, the second global data line does not input and output data at the same time, and in the case of simultaneous read operations on the first body group and write operations on the second body group, data is output to the read amplifier through the first global data line and data is simultaneously input from the write amplifier through the second global data line.

20. The memory data access method for a memory chip as claimed in claim 19, wherein each of the plurality of first memory banks included in the first bank group is a memory array, and the memory array includes a plurality of sub-memory arrays coupled to the read amplifier and the write amplifier via the first global data line, wherein when the read amplifier reads the first data of one of the plurality of sub-memory arrays from the first global data line according to the read start command during the read period, the write amplifier receives the second data in advance to start the write period, After the read amplifier completes receiving the first data from the first global data line during the read period, the write amplifier continuously transmits the second data to the first global data line for writing into the same or different sub-memory array during the write period.

21. The memory data access method for a memory chip as claimed in claim 19, wherein each of the plurality of second memory banks included in the second bank group is a memory array, and the memory array includes a plurality of sub-memory arrays coupled to the read amplifier and the write amplifier via the second global data line, wherein when the read amplifier reads the first data of one of the plurality of sub-memory arrays from the second global data line according to the read start command during the read period, the write amplifier receives the second data in advance to start the write period, After the read amplifier completes receiving the first data from the second global data line during the read period, the write amplifier continuously transmits the second data to the second global data line for writing into the same or different sub-memory array during the write period.

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