Semiconductor package and method of forming the same

Abstract

A semiconductor package and a method of forming the same, wherein the semiconductor package is manufactured by attaching a first component to a second component. The first component is assembled by forming a first redistribution structure over a substrate. A via hole is then formed over the first redistribution structure, and a chip is attached to the first redistribution structure with the active side facing down. The second component includes a second redistribution structure, which is then attached to the via hole. A molding compound is deposited between the first redistribution structure and the second redistribution structure and also surrounds the side edges of the second component.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor package. More specifically, embodiments of the present invention relate to a semiconductor package having a molding compound. Background Art

[0002] Due to the continuous improvement of the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.), the semiconductor industry has experienced rapid growth. In most cases, the improvement of integration density has been obtained from the repeated reduction of the minimum feature size, which allows more components to be integrated into a given area. Because of the growing demand for shrinking electronic devices, there has emerged a need for smaller and more innovative semiconductor chip packaging technologies. One example of such a packaging system is the Package-on-Package (PoP) technology. In a Package-on-Package device, a top semiconductor package is stacked on top of a bottom semiconductor package to provide high integration and component density. The Package-on-Package technology generally enables the production of semiconductor devices with enhanced functionality and small footprints on a printed circuit board (PCB). Summary of the Invention

[0003] Embodiments of the present invention provide a method for forming a semiconductor package, including forming a first component, and forming the first component includes: forming a first redistribution structure on a first substrate; forming a via hole on the first redistribution structure; attaching a first chip to the first redistribution structure, with the active side of the first chip facing and electrically coupled to the first redistribution structure. The method for forming a semiconductor package further includes attaching a second component to the via hole, the second component including a second redistribution structure attached to a second substrate, and after attaching the second component, depositing a molding compound between the first redistribution structure and the second redistribution structure, with a portion of the molding compound surrounding the side edges of the second redistribution structure.

[0004] Embodiments of the present invention also provide a semiconductor package, including a first component, a second component, and a molding compound. The first component includes a first redistribution structure, a via hole, and a first chip. The via hole is disposed on the first redistribution structure. The first chip is attached to the first redistribution structure, and the active side of the first chip faces the first redistribution structure. The second component includes a second redistribution structure, a connector, and a second chip. The connector couples the via hole to the second redistribution structure. The second chip is attached to a first side of the second redistribution structure, and the active side of the second chip faces the second redistribution structure. The molding compound is disposed between the first redistribution structure and the second redistribution structure.

[0005] Embodiments of the present invention further provide a semiconductor package, including a first redistribution structure, a second redistribution structure, a first chip, a second chip, a packaging adhesive, and a via hole. The first redistribution structure has a first width. The second redistribution structure is disposed on the first redistribution structure and includes a conductive via hole extending from a first metal trace to a second metal trace. The first metal trace is disposed along a first side of the second redistribution structure, and the second metal trace is disposed along a second side of the second redistribution structure. The second redistribution structure has a second width, and the first width is greater than the second width. The first chip is attached to the first redistribution structure, and a first active side of the first chip faces and is electrically coupled to the first redistribution structure. The second chip is attached to the second redistribution structure, and a second active side of the second chip faces and is electrically coupled to the second redistribution structure. The packaging adhesive is directly inserted between the first redistribution structure and the second redistribution structure. The via hole extends through the packaging adhesive, and the via hole electrically couples the first redistribution structure to the second redistribution structure. Description of the Drawings

[0006] Figure 1 is a cross-sectional view of an integrated circuit chip according to some embodiments.

[0007] Figures 2A to 2G is a cross-sectional view of an intermediate step during the process of forming a package component according to some embodiments.

[0008] Figures 3A to 3H is a cross-sectional view of an intermediate step during the process of forming a package component according to some embodiments.

[0009] Figures 4A to 4H is a cross-sectional view of an intermediate step during the process of forming a package component according to some embodiments.

[0010] Figures 5A to 5H is a cross-sectional view of an intermediate step during the process of forming a package component according to some embodiments.

[0011] Figures 6A to 6H is a cross-sectional view of an intermediate step during the process of forming a package component according to some embodiments.

[0012] Description of the Reference Numerals:

[0013] 50: Integrated Circuit Chip / First Integrated Circuit Chip / Second Integrated Circuit Chip / Third Integrated Circuit Chip / Fourth Integrated Circuit Chip

[0014] 52: Semiconductor Substrate

[0015] 54: Device

[0016] 56: Interlayer Dielectric

[0017] 58: Conductive plug

[0018] 60: Interconnection structure

[0019] 62: Pad

[0020] 64: Passivation film

[0021] 66: Chip connector

[0022] 68: Dielectric layer

[0023] 70: Adhesive layer

[0024] 100: First element / First packaged element

[0025] 102: First carrier substrate

[0026] 104: Release layer

[0027] 106: First side redistribution structure / Back side redistribution structure

[0028] 110: Dielectric layer

[0029] 112: Metallization pattern

[0030] 114: Dielectric layer

[0031] 116: Metallization pattern

[0032] 118: Dielectric layer

[0033] 120: Metallization pattern

[0034] 122: Dielectric layer

[0035] 124: Opening

[0036] 126: Through hole

[0037] 128: Bonding pad

[0038] 130: Solder joint

[0039] 132: Underfill material

[0040] 200: Second element / Second packaged element / Packaged element

[0041] 202: Second carrier substrate

[0042] 204: First metal film / Metal film

[0043] 206: Second side redistribution structure

[0044] 208: Photoresist

[0045] 210: First metal trace

[0046] 212: Dielectric layer

[0047] 214: Via opening

[0048] 216: Line opening

[0049] 218: Conductive via

[0050] 220: Second metal trace

[0051] 222: Solder mask material

[0052] 224: Opening

[0053] 226: Connector

[0054] 228: Opening

[0055] 310: Encapsulant

[0056] 320: Passivation layer

[0057] 400: Package

[0058] 401: Illustration

[0059] 402: Illustration

[0060] 404: Scored area

[0061] 406: Temporary substrate

[0062] 410: Conductive connector

[0063] 501: First component

[0064] 502: Second component

[0065] 503: Substrate

[0066] 504: Package

[0067] 510: Dielectric layer

[0068] 511: Additional device

[0069] 528: Bonding pad

[0070] 530: Solder joint

[0071] 532: Underfill material

[0072] 550: Other semiconductor device / Other device / Additional device

[0073] 601: First component

[0074] 602: Second component

[0075] 604: Package

[0076] 610: External Connector

[0077] 628: Bonding Pad

[0078] 630: Solder Joint

[0079] 632: Underfill Material

[0080] 650: Other Semiconductor Device / Additional Device

[0081] H C : Height of Connector

[0082] H IC1 : Height of Integrated Circuit Chip / First Integrated Circuit Chip

[0083] H IC2 : Height of Second Integrated Circuit Chip

[0084] H TV : Height of Through-Hole

[0085] T 1 : Thickness of First Sidewall Wiring Structure

[0086] T 2 : Thickness of Second Sidewall Wiring Structure

[0087] T 3 : Thickness between First Sidewall Wiring Structure and Second Sidewall Wiring Structure

[0088] W 1 : Width of First Sidewall Wiring Structure

[0089] W 2 : Width of Second Sidewall Wiring Structure

[0090] θ: Angle Detailed Description of the Invention

[0091] The following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. The following disclosure describes specific examples of various components and their arrangements to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if the present disclosure describes a first feature formed on or above a second feature, it means that it may include embodiments in which the first feature and the second feature are in direct contact, and may also include embodiments in which additional features are formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. Additionally, the same reference symbols and / or labels may be reused in different examples of the following disclosure. These repetitions are for the purpose of simplicity and clarity, and are not intended to limit a specific relationship between the different embodiments and / or structures described.

[0092] Furthermore, for the convenience of describing the relationship between an element or feature in the drawings and another element or feature(s), spatial relative terms may be used, such as "below", "beneath", "under", "above", "on" and similar terms. In addition to the orientation shown in the drawings, the spatial relative terms cover different orientations during the use or operation of the device. The device may also be positioned otherwise (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein may be interpreted correspondingly.

[0093] According to some embodiments, one or more integrated circuit chips or other devices are attached to a plurality of dual-sided redistribution structures and embedded in a package to form a system-in-package (SiP) structure. One of the redistribution structures may have a fan-out design, and other redistribution structures may be formed as carrier-type substrates. The placement of the integrated circuit chips and the arrangement of the redistribution structures provide diversity throughout the package. In addition, the design of the package and the redistribution structures, as well as the design methodology, enable a thinner system-level package structure to have better strength and reduced overall package warpage.

[0094] Figure 1FIG. 0 is a cross-sectional view showing an integrated circuit chip 50 according to some embodiments. The integrated circuit chip 50 will be subsequently packaged in a process to form an integrated circuit package. The integrated circuit chip 50 can be a logic chip (such as a central processing unit (CPU), a graphics processing unit (GPU), a system-on-a-chip (SoC), an application processor (AP), a microcontroller, etc.), a memory chip (such as a dynamic random access memory (DRAM) chip, a static random access memory (SRAM) chip, etc.), a power management chip (such as a power management integrated circuit (PMIC) chip), a radio frequency (RF) chip, a sensor chip, a micro-electro-mechanical-system (MEMS) chip, a signal processing chip (such as a digital signal processing (DSP) chip), a front-end chip (such as an analog front-end (AFE) chip), the like, or a combination thereof.

[0095] The integrated circuit chip 50 can be formed in a wafer, which can include multiple distinct device regions that are singulated in subsequent steps to form multiple integrated circuit chips. The integrated circuit chip 50 can be processed according to an applicable manufacturing process to form a crystalline circuit. For example, the integrated circuit chip 50 includes a semiconductor substrate 52, such as the active layer of a silicon, doped or undoped, or semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 52 can include other semiconductor materials, such as germanium, compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), alloy semiconductors (including silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP)), or a combination thereof. Other substrates, such as multi-layer or gradient substrates, can also be used. The semiconductor substrate 52 has an active surface (such as Figure 1a surface facing upward (e.g., Figure 1 a surface facing downward), the active surface is sometimes referred to as a front side, and the non-active surface is sometimes referred to as a back side.

[0096] A plurality of devices (one shown in Figure 1 FIG.) 54 may be formed on the front surface of the semiconductor substrate 52. The devices 54 may be active devices (e.g., transistors, diodes, etc.), capacitors, resistors, etc. An inter-layer dielectric (ILD) 56 is on the front surface of the semiconductor substrate 52. The inter-layer dielectric 56 surrounds the devices 54 and may cover the devices 54. The inter-layer dielectric 56 may include one or more dielectric layers, and materials for forming the dielectric layers such as Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG), Boron-Doped Phospho-Silicate Glass (BPSG), undoped Silicate Glass (USG), or the like.

[0097] The conductive plug 58 extends through the inter-layer dielectric 56 and is physically coupled to the device 54. For example, when the device 54 is a transistor, the conductive plug 58 may be coupled to the gate and source / drain regions of the transistor. The conductive plug 58 may be formed of tungsten, cobalt, nickel, copper, silver, gold, aluminum, the like, or a combination thereof. An interconnect structure 60 is on the inter-layer dielectric 56 and the conductive plug 58. The interconnect structure 60 and the device 54 are interconnected to form an integrated circuit. For example, the interconnect structure 60 may be formed of a metallization pattern in the dielectric layer of the inter-layer dielectric 56. The metallization pattern includes metal lines and vias formed of one or more low-k dielectric layers. The metallization pattern of the interconnect structure 60 is electrically coupled to the device 54 through the conductive plug 58.

[0098] The integrated circuit chip 50 further includes a plurality of pads 62 to establish external connections, such as aluminum pads. The pads 62 are located on the active side of the integrated circuit chip 50, such as within and / or on the interconnect structure 60. One or more passivation films 64 are located on the integrated circuit chip 50, such as on portions of the interconnect structure 60 and the pads 62. Openings extend through the passivation film 64 to the pads 62. Chip connectors 66 extend through the openings in the passivation film 64 and are physically and electrically coupled to the respective pads 62. The aforementioned chip connectors 66 are, for example, conductive pillars (formed of a metal such as copper, for example). In some embodiments, the chip connectors 66 include an under-bump metallization (UBM) structure. Although Figure 1 only four chip connectors 66 are shown, there may be more, which will be shown in subsequent drawings of the integrated circuit chip 50. For example, the chip connectors 66 (such as copper pillars) can be formed by electroplating or a similar method. The chip connectors 66 electrically couple the respective integrated circuits of the integrated circuit chip 50.

[0099] Optionally, solder regions (such as solder balls or solder bumps, not shown) can be provided on the pads 62 and / or the chip connectors 66. The solder regions can be used to perform a chip probe (CP) test on the integrated circuit chip 50. The chip probe test can be performed on the integrated circuit chip 50 to confirm whether the integrated circuit chip 50 is a known good die (KGD). Thus, only the integrated circuit chips 50 that are known good dies will undergo subsequent processes for packaging, and the integrated circuit chips 50 that fail the chip probe test will not be packaged. After the test, the solder regions can be removed in subsequent process steps.

[0100] A dielectric layer 68 may (or may not) be provided on the active side of the integrated circuit chip 50, such as on the passivation film 64 and the chip connectors 66. The dielectric layer 68 laterally encapsulates the chip connectors 66, and the dielectric layer 68 laterally abuts the integrated circuit chip 50 after singulation. Initially, the dielectric layer 68 may bury the chip connectors 66, such that the topmost surface of the dielectric layer 68 is above the topmost surface of the chip connectors 66. In some embodiments where the solder regions are provided on the chip connectors 66, the dielectric layer may also bury the solder regions. Alternatively, the solder regions can be removed before forming the dielectric layer 68.

[0101] The dielectric layer 68 can be a polymer (such as PBO, polyimide, BCB, or the like), a nitride (such as silicon nitride or the like), an oxide (such as silicon oxide, PSG, BSG, BPSG, or the like), the like, or a combination thereof. For example, the dielectric layer 68 can be formed by spin coating, lamination, chemical vapor deposition (CVD), or the like. In some embodiments, the chip connector 66 is exposed through the dielectric layer 68 during the formation of the integrated circuit chip 50. In some embodiments, the chip connector 66 remains buried and is exposed during a subsequent process of encapsulating the integrated circuit chip 50. Exposing the chip connector 66 can remove any solder regions present on the chip connector 66.

[0102] An adhesive layer 70 can be applied to the back side of the integrated circuit chip 50 at certain points in the process. In some embodiments, the adhesive layer is formed on top of the back side of the integrated circuit chip 50 before attaching the integrated circuit chip to a semiconductor package component (to be detailed below).

[0103] In some embodiments, the integrated circuit chip 50 is a stacked device including a plurality of semiconductor substrates 52. For example, the integrated circuit chip 50 can be a memory device, such as a hybrid memory cube (HMC) module, a high bandwidth memory (HBM) module, or the like including a plurality of memory chips. In these embodiments, the integrated circuit chip 50 includes a plurality of semiconductor substrates 52 interconnected by through-substrate vias (TSVs). Each semiconductor substrate 52 may (or may not) have an interconnect structure 60.

[0104] The formation of a semiconductor package including the integrated circuit chip 50 will be described below according to some embodiments. Figures 2A to 2G Various intermediate steps in the formation of a first element are described. As will be discussed, the first element can include a fan-out type redistribution structure with the integrated circuit chip 50 attached. Figures 3A to 3H The formation of a second element is described, where the second element can be attached to the first element Figures 2A to 2G described above. As will be discussed, the second element can include a substrate type redistribution structure. Although not specifically described, the second element can also include a fan-out type redistribution structure, and this fan-out type redistribution structure is similar to that of the first element. Figures 4A to 4H The attachment of the second element to the first element and further processes to form a semiconductor package are described according to some embodiments.

[0105] First, please refer to Figure 2A , in the formation of a first component 100, a first carrier substrate 102 is provided, and a release layer 104 is formed on the first carrier substrate 102. The first carrier substrate 102 can be a glass carrier substrate, a ceramic carrier substrate, or the like. The first carrier substrate 102 can be a wafer, so that a plurality of packages can be formed on the first carrier substrate 102 at the same time, and each package can contain one or more chips. The release layer 104 can be formed of a polymer-based material, which can be removed from the overlying structure together with the first carrier substrate 102, and the overlying structure is formed in a subsequent step. In some embodiments, the release layer 104 is an epoxy-based material, which loses its adhesiveness when heated, such as a light-to-heat-conversion (LTHC) anti-stick coating. In some embodiments, the release layer 104 can be an ultraviolet (UV) glue, which loses its adhesiveness when exposed to ultraviolet light. The release layer 104 can be dispensed and cured in a liquid form, can be a laminated film laminated on the first carrier substrate 102, or can be the like.

[0106] In Figures 2B to 2E , a first side redistribution structure 106 can be formed on the release layer 104. In the illustrated embodiment, the first side redistribution structure 106 includes one or more dielectric layers and metallization patterns (sometimes referred to as redistribution layers or redistribution lines). The first side redistribution structure 106 will be described as having three layers of metallization patterns. More or fewer dielectric layers and metallization patterns can also be formed in the first side redistribution structure 106. If fewer dielectric layers and metallization patterns are to be formed, the steps and processes discussed below can be omitted. If more dielectric layers and metallization patterns are to be formed, the steps and processes discussed below can be repeated.

[0107] Now, please refer to Figure 2B, a dielectric layer 110 is formed on the release layer 104. The bottom surface of the dielectric layer 110 can contact the top surface of the release layer 104. In some embodiments, the dielectric layer 110 can be formed of a photo-sensitive material, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like, which can be patterned using a photomask. In some embodiments, the dielectric layer 110 is formed of a nitride, such as silicon nitride, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like. The dielectric layer 110 can be formed by spin coating, lamination, chemical vapor deposition, a similar manner, or a combination thereof. The dielectric layer 110 is patterned to form an opening that exposes a portion of the release layer 104. The patterning can be performed by an acceptable process, such as by exposing the dielectric layer 110 to light, developing, and curing when the dielectric layer 110 is a photosensitive material, or by etching, for example, using anisotropic etching.

[0108] A metallization pattern 112 is then formed on the dielectric layer 110. The metallization pattern 112 includes line portions (also referred to as wires) that are located on and extend along a major surface of the dielectric layer 110. The metallization pattern 112 further includes via portions (also referred to as conductive vias) that extend through the dielectric layer 110 to physically and electrically couple the first-level rewiring structure 106 to an external connector, which may be formed in a subsequent step. As an example of forming the metallization pattern 112, a seed layer is formed on the dielectric layer 110 and in openings that extend through the dielectric layer 110. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer including multiple sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer, with the copper layer being on top of the titanium layer. For example, the seed layer may be formed by physical vapor deposition (PVD) or a similar method. A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or a similar method and may be exposed to light to be patterned. The pattern of the photoresist corresponds to the metallization pattern 112. The patterning will form openings through the photoresist to expose the seed layer. A conductive material is then formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by electroplating (such as electroplating or electroless plating) or a similar method. The conductive material may include metals such as copper, titanium, tungsten, aluminum, or the like. Portions of the photoresist and the seed layer where the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using oxygen plasma or a similar method. Once the photoresist is removed, the exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as wet etching or dry etching. The remaining portions of the conductive material and the underlying portions of the seed layer form the metallization pattern 112.

[0109] In Figure 2C a dielectric layer 114 is deposited on the metallization pattern 112 and the dielectric layer 110. The dielectric layer 114 may be formed and patterned in a manner similar to the dielectric layer 110.

[0110] Next, a metallization pattern 116 is formed. The metallization line 116 includes a line portion that is located on and extends along a major surface of the dielectric layer 114. The metallization pattern 116 also includes via portions that extend through the dielectric layer 114 to physically and electrically couple the metallization pattern 112. The metallization pattern 116 can be formed in a similar manner and with similar materials as the metallization pattern 112. In some embodiments, the metallization pattern 116 has different dimensions from the metallization pattern 112. For example, the wires and / or vias of the metallization pattern 112 can be wider or thicker than the wires and / or vias of the metallization pattern 116. Furthermore, the metallization pattern 112 can be formed with a greater pitch compared to the metallization pattern 116.

[0111] In Figure 2D , a dielectric layer 118 is deposited on the metallization pattern 116 and the dielectric layer 114. The dielectric layer 118 can be formed and patterned in a similar manner as the dielectric layer 110 and / or the dielectric layer 114.

[0112] Next, a metallization pattern 120 is formed. The metallization pattern 120 includes a line portion that is located on and extends along a major surface of the dielectric layer 118. The metallization pattern 120 also includes via portions that extend through the dielectric layer 118 to physically and electrically couple the metallization pattern 116. The metallization pattern 120 can be formed in a similar manner and with similar materials as the metallization pattern 112 and / or the metallization pattern 116.

[0113] In Figure 2E , a dielectric layer 122 is deposited on the metallization pattern 120 and the dielectric layer 118. The dielectric layer 122 can be formed and patterned in a similar manner as the dielectric layer 110 to form an opening 124.

[0114] The dielectric layer 110 and the metallization pattern 112 are respectively the bottom dielectric layer and the metallization pattern of the first heavy wiring structure 106. Therefore, all the intermediate dielectric layers and metallization patterns of the first heavy wiring structure 106 (such as dielectric layers 114, 118, 122, and metallization patterns 116, 120) are disposed between the dielectric layer 110 / metallization pattern 112 and the components to be formed or attached on the first heavy wiring structure 106 subsequently. In some embodiments, the metallization pattern 112 has different dimensions from the metallization patterns 116, 120. For example, the wires of the metallization pattern 112 may have a thickness of about 0.5 microns to about 15 microns, or a thickness of about 5 microns, and the wires of the metallization patterns 116 and 120 may have a thickness of about 0.5 microns to about 15 microns, or a thickness of about 5 microns. The ratio of the thickness of the metallization pattern 112 to the thickness of the metallization pattern 120 may be about 0.3 to about 3, or about 1. Furthermore, the metallization pattern 112 may be formed to have a greater pitch compared to the metallization patterns 116, 120. For example, the wires of the metallization pattern 112 may have a pitch of about 1 micron to about 100 microns, or a pitch of about 10 microns, and the wires of the metallization lines 116 and 120 may have a pitch of about 1 micron to about 100 microns, or a pitch of about 10 microns. The ratio of the pitch of the metallization pattern 112 to the pitch of the metallization pattern 120 may be about 0.1 to about 10, or about 1. It should be noted that the first heavy wiring structure 106 may include any number of dielectric layers and metallization patterns. If more dielectric layers and metallization patterns are to be formed, the foregoing steps and processes may be repeated.

[0115] In Figure 2FAmong them, through vias 126 are formed in some of the openings 124 and extend in a direction away from the topmost dielectric layer (such as dielectric layer 122) of the first heavy wiring structure 106. As an example of forming the through vias 126, a seed layer (not shown) is formed on the first heavy wiring structure 106, such as on the dielectric layer 122 and the exposed portions of the metallization pattern 120 through the openings. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer, and the copper layer is located above the titanium layer. In some embodiments, the seed layer is made of copper, titanium, nickel, gold, palladium, analogs, or combinations thereof. For example, the seed layer can be formed by physical vapor deposition (PVD) or similar means. A mask (such as a photoresist (not shown)) is formed and patterned on the seed layer. The photoresist can be formed by spin coating or similar means and can be exposed to light for patterning. The pattern of the photoresist corresponds to the through vias 126 and exposes the seed layer. A conductive material is then formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by electroplating (such as an electro-chemical plating process or electroless plating), chemical vapor deposition, atomic layer deposition (ALD), physical vapor deposition, similar means, or combinations thereof. The conductive material can include metals such as copper, titanium, tungsten, aluminum, or analogs. The photoresist can be removed.

[0116] Please continue to refer to Figure 2F , bonding pads 128 are formed in some of the openings 124 and extend in a direction away from the dielectric layer 122. The bonding pads 128 can be formed in a manner similar to that of the through vias 126 and can be formed of the same material as the through vias 126. In addition, the bonding pads 128 can be formed before, after, or simultaneously with the through vias 126.

[0117] The photoresist for the bonding pads 128 and the through vias 126 and the portions of the seed layer where the bonding pads 128 and the through vias 126 are not formed will be removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma or analogs. Once the photoresist is removed, the exposed portions of the seed layer will be removed, such as by using an acceptable etching process, like wet etching or dry etching. The remaining portions of the seed layer and the conductive material form the bonding pads 128 and the through vias 126.

[0118] As mentioned above, an integrated circuit chip (such as reference Figure 1The foregoing integrated circuit chip 50) can be attached to the bonding pad 128. In some embodiments, the bonding pad 128 is an under-bump metallization structure (UBMs). For example, it may include three layers of conductive materials, such as a layer of titanium, a layer of copper, and a layer of nickel. Other material and layer configurations can also be utilized to form the bonding pad 128, such as a chromium / chromium-copper alloy / copper / gold configuration, a titanium / tungsten titanium / copper configuration, or a copper / nickel / gold configuration. Any suitable materials and material layers that can be used for the bonding pad 128 are fully encompassed within the scope of the embodiments of the present invention.

[0119] In Figure 2G , one or more semiconductor devices (such as the first integrated circuit chip 50) will be attached to the bonding pad 128 to establish an electrical connection with the first fan-out wiring structure 106. For example, the first integrated circuit chip 50 can be attached by forming solder joints 130 on the chip connector 66 (whether it is a conductive pillar or an under-bump metallization structure), pressing the chip connector 66 onto the bonding pad 128, and reflowing the solder joints 130 to bond the first integrated circuit chip 50 to the first fan-out wiring structure 106. In some embodiments, the first integrated circuit chip 50 can be attached using direct metal-to-metal bonding or hybrid bonding. Figure 2G It is depicted that the integrated circuit chip 50 has a height higher than that of the vias 126. However, it should be noted that the vias 126 can have a height approximately equal to or higher than that of the integrated circuit chip 50. For example, the vias 126 can have a height H of about 10 micrometers to about 200 micrometers TV , and the integrated circuit chip 50 can have a height H of about 30 micrometers to about 250 micrometers IC1 . The height H TV and the height H IC1 can have a ratio of about 0.04 to about 8.

[0120] It should be noted that for the integrated circuit chip 50, the first fan-out wiring structure 106 can be a fan-out rewiring structure. Therefore, the metallization patterns (such as the metallization patterns 112, 116, 120) can extend more in the lateral direction than the integrated circuit chip 50. The fan-out design allows for a thinner rewiring structure and can also accommodate more external connectors, which can thus extend more in the lateral direction than the integrated circuit chip 50. The first fan-out wiring structure 106 is formed to have a thickness T 1 , and this thickness T 1 can be about 20 micrometers to 100 micrometers.

[0121] An underfill material 132 may be dispensed between the first integrated circuit chip 50 and the first side heavy wiring device 106. The underfill material 132 surrounds the solder joints 130 and the bonding pads 128. The underfill material 132 may be any acceptable material, such as a polymer, an epoxy resin, a molding underfill, or the like. The underfill material 132 may be dispensed using a needle or a jet dispenser, using a capillary flow process, or using other suitable processes. In some embodiments, a curing process may be performed to cure the underfill material 132. Although not explicitly shown in Figure 2G the underfill material 132 may extend along the sidewall of the first integrated circuit chip 50.

[0122] For illustrative purposes, Figure 2G is shown as a single integrated circuit chip 50 attached to the bonding pad 128. In some embodiments, two or more integrated circuit chips 50 (each integrated circuit chip 50 having the same or different functions) may be attached to the bonding pad 128.

[0123] Figures 3A to 3H is a cross-sectional view showing an intermediate step during the process of forming a second element 200 according to some embodiments. As previously described, the second element 200 may then be attached to the first element 100 as described with respect to Figures 2A - 2G The second element 200 may be formed as an individual package or may be formed by a wafer-level process. Only an individual packaged element 200 is shown, but it should be noted that the second element 200 may be a part of a wafer. After formation, the individual second elements 200 will be singulated. The final second element 200 may also be referred to as an integrated package.

[0124] In Figure 3A a second carrier substrate 202 is provided, and a second side heavy wiring structure may be formed on the second carrier substrate 202. The second carrier substrate 202 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The second carrier substrate 202 may be a wafer, such that multiple packages may be formed on the second carrier substrate 202 simultaneously. A first metal film 204 is formed on the second carrier substrate 202. The first metal film 204 may include copper, such as a copper foil. The second carrier substrate 202 may have a thickness of about 10 microns to about 400 microns, or a thickness of about 200 microns. The first metal film 204 may have a thickness of about 1 micron to about 20 microns, or a thickness of about 3 microns. The first metal film 204 may include copper or other conductive materials.

[0125] In Figure 3BTherein, a photoresist 208 is then formed and patterned on the first metal film 204. The photoresist 208 can be formed by spin coating or a similar method and can be exposed to light for patterning. The patterning will form openings through the photoresist 208 to expose the first metal film 204.

[0126] In Figure 3C Therein, a second-stage wiring structure 206 is formed on the first metal film 204. First, a first metal trace 210 is formed on the first metal film 204, and the photoresist 208 is removed. The first metal trace 210 can be formed by electroplating and can include one or more layers of conductive material. For example, a layer of gold (Au) can be deposited first, a layer of nickel (Ni) second, and a layer of copper (Cu) last. The gold can be deposited to a thickness greater than or about 0.1 micrometers, such as about 0.01 micrometers to about 3 micrometers. The nickel can be deposited to a thickness greater than or about 3 micrometers, such as about 0.1 micrometers to about 10 micrometers. The copper can be deposited to a thickness greater than or about 7 micrometers, such as about 1 micrometers to about 25 micrometers. Thus, the first metal trace 210 can have a thickness greater than or about 1 micrometer to 35 micrometers, such as greater than or about 10 micrometers. A thickness like this is beneficial for adhering the first metal trace 210 to the first metal film 204, maintaining internal cohesiveness, and / or providing sufficient electrical conductivity. A thickness less than this may result in poor adhesion, cohesion, and / or conductivity. The photoresist 208 can be removed by any suitable stripping method.

[0127] In Figure 3D Therein, a dielectric layer 212 is formed on the first metal trace 210. The dielectric layer 212 can be formed by a thermal lamination process. The dielectric layer 212 can include prepreg or an Ajinomoto Build-up Film (ABF). In some embodiments, the dielectric layer 212 can be a prepreg having a thickness of about 10 micrometers to about 100 micrometers, such as about 30 micrometers, or can be an ABF having a thickness of about 10 micrometers to about 100 micrometers, such as about 20 micrometers. The advantage of using prepreg or ABF film material as the dielectric layer 212 is that the second-stage wiring structure 206 will have a high level of strength and reliability. When coupled with the first-stage wiring structure 106 later, the entire semiconductor package will be less prone to warping.

[0128] In Figure 3EAmong them, the dielectric layer 212 is patterned to form openings that expose portions of the first metal traces 210. The openings include via openings 214 that extend through the dielectric layer 212 to expose portions of the first metal traces 210. The openings also include line openings 216 that connect the via openings 214 and provide routing capabilities. The dielectric layer 212 can be patterned using a single damascene or dual damascene process. The patterning can be performed by any suitable method, such as forming a photoresist and wet etching or dry etching the dielectric layer 212 and / or using a laser ablation (or laser drilling) technique. Although depicted as having vertical sidewalls, it should be noted that the laser drilling technique can produce via openings 214 with non-vertical sidewalls. The via openings 214 can have a width of from about 30 microns to about 150 microns, such as about 65 microns.

[0129] In Figure 3F Among them, in the regions above the dielectric layer 212, the via openings 214 and the line openings 216 will be filled with a conductive material to form conductive vias 218 (in the via openings 214) and second metal traces 220 (in the line openings 216). The conductive material can be deposited by electroplating or electroless plating, or any suitable method. The second metal traces 220 can have a thickness of about 10 microns. Alternatively, the conductive vias 218 can be initially formed before the dielectric layer 212 is patterned to form the second metal traces 220.

[0130] The second-level redistribution structure 206 (including the first metal traces 210, the conductive vias 218, and the second metal traces 220) is formed to have a thickness T 2 , where this thickness T 2 can be from about 20 microns to about 150 microns. The thickness of the second-level redistribution structure 206 can be greater than or equal to the thickness T 1 of the back-level redistribution structure 106. The thickness T 2 and the thickness T 1The ratio can be from about 0.3 to about 3. A ratio within this range provides suitable rigidity to avoid or reduce warping due to different coefficients of thermal expansions (CTEs), for example, when the second element 200 is subsequently attached to the first element 100, the different CTEs of the dielectric layer and metallization pattern of the first side heavy wiring structure 106 and the materials including the integrated circuit chip 50. A ratio less than this value may not provide sufficient rigidity to the second element 200 to counter the element expansion of the first element 100. A ratio greater than this value may increase the signal length, thereby reducing the performance of the packaged device.

[0131] In Figure 3G a solder mask material 222 is formed and patterned to form openings 224 that expose the conductive vias 218 and / or the second metal traces 220. Additionally, for protection purposes, the exposed portions of the conductive vias 218 and the second metal traces 220 may be treated. For example, an electroless nickel electroless palladium immersion gold (ENEPIG) treatment or an organic solderability preservative (OSP) may be implemented on the exposed portions of the conductive vias 218 and the second metal traces 220. The solder mask material may have a thickness from about 5 microns to about 40 microns, such as about 10 microns. The solder mask material 222 may also be used to protect the protected areas of the second side heavy wiring structure 206 from external damage.

[0132] In Figure 3H a connector 226 is formed over the exposed portions of the conductive vias 218 and the second metal traces 220. The connector 226 can be a solder ball, formed in a manner similar to the solder areas on the first integrated circuit chip 50, and can be formed of a material similar to the solder areas on the first integrated circuit chip 50.

[0133] Regarding the wafer - level process to form the second element 200, a singulation process can be performed by sawing along the scribe regions (saw streets) adjacent to the second elements 200. As described below, the resulting singulated second elements 200 are coupled to the first element 100. In some embodiments, the first element 100 is similarly singulated before the second element 200 is attached. In some embodiments, the first element 100 is singulated after being attached to the second element 200.

[0134] Figures 4A to 4H is a cross - sectional view showing an intermediate step of attaching the second element 200 to the first element 100 according to some embodiments, and additional processes to form a package 400.

[0135] First, refer to Figure 4A , where the encapsulation body 400 is shown, and the first element 100 is part of a wafer. In some embodiments (not shown in Figure 4A ), the first element 100 has been singulated in the scribe region 404.

[0136] Each singulated second element 200 is mounted to the first element 100 using a connector 226. As previously mentioned, the first element 100 includes vias 126 for attachment. Accordingly, the connector 226 is coupled to the corresponding via 126. In some embodiments, the connector 226 is reflowed to attach the second element 200 to the via 126. The connector 226 electrically couples the second element 200 to the first side wiring structure 106 of the first packaged element 100. The connector 226 may have an epoxy flux (not shown) formed thereon, as after the second element 200 is attached to the first element 100, it will reflow with at least some of the epoxy portion of the remaining epoxy flux. This remaining epoxy portion can act as an underfill to reduce stress and protect the joints formed by the reflowed connector 226. After the second element 200 is attached to the first element 100, the first side wiring structure 106 and the second side wiring structure 206 may be separated from each other by a thickness T 3 . The thickness T 3 can be from about 50 microns to about 500 microns. The ratio of the thickness T 3 to the thickness T 1 can be from about 0.4 to about 5. The ratio of the thickness T 3 to the thickness T 2 can be from about 0.3 to about 4.

[0137] In Figure 4B , an encapsulant 310 is formed over the first element 100 and surrounds the second element 200. The encapsulant 310 further encapsulates the via 126, the first integrated circuit chip 50, and any other devices (if any) attached to the first element 100 and / or the second element 200. The encapsulant 310 is further formed in the gap regions adjacent to the second element 200. The encapsulant 310 can be formed by a capillary flow process after the second packaged element 200 is attached, or by a suitable deposition method before the second packaged element 200 is attached. In some embodiments, the encapsulant 310 can be applied by compression molding, transfer molding, or a similar method. The encapsulant 310 can be applied in a liquid or semi-liquid form and then subsequently cured. The encapsulant 310 can be a molding compound, an epoxy resin, or the like.

[0138] As shown Figure 4B in the illustrations 401, 402, the encapsulant 310 may be formed to surround the side edges of the second layer of heavy wiring structure 206 of the second component 200. The encapsulant 310 may partially or completely cover the side edges of the second component 200. For example, as depicted in illustration 401, the encapsulant 310 may have a recessed upper surface, the highest point of which is located near the side edges of the second component 200. The encapsulant 310 may partially or completely cover the side edges of the second layer of heavy wiring structure 206. In some embodiments, the encapsulant 310 may also cover a portion of the side edges of the second carrier substrate 202. Additionally, the lowest point of the upper surface may be lower than the portion of the second layer of heavy wiring structure 206 closest to the second carrier substrate 202. As depicted in illustration 402, the encapsulant 310 may be formed to cover all of the side edges of the second layer of heavy wiring structure 206, as well as all or a portion of the side edges of the second carrier substrate 202. In some embodiments, the encapsulant 310 may cover all of the side edges of the second carrier substrate 202, and even a portion of the upper surface of the second carrier substrate 202 (not specifically depicted).

[0139] The encapsulant 310 provides additional support to the second layer of heavy wiring structure 206, which makes the overall package 400 stronger, more reliable, and less prone to warping. As previously mentioned, the increased strength and robustness are due to the upper portion of the encapsulant 310 being adhered to the side edges of the second component 200. The encapsulant 310 may slope downward away from the side edges of the second component 200, as Figure 4B depicted in illustration 401. The slope may be at an angle θ with respect to the horizontal line. The angle θ may be from about 0 degrees to about 45 degrees, or from about 45 degrees to about 60 degrees.

[0140] In Figure 4C , according to some embodiments, the second carrier substrate 202 is removed from the package 400, exposing the second layer of heavy wiring structure 206. The second carrier substrate 202 may be demounted, debonded, or mechanically peeled off from the second layer of heavy wiring structure 206 by, for example, using a heat treatment to change the adhesiveness of the release layer disposed on the second carrier substrate 202. In some embodiments, an energy source is used to irradiate and heat the release layer until the release layer loses at least some of its own adhesiveness, the energy source being, for example, an ultraviolet (UV) laser, a carbon dioxide (CO 2)a laser, or an infrared (IR) laser. Once executed, the second carrier substrate 202 and the metal film 204 can be physically separated and removed from the second-side re-wiring structure 206. In some embodiments, a planarization process or a mechanical peeling process can be executed to remove the second carrier substrate 202 to expose the second-side re-wiring structure 206. The planarization structure can also remove some encapsulant 310 that may be formed on top of the upper layer of the second-side re-wiring structure 206. For example, the planarization structure can be chemical-mechanical polish (CMP), a grinding process, or the like. It should be specifically noted that even in this embodiment, the encapsulant 310 is formed to completely cover the side edges of the second component (and perhaps above the upper surface of the second carrier substrate 202 (e.g., generally depicted in the illustration 402 of Figure 4B ), because of the protection of the second carrier substrate 202, the encapsulant 400 is still not likely to creep the encapsulant 310 on the upper surface of the second-side re-wiring structure 206. Therefore, after removing the second carrier substrate 202, there is no encapsulant 310 on the upper surface of the second-side re-wiring structure 206. Therefore, the topmost surface of the encapsulant 310 can be flush with the upper surface of the second-side re-wiring structure 206 or recessed from the upper surface of the second-side re-wiring structure 206.

[0141] Please continue to refer to Figure 4C , in some embodiments, a passivation layer 320 is formed and patterned on the exposed second-side re-wiring structure 206. The passivation layer 320 can be a dielectric material, and the method and material for forming it can be similar to any one of the dielectric layers 110, 114, 118, 122. Alternatively, the passivation layer 320 can be a solder mask material, and the method and material for forming it can be similar to the solder mask material 222.

[0142] In Figure 4D , the encapsulant 400 can be flipped over the temporary substrate 406 and attached to the temporary substrate 406, and the temporary substrate 406 is, for example, a tape, a wafer, a panel, a frame, a ring, or the like. The first carrier substrate 102 is then removed. In some embodiments, the carrier substrate removal is performed to separate (or disassemble or debond) the first carrier substrate 102 from the first-side re-wiring structure 106, such as the dielectric layer 110. According to some embodiments, the removal includes projecting light (such as laser light or ultraviolet light) on the release layer 104, so that the release layer 104 decomposes under the thermal energy of the light, and the first carrier substrate 102 can be removed.

[0143] In Figure 4EIn [the structure], a conductive connector 410 is formed on the first-layer heavy wiring structure 106. The conductive connector 410 can be a ball grid array (BGA) connector, solder balls, metal pillars, C4 (controlled collapse chip connection) bumps, micro-bumps, bumps formed by electroless nickel immersion gold (ENEPIG) technology, or the like. The conductive connector 410 can include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive connector 410 is initially formed by evaporation to form a layer of solder, electroplating, printing, solder transfer, ball placement, or a similar method. Once a layer of solder is formed on the structure, reflow soldering can be performed to shape the material into the desired bump shape. In another embodiment, the conductive connector 410 includes metal pillars (such as copper pillars) formed by sputtering, printing, electroplating, electroless plating, chemical vapor deposition, or a similar method. The metal pillars may not require solder and may have substantially vertical sidewalls. In some embodiments, a metal capping layer is formed on top of the metal pillars. The metal capping layer can include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof, and can be formed by an electroplating process.

[0144] According to some embodiments, if not yet singulated, the structure can then be singulated along the scribe region 404 (see, for example, Figure 4A ). Alternatively, the structure can be singulated before the conductive connector 410 is formed. In some embodiments, the structure can be singulated using one or more saw blades to separate the package 400 into separate pieces, forming one or more singulated packages 400. However, any suitable singulation method (including laser ablation or one or more wet etches) can also be utilized.

[0145] After singulation, the first-layer heavy wiring structure 106 has a width W 1 , and the width W 1 can be from about 3 millimeters to about 150 millimeters. The second element 200 and its second-layer heavy wiring structure 206 have a width W 2 , and the width W 2 can be from about 3 millimeters to about 150 millimeters. The width W 2 can be less than or equal to the width W 1 (e.g., the width of the first element and its first-layer heavy wiring structure 106). The width W 1 and the width W2 The ratio can be from about 1 to about 3, or about 1. A ratio within this range can make the entire semiconductor package less prone to warping when the second-stage heavy wiring structure 206 is coupled to the first-stage heavy wiring structure 106. In other words, the strength and width W of the second-stage heavy wiring structure 206 2 will balance the warping that may occur in the first-stage heavy wiring structure 106.

[0146] In Figure 4F and Figure 4G after singulation, the package 400 can be removed from the temporary substrate 406, flipped over another substrate and attached to this other substrate, such as substrate 503 (e.g., a carrier substrate, a packaging substrate, a printed circuit board (PCB), or the like). As shown, the package 400 can feature a passivation layer 320 ( Figure 4F ) or the passivation layer 320 can be omitted ( Figure 4G ). In some cases in the package 400, the vias 126 can be aligned with the conductive vias 218, as depicted in the extension of Figure 4G . Depending on the forming method, the conductive vias 218 can have inwardly inclined sidewalls. In some cases, the inwardly inclined sidewalls can have a concave shape, making the conductive vias 218 have an hourglass shape. In addition, the conductive vias 218 can have serrated sidewalls. Some portions of the serrated sidewalls are attributed to the laser ablation method of drilling through the dielectric layer 212, as previously described with respect to Figure 3F .

[0147] In Figure 4H an embodiment is shown, similar to that previously described with respect to Figure 4F where an additional device 511 is attached to the substrate 503. The additional device 511 can include active devices and / or passive devices, such as integrated passive devices and surface mount devices (SMD) (e.g., capacitors). In addition, the additional device 511 can include devices similar to the integrated circuit chip 50, and devices designed for intended purposes, such as memory chips (e.g., dynamic random access memory (DRAM) chips, stacked memory dies, high bandwidth memory (HBM) chips, etc.), logic chips, central processing unit (CPU) chips, system-on-chip (SoC), component on a wafer (CoW), integrated fan-out structure (InFO), packages, the like, or combinations thereof.

[0148] Figures 5A to 5H and Figures 6A to 6H describes various intermediate steps of forming a first element (including a first integrated circuit chip 50), forming a second element (including attachment of a second integrated circuit chip 50), and other processes of attaching the second element to the first element and forming a semiconductor package body according to some embodiments.

[0149] Figures 5A to 5H is a cross-sectional view showing intermediate steps of forming a first element 501, a second element 502, and a package body 504 according to some embodiments. Specifically, the drawing depicts certain intermediate steps of forming a first element 501, attaching a second element 502 to the first element 501 (and additional steps) to form a package body 504.

[0150] In Figure 5A , a first side wiring structure 106 of the first element 501 is provided, and vias 126 and bonding pads 128 are formed on the first side wiring structure 106. Processes and materials similar to those previously described with respect to Figures 2A to 2F can be used. In Figure 5B , a first integrated circuit chip 50 is attached together with one or more other semiconductor devices 550 (only one is shown, but there can be multiple additional semiconductor devices). Processes and materials similar to those previously described with respect to Figure 2G can be used.

[0151] The first integrated circuit chip 50 and other devices 550 can include devices designed for intended purposes, such as memory chips (e.g., dynamic random access memory (DRAM) chips, stacked memory die, high bandwidth memory (HBM) chips, etc.), logic chips, central processing unit (CPU) chips, system-on-chip (SoC), chip-on-wafer (CoW), integrated fan-out (InFO) structure, packages, the like, or combinations thereof. The first integrated circuit chip 50 and other devices 550 can be formed in processes of the same technology node, or can be formed in processes of different technology nodes. For example, the first integrated circuit chip 50 can be a more advanced technology node than other devices 550. The first integrated circuit chip 50 and other devices 550 can have different sizes (e.g., different heights and / or surface areas), or can have the same size (e.g., the same height and / or surface area). The advantage of the first side wiring structure 106 is to provide electrical connections between the integrated circuit chip 50, other devices 550, the subsequently attached second element 502, and elements subsequently attached to the other side of the first side wiring structure 106.

[0152] In some embodiments, the first integrated circuit chip 50 and other devices include transistors, capacitors, inductors, resistors, metallization layers, external connectors, and the like therein, designed for specific functions. In some embodiments, the first integrated circuit chip 50 and other devices may include more than one device of the same type, or may include different devices. Figure 5B A single integrated circuit chip 50 is shown, but in some embodiments, one, two, or more integrated circuit chips 50 or other devices may be attached to the first sidewall wiring structure 106. Figure 5B The integrated circuit chip 50 is depicted as having a lower height than the vias 126. This is to accommodate the second element 502, which will include another integrated circuit chip (as shown in subsequent figures). For example, the vias 126 may have a height H of about 10 microns to about 200 microns TV and the integrated circuit chip 50 may have a height H of about 30 microns to about 250 microns IC1 . The height H TV and the height H IC1 may have a ratio of about 0.04 to about 8.

[0153] In Figure 5C , a second sidewall wiring structure 206 for the second element 502 is provided, and the solder resist material 222 may be formed and patterned to form openings 228 in addition to the openings 224. Processes and materials similar to those previously described with respect to Figures 3A to 3H may be used. Some or all of the openings 228 may expose portions of the conductive vias 218 and the second metal traces 220. The openings 228 and the openings 224 may be formed simultaneously or at different times using the same or different patterning methods.

[0154] In Figure 5D , a second integrated circuit chip 50 may be attached to the second sidewall wiring structure 206 at the openings 228 and electrically coupled to the conductive vias 218 and the second metal traces 220. Processes and materials similar to those previously described with respect to Figures 2G to 5B may be used, including the formation of bonding pads 528, solder joints 530, and underfill material 532. Additionally, connectors 226 may be formed in the openings 224.

[0155] In Figure 5E , the second element 502 (including the second sidewall wiring structure 206 and the second integrated circuit chip 50) is attached to the first element 501, and the second carrier substrate 202 is removed using processes and materials similar to those previously described with respect to Figures 4A to 4C . As previously described with respect to the package 400, the package 504 has a width W of the first sidewall wiring structure 106 1 greater than the width W of the second sidewall wiring structure 2062 and can form an encapsulant 310 surrounding the side edges of the second secondary wiring structure 206, similar to Figures 4B to 4H as shown. As shown, the second element 502 is attached such that the back sides of the first integrated circuit chip 50 and the second integrated circuit chip 50 face each other. Either or both of the first and second integrated circuit chips 50 may have a dielectric layer 510 along the back side, which may then be directly inserted between the first and second integrated circuit chips 50.

[0156] Please continue to refer to Figure 5E , the dielectric layer 510 may be similar to the adhesive layer 70 and may be applied in a similar manner. The first and second integrated circuit chips 50 may be arranged vertically such that at least a portion of the second integrated circuit chip 50 is directly above at least a portion of the first integrated circuit chip. The first and second integrated circuit chips 50 may be centered with respect to each other or may be arranged asymmetrically.

[0157] The package 504 may then be completed, as Figures 5F to 5H shown, and may be done in a similar manner as previously described, e.g., with respect to Figures 4D to 4H . As Figure 5G shown, the third integrated circuit chip 50 may be attached to the first secondary wiring structure 106 by a process and materials similar to those previously described with respect to Figure 2G , Figure 5B , Figure 5D . As Figure 5H shown, the fourth integrated circuit chip 50 and the additional device 550 may be attached to the second secondary wiring structure 206 using a process and materials similar to those previously described with respect to Figure 2G , Figure 4H , Figure 5B , Figure 5D . Advantages of the foregoing arrangement include a more narrow package 504 in the horizontal direction and / or more space along the first secondary wiring structure 106 for attaching additional devices.

[0158] As previously described, the first secondary wiring structure 106 and the second secondary wiring structure 206 are separated by a thickness T 3 . In this embodiment, the thickness T 3 may be from about 60 microns to about 500 microns. The ratio of the thickness T 3 to the thickness T 1 may be from about 0.5 to about 25. The ratio of the thickness T 3 to the thickness T 2 may be from about 0.4 to about 25. Additionally, the connector 226 may have a height H of from about 10 microns to about 300 microns C, or about 150 microns. Thus, the total height of the vias 126 and the connectors 226 in the package 504 can be from about 50 microns to about 500 microns, or about 250 microns (it should be noted that the total height can be less than the sum of the height H C and the height H TV because the connector 226 is reflowed), and the total height can be substantially equal to the thickness T of the region between the first side heavy wiring structure 106 and the second side heavy wiring structure 206 3 . Again, as Figure 5H shown, the total height of the first integrated circuit chip 50 and the second integrated circuit chip (the height H IC1 and the height H IC2 , plus the thickness of the dielectric layer 510) can be substantially equal to the thickness T 3 .

[0159] Figures 6A to 6H is a cross-sectional view showing intermediate steps of forming a package 604 according to some embodiments. Specifically, the figure depicts certain intermediate steps of forming a first element 601 and attaching a second element 602 to the first element 601 (and additional steps) to form the package 604

[0160] In Figure 6A , the first side heavy wiring structure 106 of the first element 601 is provided, and the vias 126 and the bonding pads 128 are formed on the first side heavy wiring structure 106. Processes and materials similar to those previously described with respect to Figures 2A to 2F and Figure 5A can be used. In Figure 6B , the first integrated circuit chip 50 is attached together with one or more other semiconductor devices 650. Processes and materials similar to those previously described with respect to Figure 2G and Figure 5B can be used Figure 6B depicts the integrated circuit chip 50 as having a lower height than the via 126. This is to accommodate the second element 602, which will include another integrated circuit chip 50. For example, the via 126 can have a height H TV from about 10 microns to about 300 microns, and the integrated circuit chip 50 can have a height H IC1 from about 30 microns to about 300 microns. The ratio of the height H TV and the height H IC1 can be from about 0.03 to about 10

[0161] In Figure 6C , the second side heavy wiring structure 206 of the second element 602 is provided, and the solder resist material 222 can be formed and patterned to form openings 228 except for the opening 224. Processes and materials similar to those previously described with respect to Figures 3A to 3H andFigure 5C The processes and materials described can be used. Some or all of the openings 228 may expose portions of the conductive vias 218 and the second metal traces 220. The openings 228 and the openings 224 may be formed simultaneously or at different times using the same or different patterning methods.

[0162] In Figure 6D , a second integrated circuit chip 50 may be attached to the second re - wiring structure 206 at the opening 228 and electrically coupled to the conductive vias 218 and the second metal traces 220. Similar to the processes and materials previously described with respect to Figure 2G , Figure 5B , Figure 5D , Figure 6B , the formation of bonding pads 628, solder joints 630, and underfill materials 632 can be used.

[0163] In Figure 6E , a second component 602 (including the second re - wiring structure 206 and the second integrated circuit chip 50) is attached to a first component 601, and the second carrier substrate 202 is removed using processes and materials similar to those previously described with respect to Figures 4A to 4C and Figure 5E . As previously described with respect to the packages 400, 504, the package 604 has a width W of the first re - wiring structure 106 1 greater than the width W 2 of the second re - wiring structure 206, and an encapsulant 310 can be formed to surround the side edges of the second re - wiring structure 206, similar to Figures 4B to 4H shown. As shown, the second component 602 is attached such that the second integrated circuit chip 50 is laterally displaced from the first integrated circuit chip 50. This lateral displacement allows the back surface of the second integrated circuit chip 50 to be lower than the back surface of the first integrated circuit chip 50, although the back surfaces may be at the same level or the back surface of the second integrated circuit chip 50 may be higher than the back surface of the first integrated circuit chip 50.

[0164] The package 604 can then be completed, as Figures 6F to 6H shown, and can be done in a similar manner as previously described, for example with respect to Figures 4D to 4H and Figures 5F to 5H . As Figure 6G shown, a third integrated circuit chip 50 can be attached to the first re - wiring structure 106 using processes and materials similar to those previously described with respect to Figure 2G , Figure 5B , Figure 5D , Figure 6B , Figure 6D . In addition, external connectors 610 can be formed to provide for subsequent attachment of other integrated circuit devices or components of the package. AsFigure 6H As shown, the fourth integrated circuit chip 50 and the additional device 650 can be attached to the second re - wiring structure 206 using a process and materials similar to those previously described with respect to Figure 2G 、 Figure 4H 、 Figure 5B 、 Figure 5D 、 Figure 5G 、 Figure 5H 、 Figure 6B 、 Figure 6D The advantages of the foregoing arrangement include providing a thinner package 604.

[0165] As previously mentioned, the first re - wiring structure 106 and the second re - wiring structure 206 are separated by a thickness T 3 . In this embodiment, the thickness T 3 can be from about 50 microns to about 500 microns. The ratio of thickness T 3 to thickness T 1 can be from about 0.4 to about 25. The ratio of thickness T 3 to thickness T 2 can be from about 0.0 to about 10. In addition, the connector 226 can have a height H of about 10 microns to about 300 microns C 、or about 150 microns. Thus, the total height of the vias 126 and the connector 226 in the package 604 can be from about 100 microns to about 600 microns, or about 300 microns (it should be noted that the total height can be less than the sum of height H C and height H TV because the connector 226 is reflowed), and the total height can be approximately equal to the thickness T 3 of the region between the first re - wiring structure 106 and the second re - wiring structure 206. Again, as Figure 6H shown, the thickness T 3 is less than the total height of the stacked first integrated circuit chip 50 and the second integrated circuit chip (with heights H IC1 and H IC2 respectively). In other words, the lateral displacement of the first and second integrated circuit chips 50 relative to each other allows for a lower thickness T 3 . In some embodiments, the thickness of the encapsulant 310 between the back surface of the first re - wiring structure 106 and the second integrated circuit chip 50 can be from about 30 microns to about 300 microns, such as about 150 microns. In addition, the thickness of the encapsulant 310 between the second re - wiring structure 206 and the first integrated circuit chip 50 can be from about 30 microns to about 300 microns, such as 150 microns.

[0166] Embodiments can achieve many advantages for system-in-package (SiP) structures for integrated circuits. For example, dual-sided wiring (such as second-side and first-side redistribution structures) allows each side of the wiring to be thinner, and allows the overall semiconductor package to be thinner while reducing overall package warpage. In addition, a carrier-type substrate used in one of the wiring structures provides better structural support, which also reduces overall package warpage. Furthermore, the described design method provides diversity in the wiring of embedded integrated circuit chips and other devices. Of course, vertically stacked integrated circuit chips can provide sufficient space for additional devices to be attached to the first-side redistribution structure, while laterally displaced integrated circuit chips can allow for an overall thinner package structure. It should be noted that the first-side redistribution structure can be wider than the second-side redistribution structure, which allows for the formation of a molding compound to surround the second-side redistribution structure to strengthen the package and further reduce overall package warpage. Of course, the described design method provides a way to apply the molding compound without the risk of spreading along the outer surface of the second-side redistribution structure. This can ensure that additional devices can be attached to the outer surface of the second-side redistribution structure without being interfered with by trace amounts of the molding compound.

[0167] In one embodiment, a semiconductor package is fabricated by attaching a first component to a second component. The first component is assembled by forming a first redistribution structure over a substrate. A via is then formed over the first redistribution structure, and a chip is attached to the first redistribution structure, active side down. The second component includes a second redistribution structure, which is then attached to the via. A molding compound is deposited between the first redistribution structure and the second redistribution structure, and also surrounds the sides of the second component.

[0168] In another embodiment, a semiconductor package is fabricated by forming a first component, forming a second package component, and attaching the second component to the first component. The first component is formed by forming a redistribution structure over a substrate, forming a via over the redistribution structure, and attaching a chip to the redistribution structure. The second component is formed by forming another redistribution structure over another substrate, forming a connector over this redistribution structure, and attaching another chip to this redistribution structure. The second component is attached by flipping it over the via and using a reflow connector to bond the connector to the via. After attachment, the substrate is removed from the second component.

[0169] In yet another embodiment, a semiconductor package includes a first redistribution structure on a substrate and a second redistribution structure stacked on top of the first redistribution structure. The second redistribution structure includes a conductive via. The first redistribution structure is wider than the second redistribution structure. A through hole electrically couples the first redistribution structure to the second redistribution structure. A chip is attached to the first redistribution structure with the active side of the chip facing and electrically coupled to the first redistribution structure. Another chip is attached to the second redistribution structure with the active side of this chip facing and electrically coupled to the second redistribution structure. A molding compound is filled in the region between the first redistribution structure and the second redistribution structure.

[0170] An embodiment of the present invention provides a method for forming a semiconductor package, including forming a first element, and forming the first element includes: forming a first redistribution structure on a first substrate; forming a through hole on the first redistribution structure; attaching a first chip to the first redistribution structure with the active side of the first chip facing and electrically coupled to the first redistribution structure. The method for forming a semiconductor package further includes attaching a second element to the through hole, the second element includes a second redistribution structure attached to a second substrate, and after attaching the second element, depositing a molding compound between the first redistribution structure and the second redistribution structure, and a part of the molding compound surrounds the side edge of the second redistribution structure.

[0171] In some embodiments, the method for forming a semiconductor package further includes forming a second redistribution structure on the second substrate, attaching a second chip to the second redistribution structure with the active side of the second chip facing and electrically coupled to the second redistribution structure, and depositing a solder ball on the second redistribution structure. In some embodiments, the step of attaching the second element includes reflowing the solder ball to electrically couple the through hole to the second redistribution structure. In some embodiments, the step of attaching the second element includes attaching the second element such that the second chip is directly located above the first chip with the back side of the first chip facing the back side of the second chip. In some embodiments, the step of attaching the second element includes attaching the second element such that the second chip is laterally displaced from the first chip with the side of the first chip facing the side of the second chip. In some embodiments, the step of forming the second redistribution structure includes forming a first metal trace on the first substrate, depositing an ABF film (Ajinomoto Build-up Film) on the first metal trace, laser drilling an opening in the ABF film, forming a conductive via in the opening, and forming a second metal trace on the conductive via. In some embodiments, the method for forming a semiconductor package further includes removing the second substrate, and after removing the second substrate, attaching a plurality of passive devices to the second redistribution structure.

[0172] An embodiment of the present invention also provides a semiconductor package, including a first component, a second component, and a packaging adhesive. The first component includes a first redistribution structure, a through hole, and a first chip. The through hole is disposed on the first redistribution structure. The first chip is attached to the first redistribution structure, and the active side of the first chip faces the first redistribution structure. The second component includes a second redistribution structure, a connector, and a second chip. The connector couples the through hole to the second redistribution structure. The second chip is attached to a first side of the second redistribution structure, and the active side of the second chip faces the second redistribution structure. The packaging adhesive is disposed between the first redistribution structure and the second redistribution structure.

[0173] In some embodiments, the packaging adhesive encapsulates the side edges of the first chip and the second chip. In some embodiments, the packaging adhesive contacts the side edge of the second redistribution structure. In some embodiments, the semiconductor package further includes a passivation layer and a third chip. The passivation layer is disposed on a second side of the second redistribution structure, and the second side is opposite to the first side. The third chip is disposed on the passivation layer on the second side of the second redistribution structure. In some embodiments, in a plan view, a part of the second chip overlaps with a part of the first chip. In some embodiments, the second chip is laterally displaced from the first chip. In some embodiments, the semiconductor package further includes a passive device attached to the second side of the second redistribution structure.

[0174] An embodiment of the present invention further provides a semiconductor package, including a first redistribution structure, a second redistribution structure, a first chip, a second chip, a packaging adhesive, and a through hole. The first redistribution structure has a first width. The second redistribution structure is disposed on the first redistribution structure and includes a conductive via extending from a first metal trace to a second metal trace. The first metal trace is disposed along a first side of the second redistribution structure, and the second metal trace is disposed along a second side of the second redistribution structure. The second redistribution structure has a second width, and the first width is greater than the second width. The first chip is attached to the first redistribution structure, and a first active side of the first chip faces and is electrically coupled to the first redistribution structure. The second chip is attached to the second redistribution structure, and a second active side of the second chip faces and is electrically coupled to the second redistribution structure. The packaging adhesive is directly inserted between the first redistribution structure and the second redistribution structure. The through hole extends through the packaging adhesive, and the through hole electrically couples the first redistribution structure to the second redistribution structure.

[0175] In some embodiments, the encapsulant contacts the entire side edge of the first chip, the entire side edge of the second chip, and at least a portion of the side edge of the second redistribution structure. In some embodiments, the first redistribution structure is an outfan redistribution structure. In some embodiments, the conductive vias are directly disposed on top of the through holes and are electrically coupled to the through holes. In some embodiments, the first chip includes a first back side opposite the first active side, the second chip includes a second back side opposite the second active side, and the second back side is closer to the first redistribution structure than the first back side. In some embodiments, the semiconductor package further includes a passive device attached and electrically coupled to a side of the second redistribution structure opposite the first redistribution structure.

[0176] The features of several embodiments of the present disclosure are outlined above, so that those skilled in the art can more clearly understand the various aspects of the present disclosure. Any person skilled in the art should understand that the present disclosure can be used as a basis for the design or modification of other structures or processes to achieve the same purposes as the embodiments of the present disclosure and / or obtain the same advantages. Any person skilled in the art can also understand that the equivalent structures or processes do not depart from the concept and protection scope of the present disclosure, and can be changed, substituted, and modified without departing from the concept and scope of the present disclosure.

Claims

1. A method for forming a semiconductor package, the forming method comprises: forming a first component, and forming the first component includes: forming a first redistribution structure on a first substrate; forming a through hole on the first redistribution structure; attaching a first chip to the first redistribution structure, with the active side of the first chip facing and electrically coupled to the first redistribution structure; after attaching the first chip to the first redistribution structure, attaching a second component to the through hole, the second component including a second redistribution structure attached to a second substrate; and after attaching the second component, depositing a molding compound between the first redistribution structure and the second redistribution structure, with a portion of the molding compound surrounding the side edges of the second redistribution structure.

2. The forming method according to claim 1, further comprises: forming the second redistribution structure on the second substrate; attaching a second chip to the second redistribution structure, with the active side of the second chip facing and electrically coupled to the second redistribution structure; and depositing a solder ball on the second redistribution structure.

3. The forming method according to claim 2, wherein the step of attaching the second component includes reflowing the solder ball to electrically couple the through hole to the second redistribution structure.

4. The forming method according to claim 2, wherein the step of attaching the second component includes attaching the second component such that the second chip is directly located above the first chip, with the back side of the first chip facing the back side of the second chip.

5. The forming method according to claim 2, wherein the step of attaching the second component includes attaching the second component such that the second chip is laterally displaced from the first chip, with the side of the first chip facing the side of the second chip.

6. The forming method according to claim 2, wherein the step of forming the second redistribution structure comprises: forming a first metal trace on the second substrate; depositing an ABF film on the first metal trace; laser drilling an opening in the ABF film; forming a conductive via in the opening; and forming a second metal trace on the conductive via.

7. The forming method according to claim 1, further comprises: removing the second substrate; and after removing the second substrate, attaching a plurality of passive devices to the second redistribution structure.

8. A semiconductor package, comprises: a first component, including: a first redistribution structure; a through hole disposed on the first redistribution structure; and a first chip attached to the first redistribution structure, with the active side of the first chip facing the first redistribution structure; a second component, including: a second redistribution structure; a connector that couples the through hole to the second redistribution structure; and a second chip attached to a first side of the second redistribution structure, with the active side of the second chip facing the second redistribution structure; and a molding compound disposed between the first redistribution structure and the second redistribution structure and encapsulating the first chip and the second chip between the first redistribution structure and the second redistribution structure.

9. The semiconductor package according to claim 8, wherein the encapsulant encapsulates the side edges of the first chip and the second chip.

10. The semiconductor package according to claim 9, wherein the encapsulant contacts the side edge of the second redistribution structure.

11. The semiconductor package according to claim 8, further comprising: A passivation layer disposed on a second side of the second redistribution structure, the second side being opposite to the first side; and A third chip disposed on the passivation layer on the second side of the second redistribution structure.

12. The semiconductor package according to claim 8, wherein in a plan view, a part of the second chip overlaps with a part of the first chip.

13. The semiconductor package according to claim 8, wherein the second chip is laterally displaced from the first chip.

14. The semiconductor package according to claim 8, further comprising a passive device attached to a second side of the second redistribution structure.

15. A semiconductor package, comprising: A first redistribution structure having a first width; A second redistribution structure disposed on the first redistribution structure, the second redistribution structure includes a conductive via extending from a first metal trace to a second metal trace, the first metal trace is disposed along a first side of the second redistribution structure, the second metal trace is disposed along a second side of the second redistribution structure, the second redistribution structure has a second width, and the first width is greater than the second width; A first chip attached to the first redistribution structure, a first active side of the first chip facing and electrically coupled to the first redistribution structure; A second chip attached to the second redistribution structure, a second active side of the second chip facing and electrically coupled to the second redistribution structure; An encapsulant directly inserted between the first redistribution structure and the second redistribution structure; and A through hole extending through the encapsulant, the through hole electrically coupling the first redistribution structure to the second redistribution structure.

16. The semiconductor package according to claim 15, wherein the encapsulant contacts the entire side edge of the first chip, the entire side edge of the second chip, and at least a part of the side edge of the second redistribution structure.

17. The semiconductor package according to claim 15, wherein the first redistribution structure is a fan-out type redistribution structure.

18. The semiconductor package according to claim 15, wherein the conductive via is directly disposed above the through hole and electrically coupled to the through hole.

19. The semiconductor package according to claim 15, wherein the first chip includes a first back side opposite to the first active side, the second chip includes a second back side opposite to the second active side, and the second back side is closer to the first redistribution structure than the first back side.

20. The semiconductor package according to claim 15, further comprising a passive device attached and electrically coupled to a side of the second redistribution structure opposite to the first redistribution structure.

Images