semiconductor packaging

Abstract

The present invention discloses a semiconductor package, comprising: a carrier substrate having an upper surface; a semiconductor die mounted on the upper surface; a first bonding wire connecting the semiconductor die to the carrier substrate; an insulating material encapsulating the first bonding wire; a component mounted on the insulating material, wherein the component includes a metal layer; a second bonding wire connecting the metal layer of the component to the carrier substrate, wherein the metal layer and the second bonding wire form an electromagnetic interference shielding structure; and a molding compound covering the upper surface of the carrier substrate and encapsulating the semiconductor die, the component, the first bonding wire, the second bonding wire, and the insulating material. Because the metal layer and the second bonding wire form the electromagnetic interference shielding structure, the semiconductor die can be shielded from EMI interference and ESD damage.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor package. Background Art

[0002] As is known in the art, electrostatic discharge (ESD) and electromagnetic interference (EMI) are unresolved issues in semiconductor technology. ESD can damage semiconductors and other circuit components in integrated circuits. Electromagnetic interference, caused by electromagnetic radiation, is a key consideration in electronic circuit design. Electronic circuits and components that carry changing electrical signals emit electromagnetic radiation.

[0003] The industry desires to shield sensitive components from any source of electromagnetic radiation. It is also desirable to reduce the likelihood of ESD damaging circuit components within a semiconductor package. Summary of the Invention

[0004] In view of this, the present invention provides a semiconductor package to solve the above problems.

[0005] According to a first aspect of the present invention, a semiconductor package is disclosed, comprising:

[0006] a carrier substrate having an upper surface;

[0007] a semiconductor die mounted on the upper surface;

[0008] a first bonding wire connecting the semiconductor die to the carrier substrate;

[0009] an insulating material encapsulating the first bonding wire;

[0010] a component mounted on the insulating material, wherein the component includes a metal layer;

[0011] a second bonding wire connecting the metal layer of the component to the carrier substrate, wherein the metal layer and the second bonding wire form an electromagnetic interference shielding structure;

[0012] A molding compound covers the upper surface of the carrier substrate and encapsulates the semiconductor die, the component, the first bonding wire, the second bonding wire, and the insulating material.

[0013] According to a second aspect of the present invention, a semiconductor package is disclosed, comprising:

[0014] a carrier substrate having an upper surface;

[0015] a semiconductor die mounted on the upper surface;

[0016] a first bonding wire connecting the semiconductor die to the carrier substrate;

[0017] an insulating material encapsulating the first bonding wire;

[0018] a component mounted on the insulating material, wherein the component includes a metal layer;

[0019] a second bonding wire connecting the metal layer of the component to the carrier substrate, wherein the metal layer and the second bonding wire form an electromagnetic interference shielding structure;

[0020] a second insulating material encapsulating the second bonding wire; and

[0021] A molding compound covers the upper surface of the carrier substrate and encapsulates the semiconductor die, the component, the first bonding wire, the second bonding wire, the first insulating material, and the second insulating material.

[0022] According to a third aspect of the present invention, a semiconductor package is disclosed, comprising:

[0023] a carrier substrate having an upper surface;

[0024] a semiconductor die mounted on the upper surface in a flip-chip manner;

[0025] A component stacked on the semiconductor die, wherein the component includes a metal layer;

[0026] a bonding wire connecting the metal layer of the component to the carrier substrate, wherein the metal layer and the second bonding wire form an electromagnetic interference shielding structure;

[0027] an insulating material encapsulating the bonding wire; and

[0028] A molding compound covers the upper surface of the carrier substrate and encapsulates the semiconductor die, the component, the bonding wires and the insulating material.

[0029] The semiconductor package of the present invention uses the metal layer and the second bonding wire to form an electromagnetic interference shielding structure, so that the semiconductor die can be shielded from EMI interference and ESD damage. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a schematic top view of a semiconductor package according to one embodiment of the present invention;

[0031] Figure 2 It is along Figure 1 Schematic cross-sectional view taken along the dotted line II'.

[0032] Figure 3is a schematic cross-sectional view showing a semiconductor package according to another embodiment of the present invention.

[0033] Figure 4 is a schematic cross-sectional view showing a semiconductor package according to still another embodiment of the present invention.

[0034] Figure 5 is a schematic cross-sectional view showing a semiconductor package according to still another embodiment of the present invention.

[0035] Figure 6 is a schematic top view of a multi-die semiconductor package according to one embodiment of the present invention.

[0036] Figure 7 It is along Figure 6 Schematic cross-sectional view taken along the dotted line II-II'. DETAILED DESCRIPTION

[0037] In the following detailed description of the embodiments of the present invention, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the disclosure may be practiced.

[0038] These embodiments are described in sufficient detail to enable those skilled in the art to practice them, and it is to be understood that other embodiments may be utilized and that mechanical, chemical, electrical, and procedural changes may be made without departing from the spirit and scope of the present disclosure. The following detailed description is, therefore, not to be construed as limiting, and the scope of the embodiments of the present invention is defined solely by the appended claims.

[0039] It will be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it can be directly on, directly connected to, or coupled to the other element or layer, or there can be elements or layers intervening between the two. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. Throughout this document, like numbers represent like elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0040] Figure 1 is a schematic top view of a semiconductor package according to an embodiment of the present invention. Figure 2 It is along Figure 1 Schematic cross-sectional view taken along the dotted line II'. Figure 1 and Figure 2As shown, semiconductor package 1 includes a carrier substrate 10 having an upper surface 10a and a bottom surface 10b. A semiconductor die 20 is directly mounted on upper surface 10a. Semiconductor die 20 has an active surface 20a, on which a plurality of input / output (I / O) pads 210 are distributed. According to an illustrative embodiment, semiconductor die 20 can be electrically connected to bond fingers 110 on upper surface 10a of carrier substrate 10 via bonding wires 31. According to an illustrative embodiment, bonding wires 31 can include copper, gold, silver, or any suitable conductive material. According to an illustrative embodiment, carrier substrate 10 can include a package substrate or an interposer substrate, but is not limited thereto.

[0041] According to the illustrative embodiment, insulating material 41 is applied to encapsulate bonding wire 31. For example, insulating material 41 may be applied in a rectangular or annular shape around or around the perimeter of semiconductor die 20, but is not limited thereto. Insulating material 41 may completely cover or envelop bonding wire 31 and may only be in direct contact with the peripheral area of active surface 20a. Thus, insulating material 41 may not cover the central area of active surface 20a. However, it should be understood that insulating material 41 may only cover a portion of bonding wire 31. The annular shape of insulating material 41 may be continuous or discontinuous. According to the illustrative embodiment, insulating material 41 may be in direct contact with the sidewalls of semiconductor die 20.

[0042] According to an illustrative embodiment, insulating material 41 may include, but is not limited to, a polymer, epoxy, or resin. Insulating material 41 applied to bonding wire 31 may be cured to provide additional mechanical support for bonding wire 31. Insulating material 41 secures bonding wire 31 and resists mold line sweeping during subsequent packaging. According to an illustrative embodiment, insulating material 40 may have low permittivity or a low dielectric constant (low-k). Insulating material 40 having low permittivity or a low dielectric constant may prevent short circuits and mitigate crosstalk between adjacent wires.

[0043] According to an illustrative embodiment, component 200 is mounted directly on insulating material 41, with protrusion 230 at a distance t between the edge of component 200 and contact point CP between component 200 and insulating material 41. Component 200 insulating element 41 is supported by insulating material 41 and bonding wires 31. For example, component 200 may be a dummy silicon die, a metal sheet, a ceramic die, a glass die, or a heat sink, but is not limited thereto. Component 200 may be attached to insulating material 41 and bonding wires 31 using adhesive layer 202. According to an illustrative embodiment, component 200 may have a rectangular shape that is coextensive with carrier substrate 10 and the shape of carrier substrate 10. Component 200 may completely overlap semiconductor die 20, for example, such that semiconductor die 20 is completely covered by component 200 when viewed from above.

[0044] According to an illustrative embodiment, component 200 may be a dummy die, such as a dummy silicon die, coated with a metal layer 204 on one side of the dummy silicon die. Metal layer 204 is a continuous metal layer (continuous metal layer), such as an aluminum layer, that completely covers the upper surface of component 200, thereby forming a lid of an EMI shielding structure, or an EMI shielding lid structure. The continuous metal layer may be, for example, a single, unbroken metal layer without any blocks or breaks. Metal layer 204 is electrically coupled to carrier substrate 10 via bonding wires 32. Bonding wires 32 are bonded to respective bond fingers 120 disposed on upper surface 10a of carrier substrate 10 and may be electrically coupled to ground plane 124. Thus, bonding wires 32 and metal layer 204 are grounded. Metal layer 204 and bonding wires 32 of component 200 form a Faraday cage that shields semiconductor die 20 from EMI interference. According to another embodiment, the bonding wires 32 may be bonded to a ground ring provided on the upper surface 10 a of the carrier substrate 10. The bonding wires 32 are arranged around the periphery of the die 20 to achieve better EMI interference effect. The ground ring may be a metal ring on the upper surface 10 a and electrically connected to the ground plane 124 to increase the EMI interference effect.

[0045] In the prior art, static electricity is often encountered during the manufacture of the package, and this static electricity often interferes with and damages the circuits and wiring in the package. For example, when applying a molding compound (such as molding compound 50) for packaging, static electricity on components such as the rails of the equipment used may damage the die, etc. In the embodiment of the present invention, an electromagnetic interference shielding structure consisting of a metal layer 204 and bonding wires 32 is first formed to protect the semiconductor die 20. Therefore, in subsequent processes, such as the process of forming the molding compound 50, static electricity emitted by external equipment can be shielded by the electromagnetic interference shielding structure, thereby avoiding or reducing electrostatic interference. In addition, the use of the present invention is advantageous because the component 200 and the bonding wires 32 can protect the semiconductor die 20 from ESD damage in the early stages of the package assembly process. In addition, after the package is manufactured, the electromagnetic interference shielding structure consisting of the metal layer 204 and the bonding wires 32 can also protect the semiconductor die 20 from EMI interference and ESD damage.

[0046] According to an illustrative embodiment, a spacer 700 may be provided between the component 200 and the semiconductor die 20. The spacer 700 may be adhered to the active surface 20a of the semiconductor die 20 using an adhesive layer 702. The spacer 700 may be, but is not limited to, a dummy die or any suitable material having a matching coefficient of thermal expansion (CTE). The thickness of the spacer 700 may be adjustable. In some embodiments, the spacer 700 may be thicker so that the component 200 is not in direct contact with the insulating material 41 and the bonding wire 31. In some embodiments, the spacer 700 may be omitted, such as Figure 3 The spacer 700 can help support the component 200 to increase the mechanical strength and stability of the semiconductor package structure; and the spacer 700 helps the die dissipate heat and provides additional rigidity to the package when the package expands thermally to suppress problems such as warping and deformation of the package.

[0047] According to an illustrative embodiment, molding compound 50 is formed on upper surface 10 a of carrier substrate 10 to seal or encapsulate bonding wires 31 and 32, insulating material 41, component 200, spacer 700, and semiconductor die 20. In an illustrative embodiment, molding compound 50 may include, but is not limited to, epoxy and filler. According to an illustrative embodiment, insulating material 41 may have the same epoxy composition as molding compound 50, but without filler or with a lower filler content. According to an illustrative embodiment, insulating material 41 and molding compound 50 have different compositions. According to an illustrative embodiment, insulating material 41 contains a halogen content of less than 50 ppm to prevent corrosion of bonding wires 31. After forming molding compound 50, connecting elements 60, such as solder balls, may be formed on bottom surface 10 b. Insulating material 41 and molding compound 50 are formed in different processes and using different formation methods. In this way, static electricity is reduced or avoided when forming the insulating material 41 (for example, by dispensing), thereby protecting the semiconductor die 20 ; and when forming the molding compound 50 , the electromagnetic interference shielding structure formed by the metal layer 204 and the bonding wire 32 protects the semiconductor die 20 .

[0048] Figure 4 FIG1 is a schematic cross-sectional view showing a semiconductor package according to another embodiment of the present invention, wherein similar layers, regions or components are represented by similar numbers or labels. Figure 4 As shown, semiconductor package 2 includes a carrier substrate 10 having an upper surface 10 a and a bottom surface 10 b. A semiconductor die 20 is mounted on upper surface 10 a. Semiconductor die 20 has an active surface 20 a on which a plurality of I / O pads 210 are distributed. According to an illustrative embodiment, semiconductor die 20 can be electrically connected to bond fingers 110 on upper surface 10 a of carrier substrate 10 via bonding wires 31. According to an illustrative embodiment, bonding wires 31 can comprise copper, gold, silver, or any other suitable conductive material. According to an illustrative embodiment, carrier substrate 10 can comprise a package substrate or an interposer substrate, but is not limited thereto.

[0049] According to an illustrative embodiment, insulating material 41 is applied to bonding wire 31. For example, insulating material 41 may be applied in a rectangular or annular shape around or around semiconductor die 20, but is not limited thereto. Insulating material 41 may completely cover bonding wire 31 and only directly contact the outer periphery of active surface 20a. Thus, insulating material 41 may not cover the central area of active surface 20a. However, it should be understood that insulating material 41 may only cover a portion of bonding wire 31. The annular insulating material 41 may be continuous or discontinuous. According to an illustrative embodiment, insulating material 41 may directly contact the sidewalls of semiconductor die 20.

[0050] According to an illustrative embodiment, insulating material 41 may include, but is not limited to, a polymer, epoxy, or resin. Insulating material 41, applied to bonding wire 31, may be cured to provide additional mechanical support for bonding wire 31. Insulating material 41 secures bonding wire 31 and resists molded lead sweeping during subsequent packaging. According to an illustrative embodiment, insulating material 41 has a low dielectric constant, or low-k, which can prevent short circuits and mitigate crosstalk between adjacent wires.

[0051] According to the illustrated embodiment, component 200 is mounted directly on insulating material 41, with protrusion 230 positioned at a distance t between the edge of component 200 and contact point CP between component 200 and insulating material 41. Insulating element 41 of component 200 is supported by insulating material 41 and bonding wires 31. Component 200 may be, for example, but is not limited to, a dummy silicon die, a metal sheet, a ceramic die, a glass die, or a heat sink. Component 200 may be attached to insulating material 41 and bonding wires 31 using adhesive layer 202. According to the illustrated embodiment, component 200 may have a rectangular shape coextensive with carrier substrate 10 and the shape of carrier substrate 10. Component 200 may completely overlap semiconductor die 20.

[0052] According to an illustrative embodiment, component 200 may be a dummy die, such as a dummy silicon die, that includes a metal layer 204 serving as an EMI shielding layer and an adhesive layer 202 on metal layer 204. Component 200 may be attached to insulating material 41 and bonding wires 31 using adhesive layer 202. Component 200 includes bonding pads (or rings) 220 disposed on an upper surface of component 200. Bonding wires 32 are bonded to bonding pads 220. Bonding pads 220 are electrically connected to metal layer 202 through conductive vias 222.

[0053] According to an illustrative embodiment, insulating material 42 may be applied to bond wire 32. For example, insulating material 42 may be applied in a rectangular or annular shape around insulating material 41 and bond wire 31. Insulating material 42 may completely cover bond wire 32 and directly contact active surface 20a, spacer 700, and the perimeter and bottom surface of component 200. It will be appreciated that insulating material 42 may only cover a portion of bond wire 31. The annular shape of insulating material 42 may be continuous or discontinuous. Insulating material 41 and insulating material 42 may have different compositions. Figure 4 The embodiment shown also has Figure 2 or Figure 3 The effect shown is to protect the semiconductor grain 20.

[0054] Figure 5FIG1 is a schematic cross-sectional view showing a semiconductor package according to another embodiment of the present invention, wherein the same layers, regions or components are represented by the same numbers or labels. Figure 5 As shown, semiconductor package 3 also includes a carrier substrate 10 having an upper surface 10a and a bottom surface 10b. According to the illustrative embodiment, carrier substrate 10 may include a package substrate or an interposer substrate, but is not limited thereto. Semiconductor die 20 is flip-chip mounted on upper surface 10a, with its active surface 20a coupled to upper surface 10a of carrier substrate 10 via a plurality of connecting elements 212. According to the illustrative embodiment, connecting elements 212 may include copper, gold, silver, or any other suitable conductive material. For example, connecting elements 212 may be copper pillars or copper bumps, but are not limited thereto.

[0055] According to an illustrative embodiment, component 200 is mounted directly on the rear surface 20b of semiconductor die 20. For example, component 200 can be a dummy silicon die, a metal sheet, a ceramic die, a glass die, or a heat sink, but is not limited thereto. Component 200 can be attached to semiconductor die 20 using an adhesive layer 202. According to an illustrative embodiment, component 200 can be a dummy die, such as a dummy silicon die, coated with a metal layer 204 on one side. Metal layer 204 is a continuous metal layer, such as an aluminum layer, that completely covers the upper surface of component 200, thereby forming a cover for the EMI shielding structure. Metal layer 204 is electrically coupled to carrier substrate 10 via bonding wires 32. Bonding wires 32 are bonded to individual bonding fingers 120 disposed on upper surface 10a of carrier substrate 10 and can be electrically coupled to ground plane 124. In one embodiment, bonding fingers 120 can also be a continuous, closed bonding ring or grounding ring disposed around the semiconductor die. Therefore, metal layer 204 is grounded. The metal layer 204 of the component 200 and the bonding wires 32 form a Faraday cage that shields the semiconductor die 20 from EMI interference. According to another embodiment, the bonding wires 32 can be bonded to a ground ring provided on the upper surface 10a of the carrier substrate 10. The bonding wires 32 are arranged around the periphery of the die 20 to achieve better EMI interference effect.

[0056] According to the illustrative embodiment, the bonding wire 32 may be applied to the insulating material 42. For example, the insulating material 42 may be applied in a rectangular or annular shape around the insulating material 41 and the bonding wire 31. The insulating material 42 may completely cover the bonding wire 32 and directly contact the perimeter and active surface 20a of the semiconductor die 20, the connecting element 212, and the perimeter of the component 200. It will be appreciated that the insulating material 42 may only cover the insulating material 42. The annular insulating material 42 may be continuous or discontinuous. The insulating material 42 may fill the gap between the active surface 20a of the semiconductor die 20 and the upper surface 10a of the carrier substrate 10. Thus, the conventional underfill dispensing process may be eliminated. Figure 5 The embodiment shown also has Figure 2 or Figure 3 or Figure 4 The effect shown is to protect the semiconductor grain 20. Figure 5 In the embodiment, the insulating material between the carrier substrate 10 and the semiconductor die 20 and the insulating material within the bonding wire 32 can be formed in the same process step, so the insulating material 42 in the two locations is integrated (or a single unit or integrally formed). The embodiment of the present invention can reduce the number of process steps and improve production efficiency.

[0057] Please refer to Figure 6 and Figure 7 , Figure 6 FIG. 4 is a three-dimensional top view of a multi-die semiconductor package according to an embodiment of the present invention. Figure 7 It is along Figure 6 Schematic cross-sectional view taken along the dotted line II-II'. Figure 6 and Figure 7 As shown, semiconductor package 4 includes a carrier substrate 10 having an upper surface 10a and a bottom surface 10b. According to the illustrative embodiment, carrier substrate 10 may include a package substrate or an interposer substrate, but is not limited thereto. A semiconductor die 20, such as a system-on-a-chip (SoC), is flip-chip mounted on upper surface 10a, with its active surface 20a coupled to upper surface 10a of carrier substrate 10 via a plurality of connecting elements 212. According to the illustrative embodiment, connecting elements 212 may include copper, gold, silver, solder, or any other suitable conductive material. For example, connecting elements 212 may be copper pillars or copper bumps, but are not limited thereto.

[0058] According to the illustrative embodiment, at least the memory die M1 is stacked and mounted on the rear surface 20b of the semiconductor die 20 by using the adhesive layer 81. For example, the memory die M1 may be a 4MB serial flash RAM die, but is not limited thereto. According to the illustrative embodiment, at least the memory die M2 may be stacked and mounted on the memory die M1 by using the adhesive layer 82. For example, the memory die M2 may be a 4MB pseudo SRAM die, but is not limited thereto. According to the illustrative embodiment, the memory die M1 includes a pad P1, which is electrically connected to the respective pads BF1 on the upper surface 10a of the carrier substrate 10 through a bonding wire W1. According to the illustrative embodiment, the memory die M2 includes a pad P2, which is electrically connected to the respective pads BF2 on the upper surface 10a of the carrier substrate 10 through a bonding wire W2. It should be understood that Figure 6 and Figure 7 The 3D stack configuration in is for illustration purposes only.

[0059] According to illustrative embodiments, an insulating material WF, such as a flowable resin with suitable fluidity, can be applied to the bonding wires W1 and W2. For example, the insulating material WF can be applied along the perimeter of the memory die M1 and the memory die M2. The insulating material WF can completely cover the bonding wires W1 and W2. It is understood that the insulating material WF can only cover a portion of the bonding wires W1 and W2. When the insulating material WF is applied to the bonding wires W1 and W2, the insulating material WF also flows into the space between the semiconductor die 20 and the carrier substrate 10 through a capillary effect, allowing the insulating material WF to surround and protect the connecting element 212. Compared to the prior art, since the traditional underfill process can be omitted, the bonding pads BF1 and BF2 on the upper surface 10a of the carrier substrate 10 can be positioned closer to the semiconductor die 20. As a result, the size of the semiconductor package 4 can be more compact. According to some embodiments, additional insulating material WF can be dispensed along the perimeter of the semiconductor die 20 to ensure that the gap between the semiconductor die 20 and the carrier substrate 10 is completely underfilled.

[0060] According to an illustrative embodiment, a molding compound MC is formed on the upper surface 10a of the carrier substrate 10 to encapsulate the insulating material WF, the memory die M1, the memory die M2, the semiconductor die 20, and the upper surface 10a of the insulating material WF. According to an illustrative embodiment, the molding compound MC may include an epoxy resin and a filler material, but is not limited thereto. According to an illustrative embodiment, the insulating material WF may have the same epoxy composition as the molding compound MC, but without the filler material or with a lower content of the filler material. According to an illustrative embodiment, the insulating material WF and the molding compound MC have different compositions. According to an illustrative embodiment, the insulating material WF contains a halogen content of less than 50 ppm to prevent corrosion of the bonding wires W1 and W2. After the molding compound MC is formed, a connecting element 60 such as a solder ball may be formed on the bottom surface 10b. In the prior art, the insulating material located between the carrier substrate and the semiconductor die and the insulating material located within the bonding wires W1 and W2 are formed in different process steps, so that the process steps are more and the process is more complicated. In the present invention, Figure 6 and Figure 7 In this embodiment, the insulating material between the carrier substrate 10 and the semiconductor die 20 and the insulating material within the bonding wires W1 and W2 can be formed in the same process step, so the insulating material WF of both is integral (or a single unit or integrally formed). This embodiment of the present invention can reduce process steps, eliminate the conventional underfill dispensing process (e.g., the conventional underfill process between the carrier substrate and the semiconductor die), and improve production efficiency.

[0061] Those skilled in the art will readily appreciate that many modifications and variations of the apparatus and method can be made while maintaining the teachings of the present invention.Accordingly, the above disclosure should be interpreted as being limited only by the metes and bounds of the appended claims.

Claims

1. A semiconductor package, characterized in that: include: a carrier substrate having an upper surface; a semiconductor die mounted on the upper surface; a first bonding wire connecting the semiconductor die to the carrier substrate; a first insulating material encapsulating the first bonding wire; a component mounted on the first insulating material, wherein the component includes a metal layer; a spacer between the component and the semiconductor die; a second bonding wire connecting the metal layer of the component to the carrier substrate, wherein the metal layer and the second bonding wire form an electromagnetic interference shielding structure; a second insulating material encapsulating the second bonding wire; the second insulating material completely covering the second bonding wire and in direct contact with the active surface of the semiconductor die, the spacer, the periphery of the component, and the bottom surface of the component; the second insulating material having a different composition than the first insulating material; and a molding compound covering the upper surface of the carrier substrate and encapsulating the semiconductor die, the component, the first bonding wire, the second bonding wire, the first insulating material, and the second insulating material; the component is attached to the first insulating material via a first adhesive layer on the metal layer; The spacer is attached to the semiconductor die by a second adhesion layer.

2. The semiconductor package according to claim 1, wherein The metal layer is a continuous metal layer that completely covers the surface of the component to form a cover of the electromagnetic interference shielding structure.

3. The semiconductor package according to claim 1, wherein The second bond wire is electrically coupled to a ground ring on the upper surface of the carrier substrate.

4. The semiconductor package according to claim 1, wherein The second bonding wire and the metal layer are grounded.

5. The semiconductor package according to claim 1, wherein The first insulating material is disposed in a rectangular ring shape around the semiconductor die.

6. The semiconductor package according to claim 1, wherein The first insulating material and the molding compound have different compositions.

7. The semiconductor package according to claim 1, wherein The first insulating material completely covers the first bonding wire and is in direct contact with a peripheral region of the active surface of the semiconductor die.

8. The semiconductor package according to claim 1, wherein The second insulating material completely covers the second bond wire and is in direct contact with the perimeter and bottom surface of the component.

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