Method for forming microelectronic device and related microelectronic device, memory device and electronic system

Abstract

This patent application relates to a method for forming a microelectronic device, and to related microelectronic devices, memory devices, and electronic systems. A method for forming a microelectronic device includes forming a spacer structure having a rectangular ring horizontal cross-sectional shape above a transistor, and a portion of the spacer structure horizontally overlaps with the drain region of the transistor. A masking structure is formed above the spacer structure and the transistor, and the masking structure exhibits an opening therein, and the opening horizontally overlaps with the drain region of the transistor and the portion of the spacer structure. The masking structure and the portion of the spacer structure are used as an etching mask to remove a portion of an isolation structure covering the drain region of the transistor to form a trench, and the trench extends vertically through the isolation structure to reach the drain region of the transistor. A drain contact structure is formed in the trench in the isolation structure.

Description

[0001] Priority claim

[0002] This application claims priority to the filing date of U.S. patent application serial number 16 / 543,799 filed on August 19, 2019 for "Methods of Forming Microelectronic Devices, and Related Microelectronic Devices, Memory Devices, and Electronic Systems." Technical Field

[0003] Embodiments of the present disclosure relate to the field of microelectronic device design and manufacturing. More specifically, embodiments of the present disclosure relate to methods of forming microelectronic devices and related microelectronic devices, memory devices, and electronic systems. Background Art

[0004] Microelectronic device designers generally desire to increase the integration level or density of features within a microelectronic device by reducing the size of individual features and reducing the spacing distance between adjacent features. In addition, microelectronic device designers generally desire to design an architecture that is not only compact but also provides performance advantages and simplifies design.

[0005] A relatively common microelectronic device is a memory device. A memory device may include a memory array having a plurality of memory cells arranged in a grid pattern. One type of memory cell is a dynamic random access memory (DRAM). In the simplest design configuration, a DRAM cell includes an access device (such as a transistor) and a storage device (such as a capacitor). Modern applications of memory devices may utilize a large number of DRAM unit cells arranged in an array of rows and columns. DRAM cells may be electrically accessed via bit lines and word lines arranged along the rows and columns of the array.

[0006] Reducing the size and spacing of features in microelectronic devices (e.g., memory devices, such as DRAM devices) places increasing demands on methods for forming features in microelectronic devices. For example, one of the limiting factors in the continued shrinkage of microelectronic devices is the resistance of contact structures associated therewith. As used herein, a "contact structure" of a microelectronic device refers to a structure that facilitates a conductive path between at least two other features (e.g., structures, regions) of a microelectronic device. As the size of features in a microelectronic device decreases, the size of the contact structures associated therewith also decreases, resulting in an increase in contact resistance. The increase in contact resistance reduces the drive current of the microelectronic device, which may have an adverse effect on device performance.

[0007] Therefore, there is a need for new, simple, and cost-effective methods of forming microelectronic devices (eg, memory devices) and new microelectronic devices and electronic systems that alleviate the above-mentioned problems. Summary of the invention

[0008] Embodiments of the present disclosure relate to methods for forming microelectronic devices including transistors, and to related microelectronic devices, memory devices, and electronic systems. In some embodiments, a method for forming a microelectronic device includes forming a spacer structure having a rectangular ring horizontal cross-sectional shape above a transistor, a portion of the spacer structure horizontally overlapping with a drain region of the transistor. A masking structure is formed above the spacer structure and the transistor, the masking structure exhibiting an opening therein, the opening horizontally overlapping with the drain region of the transistor and the portion of the spacer structure. The masking structure and the portion of the spacer structure are used as an etching mask to remove a portion of an isolation structure covering the drain region of the transistor to form a trench, the trench extending vertically through the isolation structure to reach the drain region of the transistor. A drain contact structure is formed in the trench in the isolation structure.

[0009] In another embodiment, a microelectronic device includes a transistor, a source contact structure, and a drain contact structure. The transistor includes: a gate structure; a source region, the source region is horizontally adjacent to a first side of the gate structure; a drain region, the drain region is horizontally adjacent to a second side of the gate structure opposite to the first side of the gate structure; and a channel region, the channel region is vertically located below the gate structure and horizontally between the source region and the drain region. The source contact structure is horizontally adjacent to the first side of the gate structure of the transistor and contacts the source region of the transistor. The drain contact structure is horizontally adjacent to the second side of the gate structure of the transistor and contacts the drain region of the transistor. The drain contact structure is substantially horizontally aligned with the source contact structure and exhibits a horizontal area greater than or equal to the horizontal area of ​​the source contact structure.

[0010] In another embodiment, a memory device includes: a memory cell operably coupled to a bit line and a word line; and a memory controller operably coupled to the memory cell. The memory controller includes a readout device, the readout device including a transistor, a source contact structure contacting a source region of the transistor, and a drain contact structure contacting a drain region of the transistor. The length of the drain contact structure is greater than or equal to the length of the source contact structure.

[0011] In still other embodiments, a method includes forming a spacer structure in a ring shape over a transistor, the transistor including a first conductive doping region and a second conductive doping region and a gate structure, the gate structure being located over a channel region between the first conductive doping region and the second conductive doping region, a portion of the spacer structure overlapping the first conductive doping region. A masking structure is formed over the spacer structure and the transistor, the masking structure exhibiting an opening therein, the opening overlapping the first conductive doping region and the portion of the spacer structure. The masking structure and the portion of the spacer structure are used as an etching mask to remove a portion of an isolation structure covering the first conductive doping region to form a trench, the trench exposing a portion of the first conductive doping region. A first contact structure is formed through the trench, the first contact structure contacting the portion of the first conductive doping region.

[0012] In still another embodiment, an electronic system includes: an input device; an output device; a processor device, the processor device being operably coupled to the input device and the output device; and a memory device, the memory device being operably coupled to the processor device. The memory device includes a first transistor, a first source contact structure, a first drain contact structure, a second transistor, a second source contact structure, and a second drain contact structure. The first source contact structure is horizontally adjacent to a first side of a first gate structure of the first transistor and contacts a first source region of the first transistor. The first drain contact structure is horizontally adjacent to a second side of the first gate structure of the first transistor and contacts a first drain region of the first transistor. The second transistor is horizontally adjacent to the first transistor. The second source contact structure is horizontally adjacent to a first side of a second gate structure of the second transistor and contacts a second source region of the second transistor. The second drain contact structure is horizontally adjacent to a second side of the second gate structure of the second transistor and contacts a second drain region of the second transistor. The second drain contact structure is horizontally adjacent to the first drain contact structure in a first direction and is substantially horizontally aligned with the first drain contact structure in a second direction perpendicular to the first direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figures 1A to 5B is a simplified partial top view showing a method of forming a microelectronic device according to an embodiment of the present disclosure ( Figure 1A , 2A , 3A, 4A and 5A) and simplified partial cross-sectional views ( Figure 1B , 2B , 3B, 4B and 5B).

[0014] Figures 6A to 6Bis a simplified partial top view showing a method of forming a microelectronic device according to another embodiment of the present disclosure ( Fig. 6A ) and simplified partial cross-sectional views ( Figure 6B ).

[0015] Figure 7 is a functional block diagram of a memory device according to an embodiment of the present disclosure.

[0016] Figure 8 is a schematic block diagram of an electronic system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0017] The following description provides specific details, such as material composition, shape and size, so as to provide a comprehensive description of the embodiments of the present disclosure. However, it will be appreciated by those skilled in the art that the embodiments of the present disclosure may be practiced without adopting these specific details. In fact, the embodiments of the present disclosure may be practiced in conjunction with conventional microelectronic device manufacturing techniques adopted in the industry. In addition, the description provided below does not form a complete process flow for manufacturing a microelectronic device (e.g., a memory device, such as a DRAM device). The structure described below does not form a complete microelectronic device. Only those process actions and structures necessary for understanding the embodiments of the present disclosure are described in detail below. Other actions of forming a complete microelectronic device by the structure may be performed by conventional manufacturing techniques.

[0018] The drawings presented herein are for illustrative purposes only and are not intended to be actual views of any particular material, component, structure, device or system. Changes in the shapes depicted in the drawings due to, for example, manufacturing techniques and / or tolerances should be expected. Therefore, the embodiments described herein should not be interpreted as being limited to the specific shapes or zones shown, but rather include shape deviations resulting from, for example, manufacturing. For example, a zone shown or described as a frame may have rough and / or nonlinear features, and a zone shown or described as a circle may include some rough and / or linear features. In addition, the sharp angles shown may be rounded, and vice versa. Therefore, the zones shown in the figures are schematic in nature, and their shapes are not intended to represent the precise shapes of the zones and do not limit the scope of the claims of the present invention. The drawings are not necessarily drawn to scale. In addition, common elements between the figures may retain the same digital identifiers.

[0019] As used herein, "memory device" means and includes a microelectronic device that exhibits, but is not limited to, memory functionality.

[0020] As used herein, the term "configured" refers to the size, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one device that facilitates one or more of the structure and device to operate in a predetermined manner.

[0021] As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0022] As used herein, "and / or" includes any and all combinations of one or more of the associated listed items.

[0023] As used herein, the terms "longitudinal", "vertical", "lateral", and "horizontal" are referenced to a principal plane of a substrate (e.g., a substrate material, a substrate structure, a substrate configuration, etc.) in or on which one or more structures and / or features are formed and are not necessarily defined by the Earth's gravitational field. A "lateral" or "horizontal" direction is a direction substantially parallel to the principal plane of the substrate, while a "longitudinal" or "vertical" direction is a direction substantially perpendicular to the principal plane of the substrate. The principal plane of a substrate is defined by a surface of the substrate having a relatively larger area than other surfaces of the substrate.

[0024] As used herein, "vertically adjacent" or "longitudinally adjacent" features (e.g., regions, structures, devices) mean and include features that are positioned vertically proximate (e.g., vertically closest) to each other. Additionally, "horizontally adjacent" or "laterally adjacent" features (e.g., regions, structures, devices) as used herein mean and include features that are positioned horizontally proximate (e.g., horizontally closest) to each other.

[0025] As used herein, spatially relative terms such as "under", "below", "lower", "bottom", "above", "upper", "top", "front", "back", "left", "right", etc. may be used to describe the relationship between an element or feature and another or more elements or features as shown in the accompanying drawings for ease of description. Unless otherwise specified, spatially relative terms are intended to cover different orientations in addition to the orientation of the materials depicted in the figures. For example, if the material in the figure is inverted, the elements described as being "under" or "under" or "below" or "bottom" of other elements or features will be oriented as being "above" or "top" of the other elements or features. Therefore, the term "below" may cover both the upward orientation and the downward orientation, depending on the context in which the term is used, which will be apparent to one of ordinary skill in the art. The material may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped, etc.) and the spatially relative descriptors used herein may be interpreted accordingly.

[0026] The term "substantially" used herein with respect to a given parameter, property, or condition means and encompasses the extent to which one of ordinary skill in the art would understand that a given parameter, property, or condition is met with a certain degree of variance (e.g., variance within an acceptable tolerance). For example, depending on a particular parameter, property, or condition being substantially met, the parameter, property, or condition may be at least 90.0% met, at least 95.0% met, at least 99.0% met, at least 99.9% met, or even 100.0% met.

[0027] As used herein, "about" or "approximately" with respect to a numerical value of a particular parameter includes the numerical value and a certain degree of difference relative to the numerical value that will be understood by those of ordinary skill in the art as being within an acceptable tolerance for the particular parameter. For example, "about" or "approximately" with respect to a numerical value may include additional numerical values ​​that are within the range of 90.0% to 110.0% of the numerical value, such as within the range of 95.0% to 105.0% of the numerical value, within the range of 97.5% to 102.5% of the numerical value, within the range of 99.0% to 101.0% of the numerical value, within the range of 99.5% to 100.5% of the numerical value, or within the range of 99.9% to 100.1% of the numerical value.

[0028] Unless the context indicates otherwise, the materials described herein may be formed by any suitable process, including but not limited to spin coating, blanket coating, chemical vapor deposition ("CVD"), atomic layer deposition ("ALD"), plasma enhanced ALD, physical vapor deposition ("PVD") (including sputtering, evaporation, ionized PVD and / or plasma enhanced CVD), or epitaxial growth. One of ordinary skill in the art may select the technique for depositing or growing the material depending on the specific material to be formed. In addition, unless the context indicates otherwise, the materials described herein may be removed by any suitable process, including but not limited to etching (e.g., dry etching, wet etching, vapor etching), ion milling, grinding planarization, development, or other known methods.

[0029] Figures 1A to 5B is a simplified local top view ( Figure 1A , 2A , 3A, 4A and 5A) and simplified partial cross-sectional views ( Figure 1B , 2B, 3B, 4B and 5B), show embodiments of methods of forming microelectronic device structures (e.g., memory structures) of microelectronic devices (e.g., memory devices such as DRAM devices, RRAM devices, conductive bridge RAM devices, MRAM devices, PCM devices, PCRAM devices, STTRAM devices, oxygen vacancy-based memory devices, programmable conductor memory devices). From the description provided below, it will be apparent to those of ordinary skill in the art that the methods described herein can be used in a variety of devices. In other words, the methods of the present disclosure can be used whenever it is desired to form a microelectronic device.

[0030] Common Reference Figure 1A and 1B ( Figure 1B Depicted Figure 1A ), a microelectronic device structure 100 may be formed, the microelectronic device structure including a substrate structure 102, a gate structure 108 located above the substrate structure 102, and an isolation structure 110 located above the substrate structure 102 and horizontally between the gate structures 108 ( Figure 1B ), a first masking structure 116 ( Figure 1B ) and a second masking structure 118 ( Figure 1B The following further describes in detail the substrate structure 102, the gate structure 108, the isolation structure 110, the first masking structure 116 and the second masking structure 118, and the microelectronic device structure 100. Figure 1A and 1B For clarity and ease of understanding of the drawings and related descriptions, Figure 1A and 1B One of the figures is not depicted Figure 1A and 1B As a non-limiting example, Figure 1A Omitted Figure 1B The first masking structure 116 and the isolation structure 110 are shown in the figure to more clearly illustrate the features of the microelectronic device structure 100 that are vertically located below the first masking structure 116 and the isolation structure 110.

[0031] The base structure 102 may include any base material or configuration on which additional materials may be formed. The base structure 102 may include a semiconductor structure (e.g., a semiconductor substrate); a base semiconductor material on a support structure; a structure comprising one or more of different materials, structures, and regions; another base material; or another configuration. In some embodiments, the base structure 102 is formed of and comprises a semiconductor material. The base structure 102 may, for example, include a conventional silicon substrate or other bulk substrate comprising a semiconductor material layer. As used herein, the term "bulk substrate" means and includes not only silicon wafers, but also silicon-on-insulator (SOI) substrates, such as silicon-on-sapphire (SOS) substrates and silicon-on-glass (SOG) substrates, epitaxial silicon layers on a base semiconductor foundation, and other semiconductor or optoelectronic materials, such as silicon germanium, germanium, gallium arsenide, gallium nitride, and indium phosphide. One or more materials of the base structure 102 may be doped or undoped.

[0032] like Figure 1B As shown, the base structure 102 may include a conductive doped region 104 and a channel region 106. The conductive doped region 104 may include a drain region 104A and a source region 104B. The drain region 104A, the source region 104B, and the channel region 106 may each be vertically positioned (e.g., in the Z direction) close to the highest vertical boundary of the base structure 102, and the channel region 106 may be horizontally interposed (e.g., in the X direction) between the drain region 104A and the source region 104B. Each drain region 104A may be separated from the source region 104B that is horizontally closest (e.g., in the X direction) to the drain region by one of the channel regions 106. Figure 1BAs depicted, in some embodiments, a single pair of channel regions (e.g., only two channel regions) in channel region 106 is horizontally interposed between a single pair of drain regions (e.g., only two drain regions) in drain region 104A, and a single (e.g., only one) source region 104B is horizontally interposed between the single pair of channel regions in channel region 106. Such a configuration may be employed in embodiments where a single (e.g., only one) source region 104B is shared by two (2) horizontally adjacent transistors. Within such a configuration, some horizontally adjacent drain regions 104A may be free of any channel region in channel region 106 and any source region in source region 104B horizontally interposed between the channel regions. In further embodiments, a single pair of channel regions (e.g., only two channel regions) in the channel region 106 is horizontally interposed between a single pair of drain regions (e.g., only two drain regions) in the drain region 104A, and a single pair of source regions (e.g., only two source regions) in the source region 104B is horizontally interposed between the single pair of channel regions in the channel region 106. Such a configuration may be employed in embodiments where the source region 104B is not shared by horizontally adjacent transistors. Within such a configuration, some horizontally adjacent drain regions 104A may not contain any channel region in the channel region 106 and any source region in the source region 104B horizontally interposed between the channel regions, and some horizontally adjacent source regions 104B may not contain any channel region in the channel region 106 and any source region in the source region 104B horizontally interposed between the channel regions.

[0033] The conductive doped regions 104 (e.g., drain regions 104A, source regions 104B) of the substrate structure 102 may be doped with any one or more desired dopants. In some embodiments, the conductive doped regions 104 are doped with at least one P-type dopant (e.g., one or more of boron, aluminum, and gallium). Thus, the conductive doped regions 104 may exhibit a lack of valence electrons (commonly referred to as "holes"). In some such embodiments, one or more regions of the substrate structure 102 surrounding the conductive doped regions 104, such as the channel region 106, may be doped with at least one N-type dopant (e.g., one or more of phosphorus, arsenic, antimony, and bismuth). In other embodiments, the conductive doped regions 104 are doped with at least one N-type dopant (e.g., one or more of phosphorus, arsenic, antimony, and bismuth). Thus, the conductive doped regions 104 may exhibit an excess of free electrons. In some such embodiments, one or more regions of the substrate structure 102 surrounding the conductive doped regions 104, such as the channel region 106, may be doped with at least one P-type dopant (e.g., one or more of boron, aluminum, and gallium).

[0034] Continue to refer Figure 1B, a shallow trench isolation (STI) structure 105 may be horizontally interposed between horizontally adjacent drain regions 104A of the base structure 102 (e.g., in the X direction). The STI structure 105 may vertically extend from an upper vertical boundary of the base structure 102 to a lower vertical boundary of the drain region 104A of the base structure 102 (e.g., in the Z direction) or extend below the lower vertical boundary. The STI structure 105 may be formed of at least one dielectric material and include at least one dielectric material, such as one or more of the following: at least one dielectric oxide material (e.g., silicon oxide (SiO x ), phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, aluminum oxide (AlO x ), hafnium oxide (HfO x ), niobium oxide (NbO x ), titanium oxide (TiO x )、ZrO x ), tantalum oxide (TaO x ) and magnesium oxide (MgO x ), at least one dielectric nitride material (e.g., silicon nitride (SiN y )), at least one dielectric oxynitride material (e.g., silicon oxynitride (SiO x N y )) and at least one dielectric carbon oxynitride material (e.g., silicon carbon oxynitride (SiO x C z N y )). The formula herein includes one or more of "x", "y" and "z" (e.g., SiO x 、AlO x , HfO x 、NbO x 、TiO x 、SiN y 、SiO x N y 、SiO x C z N y) represents a material having, for each atom of an element (e.g., Si, Al, Hf, Nb, Ti), an average ratio of "x" atoms of another element, "y" atoms of yet another element, and "z" atoms of yet another element (if any). Since the formula represents a relative atomic ratio rather than a strict chemical structure, the STI structure 105 may include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, and the values ​​of "x", "y" and "z" (if any) may be integers or may be non-integers. The term "non-stoichiometric compound" as used herein means and includes compounds whose elemental composition cannot be represented by a ratio of well-defined natural numbers and violates the law of definite ratios. Each of the STI structures 105 may individually include a substantially uniform distribution or a substantially non-uniform distribution of the at least one dielectric material. In some embodiments, each of the STI structures 105 exhibits a substantially uniform distribution of dielectric material. In other embodiments, at least one of the STI structures 105 exhibits a substantially non-uniform distribution of at least one dielectric material. One or more of STI structures 105 may be formed of and include a stack (eg, a stack) of at least two different dielectric materials, for example. In some embodiments, STI structure 105 is formed of and includes silicon dioxide (SiO2).

[0035] Still reference Figure 1B , the gate structure 108 may be vertically located above the channel region 106 of the base structure 102 (e.g., in the Z direction). The gate structure 108 may be horizontally aligned with the channel region 106 (e.g., in the X direction). Each of the gate structures 108 may be individually horizontally located (e.g., in the X direction) between one of the drain regions 104A of the base structure 102 and one of the source regions 104B of the base structure 102 that is horizontally closest (e.g., in the X direction) to the one of the drain regions 104A. In some embodiments, such as in embodiments where a single (e.g., only one) source region 104B is horizontally located between a single pair of channel regions (e.g., only two channel regions) in the channel region 106, the horizontal distance (e.g., in the X direction) between some gate structures 108 that are horizontally adjacent to each other may be different from (e.g., smaller than, larger than) the horizontal distance (e.g., in the X direction) between other gate structures 108 that are horizontally adjacent to each other. For example, as Figure 1BAs shown, the horizontal distance (e.g., in the X direction) between two (2) gate structures in the gate structure 108 that are horizontally separated from each other by one (1) source region 104B of the base structure 102 may be smaller than the distance (e.g., in the X direction) between two (2) other gate structures in the gate structure 108 that are horizontally separated from each other by two (2) drain regions 104A of the base structure 102. In other embodiments, the horizontally adjacent gate structures 108 of the microelectronic device structure 100 may all be horizontally separated from each other (e.g., in the X direction) by substantially the same distance.

[0036] The gate structure 108 may be formed of and include at least one conductive material, such as a metal (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al)), an alloy (e.g., Co-based alloy, F-based alloy), or a plurality of other conductive materials. The gate structure 108 may include a substantially uniform distribution of the conductive material, or may include a substantially non-uniform distribution of the conductive material. The term "uniform distribution" as used herein means that the amount of the material does not vary across different portions of the structure (e.g., different horizontal portions, different vertical portions). In contrast, the term "non-uniform distribution" as used herein means that the amount of the material varies across different portions of the structure. If gate structures 108 exhibit a substantially non-uniform distribution of conductive material, the amount of conductive material may vary stepwise (e.g., abruptly) across different portions of gate structures 108, or may vary continuously (e.g., gradually, such as linearly, parabolically). In some embodiments, gate structures 108 each exhibit a substantially uniform distribution of conductive material. In further embodiments, one or more (e.g., each) of gate structures 108 exhibit a substantially non-uniform distribution of at least one conductive material. One or more of gate structures 108 may, for example, be formed of and include a stack of at least two different conductive materials.

[0037] Continue to refer Figure 1B , the isolation structure 110 may be horizontally interposed between the gate structures 108 (e.g., in the X direction), and may be vertically located above the conductive doped regions 104 (e.g., drain regions 104A, source regions 104B) of the base structure 102 (e.g., in the Z direction). The isolation structures 110 may horizontally alternate with the gate structures 108 (e.g., in the X direction), and may be horizontally aligned with the conductive doped regions 104 of the base structure 102 (e.g., in the X direction). The isolation structures 110 may horizontally extend from and between horizontal boundaries of horizontally adjacent gate structures 108, and may vertically extend from an upper boundary of the base structure 102 to a lower boundary of the first masking structure 116. The width of the isolation structure 110 (e.g., in the X direction) may correspond to (e.g., be the same as) the horizontal distance between horizontally adjacent gate structures 108 (e.g., in the X direction). Therefore, in some embodiments, such as embodiments in which a single (e.g., only one) source region 104B is horizontally interposed between a single pair (e.g., only two) of channel regions in the channel regions 106, the widths (e.g., in the X direction) of some of the isolation structures 110 may be different (e.g., smaller, larger) than the widths (e.g., in the X direction) of other isolation structures in the isolation structures 110. For example, Figure 1B As shown, the width of one isolation structure in the isolation structure 110 between two (2) gate structures in the gate structure 108 that are horizontally separated from each other by one (1) source region in the source region 104B of the base structure 102 may be smaller than the width of another isolation structure in the isolation structure 110 between two (2) other gate structures in the gate structure 108 that are horizontally separated from each other by two (2) drain regions in the drain region 104A of the base structure 102. In other embodiments, horizontally adjacent isolation structures 110 of the microelectronic device structure 100 may all be horizontally separated from each other (e.g., in the X direction) by substantially the same distance.

[0038] The isolation structure 110 may be formed of and include at least one dielectric material, such as one or more of the following: at least one dielectric oxide material (e.g., SiO x , phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlO x , HfO x 、NbO x 、TiO x 、ZrO x 、TaO x and MgO x one or more of the above), at least one dielectric nitride material (e.g., SiN y ), at least one dielectric oxynitride material (e.g., SiO xN y ) and at least one dielectric carbon oxynitride material (e.g., SiO x C z N y ). Each of the isolation structures 110 may individually include a substantially uniform distribution or a substantially non-uniform distribution of the at least one dielectric material. In some embodiments, each of the isolation structures 110 exhibits a substantially uniform distribution of the dielectric material. In other embodiments, at least one of the isolation structures 110 exhibits a substantially non-uniform distribution of the at least one dielectric material. One or more of the isolation structures 110 may, for example, be formed of and include a stack (e.g., a laminate) of at least two different dielectric materials. In some embodiments, each of the isolation structures 110 is formed of and includes SiO2.

[0039] Continue to refer Figure 1B , the microelectronic device structure 100 can further include a gate dielectric structure 112 vertically positioned between the gate structure 108 and the channel region 106 of the base structure 102 (e.g., in the Z direction). The gate dielectric structure 112 can extend horizontally from and between horizontal boundaries of horizontally adjacent gate structures 108 (e.g., in the X direction). The gate dielectric structure 112 can extend vertically from a lower vertical boundary of the gate structure 108 to an upper vertical boundary of the channel region 106 of the base structure 102. The gate dielectric structure 112 can be formed to exhibit any desired height (e.g., a vertical thickness in the Z direction), such as less than or equal to about Less than or equal to approximately Less than or equal to approximately or less than or equal to approximately In some embodiments, each of the gate dielectric structures 112 may be formed to have a height of about To date Height within range.

[0040] The gate dielectric structure 112 may be formed of and include at least one dielectric material, such as one or more of the following: at least one oxide dielectric material (e.g., SiO x 、AlO x , one or more of phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass), at least one nitride dielectric material (e.g., SiN y ), at least one low-K dielectric material (e.g., silicon oxycarbide (SiO x C y ), silicon oxynitride (SiO x N y), hydrogenated silicon oxycarbide (SiC x O y H z ) and silicon oxycarbonitride (SiO x C z N y ) and at least one high-K dielectric material (e.g., HfO x and ZrO x In some embodiments, the gate dielectric structures 112 may include one or more of the above-described dielectric materials. Each of the gate dielectric structures 112 may individually include a substantially uniform distribution or a substantially non-uniform distribution of the at least one dielectric material. In some embodiments, each of the gate dielectric structures 112 exhibits a substantially uniform distribution of the dielectric material. In other embodiments, at least one of the gate dielectric structures 112 exhibits a substantially non-uniform distribution of the at least one dielectric material. In some embodiments, the gate dielectric structure 112 is formed of and includes SiO2.

[0041] like Figure 1B As shown, the gate structure 108, the gate dielectric structure 112, and the conductive doped region 104 (including the drain region 104A and the source region 104B) and the channel region 106 of the substrate structure 102 can form transistors 115 of the microelectronic device structure 100. Each of the transistors 115 can include one of the gate structures 108, one of the gate dielectric structures 112, one of the channel regions 106, one of the drain regions 104A, and one of the source regions 104B. Some of the transistors 115 that are horizontally adjacent (e.g., in the X direction) can share a single (e.g., only one) source region 104B of the substrate structure 102 with each other. For example, as Figure 1B As depicted, the microelectronic device structure 100 may include transistor pairs 117 that each include two (2) horizontally adjacent transistors 115 that share a single source region 104B of the base structure 102. In further embodiments, the transistors 115 of the microelectronic device structure 100 may not share a source region 104B of the base structure 102 with each other.

[0042] Continue to refer Figure 1B , the microelectronic device structure 100 can further include a dielectric cap structure 114 vertically positioned between the gate structure 108 and the first masking structure 116 (e.g., in the Z direction). The dielectric cap structure 114 can extend horizontally from and between horizontal boundaries of horizontally adjacent gate structures 108 (e.g., in the X direction). The dielectric cap structure 114 can extend vertically from an upper vertical boundary of the gate structure 108 to a lower vertical boundary of the first masking structure 116. The dielectric cap structure 114 can be formed to exhibit any desired height (e.g., a vertical thickness in the Z direction), such as less than or equal to about 150 angstroms. Less than or equal to approximately Less than or equal to approximately or less than or equal to approximately In some embodiments, each of the dielectric cap structures 114 may be formed to have a height of about To date Height within the range. Figure 1A As shown, the upper boundary of the dielectric capping structure 114 may be substantially coplanar with the upper boundary of the isolation structure 110. In other embodiments, the upper boundary of the dielectric capping structure 114 may be vertically offset from (eg, vertically below, vertically above) the upper boundary of the isolation structure 110.

[0043] The dielectric cap structure 114 may be formed of and include at least one dielectric material, such as one or more of the following: at least one dielectric oxide material (e.g., SiO x , phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlO x , HfO x 、NbO x 、TiO x 、ZrO x 、TaO x and MgO x one or more of the above), at least one dielectric nitride material (e.g., SiN y ), at least one dielectric oxynitride material (e.g., SiO x N y ), at least one dielectric carbon oxynitride material (e.g., SiO x C z N y ) and amorphous carbon. The isolation structure 110 can be selectively etchable relative to the dielectric cap structure 114. As used herein, a material is "selectively etchable" relative to another material if the etch rate of the material is at least about three times (3x), such as five times (5x), about ten times (10x), about twenty times (20x), or about forty times (40x) the etch rate of the other material. In some embodiments, the dielectric cap structure 114 is formed of and includes silicon nitride (Si3N4).

[0044] Still reference Figure 1B The microelectronic device structure 100 may further include a sidewall spacer structure 113 horizontally positioned between the gate structure 108 and the isolation structure 110 (eg, in the X direction). Figure 1BAs shown, the sidewall spacer structure 113 can be formed on the sidewalls of the gate structure 108, the gate dielectric structure 112, and the dielectric capping structure 114. The sidewall spacer structure 113 can extend horizontally (e.g., in the X direction) from the sidewalls of the gate structure 108, the gate dielectric structure 112, and the dielectric capping structure 114 to the isolation structure 110. In addition, the sidewall spacer structure 113 can extend from or near the upper vertical boundary of the dielectric capping structure 114 to or near the lower vertical boundary of the gate dielectric structure 112 (e.g., in the Z direction).

[0045] The sidewall spacer structure 113 may be formed of and include at least one dielectric material, such as one or more of the following: at least one dielectric oxide material (e.g., SiO x , phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlO x , HfO x 、NbO x 、TiO x 、ZrO x 、TaO x and MgO x one or more of the above), at least one dielectric nitride material (e.g., SiN y ), at least one dielectric oxynitride material (e.g., SiO x N y ), at least one dielectric carbon oxynitride material (e.g., SiO x C z N y ) and amorphous carbon. The isolation structure 110 may be selectively etchable relative to the sidewall spacer structure 113. In some embodiments, the sidewall spacer structure 113 is formed of and includes Si3N4.

[0046] Continue to refer Figure 1B , the first masking structure 116 may be disposed on the gate structure 108 and the isolation structure 110. Figure 1B As shown, first masking structure 116 can be formed on the upper surface of isolation structure 110 and dielectric cap structure 114. First masking structure 116 can be formed on or above gate structure 108 and isolation structure 110 at any desired height (e.g., vertical thickness in the Z direction). The height of first masking structure 116 can depend at least in part on the height and material composition of isolation structure 110. In some embodiments, the thickness of first masking structure 116 is about 1000 Å. To date (For example, about To date or about To date ) within the range of .

[0047] The first masking structure 116 may be formed of and include at least one material suitable for use as an etch mask to pattern portions of the isolation structure 110 after patterning the first masking structure 116, as described in further detail below. The isolation structure 110 may be selectively etchable relative to the first masking structure 116. By way of non-limiting example, the first masking structure 116 may be formed of and include one or more of: at least one dielectric material (e.g., a dielectric oxide material such as SiO x , phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlO x , HfO x 、NbO x 、TiO x 、ZrO x 、TaO x and MgO x One or more of: dielectric nitride materials, such as SiN y ; Dielectric oxynitride materials, such as SiO x N y ; Dielectric carbon oxynitride materials, such as SiO x C z N y ; amorphous carbon), at least one metal-doped carbon material (e.g., boron-doped carbon, tungsten-doped carbon, nickel-doped carbon), at least one semiconductor material (e.g., polycrystalline silicon), at least one conductive material (e.g., metal, such as one or more of aluminum and tungsten), and at least one anti-reflective material. In some embodiments, the first masking structure 116 includes amorphous carbon. The first masking structure 116 may be substantially uniform (e.g., may be formed of only one material and include only one material), or may be non-uniform (e.g., may be formed of more than one material and include more than one material, such as a stack of at least two different materials). In some embodiments, the first masking structure 116 includes a stack of at least two different materials (e.g., two or more different materials selected from dielectric materials, metal-doped carbon materials, semiconductor materials, conductive materials, and anti-reflective materials).

[0048] Continue to refer Figure 1B, the second masking structure 118 can be formed on or above the first masking structure 116. In some embodiments, the second masking structure 118 is formed on an upper surface of the first masking structure 116. The second masking structure 118 can include an opening 120 (e.g., a hole) therein. The opening 120 can extend completely vertically (e.g., in the Z direction) through the second masking structure 118. The opening 120 can expose a predetermined area of ​​the first masking structure 116 beneath the second masking structure 118. The geometric configuration (e.g., size, shape) and position of the opening 120 can be selected to facilitate the desired geometric configuration (e.g., size, shape) and position of a structure (e.g., spacer structure, liner structure) to be subsequently formed within the opening 120, as described in further detail below. As Figure 1B As shown, the linear portion 121 of the second masking structure 118 may be between horizontally adjacent openings 120 (eg, in the X-direction).

[0049] The second masking structure 118 can be formed of and include at least one material that can be selectively removed relative to the first masking structure 116 and one or more structures (e.g., spacer structures, liner structures) to be subsequently formed within the opening 120 in the second masking structure 118, as described in further detail below. The subsequent selective removal of the material of the second masking structure 118 can, for example, facilitate a pitch density multiplication (e.g., pitch density doubling) operation performed using the subsequently formed structure. By way of non-limiting example, the second masking structure 118 can be formed of and include a conventional resist material, such as a conventional photoresist material (e.g., a conventional positive photoresist, a conventional negative photoresist) or a conventional heat-resistant material. If the second masking structure 118 includes a photoresist material, exposing the photoresist (e.g., if the photoresist material includes a positive photoresist) or not exposing (e.g., if the photoresist material includes a negative photoresist) to at least a minimum threshold dose of electromagnetic radiation can cause the photoresist material to become at least partially soluble in a developer. If the second masking structure 118 includes a heat-resistant material, exposing or not exposing the heat-resistant material to at least a minimum threshold temperature can cause the heat-resistant material to become at least partially soluble in a developer. Suitable resist materials (e.g., positive photoresist materials, negative photoresist materials, heat-resistant materials) are known in the art and are therefore not described in detail herein. In some embodiments, the second masking structure 118 includes a conventional photoresist material. The photoresist material of the second masking structure 118 can be compatible with, for example, 13.7 nm, 157 nm, 193 nm, 248 nm, or 365 nm wavelength systems; 193 nm wavelength immersion systems; and / or electron beam lithography systems.

[0050] Common Reference Figure 1A and Figure 1B, the openings 120 in the second masking structure 118 can be formed to exhibit a desired horizontal position (e.g., in the X and Y directions), horizontal cross-sectional shape, and horizontal size (e.g., in the X and Y directions) of a structure (e.g., a spacer structure, a liner structure) to be subsequently formed using the second masking structure 118. Each of the openings 120 in the second masking structure 118 can be aligned with the transistor 115 ( Figure 1B ) at least partially overlaps horizontally (e.g., in the X direction and the Y direction). In some embodiments, each of the openings 120 overlaps with the transistor 115 ( Figure 1B ) are substantially horizontally aligned with at least one transistor in the microelectronic device structure 100. For example, each of the openings 120 can be individually aligned with the transistor pair 117 ( Figure 1B ) wherein one (1) transistor pair is substantially horizontally aligned. Figure 1A As shown, the openings 120 may each exhibit a rectangular horizontal cross-sectional shape including a first length L1 (e.g., a horizontal dimension in the Y direction) and a first width W1 (e.g., a horizontal dimension in the X direction). The first length L1 of each of the openings 120 may be substantially the same as (e.g., substantially equal to) the length of the gate structure 108 or may be different from (e.g., less than or greater than) the length of the gate structure. The first width W1 of each of the openings 120 may be within the range of at least one transistor 115 (e.g., the transistor 115) horizontally overlapping the opening 120. Figure 1B ) horizontally (e.g., in the X direction) between and may extend beyond the horizontal boundary (e.g., in the X direction). Figure 1B As shown, in some embodiments, each of the openings 120 individually exhibits a first width W1 that extends horizontally (e.g., in the X direction) between and may extend beyond the horizontal boundaries (e.g., in the X direction) of one (1) of the transistor pairs 117 of the microelectronic device structure 100. The first width W1 of each of the openings 120 may encompass the entire width (e.g., in the X direction) of the transistor pair 117 with which it is horizontally aligned (e.g., from and between the outermost horizontal boundaries of the drain region 104A of the transistor pair 117), as well as at least a portion (e.g., substantially the entire distance) of each distance D1 (e.g., in the X direction) between the transistor pair 117 and each additional transistor pair 117 of a horizontally adjacent (e.g., in the X direction) transistor pair 117.

[0051] The openings 120 within the second masking structure 118 can exhibit substantially the same geometric configuration (e.g., substantially the same size, substantially the same shape) as one another, and horizontally adjacent openings 120 within the second masking structure 118 can be horizontally separated from one another by substantially the same distance (e.g., by linear portions 121 of the second masking structure 118). Thus, the spacing between horizontal centerlines (e.g., in the X-direction) of horizontally adjacent openings 120 can be substantially consistent throughout the second masking structure 118. In further embodiments, one or more of the openings 120 within the second masking structure 118 can exhibit one or more of a different geometric configuration (e.g., a different size, a different shape) and a different spacing than one or more other openings 120 within the second masking structure 118.

[0052] The base structure 102 (including its conductive doped region 104 and channel region 106), gate structure 108, isolation structure 110, gate dielectric structure 112, dielectric cap structure 114, first masking structure 116 and second masking structure 118 (including openings 120 therein) of the microelectronic device structure 100 can be formed using conventional processes (e.g., conventional deposition processes, such as one or more of in-situ growth, spin coating, blanket coating, CVD, ALD and PVD; conventional doping processes; conventional patterning and material removal processes, such as conventional photolithography exposure processes, conventional development processes, conventional etching processes) and conventional processing equipment, which are not described in detail herein.

[0053] Next reference Figure 2A , can be defined in the opening 120 ( Figure 1A and 1B ) of the second masking structure 118 ( Figure 1A and 1B ) is formed on a side surface of (e.g., directly adjacent to) the side surface, and the second masking structure 118 may then be removed selectively relative to the spacer structure 122. The spacer structure 122 may partially (e.g., incompletely) fill the opening 120 ( Figure 1A and 1B ) to form an additional opening 124 horizontally defined (eg, in the X-direction and the Y-direction) by the inner side surfaces of the spacer structure 122. Figure 2B is in Figure 2A A simplified partial cross-sectional view of a microelectronic device structure 100 (around line AA) at a stage of processing is shown. For clarity and ease of understanding of the drawings and associated description, Figure 2A and 2B One of the figures is not depicted Figure 2A and 2B All features depicted in another figure in .

[0054] The spacer structure 122 may be formed of and include at least one material having an etch selectivity different from that of the second masking structure 118. The second masking structure 118 may be selectively etchable relative to the spacer structure 122. For example, the spacer structure 122 may be formed of and include one or more of: at least one dielectric material (e.g., one or more of: at least one dielectric oxide material, such as SiO x , phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlO x , HfO x 、NbO x 、TiO x 、ZrO x 、TaO x and MgO x At least one dielectric nitride material, such as SiN y ; at least one dielectric oxynitride material, such as SiO x N y and at least one dielectric carbon oxynitride material, such as SiO x C z N y ), at least one semiconductor material (e.g., polysilicon), and at least one conductive material (e.g., at least one metal). In some embodiments, the spacer structures 122 are formed of and include a dielectric oxide material. The spacer structures 122 may be substantially uniform (e.g., may be formed of and include only one material), or may be non-uniform (e.g., may be formed of and include more than one material, such as including a stack of at least two different materials). In some embodiments, each of the spacer structures 122 is substantially uniform.

[0055] like Figure 2A As shown, the spacer structures 122 can each be individually formed to exhibit a rectangular ring horizontal cross-sectional shape. The outermost horizontal boundary of each of the spacer structures 122 can exhibit a shape that is substantially the same as the opening 120 ( Figure 1A) in the horizontal dimensions (e.g., in the X and Y directions). For example, each of the spacer structures 122 can exhibit a first length L1 (e.g., a horizontal dimension in the Y direction) and a first width W1 (e.g., a horizontal dimension in the X direction). In addition, each of the spacer structures 122 can be formed to exhibit a desired horizontal thickness (e.g., a linear horizontal dimension between an inner horizontal boundary of the spacer structure 122 and an outer horizontal boundary of the spacer structure 122 that is horizontally adjacent to the inner horizontal boundary of the spacer structure 122 and extends parallel to the inner horizontal boundary). The horizontal thickness of the spacer structure 122 can be based at least in part on the horizontally adjacent transistors 115 ( Figure 2B ) is selected by the horizontal distance between horizontally adjacent conductive doping regions 104 (eg, horizontally adjacent drain regions 104A). Figure 2A As depicted, the horizontal thickness of each spacer structure 122 can be greater than or equal to the distance D1 between horizontally adjacent transistor pairs 117 of the microelectronic device structure 100. In some embodiments, the horizontal thickness of each spacer structure 122 is substantially the same as (e.g., substantially equal to) the distance D1 between horizontally adjacent transistor pairs 117 of the microelectronic device structure 100. In other embodiments, the horizontal thickness of each spacer structure 122 is greater than the distance D1 between horizontally adjacent transistor pairs 117 of the microelectronic device structure 100.

[0056] The spacer structure 122 can be formed using conventional processes (e.g., conventional pitch density multiplication processes) and conventional processing equipment, which are not described in detail herein. By way of non-limiting example, the spacer structure 122 can be formed using conventional processes (e.g., conventional pitch density multiplication processes) and conventional processing equipment. Figure 1A and 1B ) in the opening 120 ( Figure 1A and 1B) and then the portion of the spacer material on the surface (e.g., the upper surface of the first masking structure 116) outside the opening 120 and defining the bottom (e.g., the lower vertical boundary) of the opening 120 can be removed to form the spacer structure 122 and the additional opening 124. The spacer material can be formed using one or more conventional conformal deposition processes, such as one or more of conventional ALD processes and conventional conformal CVD processes. Portions of the spacer material can be removed by one or more conventional etching processes, such as one or more of the following: anisotropic dry etching (e.g., one or more of reactive ion etching (RIE), deep RIE, plasma etching, reactive ion beam etching, and chemically assisted ion beam etching) and anisotropic wet etching (e.g., one or more of hydrofluoric acid (HF) etching, buffered HF etching, and buffered oxide etching (BOE)). After forming the spacer structures 122 , the second masking structure 118 may be selectively removed using one or more additional conventional material removal processes (eg, conventional development processes).

[0057] Next reference Figure 3A , can be in the first masking structure 116 ( Figure 2B ) and spacer structures 122 to form a third masking structure 126 on or over the exposed surface of the first masking structure 116. The third masking structure 126 can act as a mask for facilitating the selective removal of portions of the first masking structure 116 that are not covered by one or more of the third masking structure 126 and the spacer structures 122, as described in further detail below. Figure 3A As shown, the third masking structure 126 can include grooves 128 (e.g., openings, holes) therein. The grooves 128 can extend vertically completely through the third masking structure 126 to expose portions of the first masking structure 116 and the spacer structure 122. The geometric configuration (e.g., size, shape) and position of the grooves 128 can be selected at least in part based on the geometric configuration (e.g., size, shape) and position of the spacer structure 122 to facilitate the formation of a desired pattern that is subsequently transferred to the first masking structure 116, as described in further detail below. The linear portion 129 of the third masking structure 126 can be between horizontally adjacent grooves 128 (e.g., in the X direction). Figure 3B is in Figure 3A A simplified partial cross-sectional view of a microelectronic device structure 100 (around line AA) at a stage of processing is shown. For clarity and ease of understanding of the drawings and associated description, Figure 3A and 3B One of the figures is not depicted Figure 3A and 3BAll features depicted in another figure in .

[0058] refer to Figure 3B , the third masking structure 126 can be formed of and include at least one material that can facilitate the transfer of a pattern defined by the combination of the spacer structure 122 and the third masking structure 126 to the first masking structure 116, as described in further detail below. By way of non-limiting example, the third masking structure 126 can be formed of and include a conventional resist material, such as a conventional photoresist material (e.g., a conventional positive photoresist, a conventional negative photoresist) or a conventional heat-resistant material. Suitable resist materials (e.g., positive photoresist materials, negative photoresist materials, heat-resistant materials) are known in the art and are therefore not described in detail herein. In some embodiments, the third masking structure 126 can be, for example, compatible with: 13.7nm, 157nm, 193nm, 248nm, or 365nm wavelength systems; 193nm wavelength immersion systems; and / or electron beam lithography systems.

[0059] Common Reference Figure 3A and 3B , the trench 128 within the third masking structure 126 may include a first trench 128A and a second trench 128B. The first trench 128A may overlap horizontally with the source region 104B of the base structure 102 (e.g., in the X direction and the Y direction). In some embodiments, the first trench 128A is substantially horizontally aligned with the source region 104B of the base structure 102 and extends horizontally partially above the source region. The first trench 128A may be substantially horizontally centered around the source region 104B of the base structure 102 in the X direction. The second trench 128B may overlap horizontally with the drain region 104A of the base structure 102 and a portion of the spacer structure 122 that is horizontally adjacent to the drain region 104A (e.g., a portion of the spacer structure 122 that extends in the Y direction and is between the drain regions 104A that are horizontally adjacent to each other in the X direction) (e.g., in the X direction and the Y direction). In some embodiments, the second trench 128B is substantially horizontally aligned with the portion of the spacer structure 122 and extends horizontally partially over the drain region 104A of the base structure 102 that is horizontally adjacent to the portion of the spacer structure 122. The second trench 128B may be substantially horizontally centered around the portion of the spacer structure 122 in the X-direction.

[0060] like Figure 3AAs shown, the trenches 128 (including the first trench 128A and the second trench 128B) within the third masking structure 126 may each exhibit a rectangular horizontal cross-sectional shape. The first trenches 128A may each individually exhibit a second width W2 (e.g., a horizontal dimension in the X direction), and the second trenches 128B may each individually exhibit a third width W3 that is greater than the second width W2. In some embodiments, the second width W2 of each of the first trenches 128A is less than the width of the source region 104B of the base structure 102 that horizontally overlaps with the first trench 128A; and the third width W3 of each of the second trenches 128B is less than the combined width of the portion of the spacer structure 122 that horizontally overlaps with the second trench 128B and the drain region 104A of the base structure 102 that horizontally overlaps with the second trench. In addition, as Figure 3A As shown, the first trench 128A and the second trench 128B can each individually exhibit a second length L2 (e.g., a horizontal dimension in the Y direction). The second length L2 of each of the first trench 128A and the second trench 128B can be less than or equal to the length of the conductive doping region 104 of the substrate structure 102. In some embodiments, the first trench 128A and the second trench 128B are all formed to exhibit a second length L2 (e.g., the trenches 128 are all formed to have substantially uniform lengths relative to each other). In other embodiments, the length of one or more (e.g., each) first trench in the first trench 128A is different from (e.g., less than, greater than) another length (e.g., second length L2) of one or more (e.g., each) second trench in the second trench 128B (e.g., the trenches 128 are formed to have variable lengths relative to each other). As a non-limiting example, each first trench in the first trench 128A can optionally be formed to exhibit a third length L3 that is less than the second length L2 exhibited by each second trench in the second trench 128B. As another non-limiting example, each of the first trenches 128A may optionally be formed to exhibit a third length L3 that is less than a second length L2 exhibited by each of the second trenches 128B.

[0061] The third masking structure 126 can be formed using conventional processes (e.g., conventional material deposition processes, conventional photolithography processes, conventional material removal processes) and conventional processing equipment, which are not described in detail herein. By way of non-limiting example, a resist material (e.g., a photoresist material) can be formed (e.g., deposited) on or above the spacer structure 122 and the first masking structure 116, and the resist material can then be processed (e.g., photolithography processing, such as exposure and development) to remove portions thereof and form the third masking structure 126 including the trench 128 therein.

[0062] Next reference Figure 4A , the first masking structure 116 ( Figure 3B ) that is not covered by one or more of the spacer structure 122 and the third masking structure 126 to form a patterned first masking structure 130. The patterned first masking structure 130 may include additional trenches 132 therein. The additional trenches 132 may vertically extend completely through the patterned first masking structure 130 to expose the isolation structure 110 ( Figure 3B ) portion. Additional trenches 132 within the patterned first masking structure 130 may be horizontally separated from one another (eg, in the X direction) by linear portions 134 of the patterned first masking structure 130. The patterned first masking structure 130 serves as a shield for facilitating selective removal of the isolation structure 110 ( Figure 3B ) of the portions of the patterned first masking structure 130 that are not covered by the patterned first masking structure 130, as described in further detail below. Figure 4B is in Figure 4A A simplified partial cross-sectional view of a microelectronic device structure 100 (around line AA) at a stage of processing is shown. For clarity and ease of understanding of the drawings and associated description, Figure 4A and 4B One of the figures is not depicted Figure 4A and 4B All features depicted in another figure in .

[0063] like Figure 4A and 4BAs shown, the additional trenches 132 within the patterned first masking structure 130 may include a first additional trench 132A and a second additional trench 132B. The first additional trench 132A may horizontally overlap with the source region 104B of the base structure 102, and the second additional trench 132B may horizontally overlap with the drain region 104A of the base structure 102. In some embodiments, the first additional trenches 132A are each individually confined within a horizontal boundary (e.g., in the X direction and the Y direction) of one of the source regions 104B of the base structure 102, and the second additional trenches 132B are each individually confined within a horizontal boundary (e.g., in the X direction and the Y direction) of one of the drain regions 104A of the base structure. The first additional trench 132A may be substantially horizontally aligned with and may extend partially horizontally above the source region 104B of the base structure 102, and the second additional trench 132B may be substantially horizontally aligned with and may extend partially horizontally above the drain region 104A of the base structure 102. In some embodiments, each additional trench of the first additional trenches 132A is individually substantially horizontally centered in the X direction around one of the source regions 104B of the base structure 102, and each additional trench of the second additional trenches 132B is individually substantially horizontally centered in the X direction around one of the drain regions 104A of the base structure 102.

[0064] Likewise Figure 4A and 4B As shown, the linear portion 134 of the patterned first masking structure 130 horizontally between the other trenches 132 may include a first linear portion 134A and a second linear portion 134B. The first linear portion 134A may be adjacent to the gate structure 108 and the sidewall spacer structure 113 ( Figure 4B ) and isolation structure 110( Figure 4B) horizontally overlaps with a portion of one or more of the sidewall spacer structures 113 (and optionally, the isolation structure 110) horizontally adjacent to the gate structure 108. The second linear portion 134B may horizontally overlap with a region of the base structure 102 horizontally interposed between horizontally adjacent drain regions 104A of the base structure 102 (e.g., in the X direction). Each of the first additional trenches 132A may individually be substantially horizontally aligned with one of the gate structures 108 in the X direction and may extend horizontally completely over the gate structure 108 and at least over a portion of the sidewall spacer structures 113 (and optionally, the isolation structure 110) horizontally adjacent to the gate structure 108 in the X direction. Each of the second additional trenches 132B may individually be substantially horizontally aligned with one of the isolation structures 110 in the X direction and may extend horizontally partially over one of the isolation structures. In some embodiments, each of the first linear portions 134A of the patterned first masking structure 130 is individually substantially horizontally centered around one of the gate structures 108 in the X-direction, and each of the second linear portions 134B of the patterned first masking structure 130 is individually substantially horizontally centered around one of the isolation structures 110 in the X-direction.

[0065] like Figure 4A As shown, the additional grooves 132 (including the first additional groove 132A and the second additional groove 132B) within the patterned first masking structure 130 and the linear portion 134 (including the first linear portion 134A and the second linear portion 134B) of the patterned first masking structure 130 each individually exhibit a rectangular horizontal cross-sectional shape. The first additional grooves 132A can each individually exhibit a third width W3 (e.g., a horizontal dimension in the X direction), and the second additional grooves 132B can each individually exhibit a fourth width W4 (e.g., a horizontal dimension in the X direction). The third width W3 can be substantially the same as (e.g., substantially equal to) the fourth width W4, or the third width W3 can be different from (e.g., less than, greater than) the fourth width W4. In some embodiments, the third width W3 is substantially the same as the fourth width W4. The third width W3 of each of the first further trenches 132A may be smaller than the width of each individual drain region 104A of the base structure 102, and the fourth width W4 of each of the second further trenches 132B may be smaller than the width of each individual source region 104B of the base structure 102. Figure 4A As shown, each of the additional trenches 132 (eg, each of the first additional trenches 132A and each of the second additional trenches 132B) may individually exhibit a third masking structure 126 ( Figure 3A and 3B) for forming a trench 128 (eg, a first trench 128A or a second trench 128B) for forming another trench 132 ( Figure 3A and 3B ) has a length (e.g., a horizontal dimension in the Y direction) corresponding to (e.g., substantially the same, equal to) that of the third masking structure 126. As a non-limiting example, if the third masking structure 126 ( Figure 3A and 3B ) in the groove 128 ( Figure 3A and 3B ) is formed to exhibit a second length L2, each of the additional trenches 132 in the patterned first masking structure 130 may also be formed to exhibit the second length L2. As another non-limiting example, if the first trench 128A ( Figure 3A and 3B ) are each formed to exhibit a third length L3, and the second trenches 128B ( Figure 3A and 3B ) are each formed to exhibit a second length L2, the first additional trenches 132A in the patterned first masking structure 130 may each be formed to exhibit a third length L3, and the second additional trenches 132B in the patterned first masking structure 130 may each be formed to exhibit the second length L2. As another non-limiting example, if the first trenches 128A in the third masking structure 126 are each formed to exhibit a second length L2, and the second trenches 128B in the third masking structure 126 are each formed to exhibit a third length L3, the first additional trenches 132A in the patterned first masking structure 130 may each be formed to exhibit a second length L2, and the second additional trenches 132B in the patterned first masking structure 130 may each be formed to exhibit a third length L3.

[0066] The patterned first masking structure 130 may be formed using conventional processes (e.g., conventional material removal processes) and conventional processing equipment, which are not described in detail herein. By way of non-limiting example, to form the patterned first masking structure 130, the spacer structure 122 ( Figure 3A and 3B ) and the third masking structure 126 ( Figure 3A and 3B ) is used as a mask for at least one etching process (eg, an anisotropic etching process such as a reactive ion etching process) to substantially remove the first masking structure 116 ( Figure 3B) below the spacer structure and the third masking structure (e.g., a portion of the first masking structure 116 that is not covered by the material of one or more of the spacer structure 122 and the third masking structure 126, such as the groove 128 of the first masking structure 116 located within the third masking structure 126 ( Figure 3A and 3B ) that is not partially covered by the spacer structure 122). The first masking structure 116 ( Figure 3B ) while substantially maintaining the masked portions of the third masking structure 126 (e.g., portions covered by the material of one or more of the spacer structures 122 and the third masking structure 126). Thereafter, the remaining portions of the spacer structures 122 and the third masking structure 126 (if any) may be selectively removed.

[0067] Next reference Figure 5A , the isolation structure 110 can be selectively removed ( Figure 4B ) that is still not covered by the material of the patterned first masking structure 130, and the resulting trenches may be used to form contact structures 136. The contact structures 136 may be formed to contact (e.g., physically contact, electrically contact) the conductive doped regions 104 (e.g., drain regions 104A, source regions 104B) of the substrate structure 102, and may be isolated from the gate structure 108 and from each other by the remaining (e.g., not removed) portions of the isolation structure 110. The patterned first masking structure 130 ( Figure 4A and 4B ) of the linear portion 134 (e.g., the first linear portion 134A, the second linear portion 134B) ( Figure 4A and 4B ) can prevent the portion of the isolation structure 110 located below the linear portion from being removed during the material removal process, thereby ensuring that the contact structures 136 are electrically isolated from each other and from the gate structure 108. Figure 5B is in Figure 5A A simplified partial cross-sectional view of a microelectronic device structure 100 (around line AA) at a stage of processing is shown. For clarity and ease of understanding of the drawings and associated description, Figure 5A and 5B One of the figures is not depicted Figure 5A and 5B All features depicted in another figure in .

[0068] The contact structure 136 may be formed of and include at least one conductive material, such as a metal (e.g., W, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Cu, Ag, Au, Al), an alloy (e.g., a Co-based alloy, a Fe-based alloy, a Ni-based alloy, a Fe-Ni-based alloy, a Co-Ni-based alloy, a Fe-Co-based alloy, a Co-Ni-Fe-based alloy, an Al-based alloy, a Cu-based alloy, a magnesium (Mg)-based alloy, a Ti-based alloy, steel, low carbon steel, stainless steel), a conductive doped semiconductor material (e.g., conductive doped polysilicon, conductive doped Ge, conductive doped SiGe), a conductive metal-containing material (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide), or a combination thereof. The contact structure 136 may include a substantially uniform distribution of the conductive material, or may include a substantially non-uniform distribution of the conductive material. If contact structures 136 exhibit a substantially non-uniform distribution of conductive material, the amount of conductive material can change stepwise (e.g., abruptly) throughout different portions of contact structures 136, or can change continuously (e.g., gradually, such as linearly, parabolically). In some embodiments, contact structures 136 each exhibit a substantially uniform distribution of conductive material. In further embodiments, one or more (e.g., each) of contact structures 136 exhibit a substantially non-uniform distribution of at least one conductive material. One or more of contact structures 136 can, for example, be formed of and include a stack of at least two different conductive materials.

[0069] like Figure 5A and 5B As shown, the contact structure 136 includes a source contact structure 136A and a drain contact structure 136B. The source contact structure 136A may horizontally overlap and contact (e.g., physically contact, electrically contact) the source region 104B of the substrate structure 102, and the drain contact structure 136B may horizontally overlap and contact (e.g., physically contact, electrically contact) the drain region 104A of the substrate structure 102. In some embodiments, the source contact structures 136A are each individually confined within a horizontal boundary (e.g., in the X direction and the Y direction) of one of the source regions 104B of the substrate structure 102, and the drain contact structures 136B are each individually confined within a horizontal boundary (e.g., in the X direction and the Y direction) of one of the drain regions 104A of the substrate structure. The source contact structure 136A may be substantially horizontally aligned with the source region 104B of the base structure 102 and may extend horizontally partially above the source region, and the drain contact structure 136B may be substantially horizontally aligned with the drain region 104A of the base structure 102 and may extend horizontally partially above the drain region. Figure 5AAs shown, in some embodiments, each of the source contact structures 136A is individually substantially horizontally centered in the X direction and the Y direction around one of the source regions 104B of the base structure 102, and each of the drain contact structures 136B is individually substantially horizontally centered in the X direction and the Y direction around one of the drain regions 104A of the base structure 102. The contact structures 136 (including the source contact structures 136A and the drain contact structures 136B) may be offset from each other in the X direction and may be substantially aligned with each other in the Y direction.

[0070] like Figure 5A As shown, the contact structures 136 (including the source contact structure 136A and the drain contact structure 136B) each individually exhibit a rectangular horizontal cross-sectional shape. The source contact structure 136A may each individually exhibit a patterned first masking structure 130 ( Figure 4A and 4B ) for forming a first additional trench 132A ( Figure 4A and 4B ) has a third width W3 (eg, a horizontal dimension in the X direction). In addition, the drain contact structures 136B may each individually exhibit a patterned first masking structure 130 ( Figure 4A and 4B ) for forming a second additional trench 132B ( Figure 4A and 4B ) has a fourth width W4 (e.g., a horizontal dimension in the X direction). Figure 5A As shown, each contact structure in the contact structures 136 (eg, each source contact structure in the source contact structures 136A and each drain contact structure in the drain contact structures 136B) may individually exhibit a first masking structure 130 ( Figure 4A and 4B ) for forming a further trench 132 (eg, a first further trench 132A or a second further trench 132B) for forming a contact structure 136 ( Figure 4A and 4B ) has a length (e.g., a horizontal dimension in the Y direction) corresponding to (e.g., substantially the same, equal to) that of the patterned first masking structure 130. As a non-limiting example, if the patterned first masking structure 130 ( Figure 4A and 4B ) in the other groove 132 ( Figure 4A and 4B) is formed to exhibit a second length L2, each contact structure in the contact structures 136 may also be formed to exhibit a second length L2. As another non-limiting example, if the first additional trench 132A ( Figure 4A and 4B ) are each formed to exhibit a third length L3, and the second additional trenches 132B ( Figure 4A and 4B ) are each formed to exhibit a second length L2, the source contact structures 136A may each be formed to exhibit a third length L3, and the drain contact structures 136B may each be formed to exhibit the second length L2. As another non-limiting example, if the first additional trenches 132A in the patterned first masking structure 130 are each formed to exhibit a second length L2, and the second additional trenches 132B in the patterned first masking structure 130 are each formed to exhibit a third length L3, the source contact structures 136A may each be formed to exhibit the second length L2, and the drain contact structures 136B may each be formed to exhibit the third length L3. The horizontal distance between horizontally adjacent drain contact structures 136B may be substantially equal to the horizontal distance between the patterned first masking structure 130 ( Figure 4A and 4B The horizontal distance between each drain contact structure 136B and each source contact structure 136A horizontally adjacent to the drain contact structure 136B may be substantially equal to the width of each second linear portion of the second linear portion 134B of the patterned first masking structure 130 ( Figure 4A and 4B )'s width of each of the first linear portions 134A.

[0071] The contact structure 136 may be formed using conventional processes (eg, conventional material removal processes and conventional material deposition processes) and conventional processing equipment, which are not described in detail herein. As a non-limiting example, the patterned first masking structure 130 ( Figure 4A and 4B ) is used as a mask for at least one etching process (e.g., an anisotropic etching process, such as a reactive ion etching process) to substantially remove the unmasked portions of the isolation structure 110 located below the patterned first masking structure (e.g., portions of the isolation structure 110 that are not covered by the material of the patterned first masking structure 130, such as the additional trenches 132 ( Figure 4A and 4B). The unmasked portions of the isolation structure 110 may be substantially (e.g., completely) removed while the masked portions of the isolation structure 110 (e.g., portions covered by the material of the patterned first masking structure 130) are substantially maintained. A conductive material may then be formed inside and outside the resulting trenches in the isolation structure 110 (e.g., by one or more conventional deposition processes, such as one or more of an ALD process, a CVD process, a PECVD process, a PVD process, and a spin coating process), and then at least the conductive material may be subjected to at least one planarization process (e.g., at least one CMP process) to remove at least a portion of the conductive material positioned above the upper vertical boundary of the isolation structure 110 (e.g., in the Z direction) and form the contact structure 136.

[0072] The method of the present disclosure at least allows the drain contact structure 136B of the present disclosure to exhibit a larger horizontal dimension (eg, at least a larger length, such as Figure 5A Since the horizontal dimension of drain contact structure 136B is relatively large, the drain contact structure may facilitate lowering the contact resistance and increasing the drain current (I DS ), which can improve the performance of a microelectronic device (eg, a memory device) including the microelectronic device structure 100.

[0073] Therefore, according to an embodiment of the present disclosure, a method for forming a microelectronic device includes forming a spacer structure having a rectangular ring horizontal cross-sectional shape above a transistor, a portion of the spacer structure horizontally overlapping with the drain region of the transistor. A masking structure is formed above the spacer structure and the transistor, the masking structure exhibiting an opening therein, the opening horizontally overlapping with the drain region of the transistor and the portion of the spacer structure. The masking structure and the portion of the spacer structure are used as an etching mask to remove a portion of an isolation structure covering the drain region of the transistor to form a trench, the trench extending vertically through the isolation structure to reach the drain region of the transistor. A drain contact structure is formed in the trench in the isolation structure.

[0074] In addition, according to another embodiment of the present disclosure, a method includes: forming a spacer structure in a ring shape on a transistor, the transistor including a first conductive doping region and a second conductive doping region and a gate structure, the gate structure being located on a channel region between the first conductive doping region and the second conductive doping region, a portion of the spacer structure overlapping the first conductive doping region. Forming a masking structure on the spacer structure and the transistor, the masking structure showing an opening therein, the opening overlapping the first conductive doping region and the portion of the spacer structure. Using the masking structure and the portion of the spacer structure as an etching mask to remove a portion of an isolation structure covering the first conductive doping region to form a trench, the trench exposing a portion of the first conductive doping region. Forming a first contact structure through the trench, the first contact structure contacting the portion of the first conductive doping region.

[0075] In addition, a microelectronic device according to an embodiment of the present disclosure includes a transistor, a source contact structure, and a drain contact structure. The transistor includes: a gate structure; a source region, the source region is horizontally adjacent to a first side of the gate structure; a drain region, the drain region is horizontally adjacent to a second side of the gate structure opposite to the first side of the gate structure; and a channel region, the channel region is vertically located below the gate structure and horizontally between the source region and the drain region. The source contact structure is horizontally adjacent to the first side of the gate structure of the transistor and contacts the source region of the transistor. The drain contact structure is horizontally adjacent to the second side of the gate structure of the transistor and contacts the drain region of the transistor. The drain contact structure is substantially horizontally aligned with the source contact structure and exhibits a horizontal area greater than or equal to the horizontal area of ​​the source contact structure.

[0076] Those skilled in the art should understand that according to other embodiments of the present disclosure, the above description of Figures 1A to 5B One or more of the described process steps, features, and feature configurations can be easily adjusted according to the design requirements of different microelectronic devices (e.g., different memory devices, such as different DRAM devices). By way of non-limiting example, Fig. 6A and 6B is a simplified top view showing an embodiment of a method of forming another microelectronic device structure of the present disclosure ( Fig. 6A ) and partial cross-sectional views ( Figure 6B ). The microelectronic device structure 200 may be formed in a manner similar to the manner in which the microelectronic device structure 100 is formed by the previously referenced Figure 3A and 3BThe processing stages described form and may exhibit features similar to those (e.g., structure, materials) of the microelectronic device structure. Figures 1A to 5B The described configurations and spacings modify the configuration and spacing of one or more features of the microelectronic device structure 200 to accommodate a desired configuration and / or spacing in the microelectronic device structure 200. Fig. 6A and 6B In the following and related descriptions, similar reference numerals incremented by 100 are used to refer to microelectronic device structures 200 that are functionally similar to microelectronic device structures 100 ( Figures 1A to 5B ) features (e.g., structure, material). To avoid repetition, this article does not describe in detail Fig. 6A and 6B All features shown in the referenced Figures 1A to 5B Features designated by reference numerals incremented by 100 for one or more of the described features should be understood to be substantially similar to the previously described features. In addition, for clarity and ease of understanding of the drawings and related descriptions, Fig. 6A and 6B One of the figures is not depicted Fig. 6A and 6B All features depicted in another figure in .

[0077] Common Reference Fig. 6A and 6B , and for Figure 3A and 3B Compared to the configuration and location of the spacer structure 122 and the third masking pattern 126 used to form the microelectronic device structure 100 at the processing stage depicted in , the method of forming the microelectronic device structure 200 may employ different configurations and locations of the spacer structure 222 and the third masking pattern 226. For example, the spacer structure 222 may horizontally overlap with portions of the gate structure 208 and one or more of the sidewall spacer structures 213 and the isolation structure 210 that are horizontally proximate to the gate structure 208, and the linear portion 229 of the third masking structure 226 may horizontally overlap with regions of the base structure 202 that are horizontally proximate (e.g., in the X direction) to the outside of the conductive doped region 204 (e.g., the drain region 204A, the source region 204B) of the base structure 202. The spacer structure 222 is located within the horizontal boundaries of the trench 228 in the third masking structure 226 (e.g., within the horizontal boundaries of the trench 228 in the third masking structure 226). Fig. 6AThe portions of the spacer structures 222 that are located within the horizontal boundaries of the trenches 228 in the third masking structures 226 (in the X and Y directions shown) can be substantially horizontally aligned with the gate structure 208 in the X direction and can extend horizontally in the X direction completely over the gate structure 208 and at least over the portions of the sidewall spacer structures 213 (and optionally, the isolation structures 210) that are horizontally adjacent to the gate structure 208. In some embodiments, the portions of the spacer structures 222 that are located within the horizontal boundaries of the trenches 228 in the third masking structures 226 are substantially horizontally centered in the X direction around the gate structure 208. In addition, the linear portions 229 of the third masking structures 226 can each individually extend horizontally partially over one of the isolation structures 210 in the X direction.

[0078] exist Fig. 6A and 6B After the processing steps depicted, additional processing actions may be performed on the microelectronic device structure 200 to form contact structures (e.g., drain contact structures, source contact structures) that are in contact (e.g., physical contact, electrical contact) with the conductive doped regions 204 (e.g., drain regions 204A, source regions 204B) of the base structure 202. The additional processing actions may be similar to those previously described herein with reference to Figures 4A to 5B The processing actions described above for forming the contact structure 136 are as follows. For example, the first masking structure 216 ( Figure 6B ) that is not covered by one or more of the spacer structure 222 and the third masking structure 226 to form a patterned first masking structure; the isolation structure 210 ( Figure 6B ) that remains uncovered by the material of the patterned first masking structure to form a trench in the isolation structure 210 that extends vertically to the conductive doped region 204 of the base structure 202; and then a contact structure similar to the contact structure 136 ( Figure 5A and 5B ) contact structure.

[0079] The microelectronic device structure of the present disclosure formed using the method of the present disclosure (eg, a memory device) can be employed in a microelectronic device of the present disclosure (eg, a memory device). Figure 5A and 5B As a non-limiting example, Figure 7 1 shows a functional block diagram of a memory device 300 according to an embodiment of the present disclosure. The memory device 300 may include, for example, Figure 5A and 5B An embodiment of a microelectronic device structure 100 is described. Figure 7As shown, the memory device 300 may include memory cells 302 , bit lines 304 , word lines 306 , a row decoder 308 , a column decoder 310 , a memory controller 312 , a readout device 314 , and an input / output device 316 .

[0080] The memory cells 302 of the memory device 300 are programmable to at least two different logic states (e.g., logic 0 and logic 1). Each memory cell 302 may individually include a capacitor and a transistor (e.g., a pass transistor). The capacitor stores a charge representing the programmable logic state of the memory cell 302 (e.g., a charged capacitor may represent a first logic state, such as logic 1; and an uncharged capacitor may represent a second logic state, such as logic 0). When a minimum threshold voltage is applied (e.g., through one of the word lines 306) to the semiconductor channel of the transistor, the transistor permits access to the capacitor to perform operations on the capacitor (e.g., read, write, rewrite).

[0081] Bit line 304 is connected to the capacitor of memory cell 302 through the transistor of memory cell 302. The transistor of memory cell 302 may include, for example, Figure 5A and 5B 304 and word lines 306. The word lines 306 extend perpendicular to the bit lines 304 and are connected to the gates of the transistors of the memory cells 302. Operations can be performed on the memory cells 302 by activating the appropriate bit lines 304 and word lines 306. Activating the bit lines 304 or word lines 306 can include applying a voltage potential to the bit lines 304 or word lines 306. Each column of memory cells 302 can be individually connected to one of the bit lines 304, and each row of memory cells 302 can be individually connected to one of the word lines 306. Individual memory cells 302 can be addressed and accessed through the intersections (e.g., cross points) of the bit lines 304 and word lines 306.

[0082] The memory controller 312 may control the operation of the memory cell 302 through various components, including a row decoder 308, a column decoder 310, and a readout device 314 (e.g., a local I / O device). The memory controller 312 may generate a row address signal directed to the row decoder 308 to activate a predetermined word line 306 (e.g., apply a voltage potential thereto), and may generate a column address signal directed to the column decoder 310 to activate a predetermined bit line 304 (e.g., apply a voltage potential thereto). The readout device 314 may include a sense amplifier configured and operated to receive a bit line input from a bit line selected by the column decoder 310 and generate a digital data value during a read operation. The readout device 314 may include, for example, a sense amplifier previously described herein. Figure 5A and 5BThe embodiment of the microelectronic device structure 100 is described. The memory controller 312 can also generate and control various voltage potentials employed during operation of the memory device 300. In general, the amplitude, shape, and / or duration of the applied voltage can be adjusted (e.g., changed) and can be different for various operations of the memory device 300.

[0083] During use and operation of the memory device 300, the memory cell 302 can be read (e.g., sensed) by the readout device 314 after being accessed. The readout device 314 can compare the signal (e.g., voltage) of the appropriate bit line 304 with the reference signal to determine the logic state of the memory cell 302. For example, if the voltage of the bit line 304 is higher than the reference voltage, the readout device 314 can determine that the stored logic state of the memory cell 302 is a logic 1, and vice versa. The readout device 314 can include transistors and amplifiers to detect and amplify the difference in the signal (commonly referred to as "latching" in the art). The detected logic state of the memory cell 302 can be output to the input / output device 316 through the column decoder 310. In addition, the memory cell 302 can be set (e.g., written to) by activating the appropriate word line 306 and the appropriate bit line 304 of the memory device 300 in a similar manner. The memory cell 302 can be set (e.g., a logic value can be stored in the memory cell 302) by controlling the bit line 304 while activating the word line 306. The column decoder 310 can accept data from the input / output device 316 to write it to the memory cell 302. In addition, the memory cell 302 can also be refreshed (e.g., recharged) by reading the memory cell 302. The read operation will place the contents of the memory cell 302 on the appropriate bit line 304, which is then pulled up to a full level (e.g., fully charged or fully discharged) by the read device 314. When the word line 306 associated with the memory cell 302 is deactivated, all memory cells 302 in the row associated with the word line 306 are restored to be fully charged or fully discharged.

[0084] Therefore, a memory device according to an embodiment of the present disclosure includes: a memory cell operably coupled to a bit line and a word line; and a memory controller operably coupled to the memory cell. The memory controller includes a readout device, the readout device includes a transistor, a source contact structure contacting a source region of the transistor, and a drain contact structure contacting a drain region of the transistor. The length of the drain contact structure is greater than or equal to the length of the source contact structure.

[0085] A microelectronic device structure including an embodiment of the present disclosure (eg, Figure 5A and 5B The microelectronic device structure 100 shown in FIG. Figure 7 For example, Figure 8 4 is a block diagram of an illustrative electronic system 400 according to an embodiment of the present disclosure. The electronic system 400 may include, for example, a computer or computer hardware component, a server or other networking hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a Wi-Fi or cellular enabled tablet computer (e.g., or Tablet computers), electronic books, navigation devices, etc. The electronic system 400 includes at least one memory device 402. The memory device 402 may include, for example, a microelectronic device as previously described herein (e.g., Figure 7 The electronic system 400 may further include at least one electronic signal processor device 404 (commonly referred to as a "microprocessor"). The electronic signal processor device 404 may optionally include a microelectronic device as previously described herein (e.g., Figure 7 300) is an embodiment of a microelectronic device as shown in FIG. Figure 8 4. The memory device 402 and the electronic signal processor device 404 are depicted as two (2) separate devices in the electronic system 400, but in other embodiments, the electronic system 400 includes a single (e.g., only one) memory / processor device having the functionality of the memory device 402 and the electronic signal processor device 404. In such embodiments, the memory / processor device may include the microelectronic device structures previously described herein (e.g., Figure 5A and 5B Embodiments of the microelectronic device structure 100 shown in the drawings and / or microelectronic devices previously described herein (eg, Figure 7The electronic system 400 may further include one or more input devices 406 for inputting information into the electronic system 400 by a user, such as a mouse or other pointing device, a keyboard, a touch pad, buttons, or a control panel. The electronic system 400 may further include one or more output devices 408 for outputting information (e.g., visual output or audio output) to the user, such as a monitor, a display, a printer, an audio output jack, a speaker, etc. In some embodiments, the input device 406 and the output device 408 may include a single touch screen device, which may be used to input information to the electronic system 400 and to output visual information to the user. The input device 406 and the output device 408 may be in electrical communication with one or more of the memory device 402 and the electronic signal processor device 404.

[0086] Therefore, an electronic system according to an embodiment of the present disclosure includes: an input device; an output device; a processor device, the processor device being operably coupled to the input device and the output device; and a memory device, the memory device being operably coupled to the processor device. The memory device includes a first transistor, a first source contact structure, a first drain contact structure, a second transistor, a second source contact structure, and a second drain contact structure. The first source contact structure is horizontally adjacent to a first side of a first gate structure of the first transistor and contacts a first source region of the first transistor. The first drain contact structure is horizontally adjacent to a second side of the first gate structure of the first transistor and contacts a first drain region of the first transistor. The second transistor is horizontally adjacent to the first transistor. The second source contact structure is horizontally adjacent to a first side of a second gate structure of the second transistor and contacts a second source region of the second transistor. The second drain contact structure is horizontally adjacent to a second side of the second gate structure of the second transistor and contacts a second drain region of the second transistor. The second drain contact structure is horizontally adjacent to the first drain contact structure in a first direction and is substantially horizontally aligned with the first drain contact structure in a second direction perpendicular to the first direction.

[0087] The disclosed method provides an efficient and reliable way to manipulate microelectronic devices (e.g., memory devices, such as Figure 7 The memory device 300 shown in FIG. Figure 5A and 5B The contact structure (eg, Figure 5A and 5BThe contact structures 136 shown include the size, shape and spacing of the source contact structure 136A and the drain contact structure 136B. The disclosed methods facilitate forming contact structures in a simple and cost-effective manner that reduce contact resistance and increase drive current compared to conventional contact structures while reducing the risk of undesirable current leakage and short circuits compared to conventional contact structure configurations. The disclosed methods and structures can facilitate improving the reliability and performance of microelectronic devices (e.g., memory devices such as DRAM devices) and electronic systems that rely on high feature density.

[0088] Non-limiting example embodiments may include:

[0089] Embodiment 1: A method for forming a microelectronic device, the method comprising: forming a spacer structure having a rectangular ring horizontal cross-sectional shape above a transistor, a portion of the spacer structure horizontally overlapping with a drain region of the transistor; forming a masking structure above the spacer structure and the transistor, the masking structure showing an opening therein, the opening horizontally overlapping with the drain region of the transistor and the portion of the spacer structure; using the masking structure and the portion of the spacer structure as an etching mask to remove a portion of an isolation structure covering the drain region of the transistor to form a trench, the trench extending vertically through the isolation structure to reach the drain region of the transistor; and forming a drain contact structure within the trench in the isolation structure.

[0090] Embodiment 2: A method according to embodiment 1, wherein forming a spacer structure comprises: forming another masking structure above the transistor, the other masking structure showing a rectangular opening therein, the rectangular opening horizontally overlapping with the transistor; forming a spacer material on surfaces inside and outside the rectangular opening in the other masking structure; and removing a portion of the spacer material located outside the rectangular opening in the other masking structure along a lower vertical boundary of the rectangular opening to form the spacer structure.

[0091] Embodiment 3: The method according to embodiment 2, further comprising removing a remaining portion of the another masking structure after forming the spacer structure.

[0092] Embodiment 4: A method according to Embodiment 1, wherein removing a portion of the isolation structure covering the drain region comprises: using the portion of the masking structure and the spacer structure as an etching mask to remove a portion of another masking structure vertically between the isolation structure and each of the portions of the masking structure and the spacer structure to form a patterned another masking structure, wherein the patterned another masking structure exhibits an additional opening located within the horizontal boundary of the isolation structure; and using the patterned another masking structure as an etching mask to remove the portion of the isolation structure to form the trench in the isolation structure.

[0093] Embodiment 5: A method according to any one of embodiments 1 to 4, wherein forming a drain contact structure within the trench in the isolation structure comprises: forming a conductive material on surfaces inside and outside the trench in the isolation structure; and removing a portion of the conductive material located outside the boundary of the trench in the isolation structure to form the drain contact structure.

[0094] Embodiment 6: The method of any one of embodiments 1 to 5, wherein forming a spacer structure further comprises forming the portion of the spacer structure to be horizontally between the drain region of the transistor and another drain region of another transistor horizontally adjacent to the transistor.

[0095] Embodiment 7: The method of Embodiment 6, further comprising forming another portion of the spacer structure to be horizontally interposed between another drain region of another transistor and another drain region of another transistor horizontally adjacent to the other transistor.

[0096] Embodiment 8: The method according to one of embodiments 6 and 7, wherein forming a masking structure comprises forming the opening in the masking structure to horizontally overlap the drain region of the transistor, the portion of the spacer structure, and the other drain region of the other transistor.

[0097] Embodiment 9: The method of Embodiment 8, further comprising forming the masking structure to exhibit another opening therein, the another opening horizontally overlapping a source region of the transistor.

[0098] Embodiment 10: A method according to one of embodiments 8 and 9, further comprising using the masking structure and the portion of the spacer structure as an etching mask to remove another portion of the isolation structure covering the other drain region of the other transistor to form another trench, wherein the other trench vertically extends through the isolation structure to reach the other drain region of the other transistor, and another portion of the isolation structure is horizontally inserted between the trench in the isolation structure and the other trench in the isolation structure.

[0099] Embodiment 11: The method according to Embodiment 10, further comprising forming another drain contact structure in the another trench in the isolation structure.

[0100] Embodiment 12: The method of Embodiment 11, wherein forming another drain contact structure comprises forming the drain contact structure and the another drain contact structure to exhibit substantially equal horizontal dimensions to each other and to be substantially horizontally aligned to each other.

[0101] Embodiment 13: The method according to embodiment 1, wherein forming a spacer structure further comprises forming the portion of the spacer structure to overlap horizontally with a source region of the transistor and a gate structure of the transistor, the gate structure being horizontally between the source region of the transistor and the drain region of the transistor.

[0102] Embodiment 14: The method according to Embodiment 13, wherein forming a masking structure comprises forming the opening in the masking structure to horizontally overlap with the source region of the transistor, the gate structure of the transistor, the drain region of the transistor, and the portion of the spacer structure.

[0103] Embodiment 15: The method according to Embodiment 14 further includes using the masking structure and the portion of the spacer structure as an etching mask to remove the portion of another isolation structure covering the source region of the transistor to form another trench, wherein the another trench vertically extends through the another isolation structure to reach the source region of the transistor.

[0104] Embodiment 16: The method of Embodiment 15, further comprising forming a source contact structure within the another trench in the another isolation structure.

[0105] Embodiment 17: The method of Embodiment 16, wherein forming a source contact structure comprises forming the source contact structure and the drain contact structure to exhibit substantially equal horizontal dimensions to each other and to be substantially horizontally aligned to each other.

[0106] Embodiment 18: A microelectronic device, comprising: a transistor, the transistor comprising: a gate structure; a source region, the source region being horizontally adjacent to a first side of the gate structure; a drain region, the drain region being horizontally adjacent to a second side of the gate structure opposite to the first side of the gate structure; and a channel region, the channel region being vertically located below the gate structure and horizontally between the source region and the drain region; a source contact structure, the source contact structure being horizontally adjacent to the first side of the gate structure of the transistor and in contact with the source region of the transistor; and a drain contact structure, the drain contact structure being horizontally adjacent to the second side of the gate structure of the transistor and in contact with the drain region of the transistor, the drain contact structure being substantially horizontally aligned with the source contact structure and exhibiting a horizontal area greater than or equal to the horizontal area of ​​the source contact structure.

[0107] Embodiment 19: The microelectronic device of Embodiment 18, wherein the drain contact structure exhibits a width and a length that are substantially the same as a width and a length of the source contact structure.

[0108] Embodiment 20: The microelectronic device of Embodiment 18, wherein the drain contact structure exhibits a width substantially the same as a width of the source contact structure and a length greater than a length of the source contact structure.

[0109] Embodiment 21: A microelectronic device according to any one of embodiments 18 to 20, further comprising: another transistor, the other transistor being horizontally adjacent to the transistor and comprising: another gate structure; the source region, the source region being horizontally adjacent to a first side of the other gate structure, the source region being shared between the transistor and the other transistor; another drain region, the other drain region being horizontally adjacent to a second side of the other gate structure opposite to the first side of the other gate structure; and another channel region, the other channel region being vertically located below the other gate structure and horizontally between the source region and the other drain region; and another drain contact structure, the other drain contact structure being horizontally adjacent to the second side of the other gate structure of the other transistor and in contact with the other drain region of the other transistor, the other drain contact structure being substantially horizontally aligned with the source contact structure and the drain contact structure and exhibiting a horizontal area substantially the same as the horizontal area of ​​the drain contact structure.

[0110] Embodiment 22: A microelectronic device according to any one of embodiments 18 to 20, further comprising: another transistor, the other transistor being horizontally adjacent to the transistor and comprising: another gate structure; another source region, the other source region being horizontally adjacent to a first side of the other gate structure; another drain region, the other drain region being horizontally adjacent to a second side of the other gate structure opposite to the first side of the other gate structure, the other drain region of the other transistor being horizontally adjacent to the drain region of the transistor; and another channel region, the other channel region being vertically located below the other gate structure and horizontally between the other source region and the other drain region; another source contact structure, the other source contact structure being horizontally adjacent to the first side of the other gate structure of the other transistor and in contact with the other source region of the other transistor; and another drain contact structure, the other drain contact structure being horizontally adjacent to the second side of the other gate structure of the other transistor and in contact with the other drain region of the other transistor, the other drain contact structure being substantially horizontally aligned with the drain contact structure and exhibiting a horizontal area substantially the same as the horizontal area of ​​the drain contact structure.

[0111] Embodiment 23: The microelectronic device of Embodiment 22, wherein the drain contact structure, the source contact structure, the further drain contact structure, and the further source contact structure each exhibit substantially the same width and substantially the same length as one another.

[0112] Embodiment 24: A memory device comprising: a memory cell, which is operably coupled to a bit line and a word line; and a memory controller, which is operably coupled to the memory cell and includes a read-out device, the read-out device including: a transistor; a source contact structure, which is in contact with a source region of the transistor; and a drain contact structure, which is in contact with a drain region of the transistor, the length of the drain contact structure being greater than or equal to the length of the source contact structure.

[0113] Embodiment 25: A method, comprising: forming a ring-shaped spacer structure above a transistor, the transistor comprising a first conductive doping region and a second conductive doping region and a gate structure, the gate structure being located above a channel region between the first conductive doping region and the second conductive doping region, a portion of the spacer structure overlapping with the first conductive doping region; forming a masking structure above the spacer structure and the transistor, the masking structure exhibiting an opening therein, the opening overlapping with the first conductive doping region and the portion of the spacer structure; using the masking structure and the portion of the spacer structure as an etching mask to remove a portion of an isolation structure covering the first conductive doping region to form a trench, the trench exposing a portion of the first conductive doping region; and forming a first contact structure through the trench, the first contact structure contacting the portion of the first conductive doping region.

[0114] Embodiment 26: A method according to embodiment 25, wherein forming a spacer structure includes: forming another masking structure above the transistor, the other masking structure showing an opening therein, the opening overlapping the transistor; forming a spacer material over surfaces inside and outside the opening in the other masking structure; and removing selected portions of the spacer material to form the spacer structure.

[0115] Embodiment 27: A method according to one of embodiments 25 and 26, wherein removing a portion of the isolation structure covering the first conductive doped region includes: using the portion of the masking structure and the spacer structure as an etching mask to remove a portion of another masking structure between the isolation structure and each of the portions of the masking structure and the spacer structure to form a patterned another masking structure showing an additional opening; and using the patterned another masking structure as an etching mask to remove the portion of the isolation structure to form the trench.

[0116] Embodiment 28: The method of Embodiment 25, wherein forming a spacer structure further comprises forming the portion of the spacer structure to horizontally overlap the second conductive doping region and the gate structure.

[0117] Embodiment 29: The method of Embodiment 28, wherein forming a masking structure comprises forming the opening in the masking structure to overlap the second conductive doping region, the gate structure, the first conductive doping region, and the portion of the spacer structure.

[0118] Embodiment 30: The method according to embodiment 29 further includes using the masking structure and the portion of the spacer structure as an etching mask to remove a portion of another isolation structure covering the second conductive doped region to form another trench, wherein the other trench exposes a portion of the second conductive doped region.

[0119] Embodiment 31: The method according to Embodiment 30, further comprising forming a second contact structure through the another trench, the second contact structure contacting the portion of the second conductive doping region.

[0120] Embodiment 32: The method of Embodiment 31, wherein forming a second contact structure comprises forming the second contact structure and the first contact structure to exhibit substantially equal horizontal dimensions to each other and to be substantially horizontally aligned with each other.

[0121] Embodiment 33: The method according to any one of Embodiments 25 to 32, wherein the first conductive doped region acts as a drain region and the second conductive doped region acts as a source region.

[0122] Although the present disclosure may adopt various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, the present disclosure is not intended to be limited to the specific forms disclosed. On the contrary, the present disclosure will cover all modifications, equivalents and substitutes within the scope of the present disclosure as defined by the following appended claims and their legal equivalents.

Claims

1. A method of forming a microelectronic device, the method comprising: forming a spacer structure having a rectangular ring horizontal cross-sectional shape over the transistor, a portion of the spacer structure horizontally overlapping with a drain region of the transistor; forming a masking structure over the spacer structure and the transistor, the masking structure exhibiting an opening therein, the opening horizontally overlapping the drain region of the transistor and the portion of the spacer structure; removing a portion of an isolation structure covering the drain region of the transistor using the masking structure and the portion of the spacer structure as an etch mask to form a trench extending vertically through the isolation structure to the drain region of the transistor; as well as A drain contact structure is formed in the trench in the isolation structure.

2. The method of claim 1 , wherein forming the spacer structure comprises: forming another masking structure over the transistor, the another masking structure exhibiting a rectangular opening therein, the rectangular opening horizontally overlapping the transistor; forming a spacer material over surfaces inside and outside the rectangular opening in the other masking structure; as well as Portions of the spacer material located outside the rectangular opening are removed along a lower vertical boundary of the rectangular opening in the further masking structure to form the spacer structure. 3 . The method of claim 2 , further comprising removing a remaining portion of the another masking structure after forming the spacer structure.

4. The method according to claim 1 , wherein removing a portion of the isolation structure covering the drain region comprises: removing a portion of a further masking structure vertically between the isolation structure and each of the portions of the masking structure and the spacer structure using the masking structure and the portions of the spacer structure as an etch mask to form a patterned further masking structure exhibiting a further opening within a horizontal boundary of the isolation structure; as well as The portion of the isolation structure is removed using the patterned further masking structure as an etch mask to form the trench in the isolation structure.

5. The method according to claim 1, wherein forming a drain contact structure in the trench in the isolation structure comprises: forming a conductive material on surfaces inside and outside the trench in the isolation structure; as well as Portions of the conductive material outside the boundaries of the trenches in the isolation structure are removed to form the drain contact structure. 6 . The method of claim 1 , wherein forming a spacer structure further comprises forming the portion of the spacer structure to be horizontally interposed between the drain region of the transistor and another drain region of another transistor horizontally adjacent to the transistor. 7 . The method of claim 6 , further comprising forming another portion of the spacer structure to be horizontally interposed between another drain region of another transistor and another drain region of another transistor horizontally adjacent to the other transistor. 8 . The method of claim 6 , wherein forming a masking structure comprises forming the opening in the masking structure to horizontally overlap the drain region of the transistor, the portion of the spacer structure, and the further drain region of the further transistor. 9 . The method of claim 8 , further comprising forming the masking structure to exhibit another opening therein, the another opening horizontally overlapping a source region of the transistor.

10. The method according to claim 8 further includes using the masking structure and the portion of the spacer structure as an etching mask to remove another portion of the isolation structure covering the other drain region of the other transistor to form another trench, wherein the other trench vertically extends through the isolation structure to reach the other drain region of the other transistor, and another portion of the isolation structure is horizontally inserted between the trench in the isolation structure and the other trench in the isolation structure. 11 . The method of claim 10 , further comprising forming another drain contact structure within the another trench in the isolation structure. 12 . The method of claim 11 , wherein forming a further drain contact structure comprises forming the drain contact structure and the further drain contact structure to exhibit substantially equal horizontal dimensions to each other and to be substantially horizontally aligned to each other.

13. The method of claim 1, wherein forming a spacer structure further comprises forming the portion of the spacer structure to horizontally overlap a source region of the transistor and a gate structure of the transistor, the gate structure horizontally being between the source region of the transistor and the drain region of the transistor.

14. The method of claim 13, wherein forming a masking structure comprises forming the opening in the masking structure to horizontally overlap the source region of the transistor, the gate structure of the transistor, the drain region of the transistor, and the portion of the spacer structure.

15. The method according to claim 14 further includes using the masking structure and the portion of the spacer structure as an etching mask to remove a portion of another isolation structure covering the source region of the transistor to form another trench, which vertically extends through the other isolation structure to reach the source region of the transistor. 16 . The method of claim 15 , further comprising forming a source contact structure within the further trench in the further isolation structure. 17 . The method of claim 16 , wherein forming a source contact structure comprises forming the source contact structure and the drain contact structure to exhibit substantially equal horizontal dimensions to each other and to be substantially horizontally aligned to each other.

18. A microelectronic device comprising: A transistor, the transistor comprising: Gate structure; a dielectric cap structure vertically covering the gate structure and defined within a horizontal boundary of the gate structure, the dielectric cap structure having substantially the same vertical height throughout the entire horizontal length of the dielectric cap structure; a source region horizontally adjacent to the first side of the gate structure; a drain region horizontally adjacent to a second side of the gate structure opposite the first side of the gate structure; and a channel region, the channel region being vertically located below the gate structure and horizontally between the source region and the drain region; a source contact structure horizontally adjacent to the first side of the gate structure of the transistor and in contact with the source region of the transistor; and a drain contact structure horizontally adjacent to the second side of the gate structure of the transistor and in contact with the drain region of the transistor, the drain contact structure being substantially horizontally aligned with the source contact structure and exhibiting a horizontal area greater than or equal to a horizontal area of ​​the source contact structure, wherein an upper surface of each of the source contact structure and the drain contact structure is substantially coplanar with an upper surface of the dielectric cap structure. 19 . The microelectronic device according to claim 18 , further comprising a shallow trench isolation (STI) structure horizontally adjacent to the drain region and another drain region of the transistor. 20 . The microelectronic device of claim 19 , further comprising an isolation structure comprising a dielectric material covering the STI structure and portions of the drain region and the further drain region.

21. The microelectronic device of claim 18, further comprising: another transistor, the another transistor being horizontally adjacent to the transistor and comprising: another gate structure; the source region, the source region being horizontally adjacent to the first side of the another gate structure, the source region being shared between the transistor and the another transistor; another drain region horizontally adjacent to a second side of the another gate structure opposite to the first side of the another gate structure; and another channel region, the another channel region being vertically located below the another gate structure and horizontally between the source region and the another drain region; and another drain contact structure, wherein the another drain contact structure is horizontally adjacent to the second side of the another gate structure of the another transistor and in contact with the another drain region of the another transistor, the another drain contact structure being substantially horizontally aligned with the source contact structure and the drain contact structure and exhibiting a horizontal area substantially the same as a horizontal area of ​​the drain contact structure.

22. The microelectronic device of claim 18, further comprising: another transistor, the another transistor being horizontally adjacent to the transistor and comprising: another gate structure; another source region, the another source region being horizontally adjacent to the first side of the another gate structure; a further drain region horizontally adjacent to a second side of the further gate structure opposite to the first side of the further gate structure, the further drain region of the further transistor being horizontally adjacent to the drain region of the transistor; and another channel region, the another channel region being vertically located below the another gate structure and horizontally between the another source region and the another drain region; another source contact structure horizontally adjacent to the first side of the another gate structure of the another transistor and in contact with the another source region of the another transistor; and another drain contact structure, wherein the another drain contact structure is horizontally adjacent to the second side of the another gate structure of the another transistor and in contact with the another drain region of the another transistor, the another drain contact structure being substantially horizontally aligned with the drain contact structure and exhibiting a horizontal area substantially the same as a horizontal area of ​​the drain contact structure.

23. The microelectronic device of claim 22, wherein the drain contact structure, the source contact structure, the further drain contact structure, and the further source contact structure each exhibit substantially the same width and substantially the same length as one another.

24. A memory device comprising: a memory cell operatively coupled to the bit line and the word line; as well as a memory controller operatively coupled to the memory unit and comprising a readout device, the readout device comprising: A transistor, the transistor comprising: Gate structure; a dielectric cap structure vertically covering the gate structure and defined within a horizontal boundary of the gate structure, the dielectric cap structure having substantially the same vertical height throughout the entire horizontal length of the dielectric cap structure; a source region horizontally adjacent to the first side of the gate structure; a drain region horizontally adjacent to a second side of the gate structure opposite the first side of the gate structure; a source contact structure, the source contact structure being in contact with the source region of the transistor; and a drain contact structure, the drain contact structure being in contact with the drain region of the transistor, the length of the drain contact structure being greater than or equal to the length of the source contact structure, Wherein an upper surface of each of the source contact structure and the drain contact structure is substantially coplanar with an upper surface of the dielectric cap structure.

25. A method of forming a microelectronic device, comprising: forming a ring-shaped spacer structure on a transistor, the transistor comprising a first conductive doping region, a second conductive doping region and a gate structure, the gate structure being located on a channel region between the first conductive doping region and the second conductive doping region, a portion of the spacer structure overlapping the first conductive doping region; forming a masking structure over the spacer structure and the transistor, the masking structure exhibiting an opening therein, the opening overlapping the first conductive doped region and the portion of the spacer structure; removing a portion of the isolation structure covering the first conductive doped region using the masking structure and the portion of the spacer structure as an etching mask to form a trench, the trench exposing a portion of the first conductive doped region; as well as A first contact structure is formed through the trench, the first contact structure being in contact with the portion of the first conductive doping region.

26. The method of claim 25, wherein forming the spacer structure comprises: forming another masking structure over the transistor, the another masking structure exhibiting an opening therein, the opening overlapping the transistor; forming a spacer material over surfaces inside and outside the opening in the other masking structure; as well as Selected portions of the spacer material are removed to form the spacer structure.

27. The method of claim 25, wherein removing a portion of the isolation structure covering the first conductive doped region comprises: removing a portion of a further masking structure between the isolation structure and each of the portions of the masking structure and the spacer structure using the masking structure and the portions of the spacer structure as an etch mask to form a patterned further masking structure exhibiting a further opening; as well as The portion of the isolation structure is removed using the patterned further masking structure as an etch mask to form the trench. 28 . The method of claim 25 , wherein forming a spacer structure further comprises forming the portion of the spacer structure to horizontally overlap a second conductive doping region and the gate structure. 29 . The method of claim 28 , wherein forming a masking structure comprises forming the opening in the masking structure to overlap the second conductive doping region, the gate structure, the first conductive doping region, and the portion of the spacer structure.

30. The method of claim 29, further comprising using the masking structure and the portion of the spacer structure as an etching mask to remove a portion of another isolation structure covering the second conductive doped region to form another trench, the another trench exposing a portion of the second conductive doped region. 31 . The method of claim 30 , further comprising forming a second contact structure through the another trench, the second contact structure contacting the portion of the second conductive doped region.

32. The method of claim 31, wherein forming a second contact structure comprises forming the second contact structure and the first contact structure to exhibit substantially equal horizontal dimensions to each other and to be substantially horizontally aligned with each other.

33. The method of claim 25, wherein the first conductive doped region functions as a drain region and the second conductive doped region functions as a source region.

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