Memory device

Abstract

The invention discloses a memory device, which includes a channel element, a gate electrode layer, and a storage element. The channel element has a U shape. The gate electrode layer is electrically coupled to the channel element. The storage element surrounds the side channel surface of the channel element.

Description

Technical Field

[0001] The present invention relates to a memory device, and more particularly to a NAND memory device. Background Art

[0002] As the critical dimensions of components in integrated circuits are gradually reduced to the limits of process technology, designers have begun to look for technologies that can achieve higher memory density to achieve lower costs per bit. The technologies currently being focused on include NAND memory and its operation. Summary of the invention

[0003] The invention relates to a memory device.

[0004] According to one aspect of the present invention, a memory device is provided, comprising a channel element, a gate electrode layer, and a storage element. The channel element has a U shape. The gate electrode layer is electrically coupled to the channel element. The storage element surrounds a side channel surface of the channel element.

[0005] In order to better understand the above and other aspects of the present invention, embodiments are given below and described in detail with reference to the accompanying drawings: BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 A cross-sectional view of a memory device according to an embodiment is shown.

[0007] Figure 2 A longitudinal cross-sectional view of a memory device according to an embodiment is shown.

[0008] Figures 3 to 13 A method for manufacturing a memory device according to an embodiment is illustrated.

[0009]

Explanation of symbols

[0010] C: Channel element

[0011] CS1: First side channel surface

[0012] CS2: Second side channel surface

[0013] CS3: Third side channel surface

[0014] D1: First direction

[0015] D2: Second direction

[0016] D3: Third direction

[0017] M: Storage element

[0018] M1A: First storage layer

[0019] M1S1: Side surface

[0020] M2, M2A, M2B, M2C: Second storage tier

[0021] M3, M3A, M3B, M3C: The third storage layer

[0022] MA: First storage part

[0023] MB: Second storage part

[0024] MC: Third storage section

[0025] G, GT, GM, GB: gate electrode layer

[0026] GS1: Side surface

[0027] GS2: Top surface

[0028] GS3: Lower surface

[0029] 112: Dielectric Strip

[0030] 114: Conductive layer

[0031] 116: Electrode element

[0032] 118: Electrode element

[0033] 250: First stacking area

[0034] 260: Second stacking area

[0035] 330: Dielectric layer

[0036] 330S1: Side surface

[0037] 330S2: Upper surface

[0038] 330S3: Lower surface

[0039] 473, 474: Sacrificial layer

[0040] 475: Holes

[0041] 477: Notch

[0042] 480: Channel

[0043] 485: Gap

[0044] 487: Electrode Materials

[0045] 489: Conductive column

[0046] 491: Conductive strip

[0047] 493: Conductive block

[0048] 495: Conductive column

[0049] 497: Conductive strip DETAILED DESCRIPTION

[0050] The following are some examples for illustration. It should be noted that the present disclosure does not show all possible embodiments, and other embodiments not proposed in the present disclosure may also be applicable. Furthermore, the dimensional ratios on the drawings are not drawn in proportion to the actual product. Therefore, the description and illustrations are only used to describe the embodiments, and not to limit the scope of protection of the present disclosure. In addition, the descriptions in the embodiments, such as local structures, process steps, and material applications, are only for illustrative purposes and are not intended to limit the scope of protection of the present disclosure. The steps and structural details of the embodiments may be changed and modified according to the needs of the actual application process without departing from the spirit and scope of the present disclosure. The following is an illustration of the same / similar elements represented by the same / similar symbols.

[0051] Figure 1 A cross-sectional view of a memory device according to an embodiment is shown. Figure 2 A longitudinal cross-sectional view of a memory device according to an embodiment is shown. In one embodiment, Figure 1 Can be along Figure 2 The cross-section diagram drawn by the KK section line, and Figure 2 Can be along Figure 1 The cross-section diagram drawn by the JJ section line.

[0052] Please refer to Figure 1 , the memory device includes a channel element C, a gate electrode layer G and a storage element M.

[0053] In an embodiment, the channel element C has a U-shape. The side channel surface of the channel element C may include a first side channel surface CS1, a second side channel surface CS2, and a third side channel surface CS3. The second side channel surface CS2 is between the first side channel surface CS1 and the third side channel surface CS3. In an embodiment, the channel element C may have a horseshoe pattern or an open loop pattern in a U-shaped configuration. The first side channel surface CS1 (the outer side surface of the horseshoe pattern or the open loop pattern) and the third side channel surface CS3 (the inner side surface of the horseshoe pattern or the open loop pattern) have a U-shape. The second side channel surface CS2 (the end side surface of the horseshoe pattern or the open loop pattern) may have a straight shape. The dielectric pillar 110 may be on the third side channel surface CS3.

[0054] The memory element M may include several memory layers. In one embodiment, the memory element M includes a first memory layer M1A, a second memory layer M2, and a third memory layer M3. The second memory layer M2 is on the side surface of the first memory layer M1A. The third memory layer M3 is on the side surface of the second memory layer M2.

[0055] The storage element M includes a first storage portion MA and a second storage portion MB. The first storage portion MA is on the first side channel surface CS1. The first storage portion MA has a U shape. The second storage portion MB is on the second side channel surface CS2 of the channel element C. The second storage portion MB may be on a common side plane of the first storage layer M1A and the channel element C. The second storage portion MB has a straight shape. The first storage portion MA and the second storage portion MB form a ring shape, surrounding the side channel surface of the channel element C and the side surface of the dielectric pillar 110.

[0056] The number of storage layers of the first storage part MA may be different from the number of storage layers of the second storage part MB. In this embodiment, the number of storage layers of the first storage part MA is greater than the number of storage layers of the second storage part MB. The first storage part MA may include a first storage layer M1A, a second storage layer M2A, and a third storage layer M3A. In other words, the first storage part MA has 3 storage layers. The second storage part MB may include a second storage layer M2B and a third storage layer M3B. In other words, the second storage part MB has 2 storage layers. The second storage part MB may not include the first storage layer. The first storage layer M1A, the second storage layer M2A, and the third storage layer M3B of the first storage part MA have a U shape. The side surface M1S1 of the first storage layer M1A may be coplanar with the second side channel surface CS2 of the channel element C. The second storage layer M2B and the third storage layer M3B of the second storage part MB have a straight shape.

[0057] The first storage portion MA may include any charge trapping structure, such as an oxide-nitride-oxide (ONO) structure or an oxide-nitride-oxide-nitride-oxide (BE-SONOS) structure. For example, the charge trapping layer may use a nitride such as silicon nitride, or other similar high dielectric constant materials including metal oxides, such as aluminum oxide (Al2O3), zirconium oxide (HfO2), etc. The first storage layer M1A includes a tunneling layer. The second storage layer M2 (including the second storage layer M2A and the second storage layer M2B) includes a charge trapping layer. The third storage layer M3 (including the third storage layer M3A and the third storage layer M3B) includes a barrier layer. In one embodiment, the tunneling layer includes an oxide such as silicon oxide. The charge trapping layer includes a nitride such as silicon nitride. The barrier layer includes an oxide such as silicon oxide, aluminum oxide, etc.

[0058] The first storage portion MA and the channel element C are between the second storage portion MB and the gate electrode layer G. The second storage portion MB is between the dielectric pillar 110 and the dielectric strip 112. The dielectric pillar 110 may include an oxide such as silicon oxide, but is not limited thereto.

[0059] Please refer to Figure 1 and Figure 2 , the memory device may include a plurality of stacking regions, such as a first stacking region 250, a second stacking region 260, etc. The dielectric strip 112 is between the gate electrode layer G of the first stacking region 250 and the gate electrode layer G of the second stacking region 260. The first stacking region 250 and the second stacking region 260 each include a gate electrode layer G and a dielectric layer 330. The gate electrode layer G and the dielectric layer 330 are alternately arranged in a first direction D1 (e.g., a vertical direction). The gate electrode layer G is electrically coupled to the channel element C. The gate electrode layer G may include a gate electrode layer GT at the topmost layer, a gate electrode layer GB at the bottommost layer, and a gate electrode layer GM between the gate electrode layer GT and the gate electrode layer GB. The stacking regions of the memory device, such as the first stacking region 250, the second stacking region 260, etc., may be arranged in a horizontal direction (e.g., a second direction D2).

[0060] In one embodiment, the memory element M further includes a third memory portion MC. The first memory portion MA is connected between the second memory portion MB and the third memory portion MC. The third memory portion MC may extend continuously from the first memory portion MA to the side surface 330S1, the upper surface 330S2, and the lower surface 330S3 of the dielectric layer 330, and the upper surface GS2 and the lower surface GS3 of the gate electrode layer G.

[0061] The memory element M is between the gate electrode layer G and the dielectric layer 330. The memory element M is on the side surface GS1 (side electrode surface), the upper surface GS2 (upper electrode surface), and the lower surface GS3 (lower electrode surface) of the gate electrode layer G. The memory element M is on the side surface 330S1 (side dielectric surface), the upper surface 330S2 (upper dielectric surface), and the lower surface 330S3 (lower dielectric surface) of the dielectric layer 330. The side surface GS1 having the memory element M thereon is relative to the side surface 330S1 having the memory element M thereon.

[0062] The number of storage layers of the first storage part MA may be different from the number of storage layers of the third storage part MC, or have a different storage layer configuration. The number of storage layers of the first storage part MA may be greater than the number of storage layers of the third storage part MC. The number of storage layers of the third storage part MC may be the same as the number of storage layers of the second storage part MB, or have the same storage layer configuration. The storage layers of the third storage part MC may include a second storage layer M2C and a third storage layer M3C. The third storage part MC may not include the first storage layer.

[0063] The conductive layer 114 may be on the first memory layer M1A, the channel element C and the dielectric pillar 110. The electrode element 116 and the electrode element 118 are respectively electrically connected to the conductive layer 114 separated from the second memory portion MB by the dielectric strip 112.

[0064] The memory device includes a NAND memory string. The NAND memory string may include a memory cell defined in a memory element M between a gate electrode layer G of a channel element C. The NAND memory string may include a U-shaped channel NAND memory string, or a vertical channel NAND memory string.

[0065] In one embodiment, the electrode element 116 may be a bit line, and the electrode element 118 may be a common source line. The NAND memory string may include a memory cell defined in a memory element M between a channel element C and a gate electrode layer G of the first stack region 250 and the second stack region 260. The NAND memory string has a U-shaped effective channel path, and the U-shaped channel is electrically connected to the memory cell between the electrode element 116 as a bit line and the electrode element 118 as a common source line. The gate electrode layer GT of the first stack region 250 may be used as a string selection line (SSL). The gate electrode layer GT of the second stack region 260 may be used as a ground selection line (GSL). In one embodiment, the gate electrode layer GB of the first stack region 250 and the gate electrode layer GB of the second stack region 260 may be used as an inversion gate electrode. In one embodiment, the gate electrode layer GM of the first stack region 250 and the gate electrode layer GM of the second stack region 260 may be used as a word line. In one embodiment, a portion of the gate electrode layer GM adjacent to the gate electrode layer GT in the first stack region 250 and / or the second stack region 260 can be used as a dummy word line to avoid possible interference. For example, the top gate electrode layer GM in the first stack region 250 and the top gate electrode layer GM in the second stack region 260 can be used as a dummy word line. The substrate 100 can be an insulating layer, such as a buried oxide such as buried silicon oxide formed on a semiconductor substrate, but is not limited thereto.

[0066] In another embodiment, the electrode element 116 may be a bit line. The substrate 100 may be electrically connected to a common source terminal, or used as a common source element. The substrate 100 may include a semiconductor substrate such as a substrate containing a silicon material, such as a silicon substrate. The NAND memory string may include a memory cell defined in a memory element M between a channel element C and a gate electrode layer G of the first stacking region 250. The NAND memory string has an effective vertical channel path extending in a first direction D1 (e.g., a vertical direction), and is electrically connected between the electrode element 116 and the substrate 100. The gate electrode layer GT of the first stacking region 250 may be used as a string selection line (SSL). The gate electrode layer GB of the first stacking region 250 may be used as a ground selection line (GSL). In one embodiment, the gate electrode layer GM of the first stacking region 250 may be used as a word line. In one embodiment, a portion of the gate electrode layer GM of the first stacking region 250 may be used as a dummy word line. The electrode element 118 may also be used as a bit line, and the vertical channel NAND memory string on the second stacking region 260 side may also be analogized as described above.

[0067] Figures 3 to 13 A method for manufacturing a memory device according to an embodiment is illustrated.

[0068] Please refer to Figure 3 , providing a substrate 100. A stacked structure may be formed on the substrate 100. The stacked structure may include sacrificial layers and dielectric layers 330 stacked alternately on the substrate 100. The sacrificial layer may include a sacrificial layer 474 and a sacrificial layer 473 thereunder. The sacrificial layer 473, the sacrificial layer 474, and the dielectric layer 330 may include different materials. In one embodiment, the sacrificial layer 473 and the sacrificial layer 474 include nitrides, such as silicon nitride, but not limited thereto. The dielectric layer 330 includes an oxide, such as silicon oxide, but not limited thereto. The sacrificial layer 473, the sacrificial layer 474, and the dielectric layer 330 may be formed using a deposition method such as physical vapor deposition, chemical vapor deposition, or other suitable methods. A hole 475 may be formed in the stacked structure using photolithography and etching techniques. In one embodiment, the etching step for forming the hole 475 may stop on the substrate 100. In one embodiment, the hole 475 exposes the buried oxide layer of the substrate 100.

[0069] Please refer to Figure 4, the first memory layer M1A may be formed on the side surface of the stacked structure exposed by the hole 475 and the upper surface of the substrate 100. The first memory layer M1A may also be formed on the upper surface of the stacked structure. The channel element C may be formed on the first memory layer M1A exposed by the hole 475. The channel element C may also be formed on the first memory layer M1A on the upper surface of the stacked structure. The channel element C may include polysilicon or other suitable semiconductor materials. In one embodiment, a dielectric pillar 110 may be formed on the channel element C and fill the hole 475. In one embodiment, a method for forming the dielectric pillar 110 may include forming a dielectric material filling the hole 475 and extending on the channel element C on the upper surface of the stacked structure, and chemical mechanical polishing or other suitable etching methods may be used to remove the dielectric material on the upper surface of the stacked structure, and the remaining dielectric material remaining in the hole 475 forms the dielectric pillar 110. The dielectric material may include an oxide such as silicon oxide, but is not limited thereto. The first memory layer M1A and the channel element C above the upper surface of the stacked structure may also be removed by chemical mechanical polishing or other suitable etching methods. The first memory layer M1A, the channel element C and the dielectric pillar 110 in the hole 475 may be etched back by a suitable etching method to form a notch 477. The depth of the notch 477 does not reach the upper surface of the top sacrificial layer 473.

[0070] Please refer to Figure 5 , the conductive layer 114 may form a filling recess 477. In one embodiment, the method for forming the conductive layer 114 may include forming a conductive material filling recess 477 on the upper surface of the stacked structure, and removing the portion of the conductive layer 114 located on the upper surface of the stacked structure by chemical mechanical polishing or other suitable etching methods. The conductive material may include doped polysilicon, such as heavily doped N-type polysilicon, or other suitable conductive materials such as metals. In one embodiment, the sacrificial layer 474 and the conductive layer 114 above the topmost dielectric layer 330 of the stacked structure may be removed by chemical mechanical polishing or other suitable etching methods (such as back etching) to planarize the upper surface of the stacked structure.

[0071] Figure 5A Draw Figure 5 A cross-sectional view of the memory device of FIG. 1 along the KK section line. Please refer to Figure 5A In one embodiment, the dielectric pillar 110 in the hole 475 may have an elliptical shape or a playground shape. The channel element C has a ring shape and surrounds the dielectric pillar 110. The first memory layer M1A has a ring shape and surrounds the channel element C. Figure 5B Draw Figure 5 A cross-sectional view of the memory device along the QQ section line. Figure 5B , the conductive layer 114 may have an elliptical shape or a playground shape. Figure 5 for Figure 5A and Figure 5B The memory device is shown in longitudinal section along section line JJ.

[0072] Please refer to Figure 6 , a channel 480 may be formed. The channel 480 may be formed by patterning the conductive layer 114 and the stacked structure, the dielectric pillar 110, the channel element C, and the upper portion of the first storage layer M1A using photolithography and etching techniques. The channel 480 may expose the side surface of the dielectric pillar 110, the second side channel surface CS2 of the channel element C, the side surface M1S1 of the first storage layer M1A, the side surface of the sacrificial layer 473, the side surface of the dielectric layer 330, and the side surface of the conductive layer 114. The bottom of the channel 480 may expose the dielectric pillar 110, the channel element C, the first storage layer M1A, and the sacrificial layer 473 of the stacked structure. The channel 480 defines different stacking regions (the first stacking region 250 and the second stacking region 260, etc.) of the stacked structure, so that the sacrificial layers 473 of different stacking regions are separated from each other.

[0073] Fig. 6A Draw Figure 6 A cross-sectional view of the memory device of FIG. 1 along the KK section line. Please refer to Fig. 6A , the channel 480 extends in the third direction D3, and the patterned dielectric pillar 110 has a semicircular shape. The patterned channel element C may have a U shape, a horseshoe shape, or an open loop shape. The patterned first memory layer M1A may have a U shape, a horseshoe shape, or an open loop shape. Figure 6B Draw Figure 6 A cross-sectional view of the memory device along the QQ section line. Figure 6B , the patterned conductive layer 114 may have a semicircular shape. Figure 6 for Fig. 6A and Figure 6B The memory device is shown in longitudinal section along section line JJ.

[0074] Please refer to Figure 7 , the sacrificial layer 473 ( Figure 6 ) to form a gap 485. The sacrificial layer 473 can be removed by an etching process with etching selectivity. The gap 485 connects the channel 480. The gap 485 can expose the side surface of the first memory layer M1A, the upper surface 330S2 and the lower surface 330S3 of the dielectric layer 330, and the upper surface of the substrate 100.

[0075] Fig. 7A Draw Figure 7 A cross-sectional view of the memory device of FIG. 1 along the KK section line. Please refer to Fig. 7A At this step, the memory device can use the dielectric pillar 110, the channel element C and the first memory layer M1A as a support body to support other elements, such as the dielectric layer 330. Figure 7 for Fig. 7A The memory device is shown in longitudinal section along section line JJ.

[0076] Please refer to Figure 8 The second memory layer M2 may be formed on the dielectric pillar 110 , the channel element C, the first memory layer M1A, the dielectric layer 330 , and the substrate 100 where the channel 480 and the gap 485 are exposed.

[0077] Please refer to Fig. 9 , the third memory layer M3 may be formed on the second memory layer M2 exposed by the channel 480 and the slit 485 .

[0078] Fig. 9A Draw Fig. 9 A cross-sectional view of the memory device of FIG. 1 along the KK section line. Please refer to Fig. 9A The second memory layer M2 may have a ring shape and surround the dielectric pillar 110, the channel element C and the first memory layer M1A. The third memory layer M3 may have a ring shape and surround the second memory layer M2. Fig. 9 for Fig. 9A The memory device is shown in longitudinal section along section line JJ.

[0079] Please refer to Fig.10 , the electrode material 487 may be formed on the third memory layer M3 exposed by the channel 480 and the gap 485. The electrode material 487 may fill the gap 485. In one embodiment, the electrode material 487 may include a barrier metal such as titanium nitride (TiN), and a filling metal such as tungsten (W) formed on the barrier metal. However, the present disclosure is not limited thereto. The electrode material 487 may also include other suitable configurations / materials such as polysilicon or other metals and other conductive materials.

[0080] Please refer to Fig.11 , can be used for electrode material 487( Fig.10 ) performs an etch-back step to remove the portion of the electrode material 487 in the trench 480 and leave the portion in the gap 485 to form a gate electrode layer G. Different layers of the gate electrode layers G can be separated from each other and electrically isolated by the dielectric layer 330.

[0081] Please refer to Fig.12 , a dielectric strip 112 may be formed to fill the trench 480. The dielectric strip 112 may also fill a portion of the gap 485. The dielectric strip 112 may include an oxide such as silicon oxide, but is not limited thereto.

[0082] Please refer to Fig.13, a conductive column 489 may be formed on the conductive layer 114. A conductive strip 491 and a conductive block 493 may be formed on the conductive column 489. A conductive column 495 may be formed on the conductive block 493. A conductive strip 497 may be formed on the conductive column 495. In one embodiment, the conductive strip 497 may extend in the second direction D2. The conductive strip 491 may extend in the third direction D3. In one embodiment, the conductive strip 491 may be used as a common source line. The conductive strip 497 may be used as a bit line. The U-shaped channel element C may be electrically connected between the conductive strip 491 and the conductive strip 497. The first direction D1, the second direction D2, and the third direction D3 may be different from each other, for example, substantially perpendicular to each other. The first direction D1 may be the Z direction. The second direction D2 may be the X direction. The third direction D3 may be the Y direction.

[0083] In summary, although the present invention has been disclosed by way of embodiments, it is not intended to limit the present invention. A person skilled in the art of the present invention may make various modifications and alterations without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the definition of the appended claims.

Claims

1. A memory device, comprising: a dielectric strip; a channel element having a U shape and disposed symmetrically with respect to the dielectric strip; a gate electrode layer electrically coupled to the channel element; and A memory element surrounds one side channel surface of the channel element and is located between the dielectric strip and the channel element, wherein a memory cell is defined in the memory element between the channel element and the gate electrode layer.

2. The memory device of claim 1 , wherein the side channel surface of the channel element comprises a first side channel surface, a second side channel surface and a third side channel surface, the second side channel surface is between the first side channel surface and the third side channel surface, the first side channel surface and the third side channel surface have a U-shape, wherein the memory element comprises: a first storage portion on the first side channel surface; and A second storage portion is on the second side channel surface. 3 . The memory device of claim 2 , wherein the first storage portion has a U-shape and the second storage portion has a straight shape.

4. The memory device of claim 2, wherein the number of storage layers of the first storage portion is different from the number of storage layers of the second storage portion.

5. The memory device of claim 2, wherein the number of storage layers of the first storage portion is greater than the number of storage layers of the second storage portion.

6. The memory device of claim 1, wherein the storage element comprises: a first storage layer; a second storage layer on one side surface of the first storage layer; and a third storage layer, on one side surface of the second storage layer, The storage element comprises: A first storage portion, comprising the first storage layer, the second storage layer and the third storage layer; and A second storage portion is adjacent to the first storage portion and includes the second storage layer and the third storage layer.

7. The memory device as claimed in claim 1, comprising a plurality of the gate electrode layers, wherein the memory device further comprises a plurality of dielectric layers, the gate electrode layers and the dielectric layers are arranged alternately in a vertical direction, and the storage element is between the gate electrode layers and the dielectric layers.

8. The memory device of claim 7, wherein the memory element is on an upper electrode surface and a lower electrode surface of each of the gate electrode layers, and on an upper dielectric surface and a lower dielectric surface of each of the dielectric layers.

9. The memory device of claim 7, wherein the memory element is on a side electrode surface of each of the gate electrode layers and on a side dielectric surface of each of the dielectric layers, the side electrode surfaces being opposite to the side dielectric surfaces.

10. The memory device of claim 7, wherein the channel element comprises a first side channel surface, the first side channel surface having a U-shape, the memory element comprising: a first storage portion on the first side channel surface; and A third storage portion is connected to the first storage portion and continuously extends to the upper surface, the lower surface and / or the side surface of the dielectric layers.

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