Display device and method for manufacturing the same

Abstract

The present invention relates to a display device and a method for manufacturing the same. The display device includes a pixel circuit arranged in a display area and a driving circuit arranged in a peripheral area. The driving circuit includes a first transistor, and each pixel circuit includes a second transistor. The first transistor includes a first active pattern arranged on a substrate, a first gate insulating layer having a first outer portion arranged on the first active pattern, and a first gate electrode arranged on the first gate insulating layer. The second transistor includes a second active pattern arranged on the substrate, a second gate insulating layer having a second outer portion arranged on the second active pattern, and a second gate electrode arranged on the second gate insulating layer. The first outer portion does not overlap with the first gate electrode and has a first width. The second outer portion does not overlap with the second gate electrode and has a second width smaller than the first width.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority benefit of Korean Patent Application No. 10-2019-0092385 filed on July 30, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a display device and a method for manufacturing the same. Background Art

[0004] A display device, such as a liquid crystal display (LCD) and an organic light emitting diode (OLED) display, includes a display panel, and the display panel includes a display area and a peripheral area. The display area is an area where an image can be displayed.

[0005] In the display area, there are a plurality of pixels (which are units for displaying images), and a plurality of signal lines. The plurality of signal lines may include a gate line and a data line. Each pixel may include a pixel circuit portion including at least one pixel transistor, and a display portion connected to each pixel circuit portion. The pixel circuit portion may include at least one pixel transistor connected to the data line and the gate line, and the display portion may include a pixel electrode for receiving a data signal from the pixel circuit portion.

[0006] The peripheral area may include a driving circuit portion and a plurality of voltage lines connected to a plurality of signal lines to which driving signals may be applied. The driving circuit portion includes a plurality of driving transistors. Summary of the invention

[0007] At least one embodiment of the present disclosure has been attempted to provide a display device having a driving circuit portion that can stably operate without degradation of a driving transistor of the driving circuit portion when subjected to a very high voltage.

[0008] A display device according to an exemplary embodiment of the present invention includes: a substrate having a display area and a peripheral area surrounding the display area; a plurality of pixel circuit parts and a plurality of signal lines arranged in the display area; and a driving circuit part arranged in the peripheral area and connected to the plurality of signal lines. The driving circuit part includes a first transistor, the first transistor having a first active pattern arranged on the substrate, a first gate insulating layer arranged on the first active pattern, and a first gate electrode arranged on the first gate insulating layer. Each pixel circuit part includes a second transistor, the second transistor having a second active pattern arranged on the substrate, a second gate insulating layer arranged on the second active pattern, and a second gate electrode arranged on the second gate insulating layer. The first gate insulating layer includes a first outer portion that does not overlap with the first gate electrode in the first direction. The second gate insulating layer includes a second outer portion that does not overlap with the second gate electrode in the first direction. The first width of the first outer portion in a second direction different from the first direction is greater than the second width of the second outer portion in the second direction.

[0009] A display device according to an exemplary embodiment of the present invention includes: a substrate having a display area and a peripheral area surrounding the display area; a plurality of pixel circuit parts and a plurality of signal lines arranged in the display area; and a driving circuit part arranged in the peripheral area and connected to the plurality of signal lines. The driving circuit part includes a first transistor, the first transistor having a first active pattern arranged on the substrate, a first gate insulating layer arranged on the first active pattern, and a first gate electrode arranged on the first gate insulating layer. The first gate insulating layer includes a first outer portion that does not overlap with the first gate electrode in a first direction, and the first outer portion includes a portion having a different width in a second direction different from the first direction.

[0010] A display device according to an exemplary embodiment of the present invention includes: a substrate having a display area and a peripheral area surrounding the display area; a plurality of pixel circuit parts and a plurality of signal lines arranged in the display area; and a driving circuit part arranged in the peripheral area and connected to the plurality of signal lines. The driving circuit part includes a first transistor, the first transistor having a first active pattern arranged on the substrate, a first gate insulating layer arranged on the first active pattern, a first gate electrode arranged on the first gate insulating layer, a dummy insulating layer arranged on the first active pattern and separated from the first gate insulating layer, and a dummy electrode arranged on the dummy insulating layer and separated from the first gate electrode. The dummy electrode includes the same material as the material of the first gate electrode and has a width smaller than the width of the first gate electrode. The dummy insulating layer includes the same material as the material of the first gate insulating layer and has a width smaller than the width of the first gate insulating layer.

[0011] A method for manufacturing a display device according to an exemplary embodiment of the present invention includes: forming a first insulating layer on a substrate including a display area and a peripheral area surrounding the display area; forming a first active pattern on the first insulating layer in the peripheral area, and forming a second active pattern on the first insulating layer in the display area; forming a second insulating layer on the first active pattern and the second active pattern; forming a conductive layer on the second insulating layer; forming a photoresist layer on the conductive layer; applying light to the photoresist layer through a photomask; exposing the photoresist layer to a developing solution to produce a first mask pattern in the peripheral area and a second mask pattern in the display area; etching the conductive layer using the first mask pattern and the second mask pattern as masks to produce a first gate electrode in the peripheral area and a second gate electrode in the display area; and etching the second insulating layer using the first mask pattern and the second mask pattern as masks to produce a first gate insulating layer in the peripheral area and a second gate insulating layer in the display area. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a plan layout diagram of a display device according to an exemplary embodiment of the present invention,

[0013] Figure 2 is a top plan view of a pixel transistor included in a pixel circuit portion of a display device according to an exemplary embodiment of the present invention,

[0014] Figure 3 For along Figure 2 A cross-sectional view of a display device taken along line IIIa-IIIb,

[0015] Figure 4 is a top plan view of a driving transistor included in a driving circuit portion of a display device according to an exemplary embodiment of the present invention,

[0016] Figure 5 For along Figure 4 A cross-sectional view of a display device taken along line Va-Vb,

[0017] Figure 6 1 is a graph showing a change amount of a threshold voltage according to a length of an outer portion of a gate insulating layer of a driving transistor included in a driving circuit portion of a display device according to an exemplary embodiment of the present invention,

[0018] Figure 7 is a graph showing an on-current retention rate according to a length of an outer portion of a gate insulating layer of a driving transistor included in a driving circuit portion of a display device according to an exemplary embodiment of the present invention,

[0019] Figure 8Graphs for explaining changes in a source-drain current graph with respect to a gate terminal voltage of a driving transistor included in a driving circuit portion of a display device according to a comparative example, and changes in a source-drain current graph of a driving transistor included in a driving circuit portion according to an exemplary embodiment of the present invention,

[0020] Fig. 9 , Fig.10 , Fig.11 and Fig.12 A manufacturing process of a pixel transistor included in a pixel circuit portion of a display device according to an exemplary embodiment of the present invention is sequentially explained.

[0021] Fig.13 , Fig.14 , Fig.15 and Fig.16 A method of manufacturing a driving transistor included in a driving circuit portion of a display device according to an exemplary embodiment of the present invention is sequentially shown,

[0022] Fig.17 is a cross-sectional view of a driving transistor included in a driving circuit portion of a display device according to an exemplary embodiment of the present invention,

[0023] Fig.18 , Fig.19 , Fig. 20 and Fig.21 The manufacturing process of the driving transistor included in the driving circuit part of the display device according to the exemplary embodiment of the present invention is sequentially shown,

[0024] Fig. 22 is a top plan view of a driving transistor included in a driving circuit portion of a display device according to an exemplary embodiment of the present invention,

[0025] Fig.23 For along Fig. 22 A cross-sectional view of a display device taken along line XXIIIa-XXIIIb,

[0026] Fig.24 , Fig.25 , Fig.26 and Fig. 27 The manufacturing process of the driving transistor included in the driving circuit part of the display device according to the exemplary embodiment of the present invention is sequentially shown,

[0027] Fig.28 is a plan layout diagram of a plurality of pixels of a display device according to an exemplary embodiment of the present invention,

[0028] Fig.29 is a plan layout diagram of a pixel electrode and a plurality of data lines of a display device according to an exemplary embodiment of the present invention, and

[0029] Fig.30 For along Fig.28 A cross-sectional view of a display device taken along line XXXa-XXXb. DETAILED DESCRIPTION

[0030] In the following detailed description, exemplary embodiments of the present invention have been shown and described. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

[0031] The drawings and description should be regarded as illustrative in nature and not restrictive. Like reference numerals refer to like elements throughout the specification.

[0032] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present.

[0033] Throughout the specification, the term "in a plan view" means a view (also referred to as a plan view) for observing a plane parallel to two intersecting directions (e.g., a first direction DR1 and a second direction DR2), and a cross-sectional view refers to a view for observing a plane cut in a direction perpendicular to the plane parallel to the first direction DR1 and the second direction DR2 (e.g., a third direction DR3). In addition, when two constituent elements overlap, the two constituent elements overlap in the third direction DR3 (e.g., in a direction perpendicular to the top surface of the substrate) unless otherwise indicated.

[0034] refer to Figure 1 , a display device according to an exemplary embodiment of the present invention will be described.

[0035] Figure 1 is a plan layout diagram of a display device according to an exemplary embodiment of the present invention.

[0036] refer to Figure 1 , the display device 1000 according to the exemplary embodiment of the present invention includes a substrate 110 including a display area DA and a peripheral area PA around the display area DA.

[0037] The display area DA is an area where an image can be displayed, and includes a plurality of pixels PX and a plurality of signal lines including a plurality of gate lines 121 and a plurality of data lines 171 .

[0038] Each pixel PX may include a pixel circuit portion (e.g., a pixel circuit) and a display portion (e.g., a display element). The pixel circuit portion includes at least one pixel transistor Ta, and the display portion is connected to the pixel circuit portion of each pixel PX. The pixel circuit portion may be regularly arranged in the display area DA, and the display portion may be regularly arranged in the display area DA. For example, a regular arrangement may be created by setting each row of the display area DA to include an equal number of pixel circuit portions and display portions that are equally spaced from each other. In a plan view, the display portion and the pixel circuit portion corresponding to each other may overlap or may not overlap each other. The pixel circuit portion may include at least one pixel transistor Ta connected to the data line 171 and the gate line 121, and the display portion may include a pixel electrode that receives a data signal from the pixel circuit portion. The display portion may be, for example, a light emitting diode. The pixel transistor Ta includes a gate terminal Ga, a source terminal Sa, and a drain terminal Da. The detailed structure of the pixel circuit portion and the display portion will be described in more detail later.

[0039] Unlike the display area DA, most or all of the peripheral area PA is a non-display area that does not display an image, but is not limited thereto. The peripheral area PA may include a driving circuit portion 400a and a driving circuit portion 400b (e.g., a driving circuit), a plurality of driving wirings 401, and a pad portion PAD. For example, the pad portion PAD may include one or more conductive pads for receiving an external voltage to be supplied to the driving wiring 401 and / or for receiving a data voltage to be supplied to the data line 171.

[0040] The driving circuit part 400a and the driving circuit part 400b may be connected to a plurality of signal lines, for example, a plurality of gate lines 121, provided in the display area DA, and may apply a driving signal. For example, the driving circuit part 400a and the driving circuit part 400b may sequentially apply a gate signal to the plurality of gate lines 121. Sequentially applying a gate signal to the gate lines 121 may be referred to as scanning the gate lines 121. The driving circuit part 400a and the driving circuit part 400b may apply a gate signal to a gate terminal Ga of a pixel transistor Ta connected to the gate line 121 of the display area DA in units of rows.

[0041] Although the driving circuit part 400a and the driving circuit part 400b are shown as being placed at respective sides relative to the display area DA, one of the two driving circuit parts 400a and 400b can be omitted. The driving circuit part 400a and the driving circuit part 400b can include a plurality of driving circuits that can output gate signals, and each driving circuit includes at least one driving transistor Td. The driving transistor Td includes a gate terminal Gd, a source terminal Sd and a drain terminal Dd. A plurality of driving circuits included in each driving circuit part 400a and the driving circuit part 400b can be arranged in the second direction DR2. For example, the driving transistor Td can be arranged in the first column in the driving circuit part 400a, and can be arranged in the second column in the driving circuit part 400b. For example, each driving circuit can be configured as a different subset of control gate lines 121.

[0042] A plurality of drive wirings 401 may include a portion extending substantially or precisely in the second direction DR2, and may be connected to the pad portion PAD. The drive wiring 401 may include wiring for transmitting various voltages and signals for driving the drive circuit portion 400a and the drive circuit portion 400b and the pixel circuit portion, such as a plurality of voltage lines. The voltage line may include a low voltage line for transmitting a low voltage for generating a gate signal, a high voltage line for transmitting a high voltage for generating a gate signal, a drive voltage line, and various clock signal lines. For example, a low voltage may be used to generate a gate-on voltage for generating a gate signal, and a high voltage may be used to generate a gate-off voltage for generating a gate signal. The gate-on voltage may be used to turn on a transistor of a pixel circuit portion of a pixel PX to receive a data voltage from a data line 171, and the gate-off voltage may be used to turn off a transistor to prevent the pixel PX from receiving a data voltage. At least a portion of the drive wiring 401 may be connected to the drive circuit portion 400a and the drive circuit portion 400b.

[0043] The pad portion PAD may be disposed near one edge of the substrate 110 where the driving circuit portion 400a and the driving circuit portion 400b are not placed. The plurality of data lines 171 may extend to the peripheral area PA and thus may be connected to the pad portion PAD. The display device 1000 according to an exemplary embodiment of the present invention may further include at least one of a flexible printed circuit film, a driving circuit chip, and a printed circuit board connected to the pad portion PAD. The plurality of data lines 171 may receive data signals through the pad portion PAD.

[0044] The driving transistors Td of the driving circuit part 400 a and the driving circuit part 400 b may be formed on the same substrate 110 together with the pixel transistor Ta of the pixel circuit part provided in the display area DA through the same process.

[0045] refer to Figures 2 to 5 as well as Figure 1, detailed structures of the pixel transistor Ta provided in each pixel PX of the display area DA and the driving transistor Td included in the driving circuit part 400a and the driving circuit part 400b of the peripheral area PA will now be described.

[0046] Figure 2 is a top plan view of a pixel transistor Ta included in a pixel circuit portion of a display device, Figure 3 For along Figure 2 A cross-sectional view of a display device taken along line IIIa-IIIb, Figure 4 is a top plan view of a driving transistor Td included in a driving circuit portion of a display device according to an exemplary embodiment of the present invention, and Figure 5 For along Figure 4 A cross-sectional view taken along line Va-Vb of the display device shown in FIG.

[0047] A buffer layer 120, which is an insulating layer, may be disposed on the substrate 110. The substrate 110 may include an insulating material such as glass or plastic, and may have elasticity.

[0048] The active pattern 131a and the active pattern 131d are disposed on the buffer layer 120. The active pattern 131a is disposed on the pixel PX of the display area DA, and the active pattern 131d is disposed in the driving circuit part 400a and the driving circuit part 400b of the peripheral area PA.

[0049] The active pattern 131a includes a channel region 134a, a source region 133a, and a drain region 135a forming a channel of the pixel transistor Ta. The source region 133a and the drain region 135a are conductive regions connected to the channel region 134a. The active pattern 131d includes a channel region 134d, a source region 133d, and a drain region 135d forming a channel of the driving transistor Td. The source region 133d and the drain region 135d are conductive regions connected to the channel region 134d. The source region 133a and the source region 133d and the drain region 135a and the drain region 135d may be interchangeably named to distinguish the conductive regions placed on both sides of the channel region 134a and the channel region 134d. In an exemplary embodiment, the carrier concentrations of the source regions 133 a and 133 d and the drain regions 135 a and 135 d are higher than the carrier concentrations of the channel regions 134 a and 134 d .

[0050] The active pattern 131a and the active pattern 131d may include an oxide semiconductor material, such as indium gallium zinc oxide (IGZO) or zinc tin oxide (ZTO), but is not limited thereto. A patterned gate insulating layer 144a is disposed on the active pattern 131a, and a patterned gate insulating layer 144d is disposed on the active pattern 131d. The gate insulating layer 144a is disposed on the channel region 134a of the active pattern 131a while overlapping the channel region 134a, and the gate insulating layer 144d is disposed on the channel region 134d of the active pattern 131d while overlapping the channel region 134d. The gate insulating layer 144a may overlap a boundary between the source region 133a or drain region 135a of the active pattern 131a and the channel region 134a. The gate insulating layer 144d may overlap a boundary between the source region 133d or drain region 135d of the active pattern 131d and the channel region 134d.

[0051] refer to Figure 2 , a boundary between the source region 133a or the drain region 135a of the active pattern 131a and the channel region 134a may extend substantially parallel to an edge of the gate insulating layer 144a. Figure 4 , a boundary between the source region 133d or the drain region 135d and the channel region 134d of the active pattern 131d may extend substantially parallel to an edge of the gate insulating layer 144d.

[0052] The gate electrode 154a may be disposed on the gate insulating layer 144a, and the gate electrode 154d may be disposed on the gate insulating layer 144d. The gate electrode 154a may overlap the gate insulating layer 144a and the channel region 134a of the active pattern 131a, and may intersect the active pattern 131a. The gate electrode 154d may overlap the gate insulating layer 144d and the channel region 134d of the active pattern 131d, and may intersect the active pattern 131d.

[0053] refer to Figures 2 to 4 , an edge of the gate electrode 154a may be placed inside an edge of the gate insulating layer 144a, and an edge of the gate electrode 154d may be placed inside an edge of the gate insulating layer 144d. For example, an edge of the gate insulating layer 144a may extend beyond an edge of the gate electrode 154a. For example, an edge of the gate insulating layer 144d may extend beyond an edge of the gate electrode 154d. In a plan view, an edge of the gate electrode 154a may be substantially parallel to an edge of the gate insulating layer 144a, and an edge of the gate electrode 154d may be substantially parallel to an edge of the gate insulating layer 144d.

[0054] The insulating layer 160 is disposed on the gate electrode 154a and the gate electrode 154d. The insulating layer 160 may include an opening 63 disposed on the source region 133a of the active pattern 131a, an opening 65 disposed on the drain region 135a of the active pattern 131a, an opening 63d disposed on the source region 133d of the active pattern 131d, and an opening 65d disposed on the drain region 135d of the active pattern 131d.

[0055] At least one of the buffer layer 120, the gate insulating layers 144a and 144d, and the insulating layer 160 may include an inorganic insulating material, such as silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiON) and / or organic insulating materials.

[0056] Source electrodes 173a and 173d and drain electrodes 175a and 175d may be disposed on the insulating layer 160. The source electrode 173a may be electrically connected to the source region 133a through the opening 63, the drain electrode 175a may be electrically connected to the drain region 135a through the opening 65, the source electrode 173d may be electrically connected to the source region 133d through the opening 63d, and the drain electrode 175d may be electrically connected to the drain region 135d through the opening 65d.

[0057] At least one of the gate electrodes 154a and 154d, the source electrodes 173a and 173d, and the drain electrodes 175a and 175d may include at least one of copper (Cu), aluminum (Al), magnesium (Mg), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), molybdenum (Mo), tungsten (W), titanium (Ti), chromium (Cr), tantalum (Ta), and alloys thereof, and may include a single layer or a plurality of layers.

[0058] The pixel transistor Ta includes a channel region 134a, a source region 133a, a drain region 135a, and a gate electrode 154a. The source region 133a and the drain region 135a may each be included in the source terminal and the drain terminal of the pixel transistor Ta, and the gate electrode 154a may be included in the gate terminal of the pixel transistor Ta. The driving transistor Td includes a channel region 134d, a source region 133d, a drain region 135d, and a gate electrode 154d. The source region 133d and the drain region 135d may each be included in the source terminal and the drain terminal of the driving transistor Td, and the gate electrode 154d may be included in the gate terminal of the driving transistor Td.

[0059] refer to Figures 2 to 5, the gate insulating layer 144a includes an outer portion 14a that does not overlap with the gate electrode 154a in the third direction DR3, and the gate insulating layer 144d includes an outer portion 14d that does not overlap with the gate electrode 154d in the third direction DR3. The third direction DR3 may be perpendicular to the top surface of the substrate 110. In the present exemplary embodiment, the width Wa of the outer portion 14a and the width Wd of the outer portion 14d are both greater than zero. In an exemplary embodiment, the width Wd of the outer portion 14d is greater than the width Wa of the outer portion 14a. In an exemplary embodiment, the widths Wa and Wd both mean the width on a plane parallel to the top surface of the substrate 110 or the width in a plan view, and this may apply to other regions described below unless otherwise stated therein. According to another exemplary embodiment of the present invention, the width Wa of the outer portion 14a is substantially or exactly zero.

[0060] Accordingly, the distance between the drain region 135 a and the gate electrode 154 a of the pixel transistor Ta is smaller than the distance between the drain region 135 d and the gate electrode 154 d of the driving transistor Td.

[0061] In an exemplary embodiment, the outer portion 14 a has a shape extending around the gate electrode 154 a with a constant width Wa, and the outer portion 14 d has a shape extending around the gate electrode 154 d with a constant width Wd.

[0062] In an exemplary embodiment, the width Wd of the outer portion 14d is about 1 micron to about 2 microns. In an exemplary embodiment, about 1 micron is 1+ / -1%, 1+ / -2%, or 1+ / -5% of 1 micron to each produce a range, such as 0.99 microns-1.01 microns, 0.98 microns-1.02 microns, and 0.95 microns-1.05 microns. In an exemplary embodiment, about 2 microns is 1+ / -1%, 1+ / -2%, or 1+ / -5% of 2 microns to each produce a range, such as 1.98 microns-2.02 microns, 1.96 microns-2.04 microns, and 1.9 microns-2.1 microns. In an exemplary embodiment, the width Wd of the outer portion 14d is about 1.7 microns. In an exemplary embodiment, about 1.7 microns may include a range, such as 1.6 microns-1.8 microns and 1.65 microns-1.75 microns. The width Wd of the outer portion 14 d may vary depending on the characteristics of the driving transistor Td, the film conditions of the active pattern 131 d , the buffer layer 120 , the gate insulating layer 144 d , and the insulating layer 160 .

[0063] refer to Figures 6 to 8 Together with the previously described figures, the degradation prevention effect of the driving transistor Td of the display device according to the exemplary embodiment of the present invention will be described.

[0064] Figure 6Graph showing a change amount ΔVth (V) of a threshold voltage according to a length of an outer portion 14d of a gate insulating layer 144d of a driving transistor Td (which is the same as the width Wd described above) after a high voltage, for example, a high voltage exceeding 35V is applied between a source region 133d and a drain region 135d of the driving transistor Td included in the driving circuit portion 400a and the driving circuit portion 400b of the display device according to the exemplary embodiment of the present invention. Figure 6 , it can be seen that because the length of the outer portion 14d is a predetermined value, the change amount ΔVth (V) of the threshold voltage of the driving transistor Td is almost zero. Such a predetermined value of the length of the outer portion 14d according to the present exemplary embodiment may be about 1.7 microns. In an exemplary embodiment, about 1.7 microns includes a range, such as 1.6 microns-1.8 microns and 1.65 microns-1.75 microns.

[0065] Figure 7 Graph showing an on-current retention rate according to a length of an outer portion 14d of a gate insulating layer 144d of a driving transistor Td (which is the same as the above-mentioned width Wd) after a high voltage, for example, a high voltage exceeding 35V is applied between a source region 133d and a drain region 135d of the driving transistor Td included in the driving circuit portion 400a and the driving circuit portion 400b of the display device according to the exemplary embodiment of the present invention. Figure 7 , it can be seen that because the length of the outer portion 14d is a predetermined value, the retention rate of the on-current Ion is maintained at a certain level (e.g., about 0.8 or more). Such a predetermined value of the length of the outer portion 14d according to the present exemplary embodiment may be about 1.5 microns. In an exemplary embodiment, about 1.5 microns includes a range, such as 1.4 microns-1.6 microns and 1.45 microns-1.55 microns.

[0066] Figure 8 A diagram for explaining a change in a source-drain current Ids graph relative to a gate terminal voltage V of a driving transistor included in a driving circuit portion of a display device according to a comparative example, and a change in a source-drain current Ids graph relative to a gate terminal voltage V of a driving transistor Td included in a driving circuit portion 400a and a driving circuit portion 400b according to an exemplary embodiment of the present invention. The driving transistor included in the driving circuit portion of the display device according to the comparative example is mostly the same as the driving transistor Td according to the exemplary embodiment, but the width or length of the outer portion of the gate insulating layer may be 0 or more to about 1 micrometer or less. In an exemplary embodiment, about 1 micrometer includes a range, such as 0.99 micrometers-1.01 micrometers and 0.98 micrometers-1.02 micrometers.

[0067] Compared with the characteristic diagram GA before a high voltage, for example, a high voltage exceeding 35 V, is applied between the source terminal and the drain terminal of the driving transistor according to the comparative example, the characteristic diagram GB after the high voltage is applied between the source terminal and the drain terminal is obviously shifted to the right, indicating that the threshold voltage of the driving transistor is changed to be large and the on-current Ion is also reduced.

[0068] However, according to the exemplary embodiment of the present invention, the characteristic graph GA before and after the high voltage is applied between the source terminal Sd and the drain terminal Dd of the driving transistor Td is substantially equivalent, so that the change amount of the threshold voltage of the driving transistor Td is relatively small, and the on-current is also maintained. This is also consistent with Figure 6 and Figure 7 The experimental results match.

[0069] When the driving circuit part 400a and the driving circuit part 400b are driven, at least at some moments, a high voltage (e.g., 35V or more) may be applied between the source region 133d and the drain region 135d of the driving transistor Td. In this case, a strong electric field is formed between the drain region 135d and the gate electrode 154d of the driving transistor Td as described above, and carrier traps may occur, causing on-current degradation and threshold voltage shift. As a result, the characteristics of the driving transistor Td may be degraded, thereby causing the problem of unstable driving of the driving circuit part 400a and the driving circuit part 400b.

[0070] However, according to an exemplary embodiment of the present invention, the distance between the drain region 135d and the gate electrode 154d of the driving transistor Td is greater than the distance between the drain region 135a and the gate electrode 154a of the pixel transistor Ta, thereby ensuring a sufficient distance. Therefore, even if a high voltage is applied between the source region 133d and the drain region 135d, a strong electric field can be prevented from being formed between the drain region 135d and the gate electrode 154d. Therefore, the on-current degradation and the threshold voltage shift of the driving transistor Td can be prevented, and the reliability of the driving transistor Td can be improved. Accordingly, due to the tolerance to high voltage, the driving circuit part 400a and the driving circuit part 400b can be stably driven. In addition, the usable voltage range of the driving transistor Td can be expanded.

[0071] On the other hand, the width Wa of the outer part 14a of the pixel transistor Ta is set to be smaller than the width Wd of the outer part 14d of the driving transistor Td, which is used to distinguish the pixel transistor Ta from the driving transistor Td, so that when the display part is a current-driven light-emitting diode, the display characteristics of the display area DA can be improved by maintaining high on-current and mobility.

[0072] Next, refer to Figures 9 to 12, together with the above-mentioned figures, a method for manufacturing a pixel transistor Ta included in a pixel circuit portion of a display device according to an exemplary embodiment of the present invention will be described.

[0073] Fig. 9 , Fig.10 , Fig.11 and Fig.12 A manufacturing process of the pixel transistor Ta included in the pixel circuit part of the display device according to the exemplary embodiment of the present invention is sequentially explained.

[0074] First, refer to Fig. 9 , a buffer layer 120 (which is an insulating layer (e.g., a first insulating layer)) is stacked or formed on a substrate 110, an active layer is formed on the buffer layer 120, and then patterned to produce an active pattern 131a. An insulating layer 140 (e.g., a second insulating layer) is formed on the active pattern 131a, and a conductive material is stacked or formed on the insulating layer 140 to produce a conductive layer 150. A photoresist layer 50 is stacked or formed on the conductive layer 150, and then light, such as ultraviolet (UV) rays, is applied to the photoresist layer 50 through a photomask 60. For example, the photoresist layer 50 is irradiated with light.

[0075] The photoresist layer 50 may include a negative photoresist material or a positive photoresist material, and in the present exemplary embodiment, the photoresist layer 50 exemplarily includes a positive photoresist material that can remove the portion irradiated with light. For example, the portion irradiated with light may be subsequently removed using a solvent or a developing solution referred to as a developer. The portion irradiated with light may be referred to as an exposed portion, and the portion not irradiated with light may be referred to as a non-exposed portion. In an exemplary embodiment, the non-exposed portion is not removed when the developing solution is applied.

[0076] The photomask 60 includes a light-blocking portion 60a and a light-blocking portion 60b that blocks at least a portion of the light, and the light-blocking portion 60a and the light-blocking portion 60b may include two or more light-blocking portions 60a and the light-blocking portion 60b each having different transmittance or light-blocking ratios. In an exemplary embodiment, the light-blocking ratio of the light-blocking portion 60a is higher than the light-blocking ratio of the light-blocking portion 60b. For this reason, in a photomask including light-blocking portions (same as the light-blocking portion 60b) each having different transmittance or light-blocking ratios, the region that transmits or blocks only a portion of the light is called a halftone region. The portion outside the light-blocking portion 60a and the light-blocking portion 60b may be a light-transmitting portion through which light can be transmitted.

[0077] When the exposed photoresist layer 50 is exposed to a developing solution, such as Fig.10, a mask pattern 51 including a portion 51a and a portion 51b each having a different thickness in a third direction DR3 is formed. For example, the exposed photoresist layer 50 may refer to a photoresist layer including at least some portions that previously received light. The thick portion 51a of the mask pattern 51 is formed corresponding to the light blocking portion 60a of the photomask 60, and the thin portion 51b of the mask pattern 51 is formed corresponding to the light blocking portion 60b of the photomask 60. Although the elements 60a and 60b are referred to as light blocking portions, in an exemplary embodiment, the elements 60a and 60b do not block all light, but allow different amounts of light to pass through.

[0078] Next, the conductive layer 150 is etched by using the mask pattern 51 as a mask to form a gate electrode 154a. Fig.11 . In this case, wet etching may be used to etch the conductive layer 150. In the etching of the conductive layer 150, the etching time and the etchant concentration may be adjusted so that the edge of the gate electrode 154a is placed inside the edge of the mask pattern 51. For example, the wet etching may remove at least a portion of the conductive layer 150 below the thin portion 51b.

[0079] Next, the insulating layer 140 is etched by using the mask pattern 51 as a mask so that a patterned gate insulating layer 144a is formed. Fig.12 In this case, dry etching may be used to etch the insulating layer 140. In this process, the thickness of the mask pattern 51 may be reduced and the width of the thin portion 51b may be shortened, and accordingly, the edge portion of the gate insulating layer 144a is further etched so that the width of the outer portion 14a may be reduced, as previously described.

[0080] In the patterning process of the gate insulating layer 144a, the components of the etching gas are doped into the active pattern 131a not covered by the gate insulating layer 144a, so that the source region 133a and the drain region 135a having low resistance can be formed. After the gate insulating layer 144a is patterned, the active pattern 131a not covered by the gate insulating layer 144a is processed so that the source region 133a and the drain region 135a can be formed. In this case, as a processing method, a heat treatment method in a reducing atmosphere and a process containing a reducing material, such as hydrogen (H 2 ) or helium (He) gas plasma plasma treatment method.

[0081] Next, refer to the above Figure 3 , inorganic insulating materials, such as silicon nitride (SiN x ), silicon oxide (SiO x) and silicon oxynitride (SiON) are stacked or formed on the substrate 110 on which the gate electrode 154a and the gate insulating layer 144a are formed, so that the insulating layer 160 is formed. In an exemplary embodiment, the gas used in the stacking process of the insulating layer 160, such as SiH 4 or NH 3 Components included in the insulating layer 160, such as hydrogen, are injected into the active pattern 131a contacting the insulating layer 160, so that the conductive source region 133a and the drain region 135a are formed or the carrier concentration of the formed source region 133a and the drain region 135a can be increased more. Even after the insulating layer 160 is formed, components included in the insulating layer 160, such as hydrogen, can be diffused into the source region 133a and the drain region 135a so that the source region 133a and the drain region 135a can have low resistance.

[0082] Next, refer to Figures 13 to 16 As well as the above Figure 4 and Figure 5 , a method for manufacturing the driving transistor Td included in the driving circuit part of the display device according to the exemplary embodiment of the present invention will be described.

[0083] Fig.13 , Fig.14 , Fig.15 and Fig.16 A method of manufacturing the driving transistor Td included in the driving circuit part of the display device according to the exemplary embodiment of the present invention is sequentially shown.

[0084] First, refer to Fig.13 , a buffer layer 120, which is an insulating layer, is stacked on the substrate 110, an active layer is formed on the buffer layer 120, and then patterned to form an active pattern 131d. An insulating layer 140 is formed on the active pattern 131d, and a conductive material is stacked on the insulating layer 140 to form a conductive layer 150. After a photoresist layer 50 is stacked or formed on the conductive layer 150, light, such as ultraviolet rays, is applied to the photoresist layer 50 through a photomask. For example, the photoresist layer 50 is irradiated with light.

[0085] The photomask includes a light blocking portion 61 that blocks light. In an exemplary embodiment, the light blocking rate throughout the light blocking portion 61 is constant, which is different from the light blocking portions 60a and 60b having different light blocking rates. For example, each cross section of the light blocking portion 61 may block the same amount of light.

[0086] When the exposed photoresist layer 50 is exposed to a developer, a mask pattern 52 corresponding to the light blocking portion 61 of the photomask is formed. Fig.14In an exemplary embodiment, the thickness of the mask pattern 52 is thicker than the thin portion 51 b of the mask pattern 51 described above, and may have a thickness similar to or the same as that of the thick portion 51 a, but is not limited thereto.

[0087] Next, the conductive layer 150 is etched by using the mask pattern 52 as a mask to form Fig.15 154d shown in FIG. 154. In this case, wet etching may be used. The edge of the gate electrode 154d may be etched to be placed inside the edge of the mask pattern 52 by adjusting the etching time and / or the concentration of the etching solution.

[0088] Next, the insulating layer 140 is etched using the mask pattern 52 as a mask to form a gate insulating layer 144d. Fig.16 . In this case, dry etching may be used. The edge of the gate insulating layer 144d may be formed corresponding to the edge of the mask pattern 52. Accordingly, the outer portion 14d of the gate insulating layer 144d has a width wider than the outer portion 14a of the gate insulating layer 144a of the pixel transistor Ta. For example, a portion of the insulating layer 140 may be removed until the edge of the mask pattern 52.

[0089] As previously described, the etching gas component may be doped into the active pattern 131d not covered by the gate insulating layer 144d so that the source region 133d and the drain region 135d of low resistance may be formed during the process of patterning the gate insulating layer 144d, and after the patterning of the gate insulating layer 144d, the source region 133d and the drain region 135d may be formed by processing the active pattern 131d exposed by the plasma treatment method. In addition, referring to the above Figure 5 During or after a process of forming the insulating layer 160 formed on the gate electrode 154d and the gate insulating layer 144d, components, such as hydrogen included in the insulating layer 160, may diffuse into the source region 133d and the drain region 135d so that the source region 133d and the drain region 135d have low resistance.

[0090] Next, refer to Fig.17 , a display device according to an exemplary embodiment of the present invention will be described. The same reference numerals are used for the same constituent elements as those of the above-described exemplary embodiment, and accordingly, the same description is omitted.

[0091] Fig.17 is a cross-sectional view of a driving transistor Td1 included in a driving circuit portion of a display device according to an exemplary embodiment of the present invention.

[0092] The display device according to the present exemplary embodiment is almost the same as the display device of the above exemplary embodiment except for the structure of the driving transistor Td1 included in the driving circuit portion. That is, the driving transistor Td1 has almost the same structure and features as the above driving transistor Td, but the driving transistor Td1 has a gate insulating layer 144d1 instead of the above gate insulating layer 144d. The display device according to the present exemplary embodiment may include the same pixel transistor as the above pixel transistor Ta.

[0093] refer to Fig.17 , the gate insulating layer 144d1 included in the driving transistor Td1 according to the present exemplary embodiment includes an outer portion 14ad and an outer portion 14d1 that do not overlap with the gate electrode 154d in the third direction DR3, and the outer portion 14ad and the outer portion 14d1 may be portions having different widths. In an exemplary embodiment, a width Wad of the outer portion 14ad adjacent to the source region 133d is smaller than a width Wd1 of the outer portion 14d1 adjacent to the drain region 135d. In an exemplary embodiment, the width Wd1 is at least twice the width Wad. In another exemplary embodiment, the width Wd1 is at least three times the width Wad.

[0094] In the present exemplary embodiment, the width Wad of the outer portion 14ad and the width Wd1 of the outer portion 14d1 are greater than 0. The width Wd1 of the outer portion 14d1 may be similar or identical to the width Wd of the outer portion 14d of the gate insulating layer 144d of the driving transistor Td according to the above exemplary embodiment, but is not limited thereto.

[0095] When a high voltage is applied between the source region 133d and the drain region 135d, the region adjacent to the outer portion 14d1 in the source region 133d and the drain region 135d may be a region where a high potential is applied. According to the present exemplary embodiment, even when a high potential (e.g., a high voltage, such as a high voltage greater than 35 volts) is applied to the drain region 135d as described above, a strong electric field can be prevented from being formed between the drain region 135d and the gate electrode 154d, and thus the on-current drop and the shift of the threshold voltage of the driving transistor Td1 may be prevented. Therefore, the reliability of the driving transistor Td1 may be increased, and the tolerance to high voltage may be increased to stably drive the driving circuit portion 400a and the driving circuit portion 400b. In addition, the usable voltage range of the driving transistor Td1 may be expanded.

[0096] Further, according to the present exemplary embodiment, the width Wad of the outer portion 14ad adjacent to the source region 133d is relatively small so that the on-current and the mobility can be maintained.

[0097] Next, refer to Figures 18 to 21 ,as well as Fig.17, a method for manufacturing the driving transistor Td1 included in the driving circuit part of the display device according to the exemplary embodiment of the present invention will be described.

[0098] Fig.18 , Fig.19 , Fig. 20 and Fig.21 The manufacturing process of the driving transistor Td1 included in the driving circuit part of the display device according to the exemplary embodiment of the present invention is sequentially shown.

[0099] refer to Fig.18 , a buffer layer 120 (which is an insulating layer), an active pattern 131d, an insulating layer 140, a conductive layer 150, and a photoresist layer 50 are sequentially formed on a substrate 110, and then light, such as ultraviolet rays, is applied to the photoresist layer 50 through a photomask 62. For example, the photoresist layer 50 may be irradiated with light. The photomask 62 may include a light-blocking portion 62a and a light-blocking portion 62b that block at least a portion of the light, and the light-blocking portion 62a and the light-blocking portion 62b may include two or more light-blocking portions 62a and light-blocking portions 62b each having a different transmittance or light-blocking rate. In an exemplary embodiment, the light-blocking rate of the light-blocking portion 62a is higher than the light-blocking rate of the light-blocking portion 62b. A portion that does not include the light-blocking portion 62a and the light-blocking portion 62b may be a light-transmitting portion that can transmit light.

[0100] When the exposed photoresist layer 50 is exposed to a developing solution, a mask pattern 53 including a portion 53a and a portion 53b each having a different thickness in the third direction DR3 is formed. Fig.19 Thick portions 53a of mask pattern 53 are formed corresponding to light blocking portions 62a of photomask 62, and thin portions 53b of mask pattern 53 are formed corresponding to light blocking portions 62b of photomask 62. In an exemplary embodiment, thin portions 53b are disposed only on one side of thick portions 53a.

[0101] Next, the conductive layer 150 is etched by using the mask pattern 53 as a mask to form a gate electrode 154d. Fig. 20 . In this case, wet etching may be used. The edge of the gate electrode 154d may be etched to be placed inside the edge of the mask pattern 53. For example, a portion of the conductive layer 150 under the thin portion 53b may be removed, and a portion of the conductive layer 150 under the thick portion 53a may be removed.

[0102] Next, the insulating layer 140 is etched by using the mask pattern 53 as a mask to form a patterned gate insulating layer 144d1, as shown in FIG. Fig.21. In this case, dry etching may be used. In this process, the thickness of the mask pattern 53 may be reduced and the width of the thin portion 53b may be shortened, and accordingly, the edge portion of the gate insulating layer 144d1 disposed under the thin portion 53b of the mask pattern 53 may be more etched, so that the width of the outer portion 14ad may be reduced, as previously described. At the same time, the edge of the gate insulating layer 144d1 located under the thick portion 53a of the mask pattern 53 may be relatively less etched to form the outer portion 14d1 having a width greater than that of the outer portion 14ad.

[0103] Next, refer to Fig. 22 and Fig.23 , a display device according to an exemplary embodiment of the present invention will be described.

[0104] Fig. 22 is a top plan view of a driving transistor Td2 included in a driving circuit portion of a display device according to an exemplary embodiment of the present invention, and Fig.23 For along Fig. 22 A cross-sectional view of the display device taken along line XXIIIa-XXIIIb.

[0105] The display device according to the present exemplary embodiment is almost the same as the display device according to the above exemplary embodiment except for the structure of the driving transistor Td included in the driving circuit portion. That is, the driving transistor Td2 has almost the same structure and features as those of the above driving transistor Td, but the driving transistor Td2 includes a gate insulating layer 144d2 instead of the above gate insulating layer 144d, and may further include a dummy electrode 154d1 and a dummy insulating layer 144d3. In addition, in addition to the channel region 134d, the source region 133d, and the drain region 135d, the active pattern 131d may further include a dummy drain region 135d1 and a dummy channel region 134d1.

[0106] The gate insulating layer 144d2 may be the same as or similar to the gate insulating layer 144d of the driving transistor Td, or may be the same as or similar to the gate insulating layer 144a of the pixel transistor Ta according to the above exemplary embodiment. That is, the width of the outer portion 14d2 of the gate insulating layer 144d2 that does not overlap the gate electrode 154d in the third direction DR3 may be the same as or similar to the width of the outer portion 14d of the gate insulating layer 144d of the driving transistor Td, or may be the same as or similar to the width of the outer portion 14a of the gate insulating layer 144a of the pixel transistor Ta according to the above exemplary embodiment. In particular, in the present exemplary embodiment, the width of the outer portion 14d2 may be smaller than the width of the outer portion 14d of the gate insulating layer 144d of the driving transistor Td described above, so as to prevent the on-current and mobility of the driving transistor Td2 from being degraded.

[0107] In an exemplary embodiment, the dummy drain region 135d1 and the dummy channel region 134d1 are disposed adjacent to each other and disposed between the channel region 134d and the drain region 135d. In an exemplary embodiment, the dummy drain region 135d1 has a carrier concentration higher than that of the channel region 134d and the dummy channel region 134d1. In an exemplary embodiment, the dummy drain region 135d1 has a carrier concentration higher than that of the channel region 134d and the dummy channel region 134d1. Fig. 22 The width of the dummy channel region 134d1 in the horizontal direction (in the horizontal direction) is smaller than the width of the channel region 134d in the same direction.

[0108] In a plan view, the dummy electrode 154d1 is spaced apart from the gate electrode 154d and may overlap the dummy insulating layer 144d3 and the dummy channel region 134d1. The dummy insulating layer 144d3 is spaced apart from the gate insulating layer 144d2. In a plan view, an edge of the dummy electrode 154d1 may be disposed inside an edge of the dummy insulating layer 144d3, and an edge of the dummy electrode 154d1 may be substantially parallel to an edge of the dummy channel region 134d1.

[0109] In an exemplary embodiment, in the channel length direction of the driving transistor Td2 (ie, Fig. 22 The width of the dummy electrode 154d1 in the horizontal direction (in the horizontal direction) is smaller than the width of the gate electrode 154d in the same direction, and is smaller in the channel length direction of the driving transistor Td2 (ie, Fig. 22 The width of the dummy insulating layer 144d3 in the horizontal direction (in the horizontal direction) is smaller than the width of the gate insulating layer 144d2 in the same direction.

[0110] Edges of the dummy electrode 154d1 and the gate electrode 154d facing each other may extend substantially parallel to each other, and edges of the dummy insulating layer 144d3 and the gate insulating layer 144d2 facing each other may extend substantially parallel to each other.

[0111] In an exemplary embodiment, the dummy electrode 154d1 is disposed on the same layer and formed of the same conductive material as the gate electrode 154d. In an exemplary embodiment, the dummy insulating layer 144d3 is disposed on the same layer and formed of the same insulating material as the gate insulating layer 144d2.

[0112] The same gate signal as that applied to the gate electrode 154d may also be applied to the dummy electrode 154d1. In an exemplary embodiment, the dummy electrode 154d1 is insulated from the gate electrode 154d and is floating.

[0113] According to the present exemplary embodiment, since the dummy channel region 134d1, the dummy insulating layer 144d3 and the dummy electrode 154d1 are disposed between the drain region 135d and the gate electrode 154d of the driving transistor Td2, the distance between the drain region 135d and the gate electrode 154d can be increased. Therefore, even when a high voltage is applied between the source region 133d and the drain region 135d and a high potential is applied to the drain region 135d, a strong electric field can be prevented from being formed between the drain region 135d and the gate electrode 154d. Therefore, it is possible to prevent the degradation of the characteristics caused by the reduction of the on-current of the driving transistor Td2 and the shift of the threshold voltage, and it is possible to maintain reliability and tolerance to the high voltage applied to the driving transistor Td2. In addition, the usable voltage range of the driving transistor Td2 can be widened.

[0114] When the same gate signal as that applied to the gate electrode 154d is applied to the dummy electrode 154d1, it is also possible to prevent the formation of a strong electric field between the drain region 135d and the gate electrode 154d while maintaining the on-current and mobility of the driving transistor Td2.

[0115] Next, refer to Figure 24 to Figure 27 ,as well as Fig. 22 and Fig.23 , a method for manufacturing the driving transistor Td2 included in the driving circuit part of the display device according to the exemplary embodiment of the present invention will be described.

[0116] Fig.24 , Fig.25 , Fig.26 and Fig. 27 The manufacturing process of the driving transistor Td2 included in the driving circuit part of the display device according to the exemplary embodiment of the present invention is sequentially shown.

[0117] First, refer to Fig.24 , a buffer layer 120 (which is an insulating layer), an active pattern 131d, an insulating layer 140, a conductive layer 150, and a photoresist layer 50 are sequentially formed on a substrate 110, and then light, such as ultraviolet rays, is applied to the photoresist layer 50. For example, the photoresist layer 50 is irradiated with light. For example, light can be applied to the photoresist layer 50 through a photomask 64 including two light-blocking portions 64a and a light-blocking portion 64b, and the two light-blocking portions 64a and the light-blocking portions 64b are separated from each other by a light-transmitting portion 64c disposed between the two light-blocking portions 64a and the light-blocking portions 64b. The light-blocking portions 64a and the light-blocking portions 64b may have a constant light-blocking rate. The portion outside the light-blocking portions 64a and the light-blocking portions 64b may be a light-transmitting portion that transmits light.

[0118] When the exposed photoresist layer 50 is exposed to a developing solution, such as Fig.25 , a mask pattern 54 including two portions 54a and 54b is formed, the two portions 54a and 54b respectively corresponding to the light blocking portion 64a and the light blocking portion 64b of the photomask 64. The two portions 54a and 54b are separated from each other so that the top surface of the conductive layer 150 can be exposed. For example, the two portions 54a and 54b can be spaced apart from each other.

[0119] Next, the conductive layer 150 is etched by using the mask pattern 54 as a mask so as to form a gate electrode 154d and a dummy electrode 154d1, as shown in FIG. Fig.26 . In this case, wet etching may be used. The edge of the gate electrode 154d may be placed inside the edge of the portion 54a of the mask pattern 54, and the edge of the dummy electrode 154d1 may be etched to be placed inside the edge of the portion 54b of the mask pattern 54. For example, a portion of the conductive layer 150 under the portion 54a may be removed, and a portion of the conductive layer 150 under the portion 54b may be removed.

[0120] Next, if Fig. 27 , the insulating layer 140 is etched using the mask pattern 54 as a mask to form a gate insulating layer 144d2 and a dummy insulating layer 144d3. In this case, dry etching may be used. The edge of the gate insulating layer 144d2 may be formed to correspond to the edge of the portion 54a of the mask pattern 54, and the edge of the dummy insulating layer 144d3 may be formed to correspond to the edge of the portion 54b of the mask pattern 54. For example, etching may remove a portion of the insulating layer 140 to produce portions of the insulating layer 140 (e.g., the gate insulating layer 144d2 and the dummy insulating layer 144d3) that are separated from each other.

[0121] and Figures 9 to 12 As in the above-described manufacturing method shown in , the degree of etching of the conductive layer 150 may be adjusted to adjust the width of the outer portion 14d2 of the gate insulating layer 144d2. The width of the outer portion 14d2 may be narrowed by using a photomask including a halftone region. In an exemplary embodiment, the width of the portion 54a of the mask pattern 54 is reduced, and the degree of etching of the gate electrode 154d is reduced so that the edge of the gate electrode 154d is closer to the edge of the portion 54a of the mask pattern 54. Therefore, the width of the outer portion 14d2 of the gate insulating layer 144d2 may be reduced.

[0122] refer to Figures 28 to 30 , the structure of the display area DA of the display device according to the exemplary embodiment of the present invention will be described.

[0123] Fig.28 is a plan layout diagram of a plurality of pixels of a display device according to an exemplary embodiment of the present invention, Fig.29is a plan layout diagram of a pixel electrode and a plurality of data lines of a display device according to an exemplary embodiment of the present invention, and Fig.30 For along Fig.28 A cross-sectional view of a display device taken along line XXXa-XXXb.

[0124] The same description of the same constituent elements as those of the above-described exemplary embodiment will be omitted, and the description will focus on differences or additions.

[0125] The display device according to the present exemplary embodiment is a light-emitting display device, and referring to Fig.28 Each pixel may include a pixel circuit part PXC including a plurality of transistors T1, T2, and T3. A plurality of pixel circuit parts PXC corresponding to a plurality of pixels may be arranged in the second direction DR2.

[0126] refer to Fig.28 and Fig.30 , a plurality of lower patterns 111 may be disposed on the substrate 110. The lower patterns 111 may include a semiconductor material having various conductive metals or similar conductive properties.

[0127] The buffer layer 120 is disposed on the lower pattern 111, and a plurality of active patterns corresponding to each of the plurality of transistors T1, T2, and T3 may be disposed on the buffer layer 120. The active pattern of the first transistor T1 may include a channel region 134_1, a source region 133_1, and a drain region 135_1. The active pattern of the second transistor T2 may include a channel region 134_2, a source region 133_2, and a drain region 135_2. The active pattern of the third transistor T3 may include a channel region 134_3, a source region 133_3, and a drain region 135_3.

[0128] Each of the plurality of transistors T1 , T2 , and T3 may include the same structure as the above-described pixel transistor Ta, and the plurality of active patterns included in each of the plurality of transistors T1 , T2 , and T3 may have the same characteristics as those of the above-described active pattern 131 a .

[0129] A gate insulating layer 144 may be disposed on the active pattern. The gate insulating layer 144 may be the same as the above-described gate insulating layer 144a.

[0130] Scan lines 151 and 152 transmitting gate signals and a plurality of gate electrodes 154_1, 154_2, 154_3, and 155 may be disposed on the gate insulating layer 144. Each of the scan lines 151 and 152 may extend substantially in the first direction DR1. The scan lines 151 and 152 may be the same as the gate lines 121 described above.

[0131] The gate electrode 155 is provided to correspond to each pixel circuit part PXC and may be electrically connected to the gate electrode 154_1. The gate electrode 154_2 substantially extends in the second direction DR2 and may thus be electrically connected to the scan line 151. The gate electrode 154_3 substantially extends in the second direction DR2 and may thus be electrically connected to the scan line 152.

[0132] An insulating layer 160 may be disposed on the scan lines 151 and 152 and the gate electrodes 154_1 , 154_2 , 154_3 , and 155 .

[0133] A plurality of data lines 171 a , 171 b , and 171 c , a driving voltage line 172 , a common voltage line 170 , and a capacitor electrode 175 may be disposed on the insulating layer 160 .

[0134] Each of the plurality of data lines 171a, 171b, and 171c extends substantially in the second direction DR2, and each of the data lines 171a, 171b, and 171c may be electrically connected to the source region 133_2 of the second transistor T2 through the opening of the insulating layer 160. The data lines 171a, 171b, and 171c may be the same as the data line 171 described above.

[0135] The driving voltage line 172 may be electrically connected to the source region 133_1 of the first transistor T1 through the opening of the insulating layer 160 .

[0136] A single capacitor electrode 175 may be provided in each pixel circuit portion PXC, and may form a capacitor Cst by overlapping with a corresponding gate electrode 155, while an insulating layer 160 is provided between the single capacitor electrode 175 and the corresponding gate electrode 155. The capacitor electrode 175 may be electrically connected to the drain region 135_1 of the first transistor T1 and the source region 133_3 of the third transistor T3 through an opening of the insulating layer 160, and may be electrically connected to the lower pattern 111 through openings of the insulating layer 160 and the buffer layer 120.

[0137] The first transistor T1 includes a channel region 134_1 , a source region 133_1 , a drain region 135_1 , and a gate electrode 154_1 .

[0138] The second transistor T2 includes a channel region 134_2 , a source region 133_2 , a drain region 135_2 , and a gate electrode 154_2 . The drain region 135_2 of the second transistor T2 may be electrically connected to the gate electrode 154_1 through the gate electrode 155 .

[0139] The third transistor T3 includes a channel region 134_3 , a source region 133_3 , a drain region 135_3 , and a gate electrode 154_3 .

[0140] An insulating layer 180 is disposed on the data lines 171a, 171b, and 171c, the driving voltage line 172, the common voltage line 170, and the capacitor electrode 175, and a plurality of conductive patterns 183a and 183b may be disposed on the insulating layer 180. The conductive patterns 183a and 183b may be electrically connected to the data lines 171a, 171b, and 171c, the driving voltage line 172, the common voltage line 170, and the capacitor electrode 175 disposed thereunder, and may have a substantially similar planar shape to the data lines 171a, 171b, and 171c, the driving voltage line 172, the common voltage line 170, and the capacitor electrode 175.

[0141] The insulating layer 181 may be disposed on the conductive pattern 183 a and the conductive pattern 183 b. The insulating layer 181 may include an opening 80 disposed on the conductive pattern 183 b connected to the capacitor electrode 175.

[0142] A plurality of conductive ohmic contact members 190a, 190b, and 190c may be disposed on the insulating layer 181. Each of the ohmic contact members 190a, 190b, and 190c may be electrically connected to the conductive pattern 183b while contacting the conductive pattern 183b through the opening 80 in each pixel circuit portion PXC.

[0143] The insulating layer 182 may be disposed on the ohmic contact members 190a, 190b, and 190c. The insulating layer 182 may include an opening 83 disposed on each of the ohmic contact members 190a, 190b, and 190c.

[0144] refer to Fig.29 and Fig.30 , a plurality of pixel electrodes 191a, 191b, and 191c may be disposed on the insulating layer 182. In a plan view, a plurality of pixel electrodes 191a, 191b, and 191c may be arranged in the first direction DR1. However, the layout and structure of the pixel circuit portion PXC and the pixel electrodes 191a, 191b, and 191c are not limited thereto.

[0145] A plurality of pixel electrodes 191a, 191b, and 191c may be electrically connected to ohmic contact members 190a, 190b, and 190c through openings 83 of the insulating layer 182, and the ohmic contact members 190a, 190b, and 190c are electrically connected to the capacitor electrode 175. Each of the pixel electrodes 191a, 191b, and 191c may receive a data voltage by being electrically connected to the drain region 135_1 of the first transistor T1 through the conductive pattern 183b and the capacitor electrode 175.

[0146] The pixel electrode 191 a , the pixel electrode 191 b , and the pixel electrode 191 c may include a transflective conductive material or a reflective conductive material.

[0147] The insulating layer 350 may be disposed on the insulating layer 182. Fig.29 and Fig.30 The insulating layer 350 may include openings 355a, 355b, and 355c disposed on the pixel electrodes 191a, 191b, and 191c, respectively. The insulating layer 350 may include an organic insulating material such as polyacrylic resin and polyimide resin.

[0148] The emission layer 370 may be disposed on the insulating layer 350 and the pixel electrodes 191a, 191b, and 191c. The emission layer 370 may include a portion disposed inside the openings 355a, 355b, and 355c of the insulating layer 350. The emission layer 370 may include an organic light emitting material or an inorganic light emitting material.

[0149] The common electrode 270 is disposed on the emission layer 370. The common electrode 270 is electrically connected to the common voltage line 170 and thus may receive a common voltage. The common electrode 270 may include a conductive transparent material.

[0150] Each pixel electrode 191a, pixel electrode 191b and pixel electrode 191c, an emission layer 370 and a common electrode 270 form a light emitting diode ED. Pixel electrode 191a, pixel electrode 191b and pixel electrode 191c may be a cathode, and common electrode 270 may be an anode. Alternatively, pixel electrode 191a, pixel electrode 191b and pixel electrode 191c may be an anode, and common electrode 270 may be a cathode. In a plan view, the area where the openings 355a, openings 355b and openings 355c of the insulating layer 350 are formed may define a light emission area of ​​each pixel.

[0151] In the present exemplary embodiment, at least one of the insulating layers 180 , 181 , and 182 , the conductive patterns 183 a , and 183 b , and the ohmic contact members 190 a , 190 b , and 190 c may be omitted.

[0152] While the present invention has been described in conjunction with what are presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the present disclosure.

Claims

1. A display device, comprising: A substrate comprising a display area and a peripheral area surrounding the display area; A plurality of pixel circuit parts and a plurality of signal lines are arranged in the display area; and a driving circuit portion provided in the peripheral area and connected to the plurality of signal lines, wherein the driving circuit part includes a first transistor, the first transistor includes a first active pattern disposed on the substrate, a first gate insulating layer disposed on the first active pattern, and a first gate electrode disposed on the first gate insulating layer, Each pixel circuit portion includes a second transistor, the second transistor includes a second active pattern disposed on the substrate, a second gate insulating layer disposed on the second active pattern, and a second gate electrode disposed on the second gate insulating layer, wherein the first gate insulating layer includes a first outer portion that does not overlap with the first gate electrode in a first direction perpendicular to the substrate, is adjacent to a first edge of the first gate electrode, and overlaps with a first channel region of the first active pattern in the first direction, wherein the second gate insulating layer includes a second outer portion that does not overlap with the second gate electrode in the first direction, is adjacent to a second edge of the second gate electrode, and overlaps with a second channel region of the second active pattern in the first direction, and wherein an insulating layer is disposed on the first gate electrode and the second gate electrode, wherein the insulating layer has a first opening on the first active pattern and a second opening on the second active pattern, wherein the first outer portion has a first lateral side spaced from the first opening, wherein the second outer portion has a second lateral side spaced from the second opening, and wherein a first maximum width of the first outer portion in a second direction perpendicular to the first direction measured from the first edge of the first gate electrode to the first lateral side is greater than a second maximum width of the second outer portion in the second direction measured from the second edge of the second gate electrode to the second lateral side. 2 . The display device according to claim 1 , wherein the first outer portion has a shape extending along an outer circumference of the first gate electrode, and the second outer portion has a shape extending along an outer circumference of the second gate electrode. 3 . The display device according to claim 1 , wherein a width of the first outer portion is greater than or equal to 1.7 μm.

4. The display device according to claim 1, wherein The first active pattern includes a first source region, a first drain region, and the first channel region overlapping the first gate electrode, the first source region and the first drain region facing each other with respect to the first channel region, The second active pattern includes a second source region, a second drain region, and the second channel region overlapping the second gate electrode, the second source region and the second drain region facing each other with respect to the second channel region, and A distance between the first drain region and the first gate electrode is greater than a distance between the second drain region and the second gate electrode.

5. The display device according to claim 4, further comprising: a first source electrode, the first source electrode being disposed on the insulating layer and electrically connected to the first source region; and A first drain electrode is disposed on the insulating layer and electrically connected to the first drain region. 6 . The display device according to claim 1 , wherein the display area includes a plurality of pixels, and each of the plurality of pixels includes a corresponding pixel circuit portion among the plurality of pixel circuit portions and a light emitting diode electrically connected to the corresponding pixel circuit portion.

7. The display device according to claim 6, wherein The plurality of signal lines include a plurality of gate lines electrically connected to the plurality of pixel circuit portions, and The driving circuit part is connected to the plurality of gate lines, and applies gate signals to the plurality of gate lines while scanning the plurality of gate lines.

8. A display device, comprising: A substrate comprising a display area and a peripheral area surrounding the display area; A plurality of pixel circuit parts and a plurality of signal lines are arranged in the display area; and a driving circuit portion provided in the peripheral area and connected to the plurality of signal lines, wherein the driving circuit part includes a first transistor, the first transistor includes a first active pattern disposed on the substrate, a first gate insulating layer disposed on the first active pattern, and a first gate electrode disposed on the first gate insulating layer, wherein the first gate insulating layer includes a first outer portion that does not overlap with the first gate electrode in a first direction perpendicular to the substrate, and wherein the first outer portion includes a first portion adjacent to a first side edge of the first gate electrode and overlapping with a first channel region of the first active pattern in the first direction, and a second portion adjacent to a second side edge of the first gate electrode opposite to the first side edge and overlapping with the first channel region of the first active pattern in the first direction, wherein an insulating layer is disposed on the first gate electrode, wherein the insulating layer has a first opening and a second opening disposed on the first active pattern, wherein the first portion has a first lateral side spaced from the first opening, wherein the second portion has a second lateral side spaced from the second opening, wherein a maximum width of the first portion in a second direction perpendicular to the first direction measured from the first side edge of the first gate electrode to the first lateral side is different from a maximum width of the second portion in the second direction measured from the second side edge of the first gate electrode to the second lateral side.

9. The display device according to claim 8, wherein The first active pattern includes a first source region, a first drain region, and the first channel region overlapping the first gate electrode, the first source region and the first drain region facing each other with respect to the first channel region, The maximum width of the second portion is greater than the maximum width of the first portion.

10. The display device according to claim 9, further comprising: a first source electrode, the first source electrode being disposed on the insulating layer and electrically connected to the first source region; and A first drain electrode is disposed on the insulating layer and electrically connected to the first drain region. 11 . The display device according to claim 8 , wherein the first outer portion has a shape extending along an outer circumference of the first gate electrode in a plan view.

12. The display device according to claim 8, wherein each of the pixel circuit portions includes a second transistor, The second transistor comprises: a second active pattern disposed on the substrate, a second gate insulating layer disposed on the second active pattern; and a second gate electrode disposed on the second gate insulating layer, wherein the second gate insulating layer includes a second outer portion that does not overlap with the second gate electrode in the first direction, and The second outer portion has a shape extending along the outer circumference of the second gate electrode. 13 . The display device according to claim 12 , wherein the display area includes a plurality of pixels, and each of the plurality of pixels includes a corresponding pixel circuit portion among the plurality of pixel circuit portions and a light emitting diode electrically connected to the corresponding pixel circuit portion.

14. A display device, comprising: A substrate comprising a display area and a peripheral area surrounding the display area; A plurality of pixel circuit parts and a plurality of signal lines are arranged in the display area; and a driving circuit portion provided in the peripheral area and connected to the plurality of signal lines, wherein the driving circuit portion includes a first transistor, the first transistor including a first active pattern disposed on the substrate, a first gate insulating layer disposed on the first active pattern, a first gate electrode disposed on the first gate insulating layer, a dummy insulating layer disposed on the first active pattern and separated from the first gate insulating layer, and a dummy electrode disposed on the dummy insulating layer and separated from the first gate electrode, wherein the dummy electrode comprises the same material as that of the first gate electrode and has a maximum width smaller than a maximum width of the first gate electrode, wherein the dummy insulating layer comprises the same material as that of the first gate insulating layer and has a maximum width smaller than a maximum width of the first gate insulating layer, wherein the first active pattern includes a first source region, a first drain region, a dummy channel region, a dummy drain region, and a first channel region overlapping the first gate electrode, the first source region and the first drain region face each other relative to the first channel region, the dummy channel region and the dummy drain region are disposed between the first channel region and the first drain region, wherein the dummy electrode overlaps the dummy channel region, and The dummy drain region is disposed between the dummy channel region and the first channel region.

15. The display device according to claim 14, wherein The first gate insulating layer includes a first outer portion that does not overlap the first gate electrode in a direction perpendicular to a top surface of the substrate, and The first outer portion has a shape extending along the outer circumference of the first gate electrode.

16. The display device according to claim 14, wherein each of the pixel circuit parts includes a second transistor, The second transistor comprises: a second active pattern disposed on the substrate, a second gate insulating layer disposed on the second active pattern; and a second gate electrode disposed on the second gate insulating layer, wherein the second gate insulating layer includes a second outer portion that does not overlap the second gate electrode in a direction perpendicular to the top surface of the substrate, and The second outer portion has a shape extending along the outer circumference of the second gate electrode. 17 . The display device according to claim 14 , wherein the dummy electrode is electrically connected to the first gate electrode. 18 . The display device of claim 14 , wherein the dummy electrode is insulated from the first gate electrode and the dummy electrode is floating.

19. A method for manufacturing a display device, the method comprising: forming a first insulating layer on a substrate including a display area and a peripheral area surrounding the display area; forming a first active pattern in the peripheral area on the first insulating layer, and forming a second active pattern in the display area on the first insulating layer; forming a second insulating layer on the first active pattern and the second active pattern; forming a conductive layer on the second insulating layer; forming a photoresist layer on the conductive layer; applying light to the photoresist layer through a photomask; exposing the photoresist layer to a developing solution to produce a first mask pattern in the peripheral area and a second mask pattern in the display area; etching the conductive layer using the first mask pattern and the second mask pattern as masks to produce a first gate electrode in the peripheral area and a second gate electrode in the display area; as well as etching the second insulating layer using the first mask pattern and the second mask pattern as masks to produce a first gate insulating layer in the peripheral area and a second gate insulating layer in the display area, wherein the photomask includes a halftone region corresponding to the second mask pattern, wherein the first gate insulating layer includes a first outer portion that does not overlap with the first gate electrode in a first direction perpendicular to the substrate, wherein the second gate insulating layer includes a second outer portion that does not overlap with the second gate electrode in the first direction, and A first maximum width of the first outer portion in a second direction perpendicular to the first direction is greater than a second maximum width of the second outer portion in the second direction.

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