Magnetic storage devices

Abstract

A magnetic memory device includes: a first cell array structure, which includes a first free magnetic pattern and a second free magnetic pattern extending in a first direction parallel to the top surface of a substrate and spaced apart from each other in a second direction intersecting the first direction; and a second cell array structure, which includes a third free magnetic pattern between the first free magnetic pattern and the second free magnetic pattern and a fourth free magnetic pattern spaced apart from the third free magnetic pattern and between which the second free magnetic pattern is located. The first cell array structure also includes a first transistor region, which includes first transistors connected to the first free magnetic pattern and the second free magnetic pattern, respectively. The second cell array structure also includes a second transistor region, which includes second transistors connected to the third free magnetic pattern and the fourth free magnetic pattern, respectively. The second transistor region is spaced apart from the first transistor region in the first direction.

Description

Technical Field

[0001] Embodiments of the inventive concept relate to a magnetic memory device, and more particularly, to a magnetic memory device using movement of magnetic domains. Background Art

[0002] High-speed and low-voltage memory devices are needed to realize high-speed and low-power electronic devices using such memory devices. Magnetic memory devices have been studied as memory devices that meet these needs. Magnetic memory devices have received attention as next-generation memory devices due to their high-speed operation characteristics and / or non-volatile characteristics. For example, magnetic memory devices using the movement phenomenon of magnetic domain walls of magnetic materials have been recently studied and developed. Summary of the invention

[0003] Embodiments of the inventive concept may provide a magnetic memory device configured to improve or increase integration density.

[0004] In one aspect, a magnetic memory device may include: a first cell array structure including a first free magnetic pattern and a second free magnetic pattern extending in a first direction on a surface of a substrate and spaced apart from each other in a second direction intersecting the first direction; and a second cell array structure including a third free magnetic pattern between the first free magnetic pattern and the second free magnetic pattern and a fourth free magnetic pattern spaced apart from the third free magnetic pattern in the second direction and with the second free magnetic pattern therebetween. The first cell array structure may also include a first transistor region including first transistors connected to the first free magnetic pattern and the second free magnetic pattern, respectively. The second cell array structure may also include a second transistor region including second transistors connected to the third free magnetic pattern and the fourth free magnetic pattern, respectively. The second transistor region may be spaced apart from the first transistor region in the first direction.

[0005] In one aspect, a magnetic memory device may include: a first cell array structure, which includes a first group of magnetic patterns extending along a first direction on a surface of a substrate and spaced apart from each other in a second direction intersecting the first direction, and a first transistor region including a first transistor connected to the first group of magnetic patterns; and a second cell array structure, which includes a second group of magnetic patterns extending along the first direction and arranged interlaced with the first group of magnetic patterns, and a second transistor region including a second transistor connected to the second group of magnetic patterns. The first transistor may be arranged in the second direction, and the second transistor may be arranged in the second direction. The second transistor region may be spaced apart from the first transistor region in the first direction.

[0006] In one aspect, a magnetic memory device may include: a first group of magnetic patterns extending along a first direction on a surface of a substrate and spaced apart from each other in a second direction intersecting the first direction; a second group of magnetic patterns arranged interlaced with the first group of magnetic patterns; a first transistor region including a first transistor, the first transistor being connected to a first end region of the first group of magnetic patterns and arranged in a second direction; a second transistor region including a second transistor, the second transistor being connected to a second end region of the second group of magnetic patterns and arranged in a second direction; a first central transistor region including a first central transistor, the first central transistor being connected to a first central region of the first group of magnetic patterns, and a second central transistor region including a second central transistor, the second central transistor being connected to a second central region of the second group of magnetic patterns, respectively. The second transistor region may be spaced apart from the first transistor region in the first direction. Each of the first transistor region and the second transistor region and each of the first central transistor region and the second central transistor region may include a pair of gate electrodes extending in the first direction and a first dopant region between the pair of gate electrodes. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The inventive concept will become more apparent in view of the accompanying drawings and accompanying detailed description.

[0008] Figure 1 is a top view illustrating a magnetic memory device according to some embodiments of the inventive concept.

[0009] Figure 2 yes Figure 1 Magnified view of region 'Q'.

[0010] Figure 3 and Figure 4 Along Figure 1 A cross-sectional view taken along lines AA' and BB'.

[0011] Figure 5 and Figure 6 yes Figure 3 Magnified view of region 'P'.

[0012] Figure 7 and Figure 8 is a top view illustrating a magnetic memory device according to some embodiments of the inventive concept.

[0013] Fig. 9 is a top view illustrating a magnetic memory device according to some embodiments of the inventive concept.

[0014] Fig.10 yes Fig. 9 Magnified view of region 'R'.

[0015] Fig.11 is a top view illustrating a magnetic memory device according to some embodiments of the inventive concept.

[0016] Figures 12 to 18 A method of manufacturing a magnetic memory device according to some embodiments of the inventive concept is shown, wherein Fig.12 It is a top view. Fig.13 , Fig.15 and Fig.17 Corresponding to the Fig.12 A cross-sectional view taken along line A-A', Fig.14 , Fig.16 and Fig.18 Corresponding to the Fig.12 A cross-sectional view taken along line BB'. DETAILED DESCRIPTION

[0017] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0018] Figure 1 is a top view illustrating a magnetic memory device according to some embodiments of the inventive concept. Figure 2 yes Figure 1 Magnified view of region 'Q'. Figure 3 and Figure 4 Along Figure 1 A cross-sectional view taken along lines AA' and BB'. Figure 5 and Figure 6 yes Figure 3 Magnified view of region 'P'.

[0019] Reference Figures 1 to 4 , the first unit array structure CA1 may be provided on a substrate 100. The substrate 100 may be a semiconductor substrate. For example, the semiconductor substrate may include silicon (Si), silicon on insulator (SOI), silicon germanium (SiGe), germanium (Ge), or gallium arsenide (GaAs). The first unit array structure CA1 may include a first group of magnetic patterns GR1 extending longitudinally in a first direction D1 parallel to the top surface of the substrate 100. For example, the first group of magnetic patterns GR1 may include a first free magnetic pattern RC1 and a second free magnetic pattern RC2. However, embodiments of the inventive concept are not limited thereto. In some embodiments, the first group of magnetic patterns GR1 may include three or more free magnetic patterns. The terms first, second, third, etc. may be used herein to distinguish one element from another element, rather than for the purpose of limitation, and the first element discussed below may be referred to as the second element without departing from the scope of the inventive concept.

[0020] The second free magnetic pattern RC2 may be spaced apart from the first free magnetic pattern RC1 in a second direction D2 that intersects the first direction D1 and is parallel to the top surface of the substrate 100. The lengths of the first group of magnetic patterns GR1 may be substantially equal to each other. The ends of the first group of magnetic patterns GR1 may be aligned with each other in the second direction D2. For example, both ends of the second free magnetic pattern RC2 may be spaced apart from both ends of the first free magnetic pattern RC1 in the second direction D2, respectively.

[0021] The first cell array structure CA1 may include a first transistor region TD1 including a first transistor TR1 connected to the first group magnetic pattern GR1. In the present embodiment, the first transistor region TD1 may be disposed below each of the end regions ER1 and ER2 of the first group magnetic pattern GR1. For example, the (1_1)th transistor region TD1_1 may be disposed below the first end region ER1 of the first group magnetic pattern GR1, and the (1_2)th transistor region TD1_2 may be disposed below the second end region ER2 spaced apart from the first end region ER1 along the first direction D1. The structure and arrangement of the (1_2)th transistor region TD1_2 and components thereon (e.g., contacts and source lines) may be symmetrical or identical to the structure and arrangement of the (1_1)th transistor region TD1_1 and components thereon. Hereinafter, the first transistor TR1 of the (1_1)th transistor region TD1_1 will be described as an example.

[0022] The first transistors TR1 may be arranged in the second direction D2. In the present embodiment, the first transistors TR1 may be driver transistors for moving the magnetic domains of the first group magnetic pattern GR1. The first transistors TR1 may be connected to the ends of the first free magnetic pattern RC1 and the second free magnetic pattern RC2 in a one-to-one correspondence. Each of the first transistors TR1 may include a pair of gate electrodes GE extending longitudinally in the first direction D1, a first dopant region SD1 between the gate electrodes GE, and a pair of second dopant regions SD2 spaced apart from the first dopant region SD1 and with the gate electrode GE interposed therebetween.

[0023] The gate electrode GE may be provided on the substrate 100, and a gate insulating layer (or a tunnel insulating layer) may be provided between the substrate 100 and the gate electrode GE. For example, the gate electrode GE may include a conductive material such as metal and / or doped silicon. The first dopant region SD1 and the second dopant region SD2 may be provided in a region defined by a device isolation layer 11 provided in an upper portion of the substrate 100. For example, the first dopant region SD1 and the second dopant region SD2 may be doped with an N-type dopant. For ease of description, spatial relationship terms such as "under...", "below...", "below...", "above...", "on...", etc. may be used herein to describe the relationship between an element or feature as shown in the figure and another element(s) or feature(s). It will be understood that, in addition to the orientations depicted in the accompanying drawings, the spatial relationship terms are also intended to cover other different orientations of the device in use or operation.

[0024] In some embodiments, the first transistors TR1 adjacent to each other may share the second dopant region SD2 therebetween. Figure 2 As shown. For example, the first dopant region SD1 may be a drain region, and the second dopant region SD2 may be a source region. Each gate electrode GE may have a strip shape having a major axis in the first direction D1. For example, the width t1 of each gate electrode GE in the first direction D1 may be in the range of 5 to 20 times the width t2 of each gate electrode GE in the second direction D2. The first dopant region SD1 and the second dopant region SD2 may also have a strip shape extending longitudinally in the first direction D1 like the gate electrode GE.

[0025] The first contact CT1 may be provided on the first dopant region SD1, and the second contact CT2 may be provided on the second dopant region SD2. The second contact CT2 may be spaced apart from or offset from the first contact CT1 in the first direction D1. In this specification, it is understood that when the second contact CT2 is spaced apart from or offset from the first contact CT1 in the first direction D1, an imaginary line connecting the second contact CT2 is spaced apart from (not in a straight line with) an imaginary line connecting the first contact CT1 in the first direction D1.

[0026] The first contact CT1 and the second contact CT2 may be disposed in the first interlayer insulating layer 101. The bottom electrode 111 may be disposed on the first contact CT1, and the source line SL may be disposed on the second contact CT2. The bottom electrode 111 and the source line SL may be disposed in the second interlayer insulating layer 102. In the present embodiment, the bottom electrode 111 and the source line SL are disposed at the same height. However, embodiments of the inventive concept are not limited thereto.

[0027] The bottom electrodes 111 may contact the top surfaces of the first contacts CT1, respectively, and may contact the bottom surface of the lower magnetic pattern to be described later. Each source line SL may extend longitudinally in the second direction D2 and may be connected to a plurality of second contacts CT2. The first and second contacts CT1 and CT2, the bottom electrodes 111, and the source lines SL may include a metal material such as tungsten, titanium, copper, or aluminum.

[0028] The first lower magnetic pattern PL1 and the conductive spacer SP may be sequentially disposed on the bottom electrode 111. The first lower magnetic pattern PL1 and the conductive spacer SP may be disposed in the third interlayer insulating layer 103. Each first lower magnetic pattern PL1 may be a reference layer having a magnetization direction fixed in one direction. The conductive spacer SP may include a conductive material such as a metal material (e.g., tungsten, titanium, copper, or aluminum) and / or a conductive nitride thereof. Ends of the first free magnetic pattern RC1 and the second free magnetic pattern RC2 may be electrically connected to the first dopant region SD1 of the first transistor TR1 through the conductive spacer SP, the first lower magnetic pattern PL1, the bottom electrode 111, and the first contact CT1.

[0029] The first free magnetic pattern RC1 and the second free magnetic pattern RC2 may be provided on the third interlayer insulating layer 103. The first free magnetic pattern RC1 and the second free magnetic pattern RC2 may be disposed in the fourth interlayer insulating layer 104. Each of the first to fourth interlayer insulating layers 101, 102, 103, and 104 may include silicon oxide, silicon nitride, and / or silicon oxynitride.

[0030] The first central transistor region TCR1 may be provided below the central region CR between the first end region ER1 and the second end region ER2. The first central transistor region TCR1 may be disposed at an equal distance from both ends of the first group magnetic pattern GR1 in the first direction D1. However, embodiments of the inventive concept are not limited thereto. In the present embodiment, the first cell array structure CA1 includes a single first central transistor region TCR1. Alternatively, a plurality of first central transistor regions TCR1 spaced apart from each other in the first direction D1 may be provided.

[0031] The first central transistor region TCR1 may include a first central transistor TC1 arranged in the second direction D2. The shape and arrangement of the first central transistor TC1 and components disposed thereon (i.e., contacts and source lines) may be substantially the same as the shape and arrangement of the first transistor TR1 and components disposed thereon (i.e., contacts CT1 and CT2 and source line SL). A bottom electrode 111 may be provided on the first contact CT1 of the first central transistor TC1, and a second lower magnetic pattern PL2 may be provided on the bottom electrode 111. A tunnel barrier pattern TL may be provided on the second lower magnetic pattern PL2.

[0032] The first group of magnetic patterns GR1 may include a plurality of magnetic domains D and a plurality of magnetic domain walls DW. For example, the magnetic domains D and the magnetic domain walls DW may be arranged alternately and repeatedly in the first free magnetic pattern RC1 along the first direction D1. Each magnetic domain D may be a region in a magnet in which the magnetization direction is uniform. Each magnetic domain wall DW may be a region between magnetic domains D in a magnet in which the magnetization direction changes. Each magnetic domain wall DW may define a boundary between magnetic domains D having different magnetization directions. The size and magnetization direction of the magnetic domain D may be appropriately controlled by the shape and / or size of the magnet and external energy. The magnetic domain D and the magnetic domain wall DW may be moved by a magnetic field or current applied to the magnet. For example, the magnetic domain D and the magnetic domain wall DW may be moved by a first current I1 supplied to the first group of magnetic patterns GR1 via a first transistor TR1. The first group of magnetic patterns GR1 may include at least one of cobalt (Co), iron (Fe), and nickel (Ni). The tunnel barrier pattern TL may include at least one of a magnesium oxide (MgO) layer, a titanium oxide (TiO) layer, an aluminum oxide (AlO) layer, a magnesium zinc oxide (MgZnO) layer, and a magnesium boron oxide (MgBO) layer.

[0033] The second lower magnetic pattern PL2, the tunnel barrier pattern TL, and the first group of magnetic patterns GR1 (more specifically, the magnetic domains D disposed on the second lower magnetic pattern PL2) may constitute or define a magnetic tunnel junction MTJ. Figure 5 and Figure 6 Each magnetic domain D may have a magnetization direction that can be changed to be parallel or antiparallel to the magnetization direction of the second lower magnetic pattern PL2. In some embodiments, referring to Figure 5 The magnetization direction MD1 of the second lower magnetic pattern PL2 and the magnetization direction MD2 of each magnetic domain D may be substantially perpendicular to the interface between the tunnel barrier pattern TL and the second lower magnetic pattern PL2. The first lower magnetic pattern PL1 may also have the same magnetization direction as the second lower magnetic pattern PL2.

[0034] The first and second lower magnetic patterns PL1 and PL2 and the first group magnetic patterns GR1 may include a perpendicular magnetic material (eg, CoFeTb, CoFeGd, or CoFeDy), a magnetic material having L1 0 At least one of a perpendicular magnetic material having a structure, a CoPt alloy having a hexagonal close-packed (HCP) lattice structure, and a perpendicular magnetic structure. 0 The vertical magnetic material of the structure may include L1 0 FePt with L1 0 FePd with L1 0 CoPd structure and L1 0 The vertical magnetic structure may include at least one of (Co / Pt)n, (CoFe / Pt)n, (CoFe / Pd)n, (Co / Pd)n, (Co / Ni)n, (CoNi / Pt)n, (CoCr / Pt)n, and (CoCr / Pd)n, where "n" represents the number of double layers.

[0035] In certain embodiments, reference Figure 6 , the magnetization direction MD1 of the second lower magnetic pattern PL2 and the magnetization direction MD2 of each magnetic domain D may be substantially parallel to the interface between the tunnel barrier pattern TL and the second lower magnetic pattern PL2. The first lower magnetic pattern PL1 may also have the same magnetization direction as the second lower magnetic pattern PL2. In this case, the first lower magnetic pattern PL1 and the second lower magnetic pattern PL2 and the first group of magnetic patterns GR1 may include ferromagnetic materials, and the first lower magnetic pattern PL1 and the second lower magnetic pattern PL2 may also include antiferromagnetic materials for fixing the magnetization directions of the ferromagnetic materials.

[0036] Will refer to Figure 5 and Figure 6 Read and write operations of a magnetic memory device according to some embodiments of the inventive concept are described.

[0037] The first current I1 may be supplied to the first group magnetic pattern GR1 (e.g., the first free magnetic pattern RC1) through the first transistor TR1. The moving direction of the magnetic domain wall DW may be determined by the direction of the first current I1. The magnetic domain wall DW may move in the moving direction of the electrons, and thus the magnetic domain wall DW may move in a direction opposite to the direction of the first current I1. For example, the first current I1 may flow in the first direction D1, and the magnetic domain wall DW may move in a direction opposite to the first direction D1.

[0038] The second current I2 may be supplied to the magnetic tunnel junction MTJ through the second lower magnetic pattern PL2. For example, the second current I2 may be a read current. The resistance state of the magnetic tunnel junction MTJ may be detected by the second current I2 or determined by the second current I2. For example, the magnetization direction MD2 of the magnetic domain D in the magnetic tunnel junction MTJ may be parallel to the magnetization direction MD1 of the second lower magnetic pattern PL2, in which case the magnetic tunnel junction MTJ may be in a low resistance state. When the magnetization direction MD2 of the magnetic domain D in the magnetic tunnel junction MTJ is antiparallel (or opposite) to the magnetization direction MD1 of the second lower magnetic pattern PL2, the magnetic tunnel junction MTJ may be in a high resistance state. The data (0 or 1) stored in the magnetic domain D may be detected from the resistance state of the magnetic tunnel junction MTJ.

[0039] Thereafter, the first current I1 may flow through the first free magnetic pattern RC1 to move the adjacent magnetic domain D onto the second lower magnetic pattern PL2, and the moved magnetic domain D and the second lower magnetic pattern PL2 may constitute or define a magnetic tunnel junction MTJ. The second current I2 may be supplied to the magnetic domain D moved onto the second lower magnetic pattern PL2, thereby detecting the resistance state of the magnetic tunnel junction MTJ.

[0040] In some embodiments, the second current I2 may be a write current. The magnitude of the write current may be greater than the magnitude of the read current. The magnetization direction MD2 of the magnetic domain D may be reversed by the spin transfer torque generated by the write current. For example, the magnetization direction MD2 of the magnetic domain D may be switched to be antiparallel to the magnetization direction MD1 of the second lower magnetic pattern PL2 by the spin transfer torque generated by the write current. Thereafter, the first current I1 may flow through the first free magnetic pattern RC1 to move the adjacent magnetic domain D to the second lower magnetic pattern PL2, and the moved magnetic domain D and the second lower magnetic pattern PL2 may constitute or define a magnetic tunnel junction MTJ. The second current I2 may be supplied to the magnetic domain D moved to the second lower magnetic pattern PL2, thereby reversing the magnetization direction of the moved magnetic domain D.

[0041] The second cell array structure CA2 may be provided on the substrate 100. The second cell array structure CA2 may have substantially the same components as the first cell array structure CA1. For example, the second cell array structure CA2 may include a second group of magnetic patterns GR2 including a third free magnetic pattern RC3 and a fourth free magnetic pattern RC4. The second cell array structure CA2 may include a second transistor region TD2 including a second transistor TR2 connected to the second group of magnetic patterns GR2. The second transistor region TD2 may include a (2_1)th transistor region TD2_1 provided below the first end region ER1 and a (2_2)th transistor region TD2_2 provided below the second end region ER2. The second cell array structure CA2 may include a second central transistor region TCR2 provided below the central region CR between the first end region ER1 and the second end region ER2. The second central transistor region TCR2 may include a second central transistor TC2 arranged in the second direction D2.

[0042] At least one of the second group of magnetic patterns GR2 may be disposed between the first group of magnetic patterns GR1. For example, the third free magnetic pattern RC3 may be disposed between the first free magnetic pattern RC1 and the second free magnetic pattern RC2. The fourth free magnetic pattern RC4 may be spaced apart from the third free magnetic pattern RC3, and the second free magnetic pattern RC2 may be interposed therebetween. In other words, the first group of magnetic patterns GR1 and the second group of magnetic patterns GR2 may be arranged alternately in the second direction D2. The distance between the first free magnetic pattern RC1 and the third free magnetic pattern RC3 in the second direction D2 may be substantially equal to the distance between the third free magnetic pattern RC3 and the second free magnetic pattern RC2 in the second direction D2. For example, the pitch of the first to fourth free magnetic patterns RC1 to RC4 in the second direction D2 may be half the pitch of the first group of magnetic patterns GR1 in the second direction D2.

[0043] The length of the second group of magnetic patterns GR2 may be substantially equal to the length of the first group of magnetic patterns GR1. In the first end region ER1, the end of the second group of magnetic patterns GR2 may be spaced apart from the end of the first group of magnetic patterns GR1 in the first direction D1. Similarly, in the second end region ER2, the end of the second group of magnetic patterns GR2 may be spaced apart from the end of the first group of magnetic patterns GR1 in the first direction D1. In the first end region ER1 or the second end region ER2, the distance by which the end of the second group of magnetic patterns GR2 is spaced apart from the end of the first group of magnetic patterns GR1 in the first direction D1 may be greater than the distance between the first transistor region TD1 and the second transistor region TD2 in the first direction D1.

[0044] Under each of the first end region ER1 and the second end region ER2, the second transistor region TD2 may be spaced apart from or offset from the first transistor region TD1 in the first direction D1. For example, the second transistor TR2 (more specifically, the gate electrode GE of the second transistor TR2) may be spaced apart from the first transistor TR1 (more specifically, the gate electrode GE of the first transistor TR1) in the first direction D1. At least some of the gate electrodes GE of the second transistor TR2 may have corresponding side walls aligned with the side walls of at least some of the gate electrodes GE of the first transistor TR1 in the first direction D1. The first dopant region SD1 of the second transistor TR2 may be aligned with the second dopant region SD2 of the first transistor TR1 in the first direction D1. The second dopant region SD2 of the second transistor TR2 may be aligned with the first dopant region SD1 of the first transistor TR1 in the first direction D1. This arrangement of the gate electrode GE and the first dopant region SD1 and the second dopant region SD2 may also be applied to the first central transistor region TCR1 and the second central transistor region TCR2.

[0045] The distance between the (1_1)th transistor region TD1_1 and the (2_1)th transistor region TD2_1 in the first direction D1 may be substantially equal to the distance between the (1_2)th transistor region TD1_2 and the (2_2)th transistor region TD2_2 in the first direction D1. Likewise, the second central transistor region TCR2 may be spaced apart from the first central transistor region TCR1 in the first direction D1.

[0046] In a free magnetic pattern including magnetic domains arranged in a track form, the driving current for moving the magnetic domains may be relatively large, and a large-sized transistor (e.g., a transistor with a large gate width) may be required to provide the large driving current. According to an embodiment of the inventive concept, the free magnetic patterns of a plurality of cell array structures may be arranged alternately, and the transistors connected thereto may be arranged to be spaced apart from each other in the longitudinal extension direction of the free magnetic pattern. Therefore, the integration density of the magnetic memory device may be improved.

[0047] Figure 7 and Figure 8 is a top view illustrating a magnetic memory device according to some embodiments of the inventive concept. Hereinafter, for ease and convenience of explanation, descriptions of structures and features that are the same or similar to those in the above embodiments will be omitted.

[0048] Reference Figure 7, the length L2 of the gate electrode GE of the first central transistor TC1 and the second central transistor TC2 in the first direction D1 may be less than the length L1 of the gate electrode GE of the first transistor TR1 and the second transistor TR2 in the first direction D1. For example, the length L2 of the gate electrode GE of the first central transistor TC1 and the second central transistor TC2 in the first direction D1 may be in the range of about 50% to about 80% of the length L1 of the gate electrode GE of the first transistor TR1 and the second transistor TR2 in the first direction D1.

[0049] Reference Figure 8 , the arrangement of the first contact CT1 and the second contact CT2 and the source line SL of the (2_1)th transistor region TD2_1 of the first end region ER1 and the arrangement of the first contact CT1 and the second contact CT2 and the source line SL of the (2_2)th transistor region TD2_2 of the second end region ER2 may be mirror-symmetrical with respect to the central region CR. The length of the second group magnetic pattern GR2 in the first direction D1 may be smaller than the length of the first group magnetic pattern GR1 in the first direction D1. For example, the length of the third free magnetic pattern RC3 and the fourth free magnetic pattern RC4 may be shorter than the length of the first free magnetic pattern RC1 and the second free magnetic pattern RC2.

[0050] Fig. 9 is a top view illustrating a magnetic memory device according to some embodiments of the inventive concept. Fig.10 yes Fig. 9 Hereinafter, for ease and convenience of explanation, descriptions of the same structures and features as those in the above embodiments will be omitted.

[0051] Reference Fig. 9 and Fig.10 , first to fourth cell array structures CA1 to CA4 may be provided on the substrate 100. The components and arrangement of the first cell array structure CA1 and the second cell array structure CA2 may be the same as those of reference 1. Figure 1 The third cell array structure CA3 may have substantially the same components as the first cell array structure CA1. For example, the third cell array structure CA3 may include a third group of magnetic patterns GR3, which includes a fifth free magnetic pattern RC5 and a sixth free magnetic pattern RC6. The end of the third group of magnetic patterns GR3 may be spaced apart from the end of the second group of magnetic patterns GR2 in the first direction D1. The third cell array structure CA3 may include a third transistor region TD3, which includes a third transistor TR3 connected to the third group of magnetic patterns GR3. The third cell array structure CA3 may also include a third central transistor region TCR3, which includes a third central transistor TC3.

[0052] The fifth free magnetic pattern RC5 may be disposed between the second free magnetic pattern RC2 and the third free magnetic pattern RC3. The sixth free magnetic pattern RC6 may be spaced apart from the second free magnetic pattern RC2 with the fourth free magnetic pattern RC4 interposed therebetween. The third transistor region TD3 may be spaced apart from the second transistor region TD2 in the first direction D1.

[0053] The fourth cell array structure CA4 may have substantially the same components as the first cell array structure CA1. For example, the fourth cell array structure CA4 may include a fourth group of magnetic patterns GR4 including a seventh free magnetic pattern RC7 and an eighth free magnetic pattern RC8. The ends of the fourth group of magnetic patterns GR4 may be spaced apart from the ends of the third group of magnetic patterns GR3 in the first direction D1. The fourth cell array structure CA4 may include a fourth transistor region TD4 including a fourth transistor TR4 connected to the fourth group of magnetic patterns GR4. The fourth cell array structure CA4 may also include a fourth central transistor region TCR4 including a fourth central transistor TC4.

[0054] The seventh free magnetic pattern RC7 may be disposed between the first free magnetic pattern RC1 and the third free magnetic pattern RC3. The eighth free magnetic pattern RC8 may be disposed between the second free magnetic pattern RC2 and the fourth free magnetic pattern RC4. The fourth transistor region TD4 may be spaced apart from the third transistor region TD3 in the first direction D1. For example, the pitch of the first to eighth free magnetic patterns RC1 to RC8 in the second direction D2 may be 1 / 4 of the pitch of the first group magnetic pattern GR1 in the second direction D2.

[0055] Fig.11 is a top view illustrating a magnetic memory device according to some embodiments of the inventive concept.

[0056] This embodiment is one in which Fig. 9 The embodiment omits the embodiment of the fourth unit array structure CA4. The distance between the first free magnetic pattern RC1 and the second free magnetic pattern RC2 in the second direction D2 may be twice or more the distance between the second free magnetic pattern RC2 and the third free magnetic pattern RC3 in the second direction D2.

[0057] Figures 12 to 18 A method of manufacturing a magnetic memory device according to some embodiments of the inventive concept is shown, wherein Fig.12 It is a top view. Fig.13 , Fig.15 and Fig.17 Corresponding to the Fig.12 A cross-sectional view taken along line A-A', Fig.14 , Fig.16 and Fig.18 Corresponding to the Fig.12 A cross-sectional view taken along line BB'.

[0058] Reference Figure 12 to Figure 14 , the first transistor TR1 and the second transistor TR2 and the first central transistor TC1 and the second central transistor TC2 may be formed on the substrate 100. The device isolation layer 11 and the gate electrode GE may be formed on the substrate 100. A trench may be formed in the upper portion of the substrate 100, and then, by filling the trench with an insulating layer such as a silicon oxide layer, the device isolation layer 11 may be formed in the trench. A conductive layer (e.g., metal and / or doped silicon) may be stacked on the substrate 100, and then, a patterning process may be performed on the conductive layer to form the gate electrode GE. The gate insulating layer (or tunnel insulating layer) may be formed before the formation of the conductive layer. The first dopant region SD1 and the second dopant region SD2 may be formed. For example, the first dopant region SD1 and the second dopant region SD2 may be formed by implanting an N-type dopant into the substrate 100 after the formation of the gate electrode GE.

[0059] The gate electrode GE may be arranged in each of the transistor regions TD1, TD2, TCR1, and TCR2 in the second direction D2. The first dopant region SD1 and the second dopant region SD2 may be provided in the substrate 100 between the gate electrodes GE. The first interlayer insulating layer 101 may be formed to extend on the substrate 100 or cover the substrate 100. The first interlayer insulating layer 101 may be formed by a chemical vapor deposition (CVD) process. For example, the first interlayer insulating layer 101 may be formed of silicon oxide, silicon nitride, and / or silicon oxynitride.

[0060] Reference Fig.12 , Fig.15 and Fig.16 , the first contact CT1 and the second contact CT2 may be formed to penetrate the first interlayer insulating layer 101. The first contact CT1 may be connected to the first dopant region SD1, and the second contact CT2 may be connected to the second dopant region SD2. The formation of the first contact CT1 and the second contact CT2 may include forming a contact hole penetrating the first interlayer insulating layer 101 to expose the substrate 100 and filling the contact hole with a conductive material. For example, the first contact CT1 and the second contact CT2 may be formed of a conductive material such as a metal material (e.g., tungsten, titanium, copper, or aluminum) and / or a conductive nitride thereof. For example, the first contact CT1 and the second contact CT2 may be formed by a CVD method or a physical vapor deposition (PVD) method (e.g., a sputtering deposition method).

[0061] In each of the transistor regions TD1, TD2, TCR1, and TCR2, the first contacts CT1 may be aligned with each other in the second direction D2. The second contacts CT2 may also be aligned with each other in the second direction D2. The second contacts CT2 may be spaced apart from the first contacts CT1 in the first direction D1.

[0062] The second interlayer insulating layer 102 may be formed to extend on or cover the first and second contacts CT1 and CT2, and then, the bottom electrode 111 and the source line SL may be formed in the second interlayer insulating layer 102. The bottom electrodes 111 may be respectively disposed on the first contacts CT1. Each source line SL may be formed to be commonly connected to the second contacts CT2 arranged in the second direction D2. In the present embodiment, the bottom electrode 111 and the source line SL may be formed together. Alternatively, the source line SL may be formed at a height from the substrate 100 different from that of the bottom electrode 111 or at a distance from the substrate 100 in a third direction D3 perpendicular to the first and second directions D1 and D2 different from that of the bottom electrode 111. The source line SL and the bottom electrode 111 may be formed of a metal material (e.g., tungsten, titanium, copper, or aluminum) and / or a conductive nitride thereof.

[0063] The initial magnetic pattern PPL may be formed on the bottom electrode 111. The initial magnetic pattern PPL may extend in the second direction D2 and may be spaced apart from each other in the first direction D1. An initial conductive spacer PSP and an initial tunnel barrier pattern PTL may be formed on the initial magnetic pattern PPL. The initial conductive spacer PSP may be formed on the initial magnetic pattern PPL to be patterned as the first lower magnetic pattern, and the initial tunnel barrier pattern PTL may be formed on the initial magnetic pattern PPL to be patterned as the second lower magnetic pattern. For example, the initial conductive spacer PSP and the initial tunnel barrier pattern PTL may be formed together with the initial magnetic pattern PPL by the same patterning process. Therefore, the initial conductive spacer PSP and the initial tunnel barrier pattern PTL may extend in the second direction D2. The initial conductive spacer PSP may be formed of a conductive material such as a metal material (e.g., tungsten, titanium, copper, or aluminum) and / or a conductive nitride thereof. The preliminary tunnel barrier pattern PTL may be formed of at least one of a magnesium oxide (MgO) layer, a titanium oxide (TiO) layer, an aluminum oxide (AlO) layer, a magnesium zinc oxide (MgZnO) layer, and a magnesium boron oxide (MgBO) layer.

[0064] The third interlayer insulating layer 103 may be formed to extend on or cover the initial conductive spacer PSP and the initial tunnel barrier pattern PTL, and then a planarization process may be performed on the third interlayer insulating layer 103 to expose top surfaces of the initial conductive spacer PSP and the initial tunnel barrier pattern PTL.

[0065] Reference Figure 1 , Fig.17 and Fig.18 , a magnetic layer may be formed on the initial conductive spacers PSP and the initial tunnel barrier patterns PTL, and then, a patterning process may be performed on the magnetic layer to form first to fourth free magnetic patterns RC1 to RC4. Through the patterning process, each initial conductive spacer PSP may be formed as a conductive spacer SP spaced apart from each other in the second direction D2, and each initial tunnel barrier pattern PTL may be formed as a tunnel barrier pattern TL spaced apart from each other in the second direction D2. In addition, each initial magnetic pattern PPL may be formed as a lower magnetic pattern PL1 or PL2 spaced apart from each other in the second direction D2. Thereafter, a fourth interlayer insulating layer 104 may be formed to extend on or cover the first to fourth free magnetic patterns RC1 to RC4, as shown in FIG. Figure 3 and Figure 4 shown.

[0066] According to an embodiment of the inventive concept, free magnetic patterns of a plurality of cell array structures may be alternately arranged, and transistors connected thereto may be disposed to be spaced apart from each other in an extension direction of the free magnetic patterns. Thus, the integration density of the magnetic memory device may be improved.

[0067] Although the inventive concept has been described with reference to example embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the inventive concept. Therefore, it should be understood that the above embodiments are not restrictive, but illustrative. Therefore, the scope of the inventive concept is determined by the broadest permissible interpretation of the following claims and their equivalents, and should not be restricted or limited by the foregoing description.

[0068] This application claims the benefit of Korean Patent Application No. 10-2019-0100419 filed on August 16, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A magnetic storage device, comprising: a first unit array structure including a first free magnetic pattern and a second free magnetic pattern, the first free magnetic pattern and the second free magnetic pattern extending in a first direction on a surface of a substrate and spaced apart from each other in a second direction crossing the first direction; as well as a second unit array structure including a third free magnetic pattern between the first free magnetic pattern and the second free magnetic pattern and a fourth free magnetic pattern spaced apart from the third free magnetic pattern in the second direction and having the second free magnetic pattern therebetween, The first cell array structure further includes a first transistor region, wherein the first transistor region includes first transistors respectively connected to the first free magnetic pattern and the second free magnetic pattern. The second cell array structure further includes a second transistor region, wherein the second transistor region includes second transistors respectively connected to the third free magnetic pattern and the fourth free magnetic pattern. wherein the second transistor region is spaced apart from the first transistor region in the first direction, and The first transistors are arranged in the second direction, and the second transistors are arranged in the second direction.

2. The magnetic memory device according to claim 1, wherein: A distance between the first free magnetic pattern and the third free magnetic pattern in the second direction is equal to a distance between the third free magnetic pattern and the second free magnetic pattern in the second direction.

3. The magnetic memory device according to claim 1, wherein: Each of the first transistor region and the second transistor region includes: a pair of gate electrodes, the pair of gate electrodes being spaced apart from each other in the second direction with one of the first free magnetic pattern, the second free magnetic pattern, the third free magnetic pattern, and the fourth free magnetic pattern therebetween when viewed in a plan view; and a first dopant region between the pair of gate electrodes; and A second dopant region is spaced apart from the first dopant region in the second direction with the pair of gate electrodes therebetween.

4. The magnetic memory device according to claim 3, further comprising: first contacts connecting corresponding ones of the first dopant regions to the first free magnetic pattern, the second free magnetic pattern, the third free magnetic pattern, and the fourth free magnetic pattern; a first source line and a second source line extending along the second direction above the pair of gate electrodes in the first transistor region and the second transistor region, respectively; as well as A second contact connects the first source line and the second source line to the second dopant region of the first transistor region and the second transistor region, respectively.

5. The magnetic memory device according to claim 4, wherein: The second contact is spaced apart from the first contact in the first direction.

6. The magnetic memory device according to claim 5, wherein: A respective sidewall of at least one gate electrode of the pair of gate electrodes of the second transistor region is aligned with a respective sidewall of a respective gate electrode of the pair of gate electrodes of the first transistor region in the first direction.

7. The magnetic memory device according to claim 4, further comprising: conductive spacers between the first contact and the first free magnetic pattern, the second free magnetic pattern, the third free magnetic pattern, and the fourth free magnetic pattern, respectively; as well as First lower magnetic patterns are respectively between the conductive spacers and the first contacts.

8. The magnetic memory device according to claim 1, wherein: The first transistor region includes a pair of first transistor regions under opposite end regions of the first free magnetic pattern and the second free magnetic pattern, and The second transistor region includes a pair of second transistor regions under opposite end regions of the third free magnetic pattern and the fourth free magnetic pattern.

9. The magnetic memory device according to claim 3, wherein: The first transistor region is below a first central region between opposite end regions of the first free magnetic pattern and the second free magnetic pattern, and The second transistor region is below a second central region between opposite end regions of the third free magnetic pattern and the fourth free magnetic pattern.

10. The magnetic memory device according to claim 9, further comprising: first contacts connecting corresponding ones of the first dopant regions to the first free magnetic pattern, the second free magnetic pattern, the third free magnetic pattern, and the fourth free magnetic pattern; a tunnel barrier pattern between the first contact and the first free magnetic pattern, the second free magnetic pattern, the third free magnetic pattern, and the fourth free magnetic pattern, respectively; and and second lower magnetic patterns respectively between the tunnel barrier patterns and the first contacts.

11. The magnetic memory device according to claim 1, further comprising: a third unit array structure including a fifth free magnetic pattern between the second free magnetic pattern and the third free magnetic pattern and a sixth free magnetic pattern spaced apart from the second free magnetic pattern in the second direction and having the fourth free magnetic pattern therebetween, The third unit array structure further includes a third transistor region, the third transistor region includes third transistors respectively connected to the fifth free magnetic pattern and the sixth free magnetic pattern, and The third transistor region is spaced apart from the second transistor region in the first direction.

12. The magnetic memory device according to claim 11, further comprising: a fourth unit array structure comprising a seventh free magnetic pattern between the first free magnetic pattern and the third free magnetic pattern in the second direction and an eighth free magnetic pattern between the second free magnetic pattern and the fourth free magnetic pattern in the second direction, The fourth unit array structure further includes a fourth transistor region, the fourth transistor region includes fourth transistors connected to the seventh free magnetic pattern and the eighth free magnetic pattern, respectively, and The fourth transistor region is spaced apart from the third transistor region in the first direction.

13. The magnetic memory device according to claim 1, wherein: Respective ends of the third and fourth free magnetic patterns are spaced apart from respective ends of the first and second free magnetic patterns in the first direction by a distance greater than a distance between the second transistor region and the first transistor region in the first direction.

14. The magnetic memory device according to claim 1, wherein: Respective lengths of the first free magnetic pattern, the second free magnetic pattern, the third free magnetic pattern, and the fourth free magnetic pattern are equal to each other.

15. A magnetic storage device comprising: a first cell array structure including a first group of magnetic patterns extending in a first direction on a surface of a substrate and spaced apart from each other in a second direction crossing the first direction, and a first transistor region including first transistors respectively connected to the first group of magnetic patterns; as well as a second unit array structure including a second group of magnetic patterns extending along the first direction and arranged alternately with the first group of magnetic patterns, and a second transistor region including second transistors respectively connected to the second group of magnetic patterns, The first transistor is arranged in the second direction, the second transistor is arranged in the second direction, and the second transistor region is spaced apart from the first transistor region in the first direction.

16. The magnetic memory device according to claim 15, wherein: Respective ends of the second group of magnetic patterns are spaced apart from respective ends of the first group of magnetic patterns in the first direction by a distance greater than a distance between the second transistor region and the first transistor region in the first direction.

17. The magnetic memory device according to claim 15, wherein: A respective sidewall of at least one of the gate electrodes of the second transistors is aligned with a respective sidewall of a respective one of the gate electrodes of the first transistors in the first direction.

18. A magnetic storage device comprising: a first group of magnetic patterns extending along a first direction on a surface of the substrate and spaced apart from each other in a second direction intersecting the first direction; a second set of magnetic patterns arranged alternately with the first set of magnetic patterns; a first transistor region including first transistors respectively connected to first end regions of the first group of magnetic patterns and arranged in the second direction; a second transistor region including second transistors respectively connected to second end regions of the second group of magnetic patterns and arranged in the second direction; a first central transistor region including first central transistors respectively connected to first central regions of the first group of magnetic patterns; as well as a second central transistor region including second central transistors, the second central transistors being respectively connected to the second central regions of the second group of magnetic patterns, wherein the second transistor region is spaced apart from the first transistor region in the first direction, and Each of the first transistor region and the second transistor region and each of the first central transistor region and the second central transistor region includes a pair of gate electrodes extending in the first direction and a first dopant region between the pair of gate electrodes.

19. The magnetic memory device according to claim 18, wherein: The first group of magnetic patterns includes a first free magnetic pattern and a second free magnetic pattern, and the second group of magnetic patterns includes a third free magnetic pattern between the first free magnetic pattern and the second free magnetic pattern and a fourth free magnetic pattern spaced apart from the third free magnetic pattern in the second direction and with the second free magnetic pattern therebetween.

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