Control device and control method for switching voltage regulator

Abstract

The present disclosure relates to a control device and a control method for a switching voltage regulator. A control circuit and method, wherein an error signal is generated, the error signal represents the difference between the output voltage of the switching circuit and the nominal signal; a single control signal is generated, the single control signal represents the average error of the error signal; the single control signal is compared with a first periodic reference signal and a second periodic reference signal; a first pulse width modulated signal is generated by a buck modulator; and a second pulse width modulated signal is generated by a boost modulator. In a transient control mode between the buck control mode and the boost control mode, the maximum value of the first periodic reference signal and the minimum value of the second periodic reference signal are respectively higher and lower than the single control signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Italian Application No. 102019000014715, filed on August 13, 2019, which is incorporated herein by reference. Technical Field

[0003] The present invention relates to a control device and a control method for a switching voltage regulator. Background Art

[0004] As is known, switching voltage regulators operate according to different schemes, the most common being the buck (step-down) and boost (step-up) control modes. Regulators are also known that use both control modes in different operating phases of the regulator depending on the value of the input voltage and in particular on its relation to the output voltage (higher or lower) (so-called buck-boost).

[0005] This type of switching voltage regulator is based on the regulation of the duty cycle, i.e. the on and off time of the switch, and can be determined by Figure 1 The general block diagram shown in .

[0006] Figure 1 The voltage regulator 1 includes a switching circuit 2 and a control device 3 .

[0007] Here, the switching circuit 2 is formed by a first half bridge 4 and a second half bridge 5. The first half bridge 4 is formed by a first high-side switch (first HSS 11) and a first low-side switch (first LSS 12), which are coupled in series with each other between a first input terminal 6 and a second input terminal 7. An input voltage Vi is applied between the first input terminal 6 and the second input terminal 7; the second terminal 7 is coupled to a reference potential line (ground) 8.

[0008] The second half bridge 5 is formed by a second high side switch (second HSS 13) and a second low side switch (second LSS 14) which are coupled in series with each other between the output node 9 and the second input terminal 7. An output voltage Vo referenced to ground is present at the output node 9 and is provided to a load 10.

[0009] The inductor 15 is coupled between the middle nodes of the first half-bridge 4 and the second half-bridge 5 .

[0010] The control device 3 comprises an error amplifier 20 having an input coupled to the output node 9 and an input coupled to a reference voltage source 21 providing a reference voltage VR. The error amplifier 20 (e.g. an operational amplifier) ​​compares the output voltage Vo (or a portion thereof) with the reference voltage VR and outputs an error signal which is integrated by an integrator stage 22 (e.g. an RC circuit not shown) and provided to a pulse width modulator (PWM modulator 23).

[0011] The PWM modulator 23 also receives the triangular (or sawtooth) signal TR generated by the triangular signal generator 25 and generates a switching signal, which is used to control the conduction and shutdown of the switches 11-13 based on the type of control used through the corresponding drive circuits 26, 27. In particular, based on the time when the triangular signal TR is equal to the integrated error signal, the modulator 23 generates a rectangular (on-off) switching signal for the switches 11-13.

[0012] In this circuit, the triangular signal generator 25 determines the operating frequency of the voltage regulator 1 , and the PWM modulator 23 determines the duration of the rectangular pulses and thus the duty cycle of the voltage regulator 1 .

[0013] For example, Figure 2 , Figure 3 , Figure 4 refers to the voltage reduction type control implemented by the control device 3'. In particular, Figure 2 middle, Figure 1 The error amplifier 20 is implemented by a subtraction node 30 (generating an error voltage signal VE) and a transconductance amplifier 31 (generating an error current signal IE); Figure 1 The integrator stage 22 is implemented by a proportional-integral controller 32 (generating a voltage control signal VC), and the PWM modulator is implemented by a buck modulator 33, which receives a triangular signal TR having a period T and generates a first switching signal TON and a second switching signal TOFF which are opposite to each other, as described below. In the switch circuit 2, the switches 11-14 are implemented by N-channel MOSFET transistors, which are connected to Figure 1 The switch circuit 2 further includes a sense resistor 35 coupled between the second LSS 12, 14 and ground, and includes an amplifier 36 ( Figure 4 ), amplifier 36 has an input coupled across sense resistor 35, and outputs a detection voltage VCS. Sense resistor 35 and amplifier 36 form a sense circuit 37, which is part of a current stabilization loop discussed later.

[0014] In the buck operation mode, the second half bridge 5 does not switch; in particular, the second HSS 13 is always turned on, and the second LSS 14 is always turned off. The first HSS 11 and the first LSS 12 switch in opposite ways and receive the first switching signal TON and the second switching signal TOFF, respectively. Figure 3 shown.

[0015] Figure 2 The voltage regulator 1 ′ is configured to operate with an input voltage Vi that is greater than the output voltage Vo.

[0016] Also refer to Figure 3 , and temporarily ignoring the moment of action of the stabilization loop, the buck modulator 33 generates the first switching signal TON so that it is high when the voltage control signal VC is greater than the triangular signal TR, and it is low when the voltage control signal VC is lower than the triangular signal TR (see Figure 3 The first two control cycles of , between times t1 and t4).

[0017] In particular, Figure 4 As shown in FIG. 1 , in the time interval between t1 and t2, the voltage control signal VC is higher than the triangular signal TR, the first switch signal TON is 1, and the second switch signal TOFF is 0. Therefore, in the switch circuit 2, the first HSS 11 is turned on, the first LSS 12 is turned off, and the current flows in the first HSS 11, the inductor 15, and the second HSS 13, as shown by Figure 4 As shown by the dotted line in . Since the voltage on the inductor 15 is positive and equal to (Vi-Vo), the current I in the inductor 15 L It increases linearly with a slope of (Vi-Vo) / L (where L is the inductance of the inductor 15).

[0018] At time t2, the first switch signal TON and the second switch signal TOFF are switched; the first HSS 11 is turned off, the first LSS 12 is turned on, and the inductor current flows in the first LSS 12, the inductor 15 and the second HSS 13, as shown by Figure 4 In the time interval between t2 and t3, since the voltage on the inductor 15 is negative and equal to -Vo, the inductor current I L It decreases linearly with a slope of -Vo / L.

[0019] At time t3, the voltage regulator 1' switches again, and in the time interval t3-t4, the switching circuit 2 behaves as described above for the time interval t1-t2. In this case, the time interval t3-t4 is longer than the time interval t1-t2 (and thus the duty cycle is increased) because the voltage control signal VC is higher.

[0020] In the case where the output voltage Vo is substantially stable, the voltage regulator 1 ′ therefore modifies the on-off time of the switches 11 - 14 to maintain the output voltage Vo near a desired value.

[0021] In the voltage regulator 1 ′, the sensing resistor 35 detects the current I in the inductor 15 L , and provides the detection voltage VCS to the buck modulator 33 through the amplifier 36. As long as the detection voltage VCS is below the threshold, the stabilization loop does not intervene. When the detection voltage VCS exceeds the threshold (for example, due to a significant change in the output current, such as due to a change in the load), the buck modulator 33 provides an additional boost voltage (V ADD ) is injected into the triangular signal TR, thereby generating a modified triangular signal TR', which is compared with the voltage control signal VC. ADD =-kV CS , where k is a constant and V CS is the voltage detected by the sensing circuit 37. In fact, the modified triangular signal TR' is shifted upward relative to the triangular signal TR and causes the following time interval t5-t6 (when the first switching signal TON is high) to be shortened, which allows the switching circuit 2 to return to a stable state faster.

[0022] use Figure 2-Figure 4 Buck regulation, when the inductor current I L When the inductor current I flows from ground 8 through the sense resistor 35, L The detection of occurs at the valley points (time t1, t3, etc.) of the triangular signals TR and TR'.

[0023] The voltage regulator 1' has a duty cycle V given by equation (1) O / Vi:

[0024]

[0025] Where, ΔT ON It is the time that signal TON is high in period T.

[0026] Figure 5 , Figure 6 , Figure 7 Refers to boost type control.

[0027] Figure 6 The voltage regulator (indicated by 1") has Figure 2 The voltage regulator 10 is of very similar structure, but the buck modulator 33 is replaced by a boost modulator 38. Therefore, the other components are identified with the same reference numerals and will not be described again.

[0028] In the boost operation mode, the first half bridge 4 does not switch; in particular, the first HSS 11 is always on, and the first LSS 12 is always off. The second HSS 13 and the second LSS 14 switch in the opposite manner and receive the Figure 6 The first switching signal TON and the second switching signal TOFF are shown in FIG.

[0029] Figure 2 The control device 3" is configured to work with an input voltage Vi lower than the output voltage Vo and operates in a similar manner to the voltage regulator 10, such as from Figure 6 As seen in the drawing of the main electrical quantities shown in .

[0030] In particular, the voltage control signal VC is compared with the modified triangular signal TR′ to generate the first switching signal TON and the second switching signal TOFF which are provided to the second LSS 14 and the second HSS 13 , respectively.

[0031] In the time interval t1-t2, the second HSS 13 is turned off, the second LSS 14 is turned on, and current flows into the first HSS 11, the inductor 15 and the second LSS 14, as shown by Figure 7 Therefore, the voltage on the inductor 15 is positive (equal to Vi), and the current I in the inductor 15 is L Increases linearly with slope Vi / L.

[0032] At time t2, the first switch signal TON and the second switch signal TOFF are switched; the second HSS 13 is turned on, the second LSS 14 is turned off, and current flows in the first HSS 11, the inductor 15, and the second HSS 13, as shown by Figure 7 As shown by the dotted line in Figure 3 and Figure 4 In the time interval t2-t3, since the voltage on the inductor 15 is negative and equal to Vi-Vo, the current in the inductor 15 decreases linearly with a slope (Vi-Vo) / L.

[0033] The control device 3 ″ then modifies the switching duration of the switches 11 - 14 to maintain the output voltage Vo around the desired value.

[0034] Similar to the above, the detection circuit 37 detects the current I in the inductor 15 L , and the detection voltage V CS is provided to the boost modulator 38. When the detection voltage V in the inductor 15 CS When the threshold is exceeded, the boost modulator 38 injects an additional boost voltage (V ADD), thereby generating a modified triangular signal TR'. For example, V ADD = kV CS , where k is a constant and V CS is the voltage measured by the detection circuit 37. In this case too, in fact, after the intervention of the current stabilization loop, the modified triangular signal TR' is shifted upwards relative to the triangular signal TR' and allows the switching circuit 2 to return to a stable state more quickly.

[0035] use Figure 5-Figure 7 The boost regulation is when the inductor current I L When the current I in the inductor 15 flows through the sensing resistor 35 to the ground 8, L The detection of occurs at the peak points (time t2, t4, etc.) of the triangular signals TR and TR'.

[0036] The voltage regulator 1" has a duty cycle V given by equation (2) O / Vi:

[0037]

[0038] Where ΔT OFF is the time that signal TOFF is high in period T, and D BOOST is the duty cycle of the voltage regulator 1".

[0039] According to another known solution, Figure 1 The voltage regulator 1 can operate in a buck-boost mode to be able to regulate the output voltage when the output voltage is higher, lower or approximately equal to the input voltage. In this case, the voltage regulator 1 alternates buck control cycles with boost control cycles. To this end, the PWM modulator 23 includes a buck modulator (such as Figure 2 Buck modulator 33) and boost modulator (such as Figure 5 Furthermore, the PWM modulator 23 includes a selection circuit, not shown, which selectively enables the buck modulator 33 or the boost modulator 38 to generate switching signals TON, TOFF for the two half bridges 4, 5 according to the working phase.

[0040] Typically, in the voltage regulator 1 operating in the buck-boost mode, when the input voltage Vi exceeds the value of the output voltage Vo greater than the first threshold, the buck modulator 33 is enabled and controls the on / off of the first half bridge 4 to regulate the output voltage Vo, as shown in FIG. Figure 2-Figure 4 Vice versa, when the input voltage Vi is lower than the output voltage Vo by a value greater than the second threshold, the boost modulator 38 is enabled and controls the on / off of the second half-bridge 5 to adjust the output voltage Vo, as shown in reference Figure 2-Figure 4As described. When the voltage difference between the input voltage Vi and the output voltage Vo is included in the window between the first threshold and the second threshold, according to one solution, the buck modulator 33 and the boost modulator 38 alternate in each regulation cycle to turn on / off the four switches 11-14 of the first half-bridge 4 and the second half-bridge 5.

[0041] This type of regulation (using two control loops that operate independently and separately and alternate in the described manner) would include a rather high ripple in the output voltage, which is not desirable.

[0042] Another type of buck-boost regulation is described in EP 1837983 A1 and generates a Figure 8 waveform, where Vo / Vi is the ratio of the output voltage Vo to the input voltage Vi; Vi / k is a part of the input voltage Vi; Do and Di are the duty cycles of the half-bridge; e1 is the integrated error at the output of the Figure 1 integrator stage 22, which is generated by integrating the error between the output voltage Vo and the reference voltage VR (or between values proportional thereto); TR 1 is a modified triangular wave, whose maximum value is Vi / k if Vo / Vi < e1, otherwise the maximum value is e1.

[0043] Here, the duty cycles Di, Do of the half-bridge are different, but are related to the integration error e1. In particular, for example, the first duty cycle Di that regulates the switching of the first half-bridge 4 is proportional to the ratio between the integration error e1 and the output voltage Vo, and for example, the second duty cycle that regulates the switching of the second half-bridge 5 is proportional to the ratio between the output voltage Vo and the integration error e1.

[0044] Although it can operate satisfactorily to avoid fast transients and sudden changes in the output voltage, this solution can still be improved, especially in terms of efficiency and reduction of voltage ripple in the transition region.

[0045] Therefore, an object of the present invention is to provide a control device for a switching voltage regulator that overcomes the disadvantages of the prior art. Summary of the Invention

[0046] According to the present invention, there is provided a control device and a control method for a switching voltage regulator as defined in the appended claims.

[0047] In fact, in the buck-boost control mode, the instant control device uses two separate control loops to regulate the operation of the half-bridges (buck half-bridge and boost half-bridge) of the switching circuit, and each loop compares its own reference quantity with a single control quantity. The voltage control loop is unique but based on two separate modulators that operate in a continuous manner.

[0048] Specifically, compared with the single control amount, the reference amount has the same waveform (especially, a triangle or sawtooth shape), has the same period T, the same phase and the same amplitude range (such as the difference between the maximum value and the minimum value), but is shifted from each other. In particular, the boost mode reference amount is higher than the buck mode reference amount, and the shift value is such that when the regulator operates in the buck control mode, the boost mode reference amount is always greater than the single comparison amount; when the regulator operates in the boost control mode, the buck mode reference amount is always lower than the single comparison amount; and in the buck-boost control mode, both the buck and boost mode reference amounts cross the single comparison amount line. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] For the purpose of understanding the present invention, embodiments of the present invention will now be described by way of non-limiting example only, with reference to the accompanying drawings, in which:

[0050] Figure 1 is a block diagram of a known switching voltage regulator including a switching circuit;

[0051] Figure 2 is the circuit diagram of a step-down voltage regulator;

[0052] Figure 3 Shows Figure 2 Plotting of some electrical quantities in a circuit;

[0053] Figure 4 Shows Figure 2 The current flows in the switching circuit of the buck regulator;

[0054] Figure 5 is the circuit diagram of a step-up voltage regulator;

[0055] Figure 6 Shows Figure 5 Plotting of some electrical quantities in a circuit;

[0056] Figure 7 Shows Figure 5 The current flows in the switching circuit of the boost regulator;

[0057] Figure 8 A plot showing some electrical quantities in a known buck-boost regulator;

[0058] Fig. 9 is a schematic circuit diagram of a voltage regulator of the present invention;

[0059] Fig.10 yes Fig. 9 A circuit diagram of a portion of a regulator;

[0060] Fig.11 Shows Fig. 9Plotting of control signals for a switching circuit;

[0061] Fig.12 Shows Fig. 9 A circuit diagram of another part of the regulator;

[0062] Fig.13 It is shown that in the simulations performed by the applicant, Fig. 9 Plots of electrical quantities measured in circuits; and

[0063] Fig.14 yes Fig. 9 A state diagram of a regulator, showing the ideal behavior and possible actual behavior. DETAILED DESCRIPTION

[0064] Fig. 9 and Fig.10 One embodiment of a buck-boost type voltage regulator 40 is shown.

[0065] The voltage regulator 40 includes a switching circuit 41 and a control device 42. The switching circuit 41 and the control device 42 are generally formed on separate chips, but may be integrated on the same chip.

[0066] Switching circuit 41 (see in particular Fig.10 ) is formed by a first half bridge 44 and a second half bridge 45.

[0067] The first half bridge 44 is formed by a first high-side switch (first HSS 51) and a first low-side switch (first LSS 52) coupled in series with each other between an input terminal 46 and a common node 47. An input voltage Vi (referenced to a reference potential line (ground) 48) is applied at the input terminal 46; the common node 47 is coupled to the ground 48 through a sense resistor 50.

[0068] The second half bridge 45 is formed by a second high-side switch (second HSS 53) and a second low-side switch (second LSS 54) coupled in series with each other between the output node 49 and the common node 47. The first and second HSSs 51 and 53 and the first and second LSSs 52 and 54 may be implemented as power MOS devices, for example, by N-channel power MOS transistors.

[0069] The output node 49 provides an output voltage Vo, which is referenced to ground and is provided to a load 58 .

[0070] An inductor 55 is coupled between intermediate nodes 56 and 57 of the first half-bridge 44 and the second half-bridge 45 .

[0071] Control device 42 (see Fig. 9) includes a subtraction node 60, which receives a reference voltage VR at a non-inverting input and an output voltage Vo at an inverting input, and outputs an error voltage signal VE. The output of the subtraction node 60 is coupled to a transconductance amplifier 61, which generates an error current IE=g m VE, the error current is provided to the controller 62 (here of proportional-integral type), thereby generating an integrated error signal (hereinafter also referred to as the control signal V C ).

[0072] The output of the controller 62 is coupled to the respective inputs of the buck modulator 63 and the boost modulator 64, which are configured to receive the control signal V C , the first and second triangular (sawtooth) signals s generated by the triangular signal generator 65 T1 and T2 Specifically, refer to the following Fig.11 In detail, the buck modulator 63 receives the control signal V C and the first triangular signal s T1 , and generates a first timing signal T ON1 and the second timing signal T OFF1 ; The boost modulator 64 receives the control signal V C and the second triangular signal s T2 , and generates a third timing signal T ON2 and the fourth timing signal T OFF2 .

[0073] The triangular signal generator 65 has a triangular signal generator 65 through an operational amplifier 67 (see Fig.10 ) is coupled to the input of sense resistor 50 for implementing injection of additional boost, as explained below.

[0074] First triangular signal T1 and the second triangular signal s T2 has the same period T, constant minimum and maximum values, and the same amplitude range (here, 1V), but the second triangular signal s T2 Relative to the first triangular signal s T1 The offset voltage VOFF is shifted upward; in particular, Fig.11 As shown in FIG. 1 , the offset voltage VOFF is 0.75 V and the first triangular signal s T1 varies between 0V and 1V, and the second triangular signal s T2 Varies between 0.75V and 1.75V.

[0075] Timing signal T ON1 , T OFF1 , T ON2 and TOFF2 is provided to the Boolean circuit 66 to generate the first, second, third and fourth drive signals T1-T4 (T1-T4) for driving the switches 51-54 through their own drive elements 76-79. Fig.10 ).

[0076] In particular, if Fig.10 As shown in FIG. 6 , the Boolean circuit 66 includes a first OR gate 70 , a first AND gate 71 , a second OR gate 72 , and a second AND gate 73 .

[0077] The first OR gate 70 receives the first and third timing signals T ON1 , T ON2 , and generates a first driving signal T1 for the first HSS 51; the first AND gate 71 receives the second and fourth timing signals T OFF1 , T OFF2 , and generates a second driving signal T2 for the first LSS 52; the second OR gate 72 receives the second and fourth timing signals T OFF1 , T OFF2 , and generates a third driving signal T3 for the second HSS53; and the second AND gate 73 receives the first and third timing signals T ON1 , T ON2 , and generates a fourth control signal T4 for the second LSS 54.

[0078] Now refer to Fig.10 and Fig.11 To describe the operation of the voltage regulator 40, Fig.10 and Fig.11 The behavior of the regulator 40 is shown when the output voltage (initially at a value lower than the input voltage Vi) increases for any reason, thereby causing the regulator 40 to pass through the buck-boost control mode from the buck control mode to the boost control mode.

[0079] in particular, Fig.11 Plots showing:

[0080] The current I through the inductor 55 L ;

[0081] First triangular signal T1 and the second triangular signal s T2 It can be seen that the second triangular signal s T2 Above the first triangle signal s T1 , but its minimum value is lower than the first triangular signal s T1 The maximum value of

[0082] Normalized control signal V CN =V C / V M , by setting the control signal VC Divide by the maximum output voltage Vo V M get;

[0083] The first to fourth timing signals T ON1 , T OFF1 , T ON2 , T OFF2 ;as well as

[0084] First to fourth driving signals T1-T4.

[0085] exist Fig.11 In the embodiment, before time t0, the regulator 40 is in the buck control mode; therefore, the third and fourth timing signals T ON2 , T OFF2 are low and high respectively and do not change state, and the first timing signal T ON1 and the second timing signal T OFF1 Toggles between high and low states in opposite ways.

[0086] At time t0, the first triangular signal s T1 and the second triangular signal s T2 are at their respective minimum values, respectively below and above the normalized control signal V CN Therefore, the first timing signal T ON1 and the fourth timing signal T OFF2 is high, the second and third timing signals T OFF1 , T ON2 is low; the first drive signal T1 and the third drive signal T3 are high, turning on the first HSS 51 and the second HSS 53; the second drive signal T2 and the fourth drive signal T4 are low, turning off the first LSS 52 and the second LSS 54. Therefore, the control is still in the buck mode, and the inductor current I L (flows from the input terminal 46 through the first HSS 51 and the second HSS 53 and the inductor 55 to the output node 49 (such as Fig.10 The dashed arrow I L1 As shown)) increases linearly with a slope of (Vi-VO) / L.

[0087] At time t1, the first triangular signal s T1 reaches, and then exceeds, the normalized control signal V CN Therefore, the first timing signal T ON1 Switches to low, the second timing signal T OFF1 Switches to high, and the third and fourth timing signals T ON2 , T OFF2Therefore, the first drive signal T1 and the second drive signal T2 are switched to low and high, respectively, which turns off the first HSS 51 and turns on the first LSS 52, while the third drive signal T3 and the fourth drive signal T4 do not change state, and maintain the second HSS 53 turned on and the second LSS 54 turned off. Therefore, the inductor current I L From ground, through the first LSS 52, the inductor 55, and the second HSS 53, to the output node 49 (eg, Fig.10 The dashed arrow I L2 ), and decreases linearly with a slope of -VO / L.

[0088] At time t2, the first triangular signal s T1 and the second triangular signal s T2 reaches its corresponding minimum value again. This time, due to the normalized control signal V CN The increase of the triangular signal s T1 and T2 becomes lower than the normalized control signal V CN , which results in the first timing signal T ON1 Switches to high, the second timing signal T OFF1 Switches to low, the third timing signal T ON2 switches to high, and the fourth timing signal T OFF2 Therefore, the regulator 40 enters the boost stage of the buck-boost mode, the first drive signal T1 and the fourth drive signal T4 are switched to high, and the second drive signal T2 and the third drive signal T3 are switched to low, so that the first HSS 51 and the fourth LSS 54 are turned on, and the first LSS 52 and the second HSS 53 are turned off. Therefore, the inductor current I L From the input terminal 46, through the first HSS 51, the fourth LS switch 54 and the inductor 55, the current flows to the ground 48 (eg, Fig.10 By arrow I L3 As shown), and increases linearly with a slope Vi / L.

[0089] At time t3, the second triangular signal s T2 becomes higher than the normalized control signal V CN , but the first triangular signal s T1 Keep the control signal below the normalized V CN Therefore, the first timing signal T ON1 Keep high, the second timing signal TOFF keeps low, and the third timing signal T ON2 switches to low, and the fourth timing signal T OFF2is switched high. Therefore, the first and second drive signals T1 and T2 remain high and low, respectively; the third drive signal T3 is switched high, turning on the first HSS 53; and the fourth switch signal T4 is switched low, turning off the second LS switch 54. Here, the regulator 40 is in the buck-boost control mode, and the inductor current I L From input terminal 46, through first HSS 51 and second HSS 53 and inductor 55, to output node 49 (again as Fig.10 By arrow I L1 As shown), it increases linearly with a slope (Vi-Vo) / L, which is smaller than the slope in the time interval t0-t1 because the output voltage Vo is higher.

[0090] At time t4, similar to time t1, the first triangular signal s T1 reaches, and then exceeds, the normalized control signal V CN Therefore, the first timing signal T ON1 and the second timing signal T OFF1 The first drive signal T1 and the second drive signal T2 are switched, turning off the first HSS 51 and turning on the first LSS 52. The second HSS 53 remains turned on and the second LS switch 54 remains turned off. Here, the regulator 40 enters the buck stage of the buck-boost control mode, and the inductor current I L Again, it flows from ground to the output node 49 (arrow I L2 ), and decreases linearly with a slope of -VO / L.

[0091] At time t5, the first triangular signal s T1 and the second triangular signal s T2 reaches its corresponding minimum value again and becomes lower than the normalized control signal V CN . Similar to time t2, all timing signals T ON1 , T OFF1 , T ON2 and T OFF2 And all the driving signals T1 to T4 switch, turning on the first HSS 51 and the fourth LSS 54, and turning off the first LSS 52 and the second HSS 53. Therefore, due to the change of the inductor bias, the inductor current I L From input terminal 46 to ground 48 (again as Fig.10 By arrow I L3 As shown in FIG. 1 , and increases linearly with a slope Vi / L. The regulator 40 enters the boost phase of the buck-boost control mode. As can be seen, in this regulation cycle, between time t2 and t5, the inductor current I L Has a trapezoidal waveform.

[0092] In the subsequent regulation cycle, between time t5 and time t8, in the buck-boost control mode, the regulator 40 behaves as in the cycle between time t2 and t5. Here, unlike the cycle between time t2 and t5, the inductor current I L After increasing at the slope Vi / L, it decreases (rather than increases) at the slope (Vi-VO) / L because the output voltage VO is now higher than the input voltage Vi. In any case, also in this regulation cycle, the inductor current I L has a trapezoidal behavior, albeit with a different slope.

[0093] At time t8, the regulator 40 switches as described for times t2 and t5, but it enters a boost type control mode. In particular, at time t8, all timing signals T ON1 , T OFF1 , T ON2 and T OFF2 And all driving signals T1 to T4 switch, turning on the first HSS 51 and the fourth LSS 54, and turning off the first LSS 52 and the second HSS 53. Therefore, the inductor current I L Increase again ( Fig.10 Arrow I L3 ). Thereafter, the first triangular signal s T1 No longer reaches the normalized control signal V CN , so in this regulation cycle, between t8 and t10, the inductor current I L The first timing signal T has only an increasing portion between t8 and t9 and a decreasing portion between t9 and t10. ON1 and the first driving signal T1 is stable in a high state; the second timing signal T OFF1 and the second driving signal T OFF1 Stable in low state, the third timing signal T ON2 , the fourth timing signal T OFF2 , the third driving signal T3 and the fourth driving signal T OFF1 Switching between low and high to maintain the first HSS 51 turned on and the first LSS 52 turned off, the second HS switch 54 and the second LS switch 54 are alternately turned on and off according to the boost control mode.

[0094] Fig.11 Arrows V1 and V2 are also used to indicate that the first and second triangular signals s T1 、s T2 The additional boost voltage on the Figure 3 and Figure 6Detailed discussion and illustrated below. In particular, the additional boost voltages V1 and V2 are obtained using a current control loop that detects the inductor current flowing in the switch circuit 41. According to one aspect of the present disclosure, the current control loop can be integrated in a voltage control loop that controls the output voltage of the switch circuit 41.

[0095] Fig.12 A possible implementation of a circuit implementing a current control loop and generating additional boosted voltages V1 and V2 is shown.

[0096] Specifically, according to Fig.12 The triangular signal generator 65 includes a ramp generator 80 that generates a ramp signal s provided to a buck adding node 81 and a boost adding node 82. T0 The boost add node 82 also receives an offset voltage VOFF or a reference voltage generated by an offset generator 83 (eg, a memory element provided in a device test phase).

[0097] The buck and boost adding nodes 81, 82 also receive the outputs of respective buck and boost memory elements 84, 85 formed, for example, as sample and hold circuits. The buck and boost memory elements 84, 85 receive the detection voltage V CS , detection voltage V CS The inductor current I generated by the operational amplifier 67 and flowing in the switch circuit 41 L In particular, and in a manner known per se, the buck memory element 84 detects and stores the detection voltage V at the valley point of the inductor current. CS , and the boost memory element 85 detects and stores the detection voltage V at the peak point of the inductor current CS .

[0098] The outputs of the buck and boost add nodes 81, 82 are fed to the respective buck and boost modulators 63, 64. In particular, the outputs of the buck and boost add nodes 81, 82 are coupled to the inverting inputs of respective differential amplifiers 87, 88, each of which has a respective non-inverting input coupled to the output of the controller 62, and generates respective buck and boost duty cycle signals DBu, DBo, which are used by the buck and boost modulators 63, 64 for generating the timing signal T ON1 , T OFF1 , T ON2 and T OFF2 .

[0099] In steady state, the voltage regulator 40 has a duty cycle V given by equation (3) O / Vi:

[0100]

[0101] Where ΔT ON1 It is signal T ON1 The high time in period T, ΔT OFF2 It is signal T OFF2 During the period T, D BUCK and D BOOST are the duty cycle values ​​of the buck and boost control modes of the voltage regulator 40 , respectively.

[0102] Fig.13 The input voltage Vi (curve A), the output voltage Vo (curve B), the inductor current I L (curve C), the output current IO flowing in the load 58 (assuming that there is an output capacitor (not shown), curve D), the first triangular signal s T1 (curve E), the second triangular signal s T2 (curve F), control signal V C (curve G), the first timing signal T ON1 (curve H) and the second timing signal T ON2 (Curve J) is a plot during the hybrid buck / boost control mode, from which the above behavior can be seen, and in particular the inductor current I L Trapezoidal waveform.

[0103] Fig.14 A state diagram of the duty cycle of the regulator 40 is shown, wherein the abscissa shows the normalized value of pure boost mode control (DBo) and the ordinate shows the normalized value of pure buck mode control (DBu).

[0104] exist Fig.14 In the diagram of , the maximum duty cycle (DBo_M, DBu_M) and the minimum duty cycle (DBo_m, DBu_m) are identified in order to take into account the delays involved in turning on and off the switches 51-54 (usually made as power MOS devices) and the leakage conditions; therefore, the light gray square area indicates the area in which the switches 51-54 can be fully turned on or off. In addition, the transition values ​​DBo_t and DBu_t refer to the ideal transition values ​​between the pure boost control mode and the pure buck control mode to the buck-boost control mode as described above (and vice versa). These ideal values ​​define the line of the straight line portion, respectively having a horizontal portion Bu and a vertical portion Bo (referring to the pure buck control mode and the pure boost control mode) and a 45° inclined portion (BB, referring to the buck-boost control mode).

[0105] Fig.14Also shown is the ratio Vo / Vi as a function of different duty cycles, with a center line 100 corresponding to Vo / Vi=1 and two limit lines 101 and 102 corresponding to DBu_M and DBo_m.

[0106] The applicant's research also shows that direct transition through the buck-boost state space is not possible; in addition, due to the weak conductivity of the power MOS device (even for a small turn-on pulse), the discrete transition and transition line between DBo=0 and DBo_m (or DBu=1 and DBu_M) are not feasible. Therefore, a continuous smooth transition in the boundary area of ​​the desired state space is shown by the curve with a continuous line, which is included in the triangle formed by the line DBo=0 (vertical axis), the 45° inclined portion BB and the line 101, and the triangle formed by the 45° inclined portion BB, the line 102 and the line DBu=1, respectively.

[0107] The control device of the present invention is able to reduce transient times and have lower ripple in the output voltage due to the buck-boost control mode (controlled by comparing own buck and boost reference voltages with the same plot but different values ​​to the same comparison value (related to the output voltage)). The described control circuit is also able to provide a larger duty cycle interval, because the control is not based on a duty cycle threshold, but can work in a continuous manner over the complete duty cycle interval.

[0108] Finally, it is obvious that numerous variations and modifications may be made to the control device and method described and illustrated herein, all falling within the scope of the invention as defined in the appended claims.

[0109] For example, the control device 40 may be implemented in an analog manner or in a digital manner, depending on specific design requirements.

[0110] Furthermore, the Boolean circuit 66 may be omitted, and the timing signal T ON1 , T OFF1 , T ON2 , T OFF2 Drivers 76-79 that directly control switches 51-54.

Claims

1. A control device for a switching voltage regulator, the switching voltage regulator comprising a switching circuit, the control device include: a first input configured to receive a measurement signal, the measurement signal representing an output voltage of the switching circuit; an error detector configured to generate an error signal representing a difference between the measured signal and a nominal signal; a controller coupled to the error detector and configured to generate a single control signal representing an average error of the error signal; a buck modulator coupled to the controller and configured to compare the single control signal with a first periodic reference signal and generate at least one first pulse width modulated signal for the switching circuit; as well as a boost modulator coupled to the controller and configured to compare the single control signal to a second periodic reference signal and to generate at least one second pulse width modulated signal for the switching circuit; wherein the first periodic reference signal and the second periodic reference signal have the same period T, the same amplitude range, the same phase, and different maximum and minimum values; wherein in the boost control mode, the maximum value of the first periodic reference signal is lower than the single control signal; wherein in the buck control mode, the minimum value of the second periodic reference signal is higher than the single control signal; wherein in a transient control mode between the buck control mode and the boost control mode, the maximum value of the first periodic reference signal and the minimum value of the second periodic reference signal are respectively higher and lower than the single control signal; wherein in the step-down control mode and the transient control mode, the first pulse width modulation signal switches between an on control value and an off control value; wherein in the boost control mode and the transient control mode, the second pulse width modulation signal switches between the on control value and the off control value; wherein, in a buck-boost state space of the duty cycle, there is a normalized value of a pure boost control mode on the abscissa and a normalized value of a pure buck control mode on the ordinate, a line having a 45° inclined straight line portion defined by the pure boost control mode and an ideal duty cycle transition value between the pure buck control mode and the buck-boost control mode, and a first limit line defined between a maximum value of the buck duty cycle for the pure boost control mode and a unit duty cycle, and a second limit line defined between a minimum value of the boost duty cycle for the pure boost control mode and the unit duty cycle; and The control device is configured to control a continuous smooth transition along a curve included in a triangle formed by the line of the pure buck control mode, the line of the 45° inclined straight line portion and the first limit line, or a triangle formed by the line of the 45° inclined straight line portion, the second limit line and the line of the pure boost control mode. 2 . The control device according to claim 1 , wherein the first periodic reference signal and the second periodic reference signal are triangular sawtooth signals.

3. The control device according to claim 1, wherein the controller is a proportional-integral (PI) controller.

4. The control device according to claim 1, further comprising a triangular signal generator configured to generate the first periodic reference signal and the second periodic reference signal, the triangular signal generator include: a ramp generator configured to generate a ramp signal as the first periodic reference signal; An offset generator, generating an offset signal; as well as A boost adding node is coupled to the ramp generator and the offset generator and is configured to generate the second periodic reference signal.

5. The control device according to claim 4, further comprising a boost circuit, wherein the boost circuit include: A first memory element and a second memory element are configured to receive the measurement signal, detect and store a peak value and a valley value, respectively, wherein the peak value and the valley value represent current values ​​at a peak point and a valley point of the measurement signal, respectively; a buck add node coupled to the first memory element and the ramp generator; and The boost add node is also coupled to the second memory element.

6. The control device of claim 1, further comprising a Boolean circuit coupled to the buck modulator and the boost modulator.

7. The control device according to claim 6, wherein the buck modulator is configured to generate a third pulse width modulated signal, the first pulse width modulated signal and the third pulse width modulated signal are opposite to each other, the boost modulator is configured to generate a fourth pulse width modulated signal, the second pulse width modulated signal and the fourth pulse width modulated signal are opposite to each other, and wherein the Boolean circuit includes a first OR gate and a second OR gate, and a first AND gate and a second AND gate, the first OR gate is configured to receive the first pulse width modulated signal and the second pulse width modulated signal, and generate a first drive signal; the first AND gate is configured to receive the third pulse width modulated signal and the fourth pulse width modulated signal, and generate a second drive signal ； The second OR gate is configured to receive the third pulse width modulation signal and the fourth pulse width modulation signal and generate a third driving signal; And the second AND gate is configured to receive the first pulse width modulation signal and the second pulse width modulation signal and generate a fourth driving signal.

8. A switching voltage regulator, include: Control equipment, including: a first input configured to receive a measurement signal representing an output voltage of the switching circuit; an error detector configured to generate an error signal representing a difference between the measured signal and a nominal signal; a controller coupled to the error detector and configured to generate a single control signal representing an average error of the error signal; a buck modulator coupled to the controller and configured to compare the single control signal with a first periodic reference signal and generate at least one first pulse width modulated signal for the switching circuit; and a boost modulator coupled to the controller and configured to compare the single control signal with a second periodic reference signal and generate at least one second pulse width modulated signal for the switching circuit; wherein the first periodic reference signal and the second periodic reference signal have the same period T, the same amplitude range, the same phase, and different maximum and minimum values; wherein in the boost control mode, the maximum value of the first periodic reference signal is lower than the single control signal; wherein in the buck control mode, the minimum value of the second periodic reference signal is higher than the single control signal; wherein in a transient control mode between the buck control mode and the boost control mode, the maximum value of the first periodic reference signal and the minimum value of the second periodic reference signal are respectively higher and lower than the single control signal; wherein in the buck control mode and the transient control mode, the first pulse width modulation signal switches between an on control value and an off control value; and wherein in the boost control mode and the transient control mode, the second pulse width modulation signal switches between the on control value and the off control value; and The switch circuit, wherein the switch circuit comprises: a first half-bridge comprising a first switch and a second switch coupled in series between an input node and a reference potential node, wherein the first switch is configured to receive the first pulse width modulated signal, and the second switch is configured to receive a third pulse width modulated signal, the third pulse width modulated signal being opposite to the first pulse width modulated signal; a second half-bridge comprising a third switch and a fourth switch coupled in series between an output node and the reference potential node, wherein the third switch is configured to receive the second pulse width modulated signal, and the fourth switch is configured to receive a fourth pulse width modulated signal, the fourth pulse width modulated signal being opposite to the second pulse width modulated signal; and an inductive element coupled between an intermediate node of the first half-bridge and an intermediate node of the second half-bridge, wherein, in the buck-boost state space of the duty cycle, there is a normalized value of the pure boost control mode on the abscissa and a normalized value of the pure buck control mode on the ordinate, a line having a 45° inclined straight line portion defined by the pure boost control mode and an ideal duty cycle transition value between the pure buck control mode and the buck-boost control mode, and a first limit line defined between a maximum value of the buck duty cycle for the pure boost control mode and a unit duty cycle, and a second limit line defined between a minimum value of the boost duty cycle for the pure boost control mode and the unit duty cycle, and The control device is configured to control a continuous smooth transition along a curve included in a triangle formed by the line of the pure buck control mode, the line of the 45° inclined straight line portion and the first limit line, or a triangle formed by the line of the 45° inclined straight line portion, the second limit line and the line of the pure boost control mode. 9 . The switching voltage regulator of claim 8 , wherein the first periodic reference signal and the second periodic reference signal are triangular sawtooth signals.

10. The switching voltage regulator of claim 8, wherein the controller is a proportional-integral (PI) controller.

11. The switching voltage regulator according to claim 8, further comprising a triangular signal generator configured to generate the first periodic reference signal and the second periodic reference signal, the triangular signal generator include: a ramp generator configured to generate a ramp signal as the first periodic reference signal; An offset generator, generating an offset signal; as well as A boost adding node is coupled to the ramp generator and the offset generator and is configured to generate the second periodic reference signal.

12. The switching voltage regulator according to claim 11, further comprising a boost circuit, wherein the boost circuit include: A first memory element and a second memory element are configured to receive the measurement signal, detect and store a peak value and a valley value, respectively, wherein the peak value and the valley value represent current values ​​at a peak point and a valley point of the measurement signal, respectively; a buck add node coupled to the first memory element and the ramp generator; and The boost add node is also coupled to the second memory element.

13. The switching voltage regulator of claim 8, further comprising a Boolean circuit coupled to the buck modulator and the boost modulator.

14. A control method for a switching voltage regulator, the switching voltage regulator comprising a switching circuit and a control device, the control method include: receiving a measurement signal, the measurement signal representing an output voltage of the switching circuit; generating an error signal, the error signal representing a difference between the measured signal and a nominal signal; generating a single control signal, the single control signal representing an average error of the error signal; comparing the single control signal to a first periodic reference signal; generating a first pulse width modulated signal by a buck modulator; comparing the single control signal to a second periodic reference signal; generating a second pulse width modulated signal by a boost modulator; The first periodic reference signal and the second periodic reference signal have the same period, the same amplitude range, the same phase, and different maximum and minimum values; In the boost control mode, the maximum value of the first periodic reference signal is lower than the single control signal; In the buck control mode, the minimum value of the second periodic reference signal is higher than the single control signal; In a transient control mode between the step-down control mode and the step-up control mode, the maximum value of the first periodic reference signal and the minimum value of the second periodic reference signal are respectively higher and lower than the single control signal; In the buck control mode and the transient control mode, switching the first pulse width modulation signal between an on control value and an off control value; as well as In the boost control mode and the transient control mode, switching the second pulse width modulation signal between the on control value and the off control value, wherein, in the buck-boost state space of the duty cycle, there is a normalized value of the pure boost control mode on the abscissa and a normalized value of the pure buck control mode on the ordinate, a line having a 45° inclined straight line portion defined by the pure boost control mode and an ideal duty cycle transition value between the pure buck control mode and the buck-boost control mode, and a first limit line defined between a maximum value of the buck duty cycle for the pure boost control mode and a unit duty cycle, and a second limit line defined between a minimum value of the boost duty cycle for the pure boost control mode and the unit duty cycle, and The control device is configured to control a continuous smooth transition along a curve included in a triangle formed by the line of the pure buck control mode, the line of the 45° inclined straight line portion and the first limit line, or a triangle formed by the line of the 45° inclined straight line portion, the second limit line and the line of the pure boost control mode.

15. The method of claim 14, generating the single control signal include: The error signal is processed by a proportional-integral (PI) controller.

16. The method according to claim 14, further comprising: include: generating a ramp signal; generating the first periodic reference signal from the ramp signal; as well as The second periodic reference signal is generated by adding an offset signal to the ramp signal.

17. The method according to claim 16, further comprising: include: Respectively detecting a peak value and a valley value, wherein the peak value and the valley value represent current values ​​at a peak point and a valley point of the first periodic reference signal and the second periodic reference signal, respectively; storing a first additional pressure boost amount and a second additional pressure boost amount respectively related to the peak value and the valley value; as well as The first additional voltage boost amount and the second additional voltage boost amount are added to the first periodic reference signal and the second periodic reference signal, respectively.

18. The method according to claim 14, further comprising: include: A current is caused to flow in the switching circuit, the current having a trapezoidal shape in the transient control mode.

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