Negative pressure generation circuit and chip

Abstract

The present invention discloses a negative voltage generation circuit and a chip. The negative voltage generation circuit includes: a first capacitor, one plate of which is connected to a first node for outputting a first voltage signal, and the other plate is connected to a second node for outputting a second voltage signal; a first switch connected to a port for inputting an external power supply voltage and the first node; a second switch, the first node is grounded through the second switch; a third switch, the second node is grounded through the third switch; wherein, the first switch, the second switch and the third switch are based on a switch control signal, such that the second voltage signal periodically switches between a preset negative voltage signal, and the preset negative voltage signal is equal to the negative value of the external power supply voltage. The circuit structure of the negative voltage generation circuit is simple and the response speed is fast. Moreover, the first voltage signal can also be used as the power supply voltage of a circuit module.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and more specifically, to a negative voltage generation circuit and a chip. Background Art

[0002] With the continuous development of science and technology, more and more electronic devices are widely used in people's daily life and work, bringing great convenience to people's daily life and work, and becoming an indispensable important tool for people today.

[0003] The core of an electronic device to achieve various functions is various circuit systems. Based on the functions to be achieved, some circuit systems need to be connected to a floating ground voltage signal, and the floating ground voltage signal switches between 0V and a preset negative voltage.

[0004] In the prior art, a negative voltage charge pump is generally used to generate a floating ground voltage signal that switches between 0V and a preset negative voltage. The structure of the negative voltage charge pump is complex and the response speed is slow. Summary of the Invention

[0005] In view of this, the present application provides a negative voltage generation circuit and a chip, and the solutions are as follows:

[0006] A negative voltage generation circuit, the negative voltage generation circuit includes:

[0007] A first capacitor, one plate of which is connected to a first node for outputting a first voltage signal; the other plate is connected to a second node for outputting a second voltage signal;

[0008] A first switch, connecting a port for inputting an external power supply voltage to the first node;

[0009] A second switch, the first node is grounded through the second switch;

[0010] A third switch, the second node is grounded through the third switch;

[0011] Wherein, the first switch, the second switch and the third switch are based on a switch control signal, so that the second voltage signal periodically switches between 0V and a preset negative voltage signal, and the preset negative voltage signal is equal to the negative value of the external power supply voltage.

[0012] Preferably, in the above negative voltage generation circuit, the first switch is a first transistor, the second switch is a second transistor, and the third switch is a third transistor;

[0013] The gate of the first transistor is connected to a first switch control signal, the source is connected to the external power supply voltage, and the drain is connected to the first node;

[0014] The gate of the second transistor is connected to a second switch control signal, the drain is connected to the first node, and the source is grounded;

[0015] The gate of the third transistor is connected to a third switch control signal, the source is connected to the second node, and the drain is grounded.

[0016] Preferably, in the above negative voltage generation circuit, the first transistor is a PMOS, and the second and third transistors are both NMOS.

[0017] Preferably, in the above negative voltage generation circuit, the first transistor, the second transistor, and the third transistor are respectively connected to a logic controller, and the logic controller is used to generate the switch control signals;

[0018] The logic controller is used to input a first switch control signal to the gate of the first transistor, a second switch control signal to the gate of the second transistor, and a third switch control signal to the gate of the third transistor;

[0019] Among them, the first transistor and the second transistor are not simultaneously turned on, and the second transistor and the third transistor are not simultaneously turned on.

[0020] Preferably, in the above negative voltage generation circuit, the logic controller includes:

[0021] A first output module, which is used to output a second signal and the third switch control signal based on an input first signal;

[0022] A second output module, which is used to output the first switch control signal and the second switch control signal based on the second signal;

[0023] The logic controller has an input terminal for inputting the first signal, a first output terminal for outputting the first switch control signal, a second output terminal for outputting the second switch control signal, and a third output terminal for outputting the third switch control signal.

[0024] Preferably, in the above negative voltage generation circuit, the first output module includes: a first buffer, a first AND gate, a level shifter, a first inverter, a second inverter, and a first OR gate; the first AND gate is a three-input AND gate;

[0025] The input terminal of the first buffer is connected to the input terminal of the logic controller;

[0026] One input terminal of the first AND gate is connected to the output terminal of the first buffer, and its other two input terminals are respectively connected to the third node and the output terminal of the first inverter, and its output terminal is connected to the input terminal of the level shifter;

[0027] The input terminal of the first inverter is connected to the third output terminal of the logic controller;

[0028] One input terminal of the first OR gate is connected to the third node, and the other input terminal is connected to the output terminal of the first buffer, and its output terminal is connected to the input terminal of the second inverter;

[0029] The output terminal of the second inverter is connected to the third output terminal of the logic controller;

[0030] The output terminal of the level shifter is connected to the fourth node for outputting the second signal.

[0031] Preferably, in the above negative pressure generating circuit, the second output module includes: a second OR gate, a second AND gate, a second buffer, and a third buffer; the second AND gate is a two-input AND gate;

[0032] One input terminal of the second OR gate is connected to the fourth node, and the other input terminal is connected to the second output terminal of the logic controller, and its output terminal is connected to the input terminal of the second buffer;

[0033] The output terminal of the second buffer is connected to the first output terminal of the logic controller;

[0034] One input terminal of the second AND gate is connected to the fourth node, and the other input terminal is connected to the first output terminal of the logic controller, and its output terminal is connected to the input terminal of the third buffer;

[0035] The output terminal of the third buffer is connected to the second output terminal of the logic controller.

[0036] Preferably, in the above negative pressure generating circuit, a voltage detection module is connected between the first output module and the second output module, and the voltage detection module is configured to output a fourth signal based on the input third signal and the second signal;

[0037] The second output module outputs the first switch control signal and the second switch control signal based on the input fourth signal.

[0038] Preferably, in the above negative pressure generating circuit, the voltage detection module includes: a third inverter, a fourth inverter, a NOR gate, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a third AND gate;

[0039] The input terminal of the third inverter is used to input the third signal, and its output terminal is connected to one input terminal of the NOR gate;

[0040] The other input terminal of the NOR gate is connected to the fifth node, and its output terminal is connected to the sixth node;

[0041] One input terminal of the third AND gate inputs the second signal, and the other input terminal is connected to the sixth node, and its output terminal is used to output the fourth signal;

[0042] The input terminal of the fourth inverter is used to input the second signal, and its output terminal is connected to the gate of the fourth transistor;

[0043] The source of the fourth transistor is connected to the fifth node, its drain is connected to the drain of the fifth transistor, and its substrate is connected to the source;

[0044] The gate of the fifth transistor inputs the first voltage signal, its source inputs the second voltage signal, and its substrate is connected to the source;

[0045] The gate of the sixth transistor is connected to the sixth node, its source inputs the external power supply voltage, its drain is connected to the fifth node, and its substrate is connected to the source;

[0046] The gate of the seventh transistor is connected to the sixth node, its drain is connected to the fifth node, its source is grounded, and its substrate is connected to the source.

[0047] Preferably, in the above negative voltage generation circuit, the fourth transistor and the sixth transistor are both PMOS, and the fifth transistor and the seventh transistor are both NMOS.

[0048] Preferably, in the above negative voltage generation circuit, the negative voltage generation circuit is used to supply power to the circuit module;

[0049] The first voltage signal is used as the power supply voltage of the circuit module, and the second voltage signal is used as the floating ground voltage signal of the circuit module.

[0050] Preferably, in the above negative voltage generation circuit, the negative voltage generation circuit and the circuit module are integrated on the same chip or are respectively integrated on different chips.

[0051] The present invention also provides a chip, including the negative voltage generation circuit described in any one of the above.

[0052] As can be seen from the above description, in the negative voltage generation circuit and the chip provided by the technical solution of the present invention, the negative voltage generation circuit includes: a first capacitor, one plate of which is connected to a first node for outputting a first voltage signal; the other plate is connected to a second node for outputting a second voltage signal; a first switch connected to the port for inputting an external power supply voltage and the first node; a second switch, the first node is grounded through the second switch; a third switch, the second node is grounded through the third switch; wherein, the first switch, the second switch and the third switch are based on a switch control signal, so that the second voltage signal periodically switches between a preset negative voltage signal, and the preset negative voltage signal is equal to the negative value of the external power supply voltage. The technical solution of the present invention can realize a second voltage signal that periodically switches between a preset negative voltage signal with three switches and one capacitor, and the circuit structure is simple and the response speed is fast. Moreover, the first voltage signal can also be used as the power supply voltage of the circuit module. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained according to the provided drawings.

[0054] The structures, ratios, sizes, etc. shown in the drawings of this specification are only used to cooperate with the content disclosed in the specification for those who are familiar with this technology to understand and read, and are not used to limit the limiting conditions that the present invention can be implemented. Therefore, they do not have a substantial technical meaning. Any modification of the structure, change of the proportional relationship or adjustment of the size should still fall within the scope that can be covered by the technical content disclosed in the present invention without affecting the effects that the present invention can produce and the purposes that can be achieved.

[0055] Figure 1 It is a schematic structural diagram of a conventional negative voltage generation circuit;

[0056] Figure 2 It is a circuit diagram of a conventional negative voltage charge pump;

[0057] Figure 3 It is a circuit diagram of a negative voltage generation circuit provided by an embodiment of the present invention;

[0058] Figure 4 For Figure 3 a schematic diagram of the principle of a switch conduction state and a current flow path in the circuit shown;

[0059] Figure 5 For Figure 3Schematic diagram of another switch conduction state and current flow path in the shown circuit;

[0060] Figure 6 Specific implementation diagram of the negative voltage generation circuit provided by the embodiment of the present invention;

[0061] Figure 7 System circuit block diagram with the negative voltage generation circuit described in the embodiment of the present invention;

[0062] Figure 8 Timing diagram of a switch control signal provided by the embodiment of the present invention;

[0063] Figure 9 Circuit diagram of a logic controller provided by the embodiment of the present invention;

[0064] Figure 10 For Figure 9 Voltage timing diagram of each node in the shown circuit;

[0065] Figure 11 Circuit diagram of another logic controller provided by the embodiment of the present invention;

[0066] Figure 12 Circuit diagram of a voltage detection module provided by the embodiment of the present invention. Detailed implementation

[0067] Next, the embodiments in the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the scope of protection of the present application.

[0068] As Figure 1 shown, Figure 1 is a structural schematic of a conventional negative voltage generation circuit. Figure 1 The shown circuit includes: switch K11, switch K12, switch K13, capacitor C11 and a negative voltage charge pump. The two plates of capacitor C11 are respectively connected to node N11 and node N12. The connection of switch K11 inputs the port of the external power supply voltage VDD_SUPPLY and node N11. Switch K13 is connected to the ground terminal GND (0 potential) and node N12. Switch K12 is connected to the negative voltage charge pump and node N12. Among them, node N11 can provide the power supply voltage VDD for the circuit module, and node N12 can provide the floating ground voltage signal VSS for the circuit module. The floating ground voltage signal VSS can be switched between the negative voltage OUT provided by the negative voltage charge pump and 0V based on the conduction states of the three switches.

[0069] When switch K11 and switch K13 are closed and switch K12 is open, the voltage of node N11 is the external power supply voltage VDD_SUPPLY. At this time, VDD = VDD_SUPPLY, and the circuit module is powered by the external power supply voltage VDD_SUPPLY. Meanwhile, the external power supply voltage VDD_SUPPLY charges capacitor C11. When switch K11 and switch K13 are open and switch K12 is closed, node N12 and the negative voltage charge pump are turned on, VSS = OUT, and the circuit module is supplied with current by the discharge of capacitor C11.

[0070] To achieve the negative voltage OUT required for the floating ground voltage signal VSS, conventional technologies generally need to use a negative voltage charge pump. However, the negative voltage charge pump requires four relatively large-sized MOS switches and also two capacitors as the pump capacitor and the output voltage stabilizing capacitor respectively. Therefore, there are many off-chip devices, the on-chip capacitor area is large, the control logic is complex, the power consumption is high, and the negative voltage charge pump circuit requires a startup time, resulting in a slow system response speed. The structure of the negative voltage charge pump is as Figure 2 shown.

[0071] As Figure 2 shown, Figure 2 is a circuit diagram of a conventional negative voltage charge pump. The negative voltage charge pump includes: switches K14 to K17, capacitor C12, and capacitor C13. The two plates of capacitor C13 are respectively connected to node N13 and node N14. Switch K14 is connected to the ground terminal GND and node N13. Switch K15 is connected to the port for inputting the external power supply voltage VDD_SUPPLY and node N13. Switch K16 is connected to the output terminal VOUT and node N14. Switch K17 is connected to node N14 and the ground terminal GND. The two plates of capacitor C12 are respectively connected to the output terminal VOUT and the ground terminal GND, and the output terminal VOUT outputs the negative voltage OUT.

[0072] Figure 2 The negative voltage charge pump shown requires four switches and two capacitors, so it requires a large area and a large load of logic control current. Meanwhile, when the negative voltage pump starts up, it needs to charge capacitor C12 and capacitor C13. The startup time is related to the sizes of these two capacitors and the magnitude of the startup current. Therefore, the charging of these two capacitors will affect the response speed.

[0073] From the above description, it can be seen that the existing negative voltage generation circuit needs to use a negative voltage charge pump, with many circuit devices, a large area, a complex circuit structure and control method, and strict design requirements for the types of various devices and the selection of the substrate potential of the switches.

[0074] To solve the above problems, the embodiments of the present invention provide a negative voltage generation circuit with a simple circuit structure, simple control, low power consumption, fast response speed, few off-chip devices, a small circuit layout area, and good reliability.

[0075] To make the above objects, features, and advantages of the present application more obvious and understandable, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0076] As Figure 3 shown, Figure 3 The figure is a circuit diagram of a negative voltage generation circuit provided by an embodiment of the present invention. The negative voltage generation circuit includes:

[0077] A first capacitor C1, one plate of the first capacitor C1 is connected to a first node N1, and the first node N1 is used to output a first voltage signal VDD; the other plate is connected to a second node N2, and the second node N2 is used to output a second voltage signal VSS;

[0078] A first switch K1, the first switch K1 is connected to the port for inputting an external power supply voltage VDD_SUPPLY and the first node N1;

[0079] A second switch K2, the first node N1 is grounded through the second switch K2;

[0080] A third switch K3, the second node N2 is grounded through the third switch K3, that is, the second node N2 is connected to the ground terminal GND through the third switch K3;

[0081] Among them, the first switch K1, the second switch K2, and the third switch K3 are based on a switch control signal, so that the second voltage signal VSS periodically switches between 0V and a preset negative voltage signal, and the preset negative voltage signal is equal to the negative value of the external power supply voltage VDD_SUPPLY. Specifically, by controlling the on-off states of the three switches through the switch control signal, the voltage of the second node N2 can be switched between GND (0V) and -VDD_SUPPLY, and the second node N2 can be connected to the ground terminal GND through the third switch K3. In the embodiment of the present invention, the ground terminal GND is the ground of the system.

[0082] When the first switch K1 and the third switch K3 are turned on and the second switch K2 is turned off, the first node N1 is connected to the port for inputting the external power supply voltage VDD_SUPPLY, and the second node N2 is connected to the ground terminal GND, that is, VSS = 0V. The states of each switch are as Figure 4 shown.

[0083] As Figure 4 shown, Figure 4 For Figure 3Schematic diagram of the on - state of a switch and the principle of the current flow path in the shown circuit. At this time, the external power supply voltage VDD_SUPPLY supplies current to the circuit module through the on - state first switch K1 and can charge the first capacitor C1 at the same time. The dotted arrow indicates the current flow path and direction.

[0084] When the second switch K2 is closed, and the first switch K1 and the third switch K3 are open, the first node N1 is connected to the ground terminal GND through the on - state second switch K2, and the second node N2 is disconnected from the ground terminal GND. The states of each switch are as Figure 5 shown.

[0085] As Figure 5 shown, Figure 5 is Figure 3 another schematic diagram of the on - state of a switch and the principle of the current flow path in the shown circuit. The dotted arrow indicates the current flow path and direction. Based on the principle that the voltage across the first capacitor C1 cannot change suddenly, there is the following relationship:

[0086] V C1 = VDD_SUPPLY - 0 = 0 - VSS

[0087] VSS = - VDD_SUPPLY

[0088] Therefore, the second voltage signal VSS becomes the negative value of the external power supply voltage VDD_SUPPLY. Through a simple circuit and switch control method, the negative - voltage function can be realized.

[0089] The voltage change across the first capacitor C1 is:

[0090]

[0091] where I is the discharge current of the first capacitor C1, and t is the negative - voltage working time of VSS. Based on I, t, and the size of the first capacitor C1, the voltage change ΔV across the two poles of the first capacitor C1 can be calculated. C1 .

[0092] By periodically controlling the on - state of the switch, the second voltage signal VSS can be made to vary periodically between - VDD_SUPPLY and 0V. By controlling the current I and the cycle time t well and selecting a preset first capacitor C1, it can be ensured that the current provided by the first capacitor C1 and the voltage change ΔV C1 do not affect the operation of the internal circuit module of the chip.

[0093] The circuit module used in the negative pressure generation circuit according to the embodiment of the present invention can be a circuit module in a fingerprint recognition chip. The first voltage signal VDD can be used as the power supply for the internal circuit module of the chip, the second voltage signal VSS is used as the internal floating ground voltage signal of the chip, the ground terminal GND is the system ground of 0V, and the first capacitor C1 is an off-chip capacitor. Obviously, the negative pressure generation circuit described in the embodiment of the present invention is not limited to being used in the circuit module of the fingerprint recognition chip, and can also be any other circuit module that requires a floating ground voltage signal. The embodiment of the present invention does not specifically limit its usage scenario.

[0094] The negative pressure generation circuit according to the embodiment of the present invention can realize the second voltage signal VSS that periodically switches between 0V and a preset negative pressure signal through three switches and one capacitor. The circuit structure is simple and the control is simple. Moreover, the negative pressure generation circuit does not require a negative pressure charge pump, avoiding the start-up time required by the negative pressure charge pump. The system has a fast response speed, low power consumption, does not require an additional capacitor, so it does not occupy the layout area and does not increase off-chip devices, and the cost is low.

[0095] As Figure 6 shown, Figure 6 is a specific implementation diagram of the negative pressure generation circuit provided by the embodiment of the present invention. Based on Figure 3 the shown manner, the first switch K1 is the first transistor MP, the second switch K2 is the second transistor MN1, and the third switch K3 is the third transistor MN2. It is easy to know that a transistor has a gate, a source, and a drain. As a switching element, the gate is used as the control terminal, and the gate and the source can be equivalently replaced. In this application, the substrate potential of the transistor is selected to ensure that the PN junction cannot be forward-biased.

[0096] The gate of the first transistor MP is connected to the first switch control signal TX1_P, the source is connected to the external power supply voltage VDD_SUPPLY, the drain is connected to the first node, and the substrate is connected to the source. The gate of the second transistor MN1 is connected to the second switch control signal TX1_N, the drain is connected to the first node N1, the source is grounded, that is, the source is connected to the ground terminal GND, and the substrate is connected to the source. The gate of the third transistor MN2 is connected to the third switch control signal TX2, the source is connected to the second node N2, the drain is grounded, that is, the drain is connected to the ground terminal GND, and the substrate is connected to the source.

[0097] In Figure 6In the manner shown, all three switches in the negative pressure generation circuit can be easily implemented by MOS. The first voltage signal VDD switches between VDD_SUPPLY and 0V through the first transistor MP and the second transistor MN1. The second voltage signal VSS is connected to or disconnected from the ground terminal GND through the third transistor MN2. According to the voltage ranges of the first voltage signal VDD and the second voltage signal VSS, the first transistor MP is selected as a PMOS, and the second transistor MN1 and the third transistor MN2 are both NMOS. The substrates of the PMOS and NMOS are both connected to their respective sources. The implementation manners of the three switches can be designed as NMOS or PMOS based on requirements, not limited to Figure 6 the manner shown.

[0098] Through the current direction, the first transistor MP and the third transistor MN2 will conduct the current of the circuit module. In order to reduce the voltage drop (IR drop), the sizes of the first transistor MP and the third transistor MN2 need to be designed appropriately large according to the system requirements to meet the voltage drop requirements of the system. The second transistor MN1 does not need to flow through the operating current of the circuit module, so there is no need to design a too large size to avoid occupying a large layout area. The size of the second transistor MN1 is smaller than the sizes of the first transistor MP and the third transistor MN2.

[0099] As Figure 7 shown, Figure 7 is the system circuit block diagram with the negative pressure generation circuit described in the embodiment of the present invention. Combining Figure 3 、 Figure 6 and Figure 7 , the first transistor MP, the second transistor MN1, and the third transistor MN2 are respectively connected to the logic controller, and the logic controller is used to generate the switch control signals. The logic controller is used to input a first switch control signal TX1_P to the gate of the first transistor MP, a second switch control signal TX1_N to the gate of the second transistor MN1, and a third switch control signal TX2 to the gate of the third transistor MN2.

[0100] Among them, in order to avoid the path from the external power supply voltage VDD_SUPPLY to the ground terminal GND and the path of direct short - circuit between the two plates of the first capacitor C1 during the switch - switching process, it is set that the first transistor MP and the second transistor MN1 are not simultaneously turned on, and the second transistor MN1 and the third transistor MN2 are not simultaneously turned on.

[0101] As Figure 8 shown, Figure 8A timing diagram of a switch control signal provided by an embodiment of the present invention. The first switch control signal TX1_P serves as the gate control voltage of the first transistor MP, the second switch control signal TX1_N serves as the gate control voltage of the second transistor MN1, and the third switch control signal TX2 serves as the gate control voltage of the third transistor MN2.

[0102] As Figure 9 shown, Figure 9 A circuit diagram of a logic controller provided by an embodiment of the present invention. The logic controller includes: a first output module 21, the first output module 21 is configured to output a second signal TX1_IN_LS and the third switch control signal TX2 based on an input first signal TX; a second output module 22, the second output module is configured to output the first switch control signal TX1_P and the second switch control signal TX1_N based on the second signal TX1_IN_LS.

[0103] Wherein, the logic controller has an input terminal for inputting the first signal TX, a first output terminal for outputting the first switch control signal TX1_P, a second output terminal for outputting the second switch control signal TX1_N, and a third output terminal for outputting the third switch control signal TX2.

[0104] As Figure 9 shown, the first output module 21 includes: a first buffer BUF1, a first AND gate AND1, a level shifter LS, a first inverter ISLN1, a second inverter ISLN2, a first OR gate OR1; the first AND gate AND1 is a three-input AND gate.

[0105] Wherein, the input terminal of the first buffer BUF1 is connected to the input terminal of the logic controller to input the first signal TX, and its output terminal outputs a signal TX_D. One input terminal of the first AND gate AND1 is connected to the output terminal of the first buffer BUF1, and its other two input terminals are respectively connected to the third node N3 and the output terminal of the first inverter ISLN1, and its output terminal is connected to the input terminal of the level shifter LS. The input terminal of the first inverter ISLN1 is connected to the third output terminal of the logic controller. One input terminal of the first OR gate OR1 is connected to the third node N3, and the other input terminal is connected to the output terminal of the first buffer BUF1, and its output terminal is connected to the input terminal of the second inverter ISLN2. The output terminal of the second inverter ISLN2 is connected to the third output terminal of the logic controller. The output terminal of the level shifter LS is connected to the fourth node N4 for outputting the second signal TX1_IN_LS.

[0106] As Figure 9As shown, the second output module 22 includes: a second OR gate OR2, a second AND gate AND2, a second buffer BUF2, and a third buffer BUF3; the second AND gate AND2 is a two-input AND gate.

[0107] Among them, one input terminal of the second OR gate OR2 is connected to the fourth node N4, and the other input terminal is connected to the second output terminal of the logic controller, and its output terminal is connected to the input terminal of the second buffer BUF2. The output terminal of the second buffer BUF2 is connected to the first output terminal of the logic controller. One input terminal of the second AND gate AND2 is connected to the fourth node N4, and the other input terminal is connected to the first output terminal of the logic controller, and its output terminal is connected to the input terminal of the third buffer BUF3. The output terminal of the third buffer BUF3 is connected to the second output terminal of the logic controller.

[0108] Based on Figure 9 the logic controller shown, it is capable of generating a timing diagram as Figure 8 shown, and controlling Figure 6 the floating ground voltage signal of the circuit output VSS to switch periodically between 0V and -VDD_SUPPLY. The logic controller is controlled by a first signal TX, and the first signal TX can be provided by a digital logic circuit. It is a square wave signal with a period of T and a duty cycle of 50%. It should be noted that the duty cycle of the square wave signal in this application can be limited based on requirements and is not limited to 50%.

[0109] As Figure 10 shown, Figure 10 for Figure 9 the voltage timing diagram of each node in the circuit shown, it can generate the logic control signals required by the system, avoid the simultaneous conduction of the first transistor MP and the second transistor MN1, and avoid the simultaneous conduction of the second transistor MN1 and the third transistor MN2. The second voltage signal VSS is realized to switch periodically between 0V and -VDD_SUPPLY.

[0110] Through the above logic controller and voltage timing, the negative voltage required for the second voltage signal VSS is realized through a simple circuit structure and control logic. Compared with the traditional negative voltage charge pump circuit,

[0111] the circuit structure is simple, saving layout area, reducing circuit power consumption, reducing system response time, and the circuit is extremely simple.

[0112] As Figure 11 shown, Figure 11 is the circuit diagram of another logic controller provided by an embodiment of the present invention. Based on Figure 9 the manner shown, Figure 11In the shown manner, a voltage detection module is connected between the first output module 21 and the second output module 22. The voltage detection module is configured to output a fourth signal TX1 based on the input third signal POR_IN and the second signal TX1_IN_LS. The second output module 22 outputs the first switch control signal TX1_P and the second switch control signal TX1_N based on the input fourth signal TX1.

[0113] As Figure 12 shown, Figure 12 is a circuit diagram of a voltage detection module provided by an embodiment of the present invention. The voltage detection module includes: a third inverter ISLN3, a fourth inverter ISLN4, a NOR gate NOR, a fourth transistor MP41, a fifth transistor MN51, a sixth transistor MP62, a seventh transistor MN72, and a third AND gate AND3. Among them, both the fourth transistor MP41 and the sixth transistor MP62 are PMOS, and both the fifth transistor MN51 and the seventh transistor MN72 are NMOS.

[0114] The input terminal of the third inverter ISLN3 is configured to input the third signal POR_IN, and its output terminal is connected to one input terminal of the NOR gate NOR. The other input terminal of the NOR gate NOR is connected to the fifth node N5, and its output terminal is connected to the sixth node N6. One input terminal of the third AND gate AND3 inputs the second signal TX1_IN_LS, and the other input terminal is connected to the sixth node N6. Its output terminal is configured to output the fourth signal TX1. The input terminal of the fourth inverter ISLN4 is configured to input the second signal TX1_IN_LS, and its output terminal is connected to the gate of the fourth transistor MP41.

[0115] The source of the fourth transistor MP41 is connected to the fifth node N5, its drain is connected to the drain of the fifth transistor MN51, and its substrate is connected to the source. The gate of the fifth transistor MN51 inputs the first voltage signal VDD, its source inputs the second voltage signal VSS, and its substrate is connected to the source. The gate of the sixth transistor MP62 is connected to the sixth node N6, its source inputs the external power supply voltage VDD_SUPPLY, its drain is connected to the fifth node N5, and its substrate is connected to the source. The gate of the seventh transistor MN72 is connected to the sixth node N6, its drain is connected to the fifth node N5, its source is grounded to GND, and its substrate is connected to the source.

[0116] By Figure 12 the shown voltage detection module, it can be ensured that when the external power supply voltage VDD_SUPPLY is powered on, the internal circuit module can be normally powered on through the first voltage signal VDD, and the circuit structure of the voltage detection module is simple.

[0117] Combined with Figure 6 、 Figure 11 and Figure 12 As shown, the third signal POR_IN is a reset release signal for detecting the external power supply voltage VDD_SUPPLY. When the third signal POR_IN is powered on, the third signal POR_IN is at a low level, the sixth transistor MP62 is turned on, the drain voltage of the fourth transistor MP41 is VDD_SUPPLY, TX1_IN and TX are at low levels, TX1 is at a low level, TX2 is at a high level, the first transistor MP and the third transistor MN2 are turned on, the first node N1 is connected to the external power supply voltage VDD_SUPPLY, the second node N2 is connected to the ground terminal GND, and the first voltage signal VDD starts to rise. When the first voltage signal VDD rises to a high enough level, the fifth transistor MN51 is turned on, and the fourth transistor MP41 is controlled by TX1_IN_LS and is also turned on at this time. The voltage at the drain (the fifth node N5) of the fourth transistor MP41 gradually decreases and approaches VSS. After the third signal POR_IN is reset and released, it is at a high level, the output terminal (the sixth node N6) of the NOR gate is at a high level, and the fourth signal TX1 is completely controlled by the second signal TX1_IN_LS.

[0118] By adjusting the sizes of the second transistor MN1, the third transistor MN2, the fourth transistor MP41, and the sixth transistor MP62, the detection voltage of the first voltage signal VDD can be adjusted to ensure that the entire system is powered normally when the external power supply voltage VDD_SUPPLY is powered on.

[0119] As described above, the negative voltage generation circuit according to the embodiment of the present invention is used to supply power to the circuit module. The first voltage signal VDD is used as the power supply voltage of the circuit module, and the second voltage signal VSS is used as the floating ground voltage signal of the circuit module. Among them, the negative voltage generation circuit and the circuit module are integrated on the same chip or are separately integrated on different chips.

[0120] Based on the above embodiment, another embodiment of the present invention further provides a chip, which includes the negative voltage generation circuit as described in the above embodiment. The chip adopts the above negative voltage generation circuit, and has a simple circuit structure, low power consumption, low cost, and fast response speed.

[0121] In this specification, the various embodiments are described in a progressive, or parallel, or a combination of progressive and parallel manners. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the various embodiments can be referred to each other. For the chip disclosed in the embodiment, since it corresponds to the negative voltage generation circuit disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the corresponding part description of the negative voltage generation circuit.

[0122] It should be noted that in the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the present invention. When a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be intermediate components present at the same time.

[0123] It should also be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variation thereof is intended to cover non-exclusive inclusion, so that an article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the article or device comprising the above elements.

[0124] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to these embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A negative pressure generating circuit, characterized in that, The negative voltage generation circuit includes: A first capacitor, one plate of which is connected to a first node for outputting a first voltage signal; the other plate is connected to a second node for outputting a second voltage signal; A first switch, connecting the port for inputting an external power supply voltage to the first node; A second switch, the first node being grounded through the second switch; A third switch, the second node being grounded through the third switch; Wherein, the first switch, the second switch and the third switch are based on a switch control signal, such that the second voltage signal periodically switches between 0V and a preset negative voltage signal, and the preset negative voltage signal is equal to the negative value of the external power supply voltage; The negative voltage generation circuit is used to supply power to a circuit module; the first voltage signal is used as the power supply voltage of the circuit module, and the second voltage signal is used as the floating ground voltage signal of the circuit module; When the first switch and the third switch are turned on and the second switch is turned off, the first node is connected to the port for inputting the external power supply voltage, the second node is connected to the ground terminal, and the external power supply voltage supplies current to the circuit module through the turned-on first switch, and the second voltage signal is 0V; When the second switch is closed and the first switch and the third switch are turned off, the first node is connected to the ground terminal through the turned-on second switch, the second node is disconnected from the ground terminal, and the second voltage signal becomes the negative value of the external power supply voltage.

2. The negative pressure generating circuit according to claim 1, characterized in that, The first switch is a first transistor, the second switch is a second transistor, and the third switch is a third transistor; The gate of the first transistor is connected to a first switch control signal, the source is connected to the external power supply voltage, and the drain is connected to the first node; The gate of the second transistor is connected to a second switch control signal, the drain is connected to the first node, and the source is grounded; The gate of the third transistor is connected to a third switch control signal, the source is connected to the second node, and the drain is grounded.

3. The negative pressure generating circuit according to claim 2, characterized in that, The first transistor is a PMOS, and the second transistor and the third transistor are both NMOS.

4. The negative pressure generating circuit according to claim 2, characterized in that, The first transistor, the second transistor and the third transistor are respectively connected to a logic controller, and the logic controller is used to generate the switch control signal; The logic controller is used to input a first switch control signal to the gate of the first transistor, input a second switch control signal to the gate of the second transistor, and input a third switch control signal to the gate of the third transistor; Wherein, the first transistor and the second transistor are not turned on simultaneously, and the second transistor and the third transistor are not turned on simultaneously.

5. The negative pressure generating circuit according to claim 4, characterized in that, The logic controller includes: A first output module, which is used to output a second signal and the third switch control signal based on an input first signal; A second output module, which is used to output the first switch control signal and the second switch control signal based on the second signal; The logic controller has an input terminal for inputting the first signal, a first output terminal for outputting the first switch control signal, a second output terminal for outputting the second switch control signal, and a third output terminal for outputting the third switch control signal.

6. The negative pressure generating circuit according to claim 5, characterized in that, The first output module includes: a first buffer, a first AND gate, a level shifter, a first inverter, a second inverter, and a first OR gate; the first AND gate is a three-input AND gate; The input terminal of the first buffer is connected to the input terminal of the logic controller; One input terminal of the first AND gate is connected to the output terminal of the first buffer, and its other two input terminals are respectively connected to a third node and the output terminal of the first inverter, and its output terminal is connected to the input terminal of the level shifter; The input terminal of the first inverter is connected to the third output terminal of the logic controller; One input terminal of the first OR gate is connected to the third node, and the other input terminal is connected to the output terminal of the first buffer, and its output terminal is connected to the input terminal of the second inverter; The output terminal of the second inverter is connected to the third output terminal of the logic controller; The output terminal of the level shifter is connected to a fourth node for outputting the second signal.

7. The negative pressure generating circuit according to claim 5, characterized in that, The second output module includes: a second OR gate, a second AND gate, a second buffer, and a third buffer; the second AND gate is a two-input AND gate; One input terminal of the second OR gate is connected to the fourth node, and the other input terminal is connected to the second output terminal of the logic controller, and its output terminal is connected to the input terminal of the second buffer; The output terminal of the second buffer is connected to the first output terminal of the logic controller; One input terminal of the second AND gate is connected to the fourth node, and the other input terminal is connected to the first output terminal of the logic controller, and its output terminal is connected to the input terminal of the third buffer; The output terminal of the third buffer is connected to the second output terminal of the logic controller.

8. The negative pressure generating circuit according to claim 5, wherein, A voltage detection module is connected between the first output module and the second output module, and the voltage detection module is configured to output a fourth signal based on the input third signal and the second signal; The second output module outputs the first switch control signal and the second switch control signal based on the input fourth signal.

9. The negative pressure generating circuit according to claim 8, wherein, The voltage detection module includes: a third inverter, a fourth inverter, a NOR gate, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a third AND gate; The input terminal of the third inverter is used for inputting the third signal, and its output terminal is connected to one input terminal of the NOR gate; The other input terminal of the NOR gate is connected to a fifth node, and its output terminal is connected to a sixth node; One input terminal of the third AND gate inputs the second signal, and the other input terminal is connected to the sixth node, and its output terminal is used for outputting the fourth signal; The input terminal of the fourth inverter is used for inputting the second signal, and its output terminal is connected to the gate of the fourth transistor; The source of the fourth transistor is connected to the fifth node, its drain is connected to the drain of the fifth transistor, and its substrate is connected to the source; The gate of the fifth transistor receives the first voltage signal, its source receives the second voltage signal, and its substrate is connected to the source. The gate of the sixth transistor is connected to the sixth node, its source receives the external power supply voltage, its drain is connected to the fifth node, and its substrate is connected to the source. The gate of the seventh transistor is connected to the sixth node, its drain is connected to the fifth node, its source is grounded, and its substrate is connected to the source.

10. The negative pressure generating circuit according to claim 9, wherein, The fourth transistor and the sixth transistor are both PMOS, and the fifth transistor and the seventh transistor are both NMOS.

11. The negative pressure generating circuit according to claim 10, wherein, The negative voltage generation circuit and the circuit module are integrated on the same chip or are separately integrated on different chips.

12. A chip, wherein, It includes the negative voltage generation circuit according to any one of claims 1-11.

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