Method of operating a memory controller, memory controller, and storage device

Abstract

An operating method of a memory controller updates metadata using log data for a short time during a boot operation and maintains reliability of the updated metadata. The operating method of the memory controller includes loading the metadata into a sub-region of a buffer memory, updating the metadata using log data in a state in which an error correction code (ECC) function of the memory controller for the sub-region is disabled, generating first parity data of data stored in the first sub-region, and enabling the ECC function of the first sub-region after the first parity data is generated.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0101481, filed with the Korean Intellectual Property Office on August 20, 2019, the contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a memory controller, a method of operating the memory controller, and a storage device coupled to the memory controller. Background Technology

[0004] Flash memory is a non-volatile memory that retains stored data even when its power supply is interrupted. Recently, flash memory storage devices, including embedded multimedia cards (eMMC), universal flash storage (UFS), solid-state drives (SSDs), and memory cards, have been widely implemented for many applications, including storing or moving large amounts of data.

[0005] Additionally, some SSD products have a requirement for open time in the event of a sudden power outage (SPO). For example, when an SPO occurs, during the boot process, the SSD product must load metadata stored in main memory (e.g., NAND flash memory) into buffer memory (e.g., DRAM) and update the metadata using journaling data within the open time.

[0006] However, as the capacity of SSD products increases, the size of metadata / log data also increases. Therefore, updating metadata within a predetermined disconnection period becomes difficult.

[0007] Furthermore, some SSD products incorporate Error Correction Code (ECC) functionality into the cache memory to improve reliability. When using ECC, the time required to write to the cache memory increases. Therefore, updating metadata within predetermined disconnection times becomes even more difficult. Summary of the Invention

[0008] This disclosure provides a method for operating a memory controller to update metadata using log data during a short period of time suitable for boot operations, and to maintain the reliability of the updated metadata.

[0009] This disclosure also provides a memory controller for using log data to update metadata for a short period of time during boot operations and maintaining the reliability of the updated metadata.

[0010] This disclosure also provides a storage device including a memory controller.

[0011] However, the aspects of this disclosure are not limited to those set forth herein. These and other aspects of the disclosure will become more apparent to those skilled in the art upon reference to the specific embodiments of the disclosure given below.

[0012] According to an aspect of this disclosure, a method of operating a memory controller is provided, comprising: loading metadata into a plurality of sub-regions of a buffer memory; updating the metadata using log data in a state where error correction code (ECC) functionality of the memory controller is disabled for each of the plurality of sub-regions; generating first parity data of data stored in a first sub-region among the plurality of sub-regions; and enabling ECC functionality of the first sub-region after generating the first parity data.

[0013] According to an aspect of this disclosure, a method for operating a memory controller is provided, comprising: loading metadata into a plurality of sub-regions of the buffer memory during a sudden power outage (SPO) disconnection time; updating the metadata using log data in a state where the error correction code (ECC) function of the memory controller is disabled for each of the plurality of sub-regions; and, as a background operation after the SPO disconnection time, generating parity data of data stored separately in the plurality of sub-regions arranged in the buffer memory.

[0014] According to an aspect of this disclosure, a memory controller for controlling a buffer memory is provided, comprising: a log controller configured to load metadata into a plurality of sub-regions of the buffer memory and update the metadata using log data; an error correction code (ECC) controller configured to selectively enable and disable the ECC function of the memory controller for each of the plurality of sub-regions; and a parity data generator configured to generate parity data for data stored in each of the plurality of sub-regions, wherein, when the log controller uses the log data to update the metadata, the ECC controller is configured to disable the ECC function for all sub-regions of the plurality of sub-regions, and the ECC controller is configured to enable the ECC function only for the processed sub-regions of the plurality of sub-regions for which the parity data generator has generated parity data.

[0015] According to an aspect of this disclosure, a storage device is provided, comprising: a main memory, a buffer memory including multiple sub-regions, and a memory controller configured to load metadata stored in the main memory into the multiple sub-regions of the buffer memory after a sudden power failure (SPO) of the buffer memory, and to update the metadata using log data based on whether the memory controller selectively enables or disables ECC functionality for each of the multiple sub-regions during the SPO of the buffer memory. Attached Figure Description

[0016] The above and other aspects and features of this disclosure will become more apparent from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, in which:

[0017] Figure 1 This is a block diagram illustrating a storage device according to an embodiment of the present disclosure;

[0018] Figure 2 It is shown in the figure. Figure 1 A conceptual diagram of a second memory device;

[0019] Figure 3 It is shown in the figure. Figure 1 A block diagram of the ECC engine;

[0020] Figure 4 This is a flowchart illustrating an operation method of a memory controller according to an embodiment of the present disclosure;

[0021] Figure 5 This is a diagram explaining the replay operation when ECC is disabled;

[0022] Figure 6 This is a diagram explaining the playback operation when ECC is enabled;

[0023] Figure 7 This is a flowchart illustrating a method of operating a memory controller according to an embodiment of the present disclosure;

[0024] Figure 8 This is a flowchart illustrating a method of operating a memory controller according to an embodiment of the present disclosure;

[0025] Figure 9 This is a diagram illustrating a method of operating a memory controller according to an embodiment of the present disclosure;

[0026] Figure 10 This is a diagram illustrating a method of operating a memory controller according to an embodiment of the present disclosure; and

[0027] Figure 11This is a diagram illustrating a method of operating a memory controller according to an embodiment of the present disclosure. Detailed Implementation

[0028] In the following description, various embodiments of the present disclosure will be illustrated with reference to the accompanying drawings.

[0029] Figure 1 This is a block diagram illustrating a storage device according to an embodiment of the present disclosure. Figure 2 It is shown in the figure. Figure 1 A conceptual diagram of a second memory device. Figure 3 It is shown in the figure. Figure 1 A block diagram of the ECC engine.

[0030] First, refer to Figure 1 The storage device according to embodiments of the present disclosure includes a first memory device 100, a second memory device 300, and a memory controller 200. The first memory device 100 and the second memory device 300 are exemplary, and the storage device may include additional memory in addition to the first memory device 100 and the second memory device 300.

[0031] Storage devices can be implemented as, but are not limited to, smart cards, secure digital cards (SD cards), multimedia cards (MMC), embedded MMC (eMMC), embedded multi-chip package (eMCP), perfect page NAND (PPN), universal flash storage (UFS), universal serial bus (USB) flash drive, solid-state drive (SSD), or embedded SSD (eSSD).

[0032] Memory controller 200 controls the operation of first memory device 100 and second memory device 300. Memory controller 200 may include at least one microprocessor, central processing unit, or other control unit configured to control the operation of the memory controller. The memory controller may be configured to control its operation based on hardware or software configuration when executing computer-executable code stored in memory controller 200. Memory controller 200 may analyze commands provided by a host connected to the storage devices and control the operation of first memory device 100 and second memory device 300 based on the analysis results. The host may include any electronic device for storing and accessing data stored in the storage devices, such as a personal computer, cellular phone, television, consumer electronics device, etc.

[0033] The first memory device 100 may be main memory, such as a device based on non-volatile memory (e.g., NAND flash memory), but is not limited thereto. The first memory device 100 includes a user data area in which user data is stored, and a metadata area in which metadata and log data are stored.

[0034] Metadata may include, but is not limited to, location information of user data (logical address, physical address, etc.), the number of valid pages included in a memory block as a valid page in the memory block, etc.

[0035] Log data is data that records the history of changes to metadata. For example, when unexpected problems such as sudden power outages (SPO) occur, the state before the SPO can be recovered or essentially restored by referring to log data.

[0036] The second memory device 300 may be a buffer memory, such as a device based on volatile memory (e.g., DRAM and SRAM), but is not limited thereto. Because the time spent programming / reading data in the first memory device 100 is longer than the time spent communicating with the host, data processing can be accelerated by using the second memory device 300, which has fast write / read times.

[0037] For example, when the host issues a command to store user data, the memory controller 200 generates metadata related to the command and stores the metadata in the metadata area of ​​the second memory device 300. Alternatively, the memory controller 200 can update the command-related metadata stored in the metadata area of ​​the second memory device 300. The memory controller 200 generates a history of metadata changes (generation / removal / update, etc.) as log data.

[0038] When log data continues to be generated and the total size of the log data reaches a predetermined size, the memory controller 200 transfers the entire log data to the first memory device 100 (i.e., the metadata area in the first memory device 100).

[0039] The memory controller 200 can also transmit metadata stored in the second memory device 300 to the first memory device 100 according to preset logic / scheduling. Because the size of the metadata is larger than the size of the log data, it may take a relatively long time to transmit all the metadata to the first memory device 100. Therefore, for example, whenever log data is transmitted to the first memory device 100, some of the metadata may be transmitted to the first memory device 100 and written to it. Therefore, during the runtime state of the storage device, some of the metadata stored in the first memory device 100 may be up-to-date, while other parts of the metadata may not be up-to-date.

[0040] When a power failure signal is received from the host, the memory controller 200 transmits all metadata and log data to the first memory device 100 to update the metadata / log data stored in the first memory device 100.

[0041] When booting the storage device, the memory controller 200 loads metadata stored in the first storage device 100 into the second storage device 300. Additionally, the memory controller 200 uses log data to update (i.e., replay) the metadata.

[0042] The memory controller 200 includes an ECC engine 210. The ECC engine 210 performs encoding operations on user data and / or metadata to generate parity data or parity bits. The ECC engine 210 uses the parity data to perform error correction operations on the read data.

[0043] The memory controller 200 also includes a log controller 220. The log controller 220 generates log data that records the history of changes to metadata.

[0044] Metadata can be loaded into multiple sub-regions 310, 320 and 330 of the second storage device 300, and the metadata can be updated (replayed) using log data.

[0045] refer to Figure 2 The metadata area of ​​the second memory device 300 may include first sub-regions 310, 320 and 330 and a second region 390.

[0046] The first sub-regions 310, 320, and 330 may include any number of sub-regions, and the descriptions of sub-regions 310, 320, and 330 are merely examples. For each of the sub-regions 310, 320, and 330, ECC functionality can be enabled or disabled. That is, under the control of the ECC engine 210, ECC functionality can be selectively enabled or disabled for the data stored in each of the sub-regions 310, 320, and 330. The first regions 310, 320, and 330 are the regions where metadata is loaded / stored and replayed using log data.

[0047] The second region 390 is the region in which the ECC function remains enabled. That is, under the control of the ECC engine 210, the ECC function can be kept enabled for data stored in the second region 390. The second region 390 may be a region allocated for firmware operation. The descriptions of sub-regions 310, 320, and 330, and the second region 390, are merely exemplary to distinguish the sub-regions 310, 320, and 330 from the second region 390. The second memory device may include any number of regions or sub-regions, including at least one region or sub-region in which the ECC function can be selectively enabled or disabled, and at least one region or sub-region in which the ECC function can be selectively maintained in an enabled state (i.e., the ECC function is enabled).

[0048] refer to Figure 3 The ECC engine 210 includes an ECC controller 211, an ECC range controller 212, an ECC enable / disable controller 213, a parity generator 214, etc.

[0049] ECC controller 211 manages operations related to error correction and controls ECC range controller 212, ECC on / off controller 213, parity generator 214, etc.

[0050] ECC range controller 212 divides and manages the second memory device 300 into multiple regions 310, 320, 330, and 390. Specifically, ECC range controller 212 divides and manages the sub-regions 310, 320, and 330, as well as the second region 390. ECC range controller 212 can determine or adjust the size of each of the sub-regions 310, 320, 330, and 390.

[0051] The ECC enable / disable controller 213 selectively enables / disables the ECC function for each of the sub-regions 310, 320, and 330 of the second memory device 300. For example, the ECC function of all sub-regions 310, 320, and 330 can be disabled. Alternatively, the ECC function of only some of the sub-regions 310, 320, and 330 can be selectively disabled.

[0052] Specifically, during the boot process (especially when the log controller 220 uses log data to update metadata), the ECC enable / disable controller 213 disables the ECC functionality of all sub-regions 310, 320, and 330.

[0053] Following the boot operation, the ECC enable / disable controller 213 selectively enables the ECC functionality of sub-regions 310, 320, and 330. More specifically, after the boot operation, parity data is generated for each of sub-regions 310, 320, and 330 (by the parity generator 214), and the ECC enable / disable controller 213 enables the ECC functionality for the sub-regions 310, 320, and 330 for which parity data has been generated.

[0054] On the other hand, if necessary, during the boot process (especially when the log controller 220 uses log data to update metadata), ECC functionality can be enabled for some sub-regions (e.g., sub-region 310), and ECC functionality can be disabled for the remaining sub-regions (e.g., sub-regions 320 and 330). In this configuration, after the boot process, parity data can be generated only for the sub-regions where ECC functionality is disabled (e.g., sub-regions 320 and 330).

[0055] Parity generator 214 generates parity data based on the data stored in each of the sub-regions 310, 320, and 330. Parity generator 214 can be implemented as hardware logic, but is not limited thereto.

[0056] Parity generator 214 can generate parity data in a predetermined order—for example, in the order of first sub-region 310, second sub-region 320, ..., nth sub-region 330—but this disclosure is not limited thereto.

[0057] Alternatively, parity generator 214 may generate parity data based on parity data generation requests (or access requests for sub-region 310) of data stored in a sub-region of the host (e.g., sub-region 310), but this disclosure is not limited thereto.

[0058] Reference Figures 4 to 11 A detailed description is provided of how to enable / disable the ECC function.

[0059] Figure 4 This is a flowchart illustrating an operation method of a memory controller according to an embodiment of the present disclosure. Figure 5 This is a diagram explaining the playback operation when ECC is disabled. Figure 6 This is a diagram explaining the playback operation when ECC is enabled.

[0060] First, refer to Figure 4When the storage device is booted, metadata is loaded into sub-regions 310, 320, and 330 (i.e., buffer memory) of the second storage device 300 (step S10). The metadata is updated (replayed) using log data while the ECC function of sub-regions 310, 320, and 330 is disabled (step S20).

[0061] For example, such as Figure 5 As shown, when the storage device is booted, each metadata 311, 312, 313, ... through 319 is loaded into the second storage device 300. For example, each metadata 311, 312, 313, ... through 319 can be a physical page address (PPN), but the metadata is not limited to this. For example, the size of each metadata can be 6 bytes, but the size of the metadata is not limited to this.

[0062] Here, if the log data includes "the physical address PPN2 described in metadata 312 will be changed to a new physical address PPN2N", then the existing physical address PPN2 should be changed to the new physical address PPN2N at boot time based on the log data. As mentioned above, updating (or modifying) metadata based on what is described in the log data is called "replay".

[0063] In a first embodiment of this disclosure, when performing a playback operation, a normal write operation is used instead of a read-modify-write (RMW) operation while the ECC function is disabled (i.e., off or disabled). The RMW operation provides to read previously stored data, compare the read data with the data to be written, and only write the parts of the read data and the data to be written that differ from each other. For example, if the read data is 1000 and the data to be written is 1001, only the last bit (value 1) is written. Unlike the RMW operation, the normal write operation provides to write the data immediately to be written without a read / compare operation. The normal write operation is faster than the RMW operation because there is no separate read / compare operation compared to the RMW operation.

[0064] refer to Figure 6 This will describe the situation where ECC is enabled (i.e., enabled) during playback. For example, in the above example, if the log data includes "The physical address PPN2 described in metadata 312 will be changed to a new physical address PPN2N", then the existing physical address PPN2 should be changed to the new physical address PPN2N based on the log data at boot or startup time.

[0065] When ECC is enabled, parity data is generated for the metadata. In this document, the managed size of the metadata can differ from the managed size of the data used to generate the parity data. For example, as mentioned above, the managed size of the metadata can be 6 bytes, and the managed size of the data used to generate the parity data can be 8 bytes.

[0066] Additionally, when ECC is enabled, the RMW operation can be used to perform playback.

[0067] Therefore, in Figure 6 In the example, two write operations are required to change to the new physical address PPN2N. This is because a portion 3121 of the physical address PPN2N can be adjusted by changing data 311a, and another portion 3122 of the physical address PPN2N can be adjusted by changing data 312a. As described above, if the management size of the data used to generate parity data is 8 bytes, then physical address PPN1 (i.e., 6 bytes) and a portion of physical address PPN2 (i.e., 2 bytes) are read, the portion to be changed (i.e., a portion of physical address PPN2) is changed to a portion 3121 of physical address PPN2N, and parity data is generated by using physical address PPN1 and the changed portion 3121 of physical address PPN2N. Similarly, another part of physical address PPN2 (i.e., 4 bytes) and a part of physical address PPN3 (i.e., 4 bytes) are read, and the part to be changed (i.e., another part of physical address PPN2) is changed to another part of physical address PPN2N 3122, and parity data is generated by using another part of physical address PPN2N 3122 and a part of physical address PPN3.

[0068] Therefore, when ECC is enabled, it may take a long time to update metadata based on log data. In other words, the time required for booting or completing startup may be excessively long.

[0069] Therefore, in the first embodiment, when performing a playback operation, a normal write operation is used instead of an RMW operation while the ECC function is disabled. This minimizes the time required for the playback operation during boot time.

[0070] Figure 7 This is a flowchart illustrating a method of operating a memory controller according to an embodiment of the present disclosure.

[0071] Because it is executed while ECC functionality is disabled. Figure 4 The playback operation, so after completion Figure 4 Parity check data is generated after the playback operation.

[0072] Parity check data can be generated in a predetermined order. For example, it can be generated in the order of the first sub-region 310 (see...). Figure 2 ), second sub-region 320 (see Figure 2 ), ..., subregion 330 (see Figure 2 This is used to generate parity data. For simplicity, in... Figure 2 The diagram shows that the first sub-region 310, the second sub-region 320, ..., and the nth sub-region 330 are arranged from top to bottom. Therefore, it can be understood that parity check data is generated from top to bottom, but this disclosure is not limited thereto.

[0073] refer to Figure 7 First parity check data is generated and stored in the first sub-region 310 (step S31). Then, the ECC function of the first sub-region 310 is turned on (step S32).

[0074] In addition, second parity data can be generated from the data stored in the second sub-region 320. The ECC function of the second sub-region 320 can also be enabled.

[0075] Subsequently, the nth parity check data stored in the nth sub-region 330 is generated (step S33). The ECC function of the nth sub-region is changed to the enabled state (step S34).

[0076] In other words, after parity data is generated for each of sub-regions 310, 320, and 330, the ECC function is turned on for those sub-regions 310, 320, and 330 for which parity data has been generated. In this way, the host can access sub-regions 310, 320, and 330 where the ECC function has been turned on without the risk of data corruption.

[0077] In the replacement configuration, after generating parity data for the data stored in all sub-regions 310, 320, and 330, the ECC function is switched to the enabled state for all sub-regions 310, 320, and 330. In this configuration, first parity data for the data stored in the first sub-region 310 is generated, second parity data for the data stored in the second sub-region 320 is generated, and nth parity data for the data stored in the nth sub-region 330 is generated, while simultaneously enabling the ECC function for the first sub-region 310 to the nth sub-region 330.

[0078] Suppose a host needs to access a second sub-region 320. According to an embodiment, after parity data has been generated for the first sub-region 310 and the second sub-region 320, the host can also access the second sub-region 320 (even if parity data has not been generated for the third sub-region 330). However, in a comparative example, the host can access the second sub-region 320 only after parity data has been generated for all sub-regions 310, 320, and 330. Therefore, according to an embodiment of this disclosure where the ECC function for a particular sub-region is changed to an enabled state after parity data for that sub-region has been generated, the host can have relatively faster access to sub-regions (e.g., 320) for which parity data has already been generated.

[0079] The parity data generated for each of sub-regions 310, 320, and 330 can be performed as a background operation.

[0080] Furthermore, parity data for each of sub-regions 310, 320, and 330 can be generated via hardware logic. When parity data generation is performed via hardware logic, it is faster and more accurate compared to generating parity data in software.

[0081] Additional benefits and advantages can be obtained by generating parity data for each of sub-regions 310, 320 and 330 and enabling ECC functionality for each of sub-regions 310, 320 and 330.

[0082] For example, by using the metadata of a subregion where ECC functionality is enabled, the consistency of the metadata of a subregion where ECC functionality is disabled can be easily determined. As mentioned above, metadata includes location information as well as information such as the number of valid pages and identifiers or indications of which pages are valid. For example, the metadata of a subregion where ECC functionality is enabled may include the information "five valid pages in the first storage block". However, when examining the metadata of a subregion where ECC functionality is disabled, if only four valid pages of the first storage block exist, then the metadata of the subregion where ECC functionality is disabled is unreliable.

[0083] Figure 8 This is a flowchart illustrating a method of operating a memory controller according to an embodiment of the present disclosure.

[0084] Because it is executed while ECC functionality is disabled. Figure 4 The playback operation, so after completion Figure 4 Parity check data is generated after the playback operation.

[0085] refer to Figure 8 The host can query whether there is an access request for any of the sub-regions 310, 320, and 330 of the second memory device 300 (step S40). If no access request exists (No), parity data for the data stored in the next sub-region is generated according to a predetermined order (step S50). If an access request exists (Yes), parity data for the data already stored in the sub-region for which an access request has been received is generated (step S60).

[0086] Subsequently, the ECC function of the sub-region for which parity data has been generated is changed to the enabled state (step S70).

[0087] Then, it can be determined whether parity data for each of the data stored in all sub-regions has been generated (step S80). If parity data for each of the data stored in all sub-regions has not been generated (No), the process returns to step S40 and repeats the process for each sub-region. If parity data for each of the data stored in all sub-regions has been generated (Yes), the process ends.

[0088] For example, the first parity data for generating data stored in the first sub-region 310 can be initialized.

[0089] If no access request from the host occurs during the generation of the first parity data or until the generation of the first parity data is completed, the second parity data of the data stored in the second sub-region 320 is generated in a predetermined order (see steps S40 and S50).

[0090] On the other hand, during the generation of the first parity data or when the generation of the first parity data is completed, an access request for the nth sub-region 330 may occur from the host. In this case, instead of the predetermined order, the nth parity data stored in the nth sub-region 330 is generated (see S40 and S60).

[0091] Here, even if an access request for the nth sub-region 330 occurs during the generation of the first parity data, the completion of the first parity data generation should be guaranteed. For example, even if an access request occurs, after the generation of the first parity data is completed, the generation of the nth parity data of the data stored in the nth sub-region 330 can begin. Alternatively, when an access request occurs, the generation of the first parity data can be interrupted, and after the generation of the nth parity data of the data stored in the nth sub-region 330 is first executed, the interrupted generation of the first parity data can be resumed and completed.

[0092] In summary, the predetermined parity data generation order can be to generate parity data in the order of the first sub-region 310 to the nth sub-region 330. Here, when generating the mth parity data of the data stored in the mth sub-region (m is a natural number between 1 and n-2), if a request to generate the kth parity data of the data stored in the kth sub-region (k is a natural number between m+2 and n) is received (i.e., an access request for the kth sub-region), then after generating the kth parity data, the (m+1)th parity data of the data stored in the (m+1)th sub-region can be generated.

[0093] For example, the second memory device may include ten sub-regions, and parity data should be generated in a sequential order from the first sub-region to the tenth sub-region. Then, when generating the third parity data for data stored in the third sub-region, if there is a request to generate the fifth parity data for data stored in the fifth sub-region (i.e., an access request for the fifth sub-region), the fifth parity data is generated (before generating the fourth parity data). After generating the fifth parity data, the fourth parity data is generated sequentially.

[0094] As described above, if a fifth parity data generation request exists, the generation of the third parity data can be interrupted, and the generation of the third parity data can continue after the fifth parity data is generated. Subsequently, the fourth parity data can be generated sequentially.

[0095] Alternatively, if a fifth parity data generation request exists, the third parity data can be generated, and the fifth parity data can then be generated. Afterward, the fourth parity data can be generated sequentially.

[0096] Figure 9 This is a diagram illustrating a method of operating a memory controller according to an embodiment of the present disclosure.

[0097] refer to Figure 9 First, a sudden power outage (SPO) occurs in the storage device.

[0098] As described above, during runtime, metadata stored in the second memory device 300 (i.e., volatile memory device) is frequently passed to the first memory device 100 (i.e., the non-volatile memory device). Log data related to the metadata is also passed to the first memory device 100.

[0099] Because SPO has already occurred, the metadata / log data stored in the first storage device 100 may not be up-to-date.

[0100] When the storage device is powered on again (PWR ON), metadata is loaded into the first sub-region 310 to the nth sub-region 330 of the second storage device 300. In the state where the ECC function of the sub-region is disabled, the metadata is updated (replayed) using log data (step S410). In the state where the ECC function is disabled, the replay operation is performed using a normal write operation instead of an RMW operation. Figure 9 The part indicated by N in the table is used to indicate the metadata updated using log data.

[0101] When playback is complete, the memory controller 200 sends a ready signal to the host. A ready signal is a signal indicating that preparation is complete and commands can be executed (i.e., a boot completion signal). The period between power-on and ready signal generation is called the "disconnect time".

[0102] For some SSD products, there is a requirement for the time required to handle a site outage (SPO) during which an outage occurs. The larger the capacity of the SSD product, the larger the size of the metadata / log data. Therefore, updating the metadata according to demand (i.e., within a predetermined outage time) becomes difficult.

[0103] In embodiments of this disclosure, when a playback operation is performed, because a normal write operation is used in a state where the ECC function is disabled, metadata updates can be easily performed within demand (i.e., within a predetermined disconnection time) even if the storage device capacity increases or the size of the metadata / log data increases.

[0104] Then, parity check data can be generated in a predetermined order.

[0105] First parity data is generated for the data stored in the first sub-region 310. Then, the ECC function of the first sub-region 310 is changed to the enabled state (step S420).

[0106] Subsequently, second parity data is generated for the data stored in the second sub-region 320. Then, the ECC function of the second sub-region 320 is switched to the enabled state (step S430).

[0107] Subsequently, the nth parity data stored in the nth sub-region 330 is generated. The ECC function of the nth sub-region is changed to the enabled state (step S440).

[0108] In other words, after parity data is generated for each of sub-regions 310, 320, and 330, the ECC function is individually enabled for each of these sub-regions. In this way, the host can immediately access sub-regions 310, 320, and 330 where the ECC function has been enabled, without the risk of data corruption.

[0109] Figure 10 This is a diagram illustrating a method of operating a memory controller according to an embodiment of the present disclosure. For simplicity, the following description will focus on the references... Figure 9 Differences in the described embodiments.

[0110] refer to Figure 10 A sudden power outage (SPO) occurs in the storage device.

[0111] When the storage device is powered on again (PWR ON), metadata is loaded into the first sub-regions 310 to the nth sub-region 330 of the second storage device 300. In the state where the ECC function of the sub-regions is disabled, the metadata is updated using a normal write operation (step S410). Figure 10 The part indicated by N in the middle is used to indicate the metadata updated using log data.

[0112] However, because normal write operations are performed while the ECC function is disabled, the playback operation can be completed considerably faster than the required SPO disconnect time. Therefore, steps S420, which generate parity data stored in some sub-regions (e.g., the first sub-region 310) and change the ECC function of the sub-region 310 for which parity data has already been generated, can be performed within the SPO disconnect time.

[0113] In this way, playback operations can be performed as quickly as possible while meeting the requirements related to SPO disconnection time, and the risk of data corruption can be reduced for some sub-regions (e.g., sub-region 310).

[0114] Subsequently, the memory controller 200 sends a ready signal to the host.

[0115] Parity check data generation is performed on the remaining sub-regions 320 and 330 in a predetermined order. Specifically, second parity check data is generated for the data stored in the second sub-region 320. Then, the ECC function of the second sub-region 320 is turned on (step S430). Subsequently, nth parity check data is generated for the data stored in the nth sub-region 330. The ECC function of the nth sub-region is turned on (step S440).

[0116] Figure 11 This is a diagram illustrating a method of operating a memory controller according to an embodiment of the present disclosure. For simplicity, the following description will focus on the references... Figure 9 and Figure 10 Differences in the described embodiments.

[0117] refer to Figure 11 A sudden power outage (SPO) occurs in the storage device.

[0118] When the storage device is powered on again (PWR ON), metadata is loaded into the first sub-regions 310 to the nth sub-region 330 of the second storage device 300. In the state where the ECC function of the sub-regions is disabled, the metadata is updated (i.e., replayed) using a normal write operation (step S410). Figure 11 The part indicated by N in the table is used to indicate the metadata updated using log data.

[0119] Then, parity check data can be generated in a predetermined order.

[0120] First parity data is generated for the data stored in the first sub-region 310. Then, the ECC function of the first sub-region 310 is changed to the enabled state (step S420).

[0121] In this configuration, a fourth parity data generation request (i.e., an access request for the fourth sub-region) can be received from the host for the data stored in the fourth sub-region. The fourth parity data is generated (before the second parity data is generated). Then, the ECC function of the fourth sub-region is switched to the enabled state (step S431).

[0122] After generating the fourth parity data, the second parity data of the data stored in the second sub-region is generated again in sequence. Subsequently, the nth parity data of the data stored in the nth sub-region 330 is generated. The ECC function of the nth sub-region is changed to the enabled state (step S440).

[0123] In extrapolating the specific embodiments, those skilled in the art will understand that many variations and modifications can be made to the preferred embodiments without substantially departing from the principles of the inventive concept herein. Therefore, the preferred embodiments disclosed herein are used merely in a general and descriptive sense and not for purposes of limitation.

Claims

1. A method of operating a memory controller, comprising: loading metadata for restoring a state of a memory to a state before a sudden power off (SPO) into a plurality of sub-areas of a buffer memory; updating the metadata for restoring a state of a memory to a state before a sudden power off (SPO) using log data that records a change history of the metadata, the updating being performed in a state in which an error correction code (ECC) function of the memory controller is disabled for each of the plurality of sub-areas; generating first parity data of data stored in a first sub-area among the plurality of sub-areas; and after the first parity data is generated, enabling the ECC function of the first sub-area. The updating of the metadata using the log data is performed within a disconnect time of a sudden power off (SPO) of the buffer memory, and 2. The method of claim 1, wherein, wherein the generation of the first parity data is performed after the disconnect time of the SPO.

3. The method of claim 1, further comprising: after the first parity data is generated, generating second parity data of data stored in a second sub-area among the plurality of sub-areas; and after the second parity data is generated, enabling the ECC function of the second sub-area. The updating of the metadata using the log data and the generation of the first parity data are performed within a disconnect time of a sudden power off (SPO) of the buffer memory, and wherein the generation of the second parity data is performed after the disconnect time of the SPO.

4. The method of claim 3, wherein, The generation of the first parity data is performed as a background operation.

6. The method of claim 1, further comprising generating parity data of data respectively stored in the plurality of sub-areas in an order of the plurality of sub-areas arranged in the buffer memory.

5. The method of claim 1, wherein, The plurality of sub-areas includes n sub-areas, where n is a natural number of 2 or more, and wherein the method further comprises:

7. The method of claim 6, wherein, when generating m-th parity data of m-th data stored in an m-th sub-area among the plurality of sub-areas, if a k-th parity data generation request of k-th data stored in a k-th sub-area among the plurality of sub-areas is received, after completing the k-th parity generation request, generating (m+1)-th parity data of (m+1)-th data stored in an (m+1)-th sub-area among the plurality of sub-areas, where m is a natural number between 1 and n-2, and where k is a natural number between m+2 and n. The generating includes generating the parity data by hardware logic. The updating of the metadata using the log data includes a normal write operation rather than a read-modify-write (RMW) operation.

8. The method of claim 6, wherein, 10. A method of operating a memory controller, comprising:

9. The method of claim 1, wherein, loading metadata for restoring a state of a memory to a state before a sudden power off (SPO) into a plurality of sub-areas of a buffer memory during a disconnect time of a sudden power off (SPO) of the buffer memory, ​ ​ updating the metadata for restoring a state of a memory to a state before a sudden power off (SPO) using log data recording a change history of the metadata, the updating being performed in a state in which an error correction code (ECC) function of the memory controller is disabled for each of the plurality of sub-areas; and generating parity data of data respectively stored in the plurality of sub-areas in order of the plurality of sub-areas arranged in the buffer memory as a background operation after a disconnection time of the SPO.

11. The method of claim 10, wherein, the plurality of sub-areas include n sub-areas, where n is a natural number of 2 or more, and wherein the method further includes: when generating mth parity data of mth data stored in an mth sub-area among the plurality of sub-areas, if a kth parity data generation request of kth data stored in a kth sub-area among the plurality of sub-areas is received, generating (m+1)th parity data of (m+1)th data stored in an (m+1)th sub-area among the plurality of sub-areas after completing the kth parity generation request, where m is a natural number between 1 and n-2, and where k is a natural number between m+2 and n.

12. The method of claim 10, further comprising: enabling an ECC function of a first sub-area among the plurality of sub-areas after generating first parity data of the first sub-area; and enabling an ECC function of an n-th sub-area among the plurality of sub-areas after generating n-th parity data of the n-th sub-area.

13. The method of claim 10, wherein, the updating the metadata using the log data includes a normal write operation rather than a read-modify-write (RMW) operation.

14. A storage device, comprising: a main memory; a buffer memory including a plurality of sub-areas; and a memory controller configured to load metadata for restoring a state of a memory to a state before a sudden power off (SPO) stored in the main memory into the plurality of sub-areas of the buffer memory after the SPO of the buffer memory occurs, and update the metadata for restoring a state of a memory to a state before a sudden power off (SPO) using log data recording a change history of the metadata according to whether the memory controller selectively enables or disables an error correction code (ECC) function of the memory controller for each of the plurality of sub-areas at the SPO of the buffer memory, wherein the updating is performed in a state in which the ECC function of the memory controller is disabled for each of the plurality of sub-areas.

15. The storage device of claim 14, wherein, the memory controller is further configured to disable the ECC function for all of the plurality of sub-areas when updating the metadata using the log data.

16. The storage device of claim 15, wherein, the memory controller is further configured to generate parity data of data stored in each of the plurality of sub-areas after updating the metadata using the log data, and enable the ECC function only for a processed sub-area among the plurality of sub-areas for which parity data has been generated.

17. The storage device of claim 16, wherein, The memory controller is further configured to check consistency of sub-regions among the plurality of sub-regions in which the ECC function is disabled using metadata of sub-regions among the plurality of sub-regions in which the ECC function is enabled.

18. The storage device of claim 14, wherein, The memory controller is further configured to, after updating the metadata using the log data, generate parity data of data stored in each of the plurality of sub-regions by using hardware logic.

19. The storage device of claim 14, wherein, The memory controller is further configured to, when updating the metadata using the log data, enable the ECC function only for processed sub-regions among the plurality of sub-regions for which parity data has been generated, and disable the ECC function for sub-regions among the plurality of sub-regions for which the parity data has not been generated.

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