CPU interconnect bus test fixture, system and balance tuning method

Abstract

The present invention provides a CPU interconnect bus test fixture, comprising: a substrate, adapted to a CPU mounting base, the lower surface of the substrate having pins corresponding to the contacts of the CPU mounting base; a plurality of adapters, arranged in an array on the upper surface of the substrate, the adapters being electrically connected to the pins via metal interconnects inside the substrate. The technical solution provided by the present invention can accurately measure the output signal of a high-speed interconnect bus, which is beneficial to the performance tuning of the high-speed interconnect bus.

Description

Technical Field

[0001] The present invention relates to the technical field of high-speed interconnect bus testing, and in particular to a CPU interconnect bus testing fixture, system and equalization tuning method. Background Art

[0002] Multi-way CPU design is a common design in servers, and the communication between multiple CPUs involves the high-speed interconnect bus between CPUs. The quality of the high-speed interconnect bus signal affects the performance of the entire server to a certain extent, so measuring the output signal of the high-speed interconnect bus and optimizing the performance of the high-speed interconnect bus is an essential but difficult requirement. The current high-speed interconnect bus is a fully enclosed design from CPU pin to pin, and the rate is as high as 10 to 30Gbps. It has high requirements for the measurement equipment environment, and it is impossible to directly measure the physical signal at the terminal in terms of physical structure. Summary of the invention

[0003] The CPU interconnect bus test fixture and system provided by the present invention can accurately measure the output signal of the high-speed interconnect bus, which is beneficial to the performance tuning of the high-speed interconnect bus.

[0004] In a first aspect, the present invention provides a CPU interconnect bus test fixture, comprising:

[0005] A base plate adapted to the CPU mounting base, wherein the lower surface of the base plate has pins corresponding to the contacts of the CPU mounting base;

[0006] A plurality of adapters are arranged in an array on the upper surface of the substrate, and the adapters are electrically connected to the pins through metal interconnection lines inside the substrate.

[0007] Optionally, the substrate comprises:

[0008] An adaptation layer adapted to the CPU mounting base;

[0009] The fan-out layer is connected to the upper surface of the adaption layer, and the area of ​​the upper surface of the fan-out layer is larger than the area of ​​the upper surface of the adaption layer.

[0010] Optionally, the fan-out layer is provided with through holes, so that screws pass through the through holes to fix the substrate on the mainboard.

[0011] Optionally, the metal interconnects in the substrate are set according to routing, loss, crosstalk and impedance parameters of the CPU package substrate.

[0012] Optionally, a protective cover is further included, wherein the protective cover has a raised area adapted to the mainboard presser, and a position of the raised area corresponding to the adapter has an opening for exposing the adapter.

[0013] In a second aspect, the present invention provides a CPU interconnection bus test system for testing a CPU interconnection bus of a multi-way CPU mainboard, wherein a CPU is installed on the multi-way CPU mainboard, and is characterized in that it comprises:

[0014] A CPU interconnect bus test fixture as described in any one of the above items; the CPU interconnect bus test fixture cooperates with one of the CPU mounting bases of the multi-channel CPU motherboard, and the CPU interconnect bus test fixture is used to fan out the signal of the CPU interconnect bus;

[0015] An input / output device, which is communicatively connected to the input / output interface of the multi-channel CPU mainboard, and is used to control the CPU to send a signal so that the signal is transmitted to the adapter via the CPU interconnection bus;

[0016] An oscilloscope, wherein a probe of the oscilloscope is adapted to the plurality of adapters and is used for reading signals output by the adapters.

[0017] Optionally, the multi-way CPU mainboard is provided with a through hole;

[0018] The CPU interconnect bus test fixture is connected by bolts or screws passing through the through holes.

[0019] Optionally, the CPU interconnect bus test fixture is connected to the multi-channel CPU mainboard via a press fitter on a CPU mounting base.

[0020] Optionally, the CPU is mounted on a master CPU mounting base of the multi-way CPU mainboard, and the CPU interconnection bus test fixture is mounted on a slave CPU mounting base of the multi-way CPU mainboard.

[0021] Optionally, the input-output device is used to control the CPU to send signals by configuring register configuration parameters of the CPU.

[0022] In a third aspect, the present invention further provides a CPU interconnect bus balance tuning method, comprising:

[0023] Installing a CPU and a CPU interconnection bus test fixture as described in any one of the above items on two CPU mounting bases connected by CPU interconnection bus communication respectively;

[0024] configuring the CPU registers through input and output devices so that the CPU interconnect bus transmitter sends a test signal;

[0025] Using an oscilloscope to read the signal output by the adapter of the CPU interconnect bus test fixture, and generating an eye diagram according to the read signal;

[0026] The equalization parameters of the CPU interconnect bus are adjusted according to the eye diagram.

[0027] Optionally, adjusting the equalization parameter of the CPU interconnect bus according to the eye diagram includes:

[0028] When the eye height of the eye diagram is not lower than a predetermined eye height, and the eye width of the eye diagram is not lower than a predetermined eye width, determining that no equalization parameter adjustment is required;

[0029] When the eye height of the eye diagram is lower than a predetermined eye height, or the eye width of the eye diagram is lower than a predetermined eye width, the equalization parameter is adjusted.

[0030] Optionally, adjusting the equalization parameter includes:

[0031] When the eye height is lower than a predetermined eye height, one of the front mark, the rear mark or the main mark in the equalization parameter is increased, and the other two are matched according to a forward feedback equalization (FFE) rule;

[0032] When the eye width is lower than a predetermined eye width, the leading and trailing indices of the equalization parameter are increased, and the main indices are matched according to the FFE rule.

[0033] In the technical solution provided by the present invention, the pins of the substrate are contacted with the contacts of the CPU mounting base, an adapter is arranged on the substrate, and the signal transmitted by the high-speed interconnection bus is transmitted to the adapter through the wiring in the substrate, and the adapter is directly output to the oscilloscope, so that the oscilloscope can directly read the signal of the high-speed interconnection bus. When the signal of the high-speed interconnection bus is read in the above manner, the reading accuracy is high and the reading speed is fast, which is conducive to accurately adjusting the equalization value of the high-speed interconnection bus. In addition, the substrate provided by the present invention is adapted to the CPU mounting base, and its installation method is simple, convenient and reliable. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 This is a schematic diagram of the structure of a CPU interconnect bus test fixture according to an embodiment of the present invention;

[0035] Figure 2 This is a schematic structural diagram of a CPU interconnect bus test fixture according to another embodiment of the present invention;

[0036] Figure 3 for Figure 1 Top view after installing the protective cover;

[0037] Figure 4 A schematic diagram of the structure of a protective cover of a CPU interconnect bus test fixture according to an embodiment of the present invention;

[0038] Figure 5 A schematic diagram of a CPU interconnect bus test system according to an embodiment of the present invention;

[0039] Figure 6 A schematic diagram of a CPU interconnect bus test system according to another embodiment of the present invention;

[0040] Figure 7 The present invention is a flowchart of a CPU interconnect bus balance tuning method according to another embodiment of the present invention. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0042] The embodiment of the present invention provides a CPU interconnect bus test fixture, such as Figure 1 As shown, including:

[0043] The substrate 4 is adapted to the CPU mounting base, and the lower surface of the substrate 4 has pins 3 corresponding to the contacts of the CPU mounting base; in some embodiments, the substrate 4 is a board for setting the wiring, and the upper and lower surfaces of the substrate 4 are usually provided with pins 3, so that by connecting the components or chips set on the upper surface of the substrate 4 with the components or circuit boards on the lower surface of the substrate 4, in some preferred embodiments, the metal interconnection lines 2 in the substrate 4 are set according to the wiring, loss, crosstalk and impedance parameters of the CPU package substrate 4. When setting the wiring in the substrate 4, the S parameters of the CPU high-speed interconnection bus signal of the actual CPU substrate 4 can be extracted through simulation software, and then the wiring of the CPU high-speed interconnection bus test board is also extracted, and the wiring of the substrate 4 is continuously optimized to achieve the best fitting state.

[0044] A plurality of adapters 1 are arranged in an array on the upper surface of the substrate 4, and the adapters 1 are electrically connected to the pins 3 through metal interconnects 2 inside the substrate 4. In some embodiments, the adapter 1 can be set as an SMP adapter 1, which can be well adapted to the oscilloscope, so that the oscilloscope can accurately read the signal.

[0045] In the technical solution provided in this embodiment, the pin 3 of the substrate 4 is used to contact the contact of the CPU mounting base, and the adapter 1 is set on the substrate 4. The signal transmitted by the high-speed interconnection bus is transmitted to the adapter 1 through the wiring in the substrate 4, and the adapter 1 directly outputs it to the oscilloscope, so that the oscilloscope can directly read the signal of the high-speed interconnection bus. When the signal of the high-speed interconnection bus is read in the above manner, the reading accuracy is high and the reading speed is fast, which is conducive to accurately adjusting the balance value of the high-speed interconnection bus. In addition, the substrate 4 provided in this embodiment is adapted to the CPU mounting base, and its installation method is simple, convenient and reliable.

[0046] As an optional implementation, Figure 2 As shown, the substrate 4 includes:

[0047] The adaption layer 402 is adapted to the CPU mounting base; the adaption layer 402 is adapted to the CPU mounting base, and can position the test fixture and achieve communication connection with the CPU mounting base.

[0048] The fan-out layer 401 is connected to the upper surface of the adaption layer 402, and the area of ​​the upper surface of the fan-out layer 401 is larger than the area of ​​the upper surface of the adaption layer 402. The fan-out layer 401 has a larger area, which is convenient for the distribution of the adapter 1, and when the probe of the oscilloscope is used to contact the transferred signal, it is not easy to make wrong contact.

[0049] As a further optional implementation, the fan-out layer 401 is provided with a through hole, so that a screw passes through the through hole to fix the substrate 4 on the main board. The through hole is provided on the fan-out layer 401, and the screw is passed through the through hole for fixing, so that the test fixture can be firmly connected to the main board, avoiding inaccurate test results due to the looseness of the test fixture.

[0050] As a preferred embodiment, Figure 3-4 As shown, the protective cover 5 is also included, and the protective cover 5 has a protrusion 51 area adapted to the motherboard press 605, and the position of the protrusion 51 area corresponding to the adapter 1 has an opening 52 for exposing the adapter 1. The shape of the protective cover 5 is generally the same as the shape of the CPU heat dissipation cover, so as to facilitate the cooperation between the protective cover 5 and the press 605 on the motherboard. The difference is that the opening 52 is set on the protective cover 5 at the position corresponding to the adapter 1, so as to expose the adapter 1, so that the probe of the oscilloscope can smoothly contact the adapter 1.

[0051] In a second aspect, the present invention provides a CPU interconnection bus test system for testing a CPU interconnection bus of a multi-way CPU motherboard 601, wherein a CPU 604 is installed on the multi-way CPU motherboard 601. Figure 5 As shown, including:

[0052] A CPU interconnect bus test fixture as described in any one of the above items; the CPU interconnect bus test fixture cooperates with one of the CPU mounting bases 603 of the multi-channel CPU motherboard 601, and the CPU interconnect bus test fixture is used to fan out the signal of the CPU interconnect bus;

[0053] An input / output device (not shown in the figure), which is in communication connection with the input / output interface of the multi-channel CPU mainboard 601, and is used to control the CPU 604 to send a signal so that the signal is transmitted to the adapter 1 via the CPU interconnection bus;

[0054] An oscilloscope (not shown in the figure), wherein the probe of the oscilloscope is adapted to the plurality of adapters 1 and is used for reading the signals output by the adapters 1 .

[0055] In the technical solution provided in this embodiment, the pin 3 of the substrate 4 is used to contact the contact of the CPU mounting base 603, and the adapter 1 is set on the substrate 4. The signal transmitted by the high-speed interconnection bus 602 is transmitted to the adapter 1 through the wiring in the substrate 4, and the adapter 1 directly outputs it to the oscilloscope, so that the oscilloscope can directly read the signal of the high-speed interconnection bus 602. When the signal of the high-speed interconnection bus 602 is read in the above manner, the reading accuracy is high and the reading speed is fast, which is conducive to accurately adjusting the balance value of the high-speed interconnection bus 602. In addition, the substrate 4 provided in this embodiment is adapted to the CPU mounting base 603, and its installation method is simple, convenient and reliable.

[0056] In some implementations, such as Figure 6 As shown, the multi-way CPU mainboard 601 is provided with through holes;

[0057] The CPU interconnect bus test fixture is connected by bolts 606 or screws passing through the through holes. The test system in this embodiment is preferably suitable for Figure 2 The test fixture shown in the figure is provided with through holes on the fan-out layer 401 corresponding to the through holes of the main board 601, and then the test fixture is fixed to the main board 601 by screws or bolts 606 passing through the through holes, so that the main board 601 and the test fixture are firmly fixed together, avoiding test errors caused by the firmness of the fixing part.

[0058] As an optional implementation, continue as Figure 5 As shown, the CPU interconnect bus test fixture is connected to the multi-channel CPU mainboard 601 through the press 605 on the CPU mounting base 603. The test fixture is installed with the CPU mounting base 603 using the press 605 on the mainboard 601. The installation method is simple and fast, and is the same as the method of installing the CPU, without requiring any extra operations.

[0059] As a preferred implementation, the CPU is mounted on the master CPU mounting base 603 of the multi-way CPU motherboard 601, and the CPU interconnection bus test fixture is mounted on the slave CPU mounting base 603 of the multi-way CPU motherboard 601. Generally, the signals sent by the master CPU to the slave CPU are more critical and in larger quantities. During the debugging process, the work of debugging the signals sent by the master CPU to the slave CPU is more critical. Therefore, the technical solution of this implementation is adopted for debugging.

[0060] As a preferred embodiment, the input-output device is used to control the CPU to send a signal by configuring the register configuration parameters of the CPU. In this embodiment, the input-output device performs software control of the CPU register configuration, so that the high-speed interconnection bus 602 transmitter of a single CPU can send a test physical signal.

[0061] The embodiment of the present invention further provides a CPU interconnect bus balance tuning method, comprising:

[0062] Step 710, respectively installing a CPU and a CPU interconnection bus test fixture as described in any one of the above on two CPU mounting bases that are communicatively connected via a CPU interconnection bus;

[0063] In some embodiments, a motherboard capable of forming a multi-way processor will usually have at least two CPU mounting bases, and the mounting bases of multiple CPUs will usually be connected through a CPU interconnection bus. In some preferred embodiments, a CPU will be installed on one of the two CPU bases interconnected by the CPU interconnection bus, and a test fixture of the CPU interconnection bus will be installed on the other.

[0064] Step 720, configuring the CPU register through an input / output device so that the CPU interconnect bus transmitter sends a test signal;

[0065] In some embodiments, the motherboard of the multi-way processor usually has an interface for connecting input and output devices. In some preferred embodiments, the input and output devices are connected to the motherboard through the interface. Through the wiring inside the motherboard, the input device can input configuration information to the CPU, and the output device can display the corresponding configuration information. The input device inputs configuration information to the register of the CPU, so that the interconnection bus transmitter of the single CPU sends a test physical signal. The input device can be, for example, a keyboard or a mouse, and the output device can be, for example, a display. The configuration information input to the register of the CPU can be, for example, as shown in the following table:

[0066]

[0067]

[0068] Step 730, using an oscilloscope to read the signal output by the adapter of the CPU interconnect bus test fixture, and generating an eye diagram according to the read signal;

[0069] In some embodiments, since the adapter of the CPU interconnect bus test fixture can directly output the signal sent by the CPU interconnect bus, that is, the oscilloscope can directly read the signal sent by the CPU interconnect bus, the signal read by the oscilloscope is more accurate and the reading speed is faster. Therefore, the eye diagram generated based on the signal output by the adapter can be more accurate, which is conducive to the subsequent equalization parameter adjustment.

[0070] Step 740: Adjust the equalization parameters of the CPU interconnect bus according to the eye diagram.

[0071] In some embodiments, in the process of adjusting the equalization parameters using the eye diagram, the signal waveform is usually superimposed to form an eye diagram, and then the eye diagram analysis is performed. The main parameters considered in the eye diagram are the eye height and the eye width. The larger the eye height and the eye width, the better the signal quality. Since the signal in the technical solution of this embodiment is a signal of the CPU interconnect bus directly read from the adapter, the eye diagram test result can more accurately present the terminal signal quality of the current CPU high-speed interconnect bus.

[0072] As an optional implementation, step 740 includes:

[0073] When the eye height of the eye diagram is not lower than a predetermined eye height, and the eye width of the eye diagram is not lower than a predetermined eye width, determining that no equalization parameter adjustment is required;

[0074] When the eye height of the eye diagram is lower than a predetermined eye height, or the eye width of the eye diagram is lower than a predetermined eye width, the equalization parameter is adjusted.

[0075] In some embodiments, the predetermined eye height and eye width are set according to requirements. For example, the predetermined eye height and eye width may be set to be greater than 1.1 times the eye height and eye width specified in the signal quality standard in the QPI, UPI or XGMI specification.

[0076] Optionally, adjusting the equalization parameter includes:

[0077] When the eye height is lower than a predetermined eye height, one of the front mark, the rear mark or the main mark in the equalization parameter is increased, and the other two are matched according to a forward feedback equalization (FFE) rule;

[0078] In some embodiments, when the eye diagram is lower than a predetermined eye height, adjustments may be made as follows:

[0079] If the eye height is too low, it may be affected by the DC part of the signal. In this case, increase the main-cursor value and match the pre-cursor and post-cursor values ​​according to the FFE rule.

[0080] If the eye height of the eye diagram is too low, it may be affected by the rising edge of the signal. You can increase the Post-cursor value and match the pre-cursor and main-cursor values ​​according to the FFE rule.

[0081] If the eye height of the eye diagram is too low, it may be affected by the falling edge of the signal. You can increase the Pre-cursor value and match the post-cursor and main-cursor values ​​according to the FFE rule.

[0082] When the eye width is lower than a predetermined eye width, the leading and trailing indices of the equalization parameter are increased, and the main indices are matched according to the FFE rule.

[0083] In some embodiments, if the eye width number of the eye diagram is too small, the pre-cursor and post-cursor values ​​are increased, and the main-cursor value is matched according to the FFE rule.

[0084] Take an FFE rule as an example: (pre-cursor) / 4+(main-cursor)+(post-cursor) / 4=40, so the range of pre-cursor is 0~160, the range of main-cursor is 0~40, and the range of post-cursor is 0~160. When the eye diagram problem of 2.3.3 / 2.3.4 / 2.3.5 / 2.3.6 appears, based on the default pre-cursor, post-cursor and main-cursor values, the main-cursor value is increased by +3 as a step thick bar, and the pre-cursor and post-cursor are traversed with -12 as a step. If the problem cannot be solved upward, the main-cursor value is decreased by -3 as a step, and the pre-cursor and post-cursor are traversed with +12 as a step, and an optimized range of the eye diagram is obtained. After the optimization range is obtained, the main-cursor is fine-tuned with a gait of +-1, and the pre-cursor and post-cursor are traversed with a gait of +-4 to find the final result.

[0085] The signal used in the CPU interconnect bus equalization tuning method provided in the above embodiment is a signal output by the CPU interconnect bus directly read through the adapter, and the accuracy of the signal provides a basis for tuning the equalization parameters. A more accurate reading signal can eliminate the influence of noise generated during the signal reading process, which is conducive to adjusting the equalization parameters to the optimal range.

[0086] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A CPU interconnect bus test fixture, characterized in that: include: A base plate adapted to the CPU mounting base, wherein the lower surface of the base plate has pins corresponding to the contacts of the CPU mounting base, and one end of the base plate provided with the pins is inserted into a groove provided by the CPU mounting base; A plurality of adapters are arranged in an array on the upper surface of the substrate, and the adapters are electrically connected to the pins through metal interconnection lines inside the substrate.

2. The CPU interconnect bus test fixture according to claim 1, characterized in that: The substrate comprises: An adaption layer adapted to the groove on the CPU mounting base; The fan-out layer is connected to the upper surface of the adaption layer, and the area of ​​the upper surface of the fan-out layer is larger than the area of ​​the upper surface of the adaption layer.

3. The CPU interconnect bus test fixture according to claim 2, characterized in that: The fan-out layer is provided with through holes so that screws can pass through the through holes to fix the substrate on the mainboard.

4. The CPU interconnect bus test fixture according to claim 1, characterized in that: The metal interconnection lines in the substrate are set according to the routing, loss, crosstalk and impedance parameters of the CPU packaging substrate.

5. The CPU interconnect bus test fixture according to claim 1, characterized in that: It also includes a protective cover, which has a raised area adapted to the mainboard press, and a position of the raised area corresponding to the adapter has an opening for exposing the adapter.

6. A CPU interconnect bus test system for testing the CPU interconnect bus of a multi-channel CPU motherboard, wherein: The multi-way CPU mainboard is equipped with a CPU, which is characterized by comprising: The CPU interconnect bus test fixture as described in any one of claims 1 to 5; the CPU interconnect bus test fixture cooperates with one of the CPU mounting bases of the multi-channel CPU motherboard, and the CPU interconnect bus test fixture is used to fan out the signal of the CPU interconnect bus; An input / output device, which is communicatively connected to the input / output interface of the multi-channel CPU mainboard, and is used to control the CPU to send a signal so that the signal is transmitted to the adapter via the CPU interconnection bus; An oscilloscope, wherein a probe of the oscilloscope is adapted to the plurality of adapters and is used for reading signals output by the adapters.

7. The CPU interconnect bus test system according to claim 6, characterized in that: The multi-channel CPU mainboard is provided with a through hole; The CPU interconnect bus test fixture is connected by bolts or screws passing through the through holes.

8. The CPU interconnect bus test system according to claim 6, characterized in that: The CPU interconnect bus test fixture is connected to the multi-channel CPU mainboard via a press fitter on a CPU mounting base.

9. The CPU interconnect bus test system according to claim 6, characterized in that: The CPU is installed on a main CPU installation base of the multi-way CPU mainboard, and the CPU interconnection bus test fixture is installed on a slave CPU installation base of the multi-way CPU mainboard.

10. The CPU interconnect bus test system according to claim 6, characterized in that: The input and output device is used to control the CPU to send signals by configuring register configuration parameters of the CPU.

11. A CPU interconnect bus balance tuning method, comprising: Installing a CPU and a CPU interconnection bus test fixture as described in any one of claims 1 to 5 on two CPU mounting bases connected by CPU interconnection bus communication, respectively; configuring the CPU registers through input and output devices so that the CPU interconnect bus transmitter sends a test signal; Using an oscilloscope to read the signal output by the adapter of the CPU interconnect bus test fixture, and generating an eye diagram according to the read signal; The equalization parameters of the CPU interconnect bus are adjusted according to the eye diagram.

12. The CPU interconnect bus equalization tuning method according to claim 11, characterized in that: Adjusting the equalization parameters of the CPU interconnect bus according to the eye diagram includes: When the eye height of the eye diagram is not lower than a predetermined eye height, and the eye width of the eye diagram is not lower than a predetermined eye width, determining that no equalization parameter adjustment is required; When the eye height of the eye diagram is lower than a predetermined eye height, or the eye width of the eye diagram is lower than a predetermined eye width, the equalization parameter is adjusted.

13. The CPU interconnect bus balance tuning method according to claim 12, characterized in that: Adjusting the equalization parameter includes: When the eye height is lower than a predetermined eye height, one of the front mark, the rear mark or the main mark in the equalization parameter is increased, and the other two are matched according to the forward feedback equalization (FFE) rule; When the eye width is lower than a predetermined eye width, the leading and trailing indices of the equalization parameter are increased, and the main indices are matched according to the FFE rule.

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