A data processing method, a security chip device and an embedded system

Abstract

The present invention relates to a data processing method, a security chip device and an embedded system, which belongs to the field of computer technology and solves the problem that the existing data processing rate is low and cannot be adapted to encryption and decryption algorithms with large calculation amount. The method comprises: step S1: storing the first data stream in the first RAM; step S2: storing the second data stream in the second RAM, processing the first data stream by the algorithm unit and storing the processed first data stream in the first RAM; step S3: outputting the processed first data stream to the host computer, processing the second data stream by the algorithm unit and storing the processed second data stream in the second RAM; and step S4: outputting the processed second data stream to the host computer. The utilization rate of the algorithm unit is improved, thereby improving work efficiency.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a data processing method, a security chip device and an embedded system. Background Art

[0002] Random Access Memory (RAM), also known as main memory, is an internal memory that directly exchanges data with the CPU. It can be read and written at any time (except when refreshed) and is very fast. It is usually used as a temporary data storage medium for operating systems or other running programs. When working, RAM can write (store) or read (retrieve) information from any specified address at any time. RAM is used in computers and digital systems to temporarily store programs, data, and intermediate results.

[0003] In the prior art, processing a set of data requires three steps: storing the data in RAM, processing the data, and reading the data from RAM, which requires three processing cycles. Therefore, six cycles are required to process two sets of data. This working method has a low data processing rate and cannot be adapted to encryption and decryption algorithms with large computational load. Summary of the invention

[0004] In view of the above analysis, the embodiments of the present invention aim to provide a data processing method, a security chip device and an embedded system to solve the problem that the existing data processing method has a low data processing rate and cannot be adapted to encryption and decryption algorithms with large computational complexity.

[0005] On the one hand, an embodiment of the present invention provides a data processing method, including: step S1: storing a first data stream in a first RAM; step S2: storing a second data stream in a second RAM, and processing the first data stream by an algorithm unit and storing the processed first data stream in the first RAM; step S3: outputting the processed first data stream to a host computer, and processing the second data stream by the algorithm unit, and storing the processed second data stream in the second RAM; and step S4: outputting the processed second data stream to the host computer.

[0006] The beneficial effects of the above technical solution are as follows: while the second data stream is stored in the second RAM, the first data stream is processed by the algorithm unit and the processed first data stream is stored in the first RAM, and while the processed first data stream is output to the host computer, the second data stream is processed by the algorithm unit and the processed second data stream is stored in the second RAM, which can improve the utilization rate of the algorithm unit and thus improve work efficiency.

[0007] Based on the further improvement of the above method, the algorithm unit includes one or more of an SM1 cryptographic algorithm module, an SM4 cryptographic algorithm module, an AES cryptographic algorithm module, a DES cryptographic algorithm module and a Hash algorithm module.

[0008] Based on a further improvement of the above method, storing the first data stream in the first RAM further includes: inputting the first data stream via a four-wire SPI interface; and storing the first data stream in the first RAM through a RAM switching matrix.

[0009] Based on a further improvement of the above method, storing the second data stream in the second RAM, and processing the first data stream through the algorithm unit and storing the processed first data stream in the first RAM further includes: inputting the second data stream via a four-wire SPI interface, and storing the second data stream in the second RAM through a RAM switching matrix; and at the same time, the algorithm unit obtains the first data stream from the first RAM through the RAM switching matrix, performs algorithmic processing on the first data stream, and then stores the processed first data stream in the first RAM through the RAM switching matrix.

[0010] Based on the further improvement of the above method, outputting the processed first data stream to the host computer, processing the second data stream by the algorithm unit, and storing the processed second data stream in the second RAM further includes: reading the processed first data stream from the first RAM through the RAM switching matrix, and then outputting the processed first data stream to the host computer via the four-wire SPI interface; and at the same time, the algorithm unit obtains the second data stream from the second RAM through the RAM switching matrix, performs the algorithm processing on the second data stream, and then stores the processed second data stream in the second RAM through the RAM switching matrix.

[0011] Based on a further improvement of the above method, outputting the processed second data stream to the host computer further includes: reading the processed second data stream from the second RAM through the RAM switching matrix; and outputting the processed second data stream to the host computer via a four-wire SPI interface.

[0012] Based on further improvements of the above method, processing the first data stream through the algorithm unit and storing the processed first data stream in the first RAM further includes: the CPU sends a key, an operating mode and an algorithm processing start instruction to the SFR interface module through the SFR bus; the algorithm core of the algorithm unit performs algorithm processing on the first data stream based on the key, the operating mode and the algorithm processing start instruction; after the algorithm processing is completed, the algorithm completion instruction is transmitted from the SFR interface module to the CPU via the SFR bus; after the CPU completes the algorithm instruction, it generates a first RAM write instruction and configures the RAM switching matrix; and according to the first RAM write instruction, the processed first data stream is stored in the first RAM through the RAM switching matrix.

[0013] Based on a further improvement of the above method, processing the second data stream through the algorithm unit and storing the processed second data stream in the second RAM further includes: the CPU sends a key, an operating mode and an algorithm processing start instruction to the SFR interface module through the SFR bus; the algorithm core of the algorithm unit performs algorithm processing on the second data stream based on the key, the operating mode and the algorithm processing start instruction; after the algorithm processing is completed, the algorithm completion instruction is transmitted from the SFR interface module to the CPU via the SFR bus; after the CPU generates a second RAM write instruction and configures the RAM switching matrix according to the algorithm completion instruction; and according to the second RAM write instruction, the processed second data stream is stored in the second RAM through the RAM switching matrix.

[0014] Based on the further improvement of the above method, the data stream to be processed is divided into multiple cycles, each cycle includes the first data stream and the second data stream, and the processed second data stream is output to the host computer, and it also includes: obtaining the first data stream of the next cycle and executing the step S1.

[0015] Based on a further improvement of the above method, the data stream to be processed is divided into multiple cycles, each cycle includes N data streams, and the N data streams include the first data stream and the second data stream; the N data streams in each cycle are processed by N RAMs, and the N RAMs include the first RAM and the second RAM.

[0016] On the other hand, an embodiment of the present invention provides a security chip device including a first RAM, a second RAM, and an algorithm unit, wherein: the first RAM is used to store a first data stream, and output the first data stream processed by the algorithm unit to a host computer; the second RAM is used to store a second data stream, and output the second data stream processed by the algorithm unit to the host computer; the algorithm unit is used to process the first data stream and store the processed first data stream in the first RAM, and process the second data stream and store the processed second data stream in the second RAM, and the host computer is located outside the security chip device.

[0017] Based on further improvements of the above-mentioned device, the algorithm unit includes one or more of the SM1 cryptographic algorithm module, the SM4 cryptographic algorithm module, the AES cryptographic algorithm module, the DES cryptographic algorithm module and the Hash algorithm module, which are respectively used for encryption and decryption of the SM1 cryptographic algorithm, the SM4 cryptographic algorithm, the AES cryptographic algorithm, the DES cryptographic algorithm and the Hash algorithm.

[0018] Based on further improvements of the above-mentioned device, the SM1 cryptographic algorithm module includes: a first SFR interface module, used to connect to the CPU via the SFR bus; a first special function register, used to control the configuration and data cache of the SM1 core; and the SM1 core, used to perform SM1 operations; and the SM4 cryptographic algorithm module includes: a second SFR interface module, used to connect to the CPU via the SFR bus; a second special function register, used to control the configuration and data cache of the SM4 core; and the SM4 core, used to perform SM4 operations.

[0019] Based on the further improvement of the above device, the security chip device also includes: a RAM switching matrix, connected to the AHB bus, the first RAM and the second RAM are connected to the algorithm unit via the RAM switching matrix, and is used to: store the first data stream and the second data stream in the first RAM and the second RAM respectively; the algorithm unit obtains the first data stream and the second data stream respectively via the RAM switching matrix; and stores the processed first data stream and the second data stream in the first RAM and the second RAM respectively.

[0020] Based on the further improvement of the above device, the security chip device also includes a four-wire SPI interface, wherein the four-wire SPI interface connects the first RAM and the second RAM via the RAM switching matrix, and the four-wire SPI interface is used to input the first data stream and the second data stream, and output the processed first data stream and the second data stream.

[0021] Based on further improvement of the above device, the security chip device also includes: the CPU, used to connect the Hash algorithm module and the algorithm unit through the AHB bus; a storage management module EMMU, used to connect the CPU through the AHB bus, and the storage management module EMMU is directly connected to the RAM switching matrix; and the storage management module EMMU is directly connected to ROM, FLASH and SRAM.

[0022] Based on further improvement of the above device, the security chip device also includes: a Hash algorithm module for a hash algorithm, connected to the CPU through the AHB bus, and connected to the first RAM and the second RAM via the RAM switching matrix, wherein the Hash algorithm module further includes: an SFR interface module, used to connect to the CPU via the SFR bus; special function registers, used for control configuration and data caching of the HASH core; and the HASH core, used to perform HASH operations.

[0023] Based on further improvements to the above device, the transmission clock of the four-wire SPI interface reaches up to 100 MHz, and the data transmission speed reaches 50 MB / s.

[0024] Based on the further improvement of the above device, the security chip device also includes: a true random number generator TRNG, which is used to generate a random number sequence that meets security requirements for key generation and digital signature, and the TRNG further includes: TRNG0 is a switching voltage structure; TRNG1, TRNG2 and TRNG3 are switching current structures; a first XOR gate, which performs XOR processing on the outputs of TRNG0, TRNG1, TRNG2 and TRNG3 to generate a parallel random number noise source seed; a supplementary random number generator, which is used to generate a supplementary random number based on a supplementary seed or a feedback random number, wherein the supplementary seed is used for the first time, and the feedback random number is used subsequently; a random number seed generator, which is used to generate a random number seed based on the output of the first XOR gate and the supplementary random number; a linear feedback shift register LFSR, which is used to receive the random number seed and perform shift processing on the random number seed to generate a plain text and a key; and an RNG2 module, which is used to perform SM4 operation on the plain text and the key to generate a random number.

[0025] In yet another aspect, an embodiment of the present invention provides an embedded system, comprising: the security chip device described above.

[0026] Based on further improvements of the above system, the embedded system also includes: an SD card for storing data streams, wherein the data streams include the first data stream and the second data stream; and an SD card controller, for transmitting the data stream to be encrypted to the security chip device through the four-wire SPI interface to encrypt the data stream to be encrypted therein, or storing the decrypted data stream from the security chip device to the SD card through the four-wire SPI interface; wherein the security chip device and the SD card controller are arranged in the SD card.

[0027] Based on further improvement of the above system, the embedded system also includes: a Nandflash memory arranged in the SD card, the Nandflash memory includes a security area, a hidden area and a security area, wherein the SD card controller is also used to store the encrypted data stream to the Nandflash memory through the NF I / F interface, or to transmit the encrypted data stream to be decrypted to the security chip device through the four-wire SPI interface, so as to decrypt the encrypted data stream to be decrypted therein.

[0028] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0029] 1. Processing the first data stream by the algorithm unit and storing the processed first data stream in the first RAM while storing the second data stream in the second RAM, and processing the second data stream by the algorithm unit and storing the processed second data stream in the second RAM while outputting the processed first data stream to the host computer, can improve the utilization rate of the algorithm unit, thereby improving work efficiency.

[0030] 2. The data stream is input or output from the security chip device through the four-wire SPI interface, which increases the interface data transmission rate to 50MB / s.

[0031] 3. Compared with the bus, the algorithm unit directly obtains data from the first RAM or the second RAM through the RAM switching matrix, or stores the processed data in the first RAM or the second RAM, so that the encryption and decryption data processing rate is improved and can reach 40MB / s.

[0032] 4. The security chip device has four noise source generators inside, which use two different circuit architectures: switch current structure and switch voltage structure, with excellent independence. It uses a combination of physical random source and digital post-processing to generate high-quality random numbers with uniform distribution, no relation to sequence, and long period.

[0033] 5. The security chip device adopts QFN32 package, and the chip area is 5x5mm 2 Small, saving PCB space.

[0034] In the present invention, the above-mentioned technical solutions can also be combined with each other to achieve more preferred combination solutions. Other features and advantages of the present invention will be described in the subsequent description, and some advantages can become obvious from the description, or can be understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained through the contents particularly pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The drawings are only for the purpose of illustrating specific embodiments and are not to be considered limiting of the present invention. Like reference symbols denote like components throughout the drawings.

[0036] Figure 1 is a flow chart of a data processing method according to an embodiment of the present invention.

[0037] Figure 2 4 is a structural diagram of a four-wire SPI interface according to an embodiment of the present invention.

[0038] Figure 3 4 is a structural diagram of Pipeline mode data processing according to an embodiment of the present invention.

[0039] Figure 4 FIG. 4 is a general structural diagram of a security chip device according to an embodiment of the present invention.

[0040] Figure 5 FIG. 4 is a state structure diagram of the I2C interface in a security chip device.

[0041] Figure 6 This is a structural diagram of the GPIO interface in a security chip device.

[0042] Figure 7 4 is a block diagram of an SM1 cryptographic algorithm module according to an embodiment of the present invention.

[0043] Figure 8 Figure 1 is a block diagram of a PKU in a security chip device.

[0044] Fig. 9 4 is a block diagram of an SM4 cryptographic algorithm module according to an embodiment of the present invention.

[0045] Fig.10 4 is a block diagram of a HASH cryptographic algorithm module according to an embodiment of the present invention.

[0046] Fig.11 Schematic diagram of the structure of a random number generator according to an embodiment of the present invention.

[0047] Fig.12 FIG. 4 is a schematic diagram of a linear feedback shift register (LFSR) according to an embodiment of the present invention.

[0048] Fig.13 FIG. 4 is a schematic diagram of an embedded system according to an embodiment of the present invention.

[0049] Fig.14 FIG. 4 is a block diagram of a security chip device according to an embodiment of the present invention.

[0050] Fig.15 is a flow chart of a data processing method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0051] The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not used to limit the scope of the present invention.

[0052] A specific embodiment of the present invention discloses a data processing method. Figure 1 The data processing method includes: step S1: storing the first data stream in the first RAM; step S2: storing the second data stream in the second RAM, processing the first data stream by the algorithm unit and storing the processed first data stream in the first RAM; step S3: outputting the processed first data stream to the host computer, processing the second data stream by the algorithm unit and storing the processed second data stream in the second RAM; and step S4: outputting the processed second data stream to the host computer.

[0053] Compared with the prior art, the data processing method provided in this embodiment processes the first data stream through the algorithm unit and stores the processed first data stream in the first RAM while storing the second data stream in the second RAM, and processes the second data stream through the algorithm unit and stores the processed second data stream in the second RAM while outputting the processed first data stream to the host computer, thereby improving the utilization rate of the algorithm unit and thus improving work efficiency.

[0054] In the following, reference Figures 1 to 4 , step 1, step 2, step 3 and step 4 of the data processing method are described in detail.

[0055] refer to Figure 1 and Figure 3 , step S1: storing the first data stream in the first RAM. Specifically, it further includes inputting the first data stream via a four-wire SPI interface; and storing the first data stream in the first RAM through a RAM switching matrix.

[0056] refer to Figure 1 and Figure 3, step S2: storing the second data stream in the second RAM, and processing the first data stream through the algorithm unit and storing the processed first data stream in the first RAM. The algorithm unit may include one or more of an SM1 cryptographic algorithm module, an SM4 cryptographic algorithm module, an AES cryptographic algorithm module, a DES cryptographic algorithm module, and a Hash algorithm module. Specifically, step S104 further includes: inputting the second data stream via a four-wire SPI interface, and storing the second data stream in the second RAM through a RAM switching matrix; and at the same time, the algorithm unit obtains the first data stream from the first RAM through the RAM switching matrix, performs algorithm processing on the first data stream, and then stores the processed first data stream in the first RAM through the RAM switching matrix, wherein the algorithm processing is one of SM1, SM4, AES, and DES. In an embodiment, processing the first data stream by the algorithm unit and storing the processed first data stream in the first RAM further includes: the CPU sends a key, an operating mode and an algorithm processing start instruction to the SFR interface module through the SFR bus; the algorithm core (SM1, SM4, AES or DES core) of the algorithm unit performs algorithm processing on the first data stream based on the key, the operating mode and the algorithm processing start instruction; after the algorithm processing is completed, the algorithm completion instruction is transmitted from the SFR interface module to the CPU via the SFR bus; after the CPU completes the algorithm instruction, it generates a first RAM write instruction and configures the RAM switching matrix; and according to the first RAM write instruction, the processed first data stream is stored in the first RAM through the RAM switching matrix.

[0057] refer to Figure 1 and Figure 3, step S3: output the processed first data stream to the host computer, and process the second data stream through the algorithm unit at the same time, and store the processed second data stream in the second RAM. Specifically, it further includes: reading the processed first data stream from the first RAM through the RAM switching matrix, and then outputting the processed first data stream to the host computer via the four-wire SPI interface; and at the same time, the algorithm unit obtains the second data stream from the second RAM through the RAM switching matrix, performs algorithm processing on the second data stream, and then stores the processed second data stream in the second RAM through the RAM switching matrix. In an embodiment, processing the second data stream by the algorithm unit and storing the processed second data stream in the second RAM further includes: the CPU sends a key, an operating mode and an algorithm processing start instruction to the SFR interface module through the SFR bus; the algorithm core (SM1, SM4, AES or DES core) of the algorithm unit performs algorithm processing on the second data stream based on the key, the operating mode and the algorithm processing start instruction; after the algorithm processing is completed, the algorithm completion instruction is transmitted from the SFR interface module to the CPU via the SFR bus; after the CPU completes the algorithm instruction, it generates a second RAM write instruction and configures the RAM switching matrix; and according to the second RAM write instruction, the processed second data stream is stored in the second RAM through the RAM switching matrix.

[0058] refer to Figure 1 and Figure 3 , step S4: outputting the processed second data stream to the host computer. Further comprising: reading the processed second data stream from the second RAM through the RAM switching matrix; and outputting the processed second data stream to the host computer via the four-wire SPI interface.

[0059] The data stream to be processed is divided into a plurality of cycles, each cycle includes a first data stream and a second data stream, and the processed second data stream is output to the host computer, and the following steps are also included: obtaining the first data stream of the next cycle, and executing step S1 (refer to Fig.15 ). For example, the host computer usually divides the first data stream and the second data stream, and the first data stream and the second data stream in each cycle are usually equal, but may be unequal in some cases, and the data length of each cycle is usually equal, but may be unequal in some cases. In addition, the data stream to be processed is divided into multiple cycles, each cycle includes N data streams, and the N data streams include the first data stream and the second data stream; the N data streams in each cycle are processed by N RAMs, and the N RAMs include the first RAM and the second RAM. For example, there can be 3 RAMs, and there can be 3 data streams in one cycle; or 4 RAMs can process 4 data streams in one cycle. In order to improve data processing efficiency, multiple algorithm units can be added to process data streams in multiple RAMs at the same time.

[0060] The following takes processing of a data stream of a cycle as an example for explanation. Assuming that the time for starting to process a data stream of a cycle is T, and a data stream of a cycle includes a first data stream and a second data stream, processing a data stream of a cycle can be divided into four moments from T+0 to T+3: at T+0, the first data stream is stored in the first RAM;

[0061] At time T+1, the second data stream is stored in the second RAM, and the first data stream is processed by the algorithm unit and the processed first data stream is stored in the first RAM;

[0062] At time T+2, the processed first data stream is output to the host computer, the second data stream is processed by the algorithm unit, and the processed second data stream is stored in the second RAM; and

[0063] At time T+3, the processed second data stream is output to the host computer.

[0064] A specific embodiment of the present invention discloses a security chip device. Fig.14 The security chip device includes: a first RAM (RAM_A), a second RAM (RAM_B), an algorithm unit DES / AES / SM1 / SM2, a RAM switching matrix RAM_Matrix, a four-wire SPI interface (Quad SPI), a Hash algorithm module (HASH), a CPU, a memory management module (EMMU), a ROM, a FLASH, a SRAM, a true random number generator TRNG and a host computer. Fig.14 The host computer is arranged outside the security chip device. In an optional embodiment, the host computer can also be arranged inside the security chip device.

[0065] refer to Figure 2 , the first RAM (RAM_A) is used to store the first data stream and output the first data stream processed by the algorithm unit to the host computer. The second RAM (RAM_B) is used to store the second data stream and output the second data stream processed by the algorithm unit to the host computer. The algorithm unit DES / AES / SM1 / SM2 is used to process the first data stream and store the processed first data stream in the first RAM, and process the second data stream and store the processed second data stream in the second RAM. The host computer is located outside the security chip device. Reference Figure 4 The algorithm unit also includes one or more of the SM1 cryptographic algorithm module, the SM4 cryptographic algorithm module, the AES cryptographic algorithm module, the DES cryptographic algorithm module and the Hash algorithm module, which are used for encryption and decryption of the SM1 cryptographic algorithm, the SM4 cryptographic algorithm, the AES cryptographic algorithm, the DES cryptographic algorithm and the Hash algorithm, respectively. Figure 7The SM1 cryptographic algorithm module includes: a first SFR interface module, used to connect to the CPU via the SFR bus; a first special function register, used to control the configuration and data cache of the SM1 core; and an SM1 core, used to perform SM1 operations. Fig. 9 The SM4 cryptographic algorithm module includes: a second SFR interface module for connecting to the CPU via an SFR bus; a second special function register for controlling the configuration and data cache of the SM4 core; and an SM4 core for performing SM4 operations.

[0066] refer to Figure 4 , the RAM switching matrix can be connected to the AHB bus. The first RAM and the second RAM are directly connected to the algorithm unit via the RAM switching matrix. The RAM switching matrix is ​​used to store the first data stream and the second data stream in the first RAM and the second RAM respectively via the RAM switching matrix; the algorithm unit obtains the first data stream and the second data stream respectively via the RAM switching matrix; and stores the processed first data stream and the second data stream in the first RAM and the second RAM respectively.

[0067] refer to Figure 4 The four-wire SPI interface can connect the first RAM and the second RAM via the RAM switching matrix. The four-wire SPI interface is used to input the first data stream and the second data stream, and to output the processed first data stream and the second data stream. The transmission clock of the four-wire SPI interface is up to 100MHz, and the data transmission speed is up to 50MB / s.

[0068] The hash algorithm module is used for hashing algorithm, connected to the CPU via the AHB bus, and connected to the first RAM and the second RAM via the RAM switching matrix. Fig.10 , the Hash algorithm module further includes: an SFR interface module for connecting to the CPU via an SFR bus; a special function register for controlling the configuration and data cache of the HASH core; and a HASH core for performing HASH operations.

[0069] refer to Figure 4 The CPU is used to connect the Hash algorithm module and the algorithm unit through the AHB bus. The storage management module EMMU is used to connect the CPU through the AHB bus, and the storage management module EMMU is directly connected to the RAM switching matrix; and the storage management module EMMU is directly connected to the ROM, FLASH and SRAM.

[0070] True random number generator TRNG is used to generate random number sequences that meet security requirements for key generation and digital signature. Fig.11, TRNG further includes: TRNG0 is a switching voltage structure; TRNG1, TRNG2 and TRNG3 are switching current structures; a first XOR gate XOR, XORing the outputs of TRNG0, TRNG1, TRNG2 and TRNG3 to generate a parallel random number noise source seed; a supplementary random number generator, used to generate a supplementary random number according to a supplementary seed or a feedback random number, wherein the supplementary seed is used for the first time, and the feedback random number is used subsequently; a random number seed generator, used to generate a random number seed according to the output of the first XOR gate and the supplementary random number; a linear feedback shift register LFSR, used to receive a random number seed and shift the random number seed to generate a plain text and a key; and a RNG2 module, used to perform an SM4 operation on the plain text and the key to generate a random number.

[0071] In the following, reference Figures 2 to 12 , a security chip device and a data processing method are described in detail by way of specific examples.

[0072] 1. Chip Architecture

[0073] The security chip uses the ARM SC000 CPU core to achieve central control, and the program storage space is in 36KB ROM and 256KB FLASH on the chip. The program variables are temporarily stored in the system SRAM, which is 32KB in size. The CPU can access the control registers of each IP through the system bus, thereby scheduling each IP to complete specific work. The system provides interrupt and DMA services to achieve fast response to IP requests and fast data transmission.

[0074] refer to Figure 1 , each module in the functional block diagram is described as follows:

[0075] CPU, based on ARM's 32-bit secure CPU core - SC000;

[0076] AHB bus, used to transmit data and instructions;

[0077] APB slow bus, used to transmit data and instructions;

[0078] EMMU storage management module, used to implement memory mapping, and perform authority management on chip management programs / data, factory codes, cryptographic operation unit programs, and user programs;

[0079] DMA, direct access control unit, is used to directly access data between the storage unit and each cryptographic operation unit;

[0080] ROM (Read Only Memory) is a memory that stores programs. It has the characteristic of being non-rewritable, that is, the program is fixed into the chip during the chip manufacturing process and cannot be rewritten during the use of the chip;

[0081] RAM and register files are memories that store intermediate data that the CPU runs;

[0082] FLASH is a non-volatile memory that stores user programs and data;

[0083] RAM_Matrix, connected to the AHB bus, through which the CPU and cryptographic operation unit can directly access the data in SPI_Buffer;

[0084] DES cryptographic algorithm module, which implements the encryption and decryption functions of the DES cryptographic algorithm;

[0085] AES cryptographic algorithm module, which implements the encryption and decryption functions of the AES cryptographic algorithm;

[0086] The PKU coprocessor implements large number modular addition, modular subtraction, modular multiplication, modular exponentiation and other operations, as well as large number modular multiplication and elliptic curve point operations;

[0087] SM1 cryptographic algorithm module, which implements the encryption and decryption functions of the SM1 cryptographic algorithm;

[0088] SM4 cryptographic algorithm module, which implements the encryption and decryption functions of the SM4 cryptographic algorithm;

[0089] The HASH algorithm module implements the operation of key functions of the hash algorithm;

[0090] CKMU clock control unit, used to set the operating frequency of the system and cryptographic algorithm module;

[0091] RST is a power-on and power-off reset, generating a reset signal for all circuit modules in this chip;

[0092] PWMU power management unit, power on and off and power consumption control;

[0093] FD\VD\TD abnormal detection circuit, which can detect external power supply voltage, temperature, and frequency to prevent illegal attacks;

[0094] CRC module, used to implement CRC16 data verification;

[0095] TIMER counter / timer, which can be used as a counter or timer, is a functional component of a commonly used microcontroller;

[0096] WDT watchdog module can realize the watchdog reset function;

[0097] TRNG true random number generator, a total of four channels, used to generate random number sequences that meet security requirements. Random numbers are used for important functions such as key generation and digital signatures;

[0098] MSEQ module, which implements the digital post-processing function of random numbers;

[0099] OSC internal oscillator is the clock source of this chip;

[0100] SPI interface, to achieve high-speed data transmission with microcontroller or other devices;

[0101] I 2 C interface, realizes I2C protocol interface function, and can connect external I2C interface devices;

[0102] GPIO interface, which realizes the common communication functions of microcontrollers such as external interrupt;

[0103] 2. Working Principle

[0104] The security chip mainly implements the security functions of multiple identity authentication and data symmetric encryption based on the national secret algorithm. It can meet the needs of IoT terminals such as embedded devices and provide cross-platform network identity authentication solutions.

[0105] The chip is designed based on the AHB and APB dual-bus architecture, uses an ARM security processor, is equipped with abundant FLASH and RAM space, supports cryptographic operation units such as SM1, SM2, SM3, SM4, SHA-256, RSA, and multiple communication interfaces such as high-speed SPI, I2C and GPIO. It can be used for security module units of IoT devices and has a high level of security protection.

[0106] 1. CPU processor

[0107] The chip uses the ARM SC000 processor core. SC000 is a 32-bit SecureCore microprocessor based on the ARM Cortex-M0 processor, using a 3-stage pipeline Von Neumann architecture. It achieves extremely high code efficiency through a simple and powerful instruction set and a fully optimized design (providing high-end processing hardware including a single-cycle multiplier).

[0108] The SC000 processor is based on the ARMv6-M architecture and uses the 16-bit Thumb2 instruction set, providing the performance of a 32-bit processor with higher code density than other 8-bit and 16-bit microcontrollers.

[0109] The SC000 processor tightly integrates a configurable nested vector interrupt processor (NVIC), which has the following functions: contains a non-maskable interrupt (NMI); provides 32 maskable interrupt sources (IRQ); provides 4 configurable interrupt priority levels.

[0110] The close integration of the processor core and NVIC allows the interrupt service routine (ISR) to execute quickly, greatly reducing interrupt latency. The interrupt handler does not require any assembly wrapper code and does not consume any ISR code. The tail chain optimization also greatly reduces the overhead when switching from one ISR to another. In order to optimize low-power design, NVIC is also combined with the sleep mode (WIC), which can quickly wake up from the sleep mode through an interrupt.

[0111] SC000 is combined with the chip system to implement safety features such as register verification, system polarity control, jump instruction normalization, and register group clearing after interruption.

[0112] 2. Memory

[0113] (1)ROM

[0114] The chip has an embedded 36KB ROM memory, which uses data and address encryption to store the chip boot firmware program. It is responsible for hardware testing, self-testing, and user COS downloading. This area is only visible in CMS mode and is invisible in other modes.

[0115] (2) RAM

[0116] The RAM in the chip that can be used directly by the CPU is 32KB SRAM.

[0117] 32K SRAM supports 8, 16, and 32-bit access. In order to enhance the security of chip RAM data, the address and data of SRAM are scrambled. The encryption scrambling key is regenerated every time the chip is powered on and is unpredictable. In addition, RAM data supports 1:1 data verification, and the starting address and size of the verification area can be set.

[0118] (3) Flash

[0119] The on-chip FLASH is a 256KB Nor Flash used to store code and data. The features of the on-chip Flash are as follows: 1) The maximum read frequency is 40MHz; 2) Supports 8 / 16 / 32-bit read operations and 8-bit write operations of FLASH; 3) Supports FLASH read, chip erase, page erase, and byte write; 4) Supports Flash address scrambling; 5) Supports Flash data reordering.

[0120] In order to improve data security, Flash address and data can be scrambled. Flash address scrambling is implemented within the range of 512Byte.

[0121] Flash erase and programming operations are implemented through the system control register. During the Flash erase and programming operations, the CPU clock will be stopped and the program cannot be executed until the erase and programming operations are completed.

[0122] 3. Memory Management Unit MMU

[0123] In order to enhance the security performance of the system, an MMU module is added to implement memory mapping, and perform permission management on chip management programs / data, factory codes, cryptographic operation unit programs, and user programs.

[0124] The security algorithm program is fixed at a fixed address in FLASH during the chip production stage, and has security algorithm permissions. After it takes effect, the user application mode cannot be changed. The application mode can only call the corresponding function through the specified interface provided by the cryptographic operation unit program. Any read, write, and erase operations will cause CPU abnormalities.

[0125] After the chip is externally reset, the program in the chip management program area will be executed first to complete the necessary system configuration, security management, self-test and user COS download functions, and then exit the chip management program through soft reset and enter the user program.

[0126] The chip provides three working modes for users, namely security algorithm mode, super user mode and normal user mode. In different modes, the permissions for accessing system resources are different. As shown in the following table:

[0127] Table 1 Storage management permissions

[0128]

[0129] 4. OSC clock

[0130] Internal Oscillator: can generate 58MHz high-frequency clock for normal system operation, and can also generate 400KHz low-frequency clock for low power consumption control;

[0131] 5. RST reset

[0132] It can be mainly divided into three categories: power-on reset, software reset and hardware reset: power-on reset; hardware reset: including power-on reset; pin reset in test mode; sensor abnormality reset (voltage, frequency, temperature, voltage glitch abnormality detection); watchdog reset; safety function detection reset; software reset: the CPU can generate software reset by setting registers.

[0133] 6.TIMER

[0134] (1) Functional description: 4 16 / 32-bit timers; 3 configurable working modes; 3 pre-divided timer clocks; interrupt output; each timer can count the chip CPU clock; supports counting the divided frequency (16 / 256 division) of the chip CPU bus clock / external asynchronous pulse signal.

[0135] (2) Design principle: The internal working registers of TIMER include: timer control register TimerControl, timer initial value register TimerLoad, timer current count value register TimerValue and timer interrupt status register TimerIS. By configuring the timer control register TimerControl, the three working modes can be switched. Working mode 0 is the cyclic mode. When the count value overflows, the timer interrupt status register TimerIS is set and the timer initial value register TimerLoad is reloaded to the counter to continue counting. Working mode 1 is the one-shot mode. When the count value overflows, the timer interrupt status register TimerIS is set and counting stops.

[0136] 7. Interruptions

[0137] Interrupts are a way for the CPU to exchange information with peripherals. The introduction of interrupts solves the speed coordination problem between the CPU and peripherals, improves the execution efficiency of the CPU, and enables embedded software to process peripheral data in real time.

[0138] The chip provides an interrupt controller unit to centrally manage all external event interrupts on the system integration. The chip provides a total of 23 maskable interrupt sources IRQ and 1 non-maskable interrupt NMI, and provides 4 levels of configurable priority interrupt nesting to optimize interrupt processing performance.

[0139] The chip provides an interrupt controller unit to centrally manage all interrupts on the system integration.

[0140] Up to 23 maskable event interrupt sources are connected to the CPU input signal IRQ. These interrupts can be configured to be masked or enabled through registers; the system abnormal interrupt source NMI source cannot be masked by the system. This interrupt has the highest priority and can interrupt any other interrupt; 4 levels of configurable priority interrupt nesting are provided to optimize interrupt processing performance.

[0141] 8. Communication interface

[0142] (1) SPI interface

[0143] Functional description: Full-duplex synchronous serial interface, SPI interface; Support Slave operation mode; Support Mode0 (CPOL = 0, CPHA = 0) configuration; Support the configuration of the transmission order within the byte as MSB or LSB priority transmission; Support configurable transmission length (1 to 2112 bytes) at a time; Support Normal, Dual, Quad port three connection mode selections. The SPI_CLK transmission clock supports a maximum of 100MHz.

[0144] Design principle: reference Figure 2 The spi_sett_if module is the communication logic between the chip main control CPU and the IP, which implements functions such as address decoding, register definition, register reading and writing; the Spi_transactor module is the SPI communication transmission module, which contains two 4-Bytes cache buffers. RAM is used to store data to be sent and received.

[0145] (2)I 2 C-Mount

[0146] Functional description: Master / Slave mode; software programmable slave address; software programmable clock frequency; can generate Start / Stop / Repeated Start / Acknowledge; can detect Start / Stop / Repeated Start; support 7 / 10-bit address; Time out function; software programmable maximum time of effective SCL low level; support S / F mode; maximum supported frequency 400Khz; support clock wait state generation and clock stretching; support clocksynchronization; do not support HS mode; do not support automatic conversion to Slave mode after Master mode loses arbitration;

[0147] Design principle: reference Figure 5 The processor_interface module is the communication logic between the chip main control CPU and the IP, which implements functions such as timing conversion, address decoding, register definition, register reading and writing, etc. 2 The c_core module implements the physical layer of the I2C protocol, including I2C bus status detection, I2C bus timing generation and other functions.

[0148] (3)GPIO interface

[0149] Functional description: Supports 9 bidirectional IOs to communicate with the outside world; all GPIO ports can be configured as input or output; when GPIO is used as an input port, it supports high level, low level, rising edge, falling edge, and double edge trigger interrupts;

[0150] Design principle: reference Figure 6 The interface module implements the control / configuration interface and status feedback interface between the interface IP and the CPU; the synchronization logic (sync) implements the asynchronous processing logic from the external asynchronous interface signal to the internal signal of the chip; the Process module implements the corresponding functions according to the different configurations of the CPU to the IP.

[0151] 9. Algorithm module

[0152] (1) SM1 algorithm module

[0153] Function description: Support ECB, CBC, CFB and OFB working modes; support 8 rounds, 10 rounds, 12 rounds and 14 rounds of operation optional; system parameter SK can use internal inherent parameters, internal and external combined parameters or external input parameters; initial vector IV value can be configured in CBC, CFB and OFB working modes; support anti-high-order DPA function.

[0154] Design principle: reference Figure 7 The first SFR interface module 702 implements the conversion of the interface timing; the first special function register module 704 implements the control configuration and data cache of the SM1 core; the SM1 core 706 is controlled by its internal state machine to implement the SM1 protocol.

[0155] (2)PKU algorithm module

[0156] Functional description: The PKU coprocessor is used to implement RSA modular addition, modular subtraction, modular multiplication and modular exponentiation functions, as well as ECC / SM2 modular addition, modular subtraction, modular multiplication, point addition and point multiplication functions. The software accesses them through the PKURAM, PKUCMD, PKUMC0, PKUMC1, PKUSEGN, PKUEXP and PKUINT registers; the operation data is written into the internal data buffer of the PKU coprocessor through the PKURAM register, and the operation result is read out from the internal data buffer of the PKU coprocessor through the PKURAM register; the internal data buffer is defined by configuring the PKUCMD register, and the operation status is determined by the PKUCMD register; the 64-bit Montgomery Constant is defined by writing PKUMC twice; the number of operation bits (in 64 bits) is defined by configuring the PKUSEGN register, and the RSA operation can support up to 2048 bits, and the ECC operation can support up to 256 bits; the 32-bit modular exponent is defined by configuring the PKUEXP register; the internal data buffer is inaccessible during the PKU operation;

[0157] Design principle: reference Figure 8, dual-port RAM can be read and written from the AHB bus, registers such as mc, SegN, e_reg and cmd can be written, and the ready_busy flag can be read. The mc register stores the Montgomery constant, and e_reg is the highest bit data register of the exponent register. The cmd is the command control word register (ECC) of the master CPU, and the RAM is a 128X64bit dual-port SRAM. The MultiMod module is the core module for implementing operations. ModOpFSM controls the MultiMod module to implement the internal Montgomery operations between large integers, and pkuFSM controls the ModOpFSM module to complete modular addition, modular subtraction, modular multiplication, modular exponentiation, and point addition and point multiplication operations of ECC operations. After the operation is completed, PKU sends an interrupt signal to the CPU, or the CPU continuously reads the status word in the algorithm chip, queries the sfr register flag and waits for the operation to be completed, and then the master CPU reads the operation result from the chip.

[0158] (3) SM4 algorithm module

[0159] Function description: Supports ECB, CBC, CFB and OFB working modes; supports query mode; supports hardware anti-DPA; complies with "GM / T 0002SM4 Block Cipher Algorithm".

[0160] Design principle: This algorithm module can prevent timing attacks. The algorithm hardware engine implements operations strictly according to the number of rounds defined by the SM4 algorithm standard. Each round of operation has a fixed number of clock cycles and is independent of the external input data (including plaintext, ciphertext, and key).

[0161] This algorithm module is specially protected against side channel attacks. The entire operation chain of SM4 is protected. The input data is first randomized. When the SBOX is transformed, the SBOX is transformed accordingly. Finally, all the data on the entire SM4 operation chain is random until the final result is output. SM4 encryption and decryption requires 32 rounds of operations. Before each round of operation, two 8-bit random numbers will be used to mask the S-boxes in this round of operation. Therefore, in a single SM4 encryption and decryption operation, the S-boxes used between rounds are different. For a single round of SM4 encryption and decryption, 4 S-boxes are required to process 32 bits of data. This chip uses four identical masked S-boxes to process 32 bits of data in parallel.

[0162] refer to Fig. 9 The second SFR interface module 902 implements the conversion of the interface timing; the second special function register module 904 implements the control configuration and data cache of the SM4 core; the SM4 core 906 implements the SM4 protocol through its internal state machine control.

[0163] (4) HASH algorithm module

[0164] Function description: Realize hardware HASH operation function, support SM3 and SHA-256 HASH algorithms; support 32-bit dual-port SRAM interface; support interrupt and query mode; comply with the "SM3 Cryptographic Hash Algorithm" standard and "FIPS PUB 180-2" SHA-256 standard.

[0165] Design principle: The chip integrates a secure hash algorithm HASH operation module, provides hardware HASH operation function, and supports two HASH algorithms: SM3 and SHA-256.

[0166] refer to Fig.10 The internal structure of IP mainly includes HASH core, SFR interface module, SRAM interface module and special function registers, etc. The functions of each component are as follows: HASH core: realize HASH operation function (SM3 and SHA-256); SFR interface module: communication interface with external controller, supporting 8 / 16 / 32-bit operation; SRAM interface module: dual-port SRAM with external 32-bit data bus, supporting 32X32-bit dual-port SRAM, storing operation data and results; special function registers: storing control information.

[0167] 10. Random Number Generator

[0168] Random numbers are a basic element of physical security mechanisms and an indispensable part of cryptographic applications.

[0169] The random number generator is divided into two parts: the true random number (TRNG) generator and the digital post-processing circuit (MSEQ). The true random number generator generates a random seed and sends it to the post-processing circuit. The software reads the post-processing result to obtain a random number. The software can also directly write the RNGIN register as the seed for random number generation.

[0170] The chip has four built-in noise source generators. Based on chaos theory, it uses two different circuit architectures: switch current structure and switch voltage structure. They are implemented independently of each other, and it can be considered that the two types of random sources have excellent independence. By combining physical random sources with digital post-processing, high-quality random numbers with uniform distribution, no relation to sequence, and long period can be generated.

[0171] Fig.11 The overall design scheme framework diagram of random number generation of the chip is shown. The hardware automatically collects the serial random numbers generated by the random number noise source, and after serial conversion, enters the digital post-processing circuit for processing, and the software reads the processing results.

[0172] The digital post-processing circuit consists of two parts: a linear feedback shift register (LFSR) and an SM4 algorithm.

[0173] refer to Fig.11 The method of extracting 64 to 48 bits of the feedback random number is to remove bit3 every 4 bits and retain bit0 to bit2. Fig.11 In the physical noise source part, TRNG0 is designed as a switch voltage structure, and TRNG1 / TRNG2 / TRNG3 is designed as a switch current structure. Four independent physical noise sources generate four serial random number bit streams respectively. The following digital circuit converts the four serial bit streams into serial-to-parallel, and then generates four independent 48-bit parallel random numbers. Then, a set of 48-bit random numbers is generated by bitwise XOR processing, and finally sent to the LFSR circuit for subsequent processing. The frequency of the random number output by the physical noise source is about 1MHz, and the frequency of the digital post-processing circuit is 58MHz at the fastest and 2MHz at the slowest. Even if the frequency of the post-processing circuit is faster, the design ensures that the digital post-processing circuit is started to use the 48-bit random number seed only after the 48-bit random number seed is generated, so that the output of the physical noise source will not be used unreasonably due to frequency deviation.

[0174] In addition, in order to ensure the effectiveness of the output of the physical noise source, the output of the physical noise source will be self-checked. There are two self-checking methods: one is to check the abnormal output of all 0s or all 1s of the TRNG0 / 1 / 2 / 3 modules respectively; the other is to collect 128 or 1024-bit data output by the TRNG0 / 1 / 2 / 3 modules respectively, and check the ratio of the number of 1s (optional 1 / 16, 1 / 8, 1 / 4, 3 / 8). If it is less than this ratio, it will be considered as an abnormal output.

[0175] The seed of the digital post-processing circuit is generated by a combination of true random numbers and supplementary random numbers, where the true random number is generated by the on-chip physical noise source, and the outputs of the four physical noise sources are XORed and enter the subsequent circuit; the supplementary random number is generated based on the supplementary seed and the feedback random number, where the supplementary seed is generated according to the factory code when the BootLoader is powered on and initialized, and is set into the random number module and is only performed once; the feedback random number is generated based on the previous random number operation data and is updated once each random number generation is completed.

[0176] After the seed is generated, it enters the linear feedback shift register (LFSR), which has the following advantages: the LFSR structure is simple and very suitable for hardware implementation; it runs fast; it can generate large period sequences with a length of up to 248 bits; it can generate sequences with good statistical properties, that is, each bit in the sequence is nearly evenly distributed.

[0177] Fig.12The circuit structure diagram of the linear feedback shift register (LFSR) is shown in FIG. The LFSR uses a 48-stage linear feedback shift register, and its feedback primitive polynomial is: f(x) = X48 + X7 + X5 + X4 + X2 + X+1.

[0178] The initial seed value of LFSR can be set by software, and the seed is selected from random data generated by a random number noise source. In circuit implementation, x0-x47 is implemented with registers, and the XOR circuit is implemented with a combinational circuit.

[0179] The RNG2 module uses the SM4 algorithm to further process the data output by the LFSR to make the random characteristics of the output random numbers better.

[0180] Random number generation process

[0181] The process of generating random numbers required by the cryptographic algorithm is as follows:

[0182] 1) The four independent random numbers generated by the four independent physical noise sources are processed by serial-to-parallel conversion, XOR merging, etc. to obtain a 48-bit parallel random number noise source seed.

[0183] 2) The hardware uses the collected 48-bit serial random number noise source seed to perform XOR processing with the 48-bit random number seed input by the software (the first use, and then the SM4 operation intermediate result is used to perform XOR with the random number noise source seed), and provides it to the LFSR for processing. After 256 system clock cycles, the 128-bit plaintext and 128-bit KEY required for the SM4 operation are generated;

[0184] 3) After receiving the required plaintext and KEY, the RNG2 module automatically starts the operation. After 32 system clock cycles, it generates a 128-bit calculation result, and then uses the highest and lowest 64-bit vectors to perform XOR, output a 64-bit vector, generate a DONE signal, and notify the software to read the random number;

[0185] 4) After the software finishes reading the 64-bit random number, the hardware automatically starts generating the next round of 64-bit random numbers;

[0186] 5) The software performs XOR on the 64-bit random number generated by the hardware, and finally outputs a 32-bit random number for the algorithm to use;

[0187] 3. Data processing flow

[0188] The data processing flow supports the following normal mode and Pipeline mode.

[0189] Normal mode:

[0190] Step 1, the Quad SPI interface inputs the data stream and stores it in RAM_A;

[0191] Step 2, the CPU parses the data in RAM_A;

[0192] Step 3: If the data is parsed as COS data, the CPU configures the RAM_Matrix path and DMA to write the data in RAM_A to the Flash through the AHB bus.

[0193] Step 4: If the data is parsed as symmetric algorithm data or hashed data, the CPU configures the RAM_Matrix path, configures the corresponding algorithm unit, starts the algorithm, and stores the data into RAM_A after the algorithm module completes the processing;

[0194] Step 5, if the data is parsed as asymmetric algorithm data, the CPU configures the RAM_Matrix path, configures the DMA, and writes the data in RAM_A to the RAM corresponding to PKU through the AHB bus. After the data is ready, the CPU configures and starts the PKU algorithm module. After the algorithm module completes the processing, the CPU configures the DMA to store the data in RAM_A through the AHB bus.

[0195] Step 6, the CPU frames the data in RAM_A and outputs it through the Quad SPI interface;

[0196] Pipeline mode:

[0197] It mainly targets symmetrically encrypted data and performs security algorithm processing while the interface transmits data, which greatly saves waiting time and improves the chip's ability to process data. Figure 3 , the process is as follows:

[0198] Step 1, at time T+0, the Quad SPI interface inputs data stream X1 and stores it in RAM_A;

[0199] Step 2, at time T+1, the Quad SPI interface inputs data stream X2, the algorithm unit (SM1 or SM4) processes data stream X1, and stores the processed data in RAM_A;

[0200] Step 3, at time T+2, the Quad SPI interface reads data stream X1 from RAM_A and outputs it to the host computer; the algorithm unit (SM1 or SM4) processes data stream X2 and stores the processed data in RAM_B;

[0201] Step 4: At time T+3, the SPI interface reads data stream X2 from RAM_B and outputs it to the host computer;

[0202] Table 2 Pipeline mode data processing

[0203]

[0204] 4. Innovative Technology

[0205] The innovations of the present invention are as follows: (1) It is the first domestic security chip to adopt a high-speed four-wire SPI interface, with a transmission clock of up to 100 MHz and an interface data transmission rate of 50 MB / s; (2) High-speed data stream encryption: It adopts optimized SM1 and SM4 symmetric encryption algorithm units and a high-speed four-wire SPI interface and dual BUFFER (RAM_A and RAM_B) cache to facilitate pipeline data transmission. The algorithm unit directly accesses data from the BUFFER without passing through the bus, and the encryption and decryption data processing rate can reach 40 MB / s; (3) The SM2 signature times are 307 times / second @58 MHz, and the verification times are 177 times / second @58 MHz (actual measured speed), which are higher than similar domestic products; (4) Four noise source generators are arranged inside the chip. Based on chaos theory, two different circuit architectures, namely a switch current structure and a switch voltage structure, are adopted to achieve excellent independence. By combining a physical random source with digital post-processing, it generates high-quality random numbers that are uniformly distributed, independent of the sequence, and have a long period. It has passed the security chip password detection test; (5) QFN32 package, 5x5mm^2 small area, saving PCB space; (6) Low cost and low power consumption.

[0206] Another specific embodiment of the present invention discloses an embedded system. Fig.13The embedded system includes: the above-mentioned security chip device, SD card, SD card controller (SD controller, SDC for short) and Nandflash memory. The SD card is used to store data streams, wherein the data streams include a first data stream and a second data stream; the SD interface (SDInterface) is SD I / F, which is used for the SD card to communicate with an external device; and the SD card controller is used to transmit the data stream to be encrypted to the security chip device through a four-wire SPI interface so as to encrypt the data stream to be encrypted therein, or to store the decrypted data stream from the security chip device to the SD card through a four-wire SPI interface; wherein the security chip device and the SD card controller are arranged in the SD card. The Nandflash memory is arranged in the SD card, and the Nandflash memory includes a security area, a hidden area and a security area, wherein the SD card controller is also used to store the encrypted data stream to the Nandflash memory through an NF I / F interface (NadFlash Interface, i.e., NadFlash interface), or to transmit the encrypted data stream to be decrypted to the security chip device through a four-wire SPI interface so as to decrypt the encrypted data stream to be decrypted therein. Security chip devices are typically used in embedded systems and can be directly used as security modules to complete functions such as identity authentication, encryption and decryption.

[0207] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0208] 1. Processing the first data stream by the algorithm unit and storing the processed first data stream in the first RAM while storing the second data stream in the second RAM, and processing the second data stream by the algorithm unit and storing the processed second data stream in the second RAM while outputting the processed first data stream to the host computer, can improve the utilization rate of the algorithm unit, thereby improving work efficiency.

[0209] 2. The data stream is input or output from the security chip device through the four-wire SPI interface, so that the interface data transmission rate reaches 50MB / s.

[0210] 3. Compared with the bus, the algorithm unit directly obtains data from the first RAM or the second RAM through the RAM switching matrix, or stores the processed data in the first RAM or the second RAM, so that the encryption and decryption data processing rate can reach 40MB / s.

[0211] 4. The security chip device has four noise source generators inside, which use two different circuit architectures: switch current structure and switch voltage structure, with excellent independence. It uses a combination of physical random source and digital post-processing to generate high-quality random numbers with uniform distribution, no relation to sequence, and long period.

[0212] 5. The security chip device adopts QFN32 package, and the chip area is 5x5mm 2 Small, saving PCB space.

[0213] Those skilled in the art will appreciate that all or part of the processes of the above-mentioned embodiments can be implemented by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, wherein the computer-readable storage medium is a disk, an optical disk, a read-only storage memory, or a random access memory, etc.

[0214] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A data processing method, characterized in that: include: The data stream to be processed is divided into multiple cycles, each cycle includes a first data stream and a second data stream, and the data stream processing of one cycle is divided into four time points from T+0 to T+3. Step S1: at time T+0, storing the first data stream in the first RAM, wherein storing the first data stream in the first RAM further comprises: inputting the first data stream via a four-wire SPI interface; and storing the first data stream in the first RAM through a RAM switching matrix; Step S2: at time T+1, the second data stream is stored in the second RAM, and at the same time, the first data stream is processed by the algorithm unit and the processed first data stream is stored in the first RAM; Step S3: at time T+2, outputting the processed first data stream to the host computer, processing the second data stream by the algorithm unit, and storing the processed second data stream in the second RAM; and Step S4: at time T+3, outputting the processed second data stream to the host computer, wherein outputting the processed second data stream to the host computer further comprises: reading the processed second data stream from the second RAM through a RAM switching matrix; and outputting the processed second data stream to the host computer via a four-wire SPI interface; Wherein, while the processed second data stream is output to the host computer, the first data stream of the next cycle is obtained and the step S1 is executed.

2. The data processing method according to claim 1, characterized in that: Storing the second data stream in the second RAM, while processing the first data stream by the algorithm unit and storing the processed first data stream in the first RAM further comprises: Input the second data stream via a four-wire SPI interface, and store the second data stream in the second RAM through a RAM switch matrix; and At the same time, the algorithm unit obtains the first data stream from the first RAM through the RAM switching matrix, performs algorithm processing on the first data stream, and then stores the processed first data stream in the first RAM through the RAM switching matrix.

3. The data processing method according to claim 1, characterized in that: Outputting the processed first data stream to the host computer, processing the second data stream by the algorithm unit, and storing the processed second data stream in the second RAM further includes: Reading the processed first data stream from the first RAM through the RAM switching matrix, and then outputting the processed first data stream to the host computer via a four-wire SPI interface; and At the same time, the algorithm unit obtains the second data stream from the second RAM through the RAM switching matrix, performs algorithm processing on the second data stream, and then stores the processed second data stream in the second RAM through the RAM switching matrix.

4. The data processing method according to claim 2, characterized in that: Processing the first data stream by the algorithm unit and storing the processed first data stream in the first RAM further comprises: The CPU sends the key, working mode and algorithm processing start instruction to the SFR interface module through the SFR bus; The algorithm core of the algorithm unit performs algorithm processing on the first data stream based on the key, the working mode and the algorithm processing start instruction; After the algorithm processing is completed, transmitting the algorithm completion instruction from the SFR interface module to the CPU via the SFR bus; After the CPU completes the instruction according to the algorithm, it generates a first RAM write instruction and configures the RAM switching matrix; and According to the first RAM write instruction, the processed first data stream is stored in the first RAM through the RAM switching matrix.

5. The data processing method according to claim 3, characterized in that: Processing the second data stream by the algorithm unit and storing the processed second data stream in the second RAM further comprises: The CPU sends the key, working mode and algorithm processing start instruction to the SFR interface module through the SFR bus; The algorithm core of the algorithm unit performs algorithm processing on the second data stream based on the key, the working mode and the algorithm processing start instruction; After the algorithm processing is completed, transmitting the algorithm completion instruction from the SFR interface module to the CPU via the SFR bus; After the CPU completes the instruction according to the algorithm, it generates a second RAM write instruction and configures the RAM switching matrix; and According to the second RAM write instruction, the processed second data stream is stored in the second RAM through the RAM switching matrix.

6. A security chip device, characterized in that: Used to implement the data processing method according to claim 1, comprising a first RAM, a second RAM, and an algorithm unit, wherein: The first RAM is used to store the first data stream and output the first data stream processed by the algorithm unit to the host computer; The second RAM is used to store the second data stream and output the second data stream processed by the algorithm unit to the host computer; The algorithm unit is used to process the first data stream and store the processed first data stream in the first RAM, and process the second data stream and store the processed second data stream in the second RAM. The host computer is located outside the security chip device.

7. The security chip device according to claim 6, characterized in that: Also includes: A RAM switching matrix is ​​connected to the AHB bus, and the first RAM and the second RAM are connected to the algorithm unit via the RAM switching matrix, and are used for: storing the first data stream and the second data stream in the first RAM and the second RAM respectively; The algorithm unit obtains the first data stream and the second data stream respectively via the RAM switching matrix; as well as The processed first data stream and the processed second data stream are stored in the first RAM and the second RAM respectively.

8. The security chip device according to claim 7, characterized in that: Also includes: CPU, used for connecting the Hash algorithm module and the algorithm unit through the AHB bus; A memory management module EMMU, used for connecting to the CPU via the AHB bus, and the memory management module EMMU is directly connected to the RAM switch matrix; and The memory management module EMMU is directly connected to ROM, FLASH and SRAM.

9. An embedded system, characterized in that: include: The security chip device according to any one of claims 6 to 8.

10. The embedded system according to claim 9, characterized in that: Also includes: An SD card, used for storing data streams, wherein the data streams include the first data stream and the second data stream; and An SD card controller, configured to transmit the data stream to be encrypted to the security chip device through the four-wire SPI interface so as to encrypt the data stream to be encrypted therein, or to store the decrypted data stream from the security chip device to the SD card through the four-wire SPI interface; Wherein, the security chip device and the SD card controller are arranged in the SD card.

11. The embedded system according to claim 10, characterized in that: Also includes: A Nandflash memory is provided in the SD card, wherein the Nandflash memory includes a security area, a hidden area and a safe area, wherein: The SD card controller is also used to store the encrypted data stream in the Nandflash memory through the NF I / F interface, or transmit the encrypted data stream to be decrypted to the security chip device through the four-wire SPI interface to decrypt the encrypted data stream to be decrypted therein.

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