Memory refresh operation using reduced power

Abstract

This application relates to memory refresh operations using reduced power. The technology described herein relates to protecting at least a portion of data stored in a memory array. A method can include detecting an invalid memory access request based at least in part on a secret key and an identifier, and preventing unauthorized access of a memory array by stopping internal refresh of one or more memory cells associated with the memory array in response to detecting the invalid memory access request.

Description

Technical Field

[0001] This disclosure relates generally to memory devices, and more specifically to memory refresh operations for storing data stored in the memory device. Background Technology

[0002] This section is intended to introduce the reader to various aspects that may relate to the various aspects of the invention described and / or claimed below. It is believed that this discussion will help provide the reader with background information to facilitate a better understanding of the various aspects of this disclosure. Therefore, it should be understood that these statements are to be read in this regard and not as an admission of prior art.

[0003] Typically, a computing system includes processing circuitry such as one or more processors or other suitable components, and memory devices such as chips or integrated circuits. One or more memory devices may be implemented on a memory module as part of a memory array, such as dynamic random access memory (DRAM) devices used on a dual in-line memory module (DIMM), to store data accessible to the processing circuitry. For example, based on user input to the computing system, the processing circuitry may request the memory module to retrieve data corresponding to the user input from its memory devices. In some cases, the retrieved data may contain instructions executable by the processing circuitry to perform operations and / or may contain data used as input to the operations. Furthermore, in some cases, data output from the operations may be stored in memory, for example, to enable subsequent retrieval. These memory devices may include storage circuitry that will be periodically refreshed via memory refresh operations (e.g., refresh operations) to maintain the data stored via the memory devices. However, refresh operations may consume undesirable amounts of power. Summary of the Invention

[0004] One aspect relates to an apparatus. The apparatus includes: a plurality of memory banks, including a first memory bank and a second memory bank, wherein each memory bank includes a plurality of memory circuits and is configured to store information; and a first sub-memory bank logic circuit communicatively coupled to the first and second memory banks via a multiplexer, wherein the first sub-memory bank logic circuit transmits control signals to the second and first memory banks when the multiplexer is operated to allow the sharing of control signals between the first and second memory banks.

[0005] On the other hand, a method is involved. The method includes: performing a memory operation via a first memory bank logic circuit; receiving an instruction to initiate a refresh operation via the first memory bank logic circuit; receiving an instruction to operate in a reduced power operation via the first memory bank logic circuit; and transmitting a refresh control signal via the first memory bank logic circuit to a multiplexer coupled between the first memory bank logic circuit, a second memory bank logic circuit, and the memory bank to initiate a reduced power refresh operation, wherein the reduced power refresh operation causes the power supplied to the second memory bank logic circuit to be reduced during a refresh of the memory bank.

[0006] Another aspect relates to a system. The system includes: a memory controller; and a memory module communicatively coupled to the memory controller, wherein the memory module includes: a first memory bank logic circuit coupled to a first memory bank; a second memory bank logic circuit configured to be coupled to a second memory bank; and a switching circuit configured to, in response to a control signal from the memory controller, couple the first memory bank logic circuit to the second memory bank instead of the second memory bank logic circuit during a memory refresh operation. Attached Figure Description

[0007] A better understanding of the various aspects of this disclosure can be achieved by reading the following detailed description and referring to the accompanying drawings, in which:

[0008] Figure 1 This is a block diagram of a system-on-a-chip (SOC) that includes a storage access device, according to an embodiment.

[0009] Figure 2 According to the embodiments Figure 1 A block diagram of the system's memory array;

[0010] Figure 3 According to the embodiments Figure 1 A block diagram of a pair of memory banks in a memory array;

[0011] Figure 4 According to the embodiments Figure 3 A block diagram of the pair of memory banks, the pair of memory banks including multiplexing circuitry for sharing refresh control signals between the pair of memory banks;

[0012] Figure 5 According to the embodiment, the command controller executes the command to operate in a reduced power mode during a memory refresh operation. Figure 1 The system's process flowchart; and

[0013] Figure 6 According to the embodiments Figure 3The block diagram of the pair of memory banks is another example of a multiplexing circuit for sharing refresh control signals between the pair of memory banks. Detailed Implementation

[0014] One or more specific embodiments will be described below. For the sake of providing a concise description of these embodiments, not all features of the actual implementation are described in the specification. It should be understood that in the development of any such actual implementation, as in any engineering or design project, many implementation-specific decisions are made to achieve the developer's specific goals, such as compliance with system-related and business-related constraints, which will vary from implementation to implementation. Furthermore, it should be appreciated that this development work may be complex and time-consuming, but it remains routine design, production, and manufacturing work for those skilled in the art who will benefit from this invention.

[0015] In describing the elements of various embodiments of this disclosure, the terms "a," "an," and "the" are intended to indicate one or more elements. The terms "comprising," "including," and "having" are intended to be inclusive and indicate that additional elements may be present in addition to those listed. Furthermore, it should be understood that references to "an embodiment" or "an embodiment" of this disclosure are not intended to be construed as excluding the existence of other embodiments that also include the described features.

[0016] A computing system may include electronic devices that transmit information via electrical signals during operation. For example, the electronic devices in a computing system may include a processor communicatively coupled to memory. In this way, the processor can communicate with memory to retrieve executable instructions, retrieve data to be processed by the processor, and / or store data output from the processor. However, different types of memory may be refreshed periodically or occasionally to appropriately retain information in memory.

[0017] For example, dynamic random access memory (DRAM) devices or other types of volatile semiconductor memory devices may lose information stored in their memory circuitry over time. To counteract this degradation over time, the DRAM device can be refreshed as part of a memory refresh operation. During a memory refresh operation, portions of the DRAM device are read and rewritten in a manner that refreshes (e.g., restores) the electrical signals representing the information stored in the memory circuitry.

[0018] Similar to many operations within an electronic device, a memory refresh operation can be initiated by the device's controller and managed by subsequent logic circuitry that generates one or more additional control signals in response to the initiation of the memory refresh operation. The memory device may comprise memory banks, and groups of memory banks may be coupled to memory bank logic circuitry that generates one or more additional control signals to perform the memory refresh operation. Depending on the specific configuration of the electronic device and its DRAM components, the memory bank logic circuitry may generate unintended redundant refresh control signals.

[0019] For example, a subset of bank logic circuits can generate equivalent memory refresh control signals for different sections of the DRAM. Since at least two bank logic circuits can generate these equivalent memory refresh control signals, unintentional redundant refresh control signals can be generated. Sharing these redundant refresh control signals among sections of the DRAM can reduce the power consumption of the DRAM device and thus the power consumption of the electronic device. For example, bank logic circuits can be shared among sections of the DRAM such that at least one memory refresh control signal is shared among the banks of the DRAM to complete the memory refresh operation.

[0020] Considering the foregoing, Figure 1 This is a block diagram of an electronic device (e.g., a semiconductor memory device, such as a dynamic random access memory (DRAM) device). The electronic device may include an array of memory cells, such as memory array 10. Memory array 10 may include memory banks 12, each containing one or more memory cells. Each of memory banks 12 may include a word line (WL), a bit line (BL), and memory cells arranged at the intersections of the word line and the bit line. Memory cells may include any of several different memory medium types, including capacitive, magnetoresistive, ferroelectric, phase-change, or the like. Word line selection may be performed by row decoder 14, and bit line selection may be performed by column decoder 16. Sensing amplifiers (SAMPs) may be provided for corresponding bit lines and connected to at least one corresponding local input / output (I / O) line pair (LIOT / B), which may be coupled to at least one corresponding main I / O line pair (MIOT / B) via a transmission gate (TG) that can operate as a switch. The memory array 10 may also include board lines and corresponding circuitry for managing its operation.

[0021] The memory array 10 can use external terminals, including command and address terminals coupled to the command bus and address bus, to receive command signals (CMD) and address signals (ADDR), respectively. The memory array 10 may further include a chip select terminal for receiving chip select signals (CS), a clock terminal for receiving clock signals (CK and CKF), a data clock terminal for receiving data clock signals (WCK and WCKF), data terminals (DQ, RDQS, DBI, and DMI), and power supply terminals (VDD, VSS, VDDQ, and VSSQ).

[0022] Address signals and memory address signals from external sources can be supplied to the command and address terminals. The address signals and memory address signals supplied to the address terminals can be transmitted to the address decoder 18 via the command address input circuit 22. The address decoder 18 can receive the address signals and supply the decoded row address signal (XADD) to the row decoder 14, and the decoded column address signal (YADD) to the column decoder 16. The address decoder 18 can also receive the memory address signal (BADD) and supply it to both the row decoder 14 and the column decoder 16.

[0023] Command signals (CMD), address signals (ADDR), and chip select signals (CS) from the memory controller can be supplied to the command and address terminals. The command signals can represent various memory commands from the memory controller (e.g., access commands, which may include read and / or write commands). The chip select signal (CS) can be used to select the memory array 10 in response to the commands and addresses supplied to the command and address terminals. When the active chip select signal (CS) is supplied to the memory array 10, the command signals (CMD) and address signals (ADDR) can be decoded, and memory operations can be performed. The command signal (CMD) can be provided as an internal command signal (ICMD) to the command decoder 20 via the command address input circuitry 22. The command decoder 20 can include circuitry for decoding the internal command signal to generate various internal signals and commands for performing memory operations (such as row command signals for selecting word lines and column command signals for selecting bit lines). The internal command signal (ICMD) can also include output and input activation commands, such as timing commands (CMDCK). Command decoder 20 may further include one or more registers for tracking various counts or values ​​(e.g., counts of refresh commands received by memory array 10 and / or counts of self-refresh operations performed by memory array 10).

[0024] When a read command is issued and the row and column addresses are supplied in a timely manner, read data can be read from the memory cells in the memory array 10 specified by the row and column addresses. The read command can be received by a command decoder 20, which can provide internal commands to the I / O circuit 26 so that read data can be output from the data terminals via the read / write amplifier 28 and the I / O circuit 26 according to a clock signal. Read data can be provided at a time defined by read delay information (RL), which can be programmed in the memory array 10, such as in the mode register (…). Figure 1 (Not shown in the image). The read latency information can be defined according to the clock cycle of the clock signal (CK). For example, the read latency information can be a number of clock cycles of the clock signal (e.g., CK) after the memory array 10 receives a read command when providing associated read data.

[0025] When a write command is issued and the row and column addresses are supplied in a timely manner, write data can be supplied to the data terminals according to clock signals (e.g., WCK and WCKF). The write command can be received by command decoder 20, which can provide internal commands to I / O circuit 26 so that write data is received by the data receiver in I / O circuit 26 and supplied to memory array 10 via I / O circuit 26 and read / write amplifier 28. Write data can be written to the memory cells specified by the row and column addresses. Write data can be supplied to the data terminals at a time defined by write latency information. Write latency information can be programmed in memory array 10, such as in the mode register (…). Figure 1 (Not shown in the image). The write latency information can be defined according to the clock cycle of the clock signal (CK). For example, the write latency information can be a number of clock cycles of the clock signal (CK) after the memory array 10 receives the write command when receiving associated write data.

[0026] Power supply potentials (VDD and VSS) can be supplied to the power supply terminals. These power supply potentials (VDD and VSS) can be supplied to the internal voltage generator circuit 30. The internal voltage generator circuit 30 can generate various internal potentials (VPP, VOD, VARY, VPERI, and the like) based on the power supply potentials (VDD and VSS). The internal potential (VPP) can be used in the line decoder 14, the internal potentials (VOD and VARY) can be used in the sense amplifier included in the memory array 10, and the internal potential (VPERI) can be used in many other circuit blocks.

[0027] A power supply potential (VDDQ) can also be supplied to the power terminals. This power supply potential (VDDQ) can be supplied to the I / O circuit 26 together with the power supply potential (VSS). The power supply potential (VDDQ) can be the same as the power supply potential (VDD) in an embodiment of this technology. The power supply potential (VDDQ) can also be a different potential from the power supply potential (VDD) in another embodiment of this technology. However, a dedicated power supply potential (VDDQ) can be used for the I / O circuit 26 so that power supply noise generated by the I / O circuit 26 does not propagate to other circuit blocks.

[0028] External clock signals and complementary external clock signals can be supplied to the clock terminal and data clock terminal. External clock signals (CK, CKF, WCK, and WCKF) can be supplied to the clock input circuit 32. Some clock signals (CK and CKF, WCK and WCK) can be complementary. Complementary clock signals can have opposite clock levels and transition between opposite clock levels simultaneously. For example, when the clock signal is at a low clock level, the complementary clock signal is at a high level, and when the clock signal is at a high clock level, the complementary clock signal is at a low clock level. Furthermore, when the clock signal transitions from a low clock level to a high clock level, the complementary clock signal transitions from a high clock level to a low clock level, and when the clock signal transitions from a high clock level to a low clock level, the complementary clock signal transitions from a low clock level to a high clock level.

[0029] The input buffer included in the clock input circuit 32 can receive external clock signals. For example, when enabled by a signal (CKE) from the command decoder 20, the input buffer can receive clock signals (CK, CKF, WCK, and WCKF). The clock input circuit 32 can receive external clock signals to generate an internal clock signal (ICLK). The internal clock signal can be supplied to the internal clock circuit 34. The internal clock circuit 34 can provide various phase- and frequency-controlled internal clock signals based on the received internal clock signal and the clock enable signal (CKE) from the command address input circuit 22. For example, the internal clock circuit 34 can include a clock path that receives the internal clock signal and provides various clock signals to the command decoder 20. Figure 1(Not shown in the diagram). The internal clock circuit 34 can further provide input / output (I / O) clock signals. The I / O clock signal, used as a timing signal, can be supplied to the I / O circuit 26 to determine the output timing for reading data and the input timing for writing data. The I / O clock signal can be provided at multiple clock frequencies so that data can be output from and / or input to the memory array 10 at different data rates. A higher clock frequency may be desired when high memory speed is desired. A lower clock frequency may be desired when low power consumption is desired. The internal clock signal can also be supplied to the timing generator 36 and used to generate various internal clock signals.

[0030] The memory array 10 can be coupled to any suitable electronic device that serves as a host device, using at least a portion of the memory for temporary and / or persistent storage of information. For example, the host device may include a desktop or portable computer, a server, a handheld device (e.g., a mobile phone, tablet, digital reader, digital media player), or at least a portion of processing circuitry, such as a central processing unit, coprocessor, dedicated memory controller, or the like. The host device may sometimes be a networking device (e.g., a switch, router) or a recorder of digital images, audio, and / or video, a vehicle, appliance, toy, or any of several other products. In one embodiment, the host device may be directly connected to the memory array 10, but in other embodiments, the host device may be indirectly connected to the memory array 10 (e.g., via a network connection or through communication with an intermediate device).

[0031] As described above, the memory array 10 may contain a plurality of memory banks 12. Figure 2 This is a block diagram of a memory array 10 with memory banks 12. One or more memory banks 12 may be operatively coupled to memory bank logic circuitry 54. In this example, memory array 10 contains 32 memory banks 12; however, it should be noted that memory array 10 may contain any suitable number of memory banks 12. To perform a refresh operation, memory bank logic circuitry 54 receives at least one refresh control signal from command controller 56. Command controller 56 may be control or processing circuitry coupled between memory controller and memory banks 12. Command controller 56 may initiate a refresh operation on a predetermined basis and / or in response to sensed operating conditions of system 8. For example, the memory may be refreshed at regular or defined time intervals to prevent information decay and / or the memory may be refreshed in response to sensed operating conditions that may impair the information retention capabilities of one or more materials in the memory.

[0032] Command controller 56 can transmit a global row address (GRA<15:0>) signal and an active memory bank (ActBnk<31:0>) signal. The global row address (GRA<15:0>) signal and the active memory bank (ActBnk<31:0>) signal enable command controller 56 to refresh each row in each of the memory banks 12 by incrementing the address used for each row. Note that each memory bank 12 can have the same number of rows, and the number of rows can be greater than or less than sixteen.

[0033] Memory channels 58 can be deployed between memory banks 12. Memory channels 58 can include communication couplings used during memory operations, such as when individually activating or deactivating rows of memory banks 12 during refresh operations and / or distributing refresh operation signals (e.g., global row address (GRA<15:0>) signals, memory bank activation (ActBnk<31:0>) signals). Thus, memory channels 58 can include one or more hardwire couplings between the individual memory banks 12.

[0034] To help describe memory channel 58 and memory bank 12, Figure 3 This is a block diagram of a pair of memory banks 12 (12A, 12B) of memory array 10. Deployed between the memory banks 12 are memory channels 58 (58A, 58B). Each of the memory channels 58 may contain one or more sub-channels 64 that couple the output from sub-memory bank logic circuitry 66 (66A, 66B) to the row and / or column of the corresponding memory bank 12. The sub-memory bank logic circuitry 66 may include circuitry that generates refresh control signals in response to control signals from command controller 56. The refresh control signals may be generated individually or appropriately distributed via the memory channels 58 to facilitate row-by-row or column-by-column refresh operations.

[0035] In some cases, the refresh operation involves generating refresh control signals for each memory bank 12 at approximately the same time. For example, memory bank 12A may receive refresh control signals simultaneously with memory bank 12B. In these cases, the refresh control signals for each pair of memory banks 12A, 12B may be the same and / or at least similar for a portion of the refresh control signals. Therefore, when refreshing control signals are generated and distributed due to the system 8 generating repetitive signals, the system 8 may consume an undesirable amount of power. As described herein, if circuitry is included to allow the refresh control signals to be shared between the pairs of memory banks 12 (e.g., the pairs of memory banks 12A, 12B), the power consumption of the memory banks 12 can be reduced, and thus the power consumption of the system 8 can be reduced.

[0036] Figure 4This is a block diagram of memory array 10, which includes circuitry such as multiplexer 78 or other suitable switching circuitry that allows refresh control signals to be shared among one or more memory banks 12 via buffer circuitry 80. Multiplexer 78 can selectively allow refresh control signals to be shared among sub-memory logic circuits 66 (66A, 66B). When refresh control signals are shared among one or more memory banks 12, at least one of the memory banks 12 can be de-energized, thereby reducing the power consumed by system 8. Command controller 56 can control the de-energization of sub-memory logic circuits 66, and thus control the operating state of multiplexer 78. For example, command controller 56 can generate control signals and transmit these control signals to multiplexer 78 to cause multiplexer 78 to transmit signals from sub-memory logic circuit system 66B instead of signals from sub-memory logic circuit system 66A.

[0037] Memory channel 58 can be considered as a memory channel region of memory array 10, containing sub-channels 64 for transmitting control signals from sub-memory logic circuits 66 and memory bank 12. Thus, multiplexer 78 is contained outside memory channel 58 and / or memory channel region of memory array 10. Multiplexer 78 is coupled to the input of buffer circuit 80 and thus indirectly transmits to memory channel 58. In a first operating state, multiplexer 78 allows control signals from sub-memory logic circuit 66A to be transmitted to memory bank 12A via memory channel 58A. However, in a second operating state corresponding to a refresh operation of memory array 10, multiplexer 78 does not allow control signals from sub-memory logic circuit 66A to be transmitted to memory bank 12A. Instead, in the second operating state, multiplexer 78 transmits control signals from sub-memory logic circuit 66B to memory bank 12A via the same memory channel 58A. In practice, since the control signal generated by the sub-logic memory logic circuit 66B is shared among the memory banks 12 during the refresh operation, the sub-logic memory logic circuit 66A can be powered off or have its supply power reduced while the memory refresh operation is being performed. Thus, the command controller 56 can generate half of the active memory bank (ActBnk<31:0>) signal (e.g., ActBnk...). <0> 、ActBnk <2> 、ActBnk <4> …ActBnk <30> This is to perform an equivalent refresh operation as with all active memory (ActBnk<31:0>) signals. Since the active memory signals used during the refresh operation are reduced by half, power savings can be achieved at least in part by reducing the power consumed by the circuitry transmitting the signals (e.g., communication coupling) (e.g., power lost due to heat, power reduced during production) and at least in part by reducing the power consumed by the sub-memory logic circuitry 66 by operating without responding to the active memory signals.

[0038] Figure 5 The document describes the operation involving sharing refresh control signals between memory banks 12A and 12B. Figure 5This is a flowchart of process 90, executed by command controller 56, to operate system 8 in a reduced power mode during a memory refresh operation. Typically, process 90 includes the command controller performing memory operations (box 92), receiving instructions to initiate refresh operations for n memory banks (box 94), receiving instructions for reduced power operations (box 96), transmitting control signals to (one or more) multiplexers (box 98), and generating n / 2 refresh control signals to perform the refresh operation (box 100). It should be understood that while the specific operations of process 90 are described in a particular order, these operations can be performed in any suitable order. Furthermore, although process 90 is described as being executed by command controller 56, it should be understood that any suitable system and / or circuitry (e.g., circuitry integrated with a control system) can perform the described operations.

[0039] In box 92, command controller 56 can perform memory operations. Memory operations may include operations associated with command controller 56 that facilitate read and / or write operations. Figure 1 The memory controller described herein can instruct command controller 56 to perform memory operations. Figure 1 The memory controller described herein can also instruct command controller 56 to perform refresh operations on memory banks 12. Therefore, at block 94, command controller 56 can receive an instruction to initiate refresh operations for the n memory banks 12 of memory array 10. Command controller 56 can receive an instruction to initiate refresh operations that is a command interpretable by the software or processing circuitry of command controller 56. However, in some embodiments, command controller 56 can receive an instruction interpretable by the logic circuitry of command controller 56 from the memory controller, such as a voltage signal for a logic low or logic high voltage level for system 8 and / or memory array 10. A refresh operation can be initiated for each memory bank 12 of memory array 10 (e.g., n memory banks 12).

[0040] In addition to receiving an instruction to initiate a refresh operation, in block 96, command controller 56 can receive an instruction for reduced power operation. In reduced power operation mode, memory array 10 can share refresh control signals among subsets of memory banks 12. For example, during reduced power operation mode, sub-memory logic circuitry 66B can generate refresh control signals for both memory banks 12A and 12B. The portion of sub-memory logic circuitry 66 corresponding to the portion not used to generate refresh control signals can be de-energized or operated in a reduced power state. For example, in… Figure 4In this context, when sharing a refresh control signal from sub-memory logic circuit 66B during reduced power operation, sub-memory logic circuit 66A can be de-energized or have its supply power reduced. An indication for reduced power operation can be signaled to command controller 56 to de-energize or reduce the power supplied to a portion of sub-memory logic circuit 66 (e.g., at least sub-memory logic circuit 66A and similarly deployed sub-memory logic circuits 66 of the other 12 pairs of memory banks). Note that either sub-memory logic circuit 66A or sub-memory logic circuit 66B can be de-energized to achieve the power consumption reduction of this disclosure. The indication for reduced power operation can also be a command or instruction interpretable by the logic circuitry, software, and / or processing circuitry of command controller 56.

[0041] In block 98, command controller 56 can initiate a reduced-power refresh operation at least in part by transmitting control signals to one or more multiplexers 78 and reducing the power to a subset of the sub-memory logic circuitry 66. The control signals can cause multiplexers 78 to change state to operate memory array 10 into a reduced-power operating mode. Multiplexers 78 can change state to change the permitted signal transmission from between a first portion of the sub-memory logic circuitry 66 and the corresponding memory bank 12 to between a second portion of the sub-memory logic circuitry system 66 and the corresponding memory bank 12. For example, Figure 4 The multiplexer 78 can transmit refresh control signals between sub-memory logic circuit 66A and memory bank 12A in its first state, but can transmit refresh control signals between sub-memory logic circuit 66B and memory bank 12A after receiving a control signal from command controller 56 (e.g., in block 98). During reduced power refresh operation, the command controller can reduce the supplied power or de-energize a subset of sub-memory logic circuit 66. For example, sub-memory logic circuit 66A can be operated at reduced power or no power when sub-memory logic circuit 66B generates refresh control signals on behalf of sub-memory logic circuit 66A. To reduce the power supplied to sub-memory logic circuit 66A, command controller 56 can suppress or reduce the voltage supplied to one or more portions electrically coupled to sub-memory logic circuit 66A, electrically couple sub-memory logic circuit 66A to a different power source supplying less power than the original power supply of sub-memory logic circuit 66, and / or decouple sub-memory logic circuit 66A from the power source, for example, via a switching circuit.

[0042] In block 100, command controller 56 can generate several refresh control signals corresponding to half (e.g., n / 2) of several memory banks 12. Since the refresh control signals are shared among one or more memory banks 12 (e.g., two memory banks), half of the sub-memory bank logic circuitry 66 for memory array 10 can be de-energized or have a reduced amount of supplied power. This reduces the power consumed by memory array 10 and therefore by system 8 during refresh operations. The power consumed by memory array 10 can be reduced in response to memory array 10 using less power to generate refresh control signals and / or in response to a subset of sub-memory bank logic circuitry 66 being electrically decoupled, and therefore cannot be passively consumed during refresh operations.

[0043] Although Figure 4 An example of a memory array 10 using circuitry to allow the sharing of refresh control signals among one or more memory banks is depicted, but further reductions in power consumption can be achieved. Figure 6 This is a block diagram of memory array 10, which includes a multiplexer 78 coupled to each row of each memory bank 12 to allow sharing of refresh control signals among one or more memory banks 12. Multiplexer 78 can selectively allow sharing of refresh control signals among sub-memory bank logic circuits 66 (66A, 66B). Similar to... Figure 4 In the example memory array 10, when a refresh control signal is shared among one or more memory banks 12, at least one of the memory banks 12 can be powered off, thereby reducing the power consumed by the system 8. The command controller 56 can control the power-off of the sub-memory logic circuitry 66, and thus control the operating state of the multiplexer 78. For example, the command controller 56 can generate a control signal and transmit it to the multiplexer 78 to cause the multiplexer 78 to transmit a signal from the sub-memory logic circuitry system 66B instead of a signal from the sub-memory logic circuitry system 66A.

[0044] However, with Figure 4 Unlike the example memory array 10, multiplexer 78 couples memory bank 12A to a subchannel 64 shared with memory bank 12B. In this case, multiplexer 78 is contained within the memory channel region of memory array 10 and is directly coupled to memory channel 58B (e.g., via direct coupling). As used herein, “directly coupled” or “direct coupling” can refer to a physical connection between two components formed without intermediate components. Figure 4 The memory array 10 can turn off or reduce the power supplied to the sub-memory logic circuit 66A, but can continue to transmit refresh control signals through one or more sub-channels 64 via the buffer circuit 80. Figure 6The memory array 10 can turn off or reduce the power supplied to the sub-memory logic circuit 66A and reduce the power consumed via sub-channel 64 by using fewer sub-channels 64 to transmit refresh control signals to memory bank 12A. Since memory channel 58B is shared with memory bank 12A to transmit the same refresh control signal to both memory bank 12A and memory bank 12B, memory channel 58A can be omitted during memory refresh operations. Therefore, memory channel 58A can consume no power when transmitting refresh control signals. Similar to... Figure 4 and Figure 5 As described, command controller 56 can generate and transmit control signals to operate memory array 10 into a reduced power refresh operation, which typically involves de-energizing a subset of sub-memory logic circuitry 66 (e.g., at least sub-memory logic circuitry 66A) and changing the state of multiplexer 78 to allow signal transmission between sub-channel 64 of memory channel 58B and memory bank 12A. Note that either sub-memory logic circuitry 66A or sub-memory logic circuitry 66B can be de-energized to achieve the power consumption reduction of this disclosure.

[0045] Considering the foregoing, in some embodiments, memory channel 58 transmits additional control signals to the refresh control signals. In these cases, the additional control signals may be generated at a subset of the sub-memory logic circuitry 66 and transmitted to the remaining sub-memory logic circuitry 66. The additional control signals may include refresh addresses, word line control signals, sense amplifier control signals, or the like, which may be multiplexed into memory bank 12A via multiplexer 78 to assist in operating memory array 10 to perform memory refresh operations while operating memory bank 12A in a reduced-power refresh operation. Note that various logic gates are discussed in this disclosure; however, it should be understood that the depicted logic gates may each be replaced by various valid logic gates, and may be used in combination with various valid logic gates, including NAND gates, NOR gates, XOR gates, AND gates, OR gates, inverter gates, or the like (even if not explicitly stated herein).

[0046] Therefore, the technical effects of this disclosure include systems and methods for improving memory refresh operations. Using the aforementioned multiplexing circuitry, at least two memory banks can perform memory refresh operations using a shared refresh control signal. Sharing the refresh control signal allows one or more sub-memory bank logic circuits to be de-energized, thereby reducing power consumption during refresh operations. Furthermore, by deploying the multiplexing circuitry between the first memory array and the sub-channel circuitry for the second memory array, at least a portion of the memory channels corresponding to the first memory array can be bypassed, enabling further improvements in power consumption.

[0047] While this disclosure allows for various modifications and alternatives, specific embodiments have been shown by way of example in the accompanying drawings and have been described in detail herein. However, it should be understood that this disclosure is not intended to be limited to the specific forms disclosed. Rather, this disclosure is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of this disclosure as defined by the appended claims.

[0048] The techniques proposed and claimed herein are referenced and applied to practical material objects and concrete instances, which significantly improve the field of technology and are therefore not abstract, intangible, or purely theoretical.

Claims

1. A memory device comprising: a plurality of memory banks including a first memory bank and a second memory bank, wherein each memory bank includes a plurality of memory circuits and is configured to store information; and a first sub-bank logic circuit communicatively coupled to the first memory bank and the second memory bank via a plurality of multiplexers, wherein the first sub-bank logic circuit is configured to be coupled to the first memory bank via the plurality of multiplexers and via a plurality of couplings that bypass the plurality of multiplexers, and wherein the first sub-bank logic circuit transmits control signals to refresh the second memory bank and the first memory bank to allow the control signals to be shared between the first memory bank and the second memory bank when the plurality of multiplexers are operated.

2. The device of claim 1, wherein the control signals are shared with a first row of the first memory bank at the same time as the control signals are shared with a first row of the second memory bank, wherein the first row of the first memory bank corresponds to the same row location as the first row of the second memory bank.

3. The device of claim 1, wherein a respective multiplexer of the plurality of multiplexers is configured to be coupled to a memory channel via a buffer circuit.

4. The device of claim 3, wherein the plurality of multiplexers are disposed outside of the memory channel, and wherein the buffer circuit is disposed between the respective multiplexer of the plurality of multiplexers and the memory channel.

5. The device of claim 1, wherein the plurality of multiplexers are configured to be directly coupled to a plurality of memory channels.

6. The device of claim 5, wherein the plurality of multiplexers are disposed inside of the plurality of memory channels, and wherein a buffer circuit directly couples the plurality of memory channels to the first sub-bank logic circuit.

7. The device of claim 1, wherein the control signals are transmitted from the first sub-bank logic circuit in response to an initiated refresh operation, and wherein the control signals are ones of a plurality of refresh control signals used to refresh respective rows of the first memory bank at least partially concurrently with rows of the second memory bank.

8. The device of claim 7, wherein the first memory bank is coupled to a second sub-bank logic circuit, and wherein the second sub-bank logic circuit operates in a reduced power mode of operation during the refresh operation.

9. The device of claim 8, wherein the reduced power mode of operation includes powering off the second sub-bank logic circuit.

10. The device of claim 1, including the second sub-bank logic circuit configured to be powered off concurrently with the second sub-bank refresh operation.

11. A memory bank refresh method comprising: performing memory operations via a first memory bank logic circuit; receiving an indication to initiate a refresh operation via the first memory bank logic circuit; receiving an indication to operate in a reduced power mode via the first memory bank logic circuit; transmitting a refresh control signal via the first bank logic circuit to a buffer circuit coupled to a multiplexer to initiate a reduced power refresh operation, wherein the multiplexer is coupled between the first bank logic circuit, a second bank logic circuit, and a bank, wherein the reduced power refresh operation causes power supplied to the second bank logic circuit to be reduced during a refresh of the bank.

12. The method of claim 11, comprising transmitting a plurality of refresh control signals including the refresh control signal, and wherein an amount of the plurality of refresh control signals is equal to half an amount of a plurality of banks including the bank.

13. The method of claim 11, comprising powering off the second bank logic circuit from its power supply.

14. The method of claim 11, comprising transmitting a plurality of operation control signals to a plurality of multiplexers to alter a state of each of the plurality of multiplexers such that signals can be shared between the first bank logic circuit and the bank without sharing signals from the second bank logic circuit, wherein the plurality of multiplexers includes the multiplexer.

15. A memory system comprising: a memory controller; and a memory module communicatively coupled to the memory controller, wherein the memory module comprises: a first bank logic circuit coupled to a first bank; a second bank logic circuit configured to be coupled to a second bank and configured to be powered off while the second sub-bank refresh operation; and a switch circuit configured to couple the first bank logic circuit to the second bank instead of the second bank logic circuit during a memory refresh operation in response to a control signal from the memory controller.

16. The system of claim 15, wherein the memory module comprises a memory channel region to transmit one or more control signals between the first bank and the first bank logic circuit.

17. The system of claim 16, wherein the switch circuit is disposed within the memory channel region.

18. The system of claim 16, wherein the switch circuit is disposed outside of the memory channel region and coupled between a buffer and the first bank logic circuit.

19. The system of claim 15, wherein the memory controller is configured to power off the second bank logic circuit at least by: transmitting a first indication to cause the first bank logic circuit to initiate a refresh operation associated with the memory module; transmitting a second indication to cause the second bank logic circuit to be powered off; and transmitting a refresh control signal to the first bank logic circuit.

20. The system of claim 15, wherein the switch circuit is coupled to a first communicative coupling routed between the first bank logic circuit and the first bank and a second communicative coupling routed between the second bank logic circuit and the second bank.

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