Non-volatile memory devices

Abstract

A nonvolatile memory device capable of minimizing monitoring overhead associated with read disturbance is provided. The nonvolatile memory device includes: a memory cell array including a first cell string including a plurality of memory cells connected in series, wherein the plurality of memory cells include a first monitoring cell, a first memory cell, and a second memory cell; and a row decoder that, when reading a first memory cell among the memory cells, provides a first read voltage to the first memory cell and provides a first monitoring voltage to the first monitoring cell, and when reading a second memory cell, provides the first read voltage to the second memory cell and provides a second monitoring voltage different from the first monitoring voltage to the first monitoring cell.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority benefit of Korean Patent Application No. 10-2019-0101486 filed on August 20, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a non-volatile memory device. Background Art

[0004] Flash memory is a non-volatile memory that can retain stored data even when power is interrupted. Recently, storage devices including flash memories such as embedded multimedia card (eMMC), universal flash storage (UFS), solid state drive (SSD), and memory card are widely used. Storage devices are used to store or move large amounts of data.

[0005] Repeated read operations of NAND flash memory devices can cause read disturbances, in which a memory cell that is an on cell is identified as an off cell. During a read operation, when a non-select read voltage Vread is applied to a word line connected to a memory cell that is an on cell, electrons are introduced into the capture layer of the on cell little by little. "Vread" can be referred to as a "pass voltage". As the introduced electrons accumulate in the capture layer, the on cell can be identified as an off cell.

[0006] In order to monitor the read disturbance, a plurality of word lines showing weak characteristics during the read operation may all be monitored. However, as the number of word lines showing weak characteristics increases, this method may inevitably increase the monitoring overhead. Summary of the invention

[0007] Aspects of the present disclosure provide a nonvolatile memory device capable of minimizing monitoring overhead associated with read disturb.

[0008] However, aspects of the present disclosure are not limited to the one aspect set forth herein. The above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure belongs by referring to the detailed embodiments of the present disclosure given below.

[0009] A nonvolatile memory device is provided herein, comprising: a memory cell array, wherein the memory cell array comprises a first cell string, the first cell string comprises a plurality of memory cells connected in series, and wherein the plurality of memory cells comprises a first monitoring cell, a first memory cell, and a second memory cell; and a row decoder, wherein the row decoder is configured to: when reading the first memory cell, provide a first read voltage to the first memory cell and provide a first monitoring voltage to the first monitoring cell, and when reading the second memory cell, provide the first read voltage to the second memory cell and provide a second monitoring voltage different from the first monitoring voltage to the first monitoring cell.

[0010] Another nonvolatile memory device is also provided herein, comprising: a memory cell array, wherein the memory cell array comprises a plurality of memory blocks, each of the plurality of memory blocks comprises a plurality of cell strings, each of the plurality of cell strings comprises a plurality of memory cells and a monitoring unit, a first memory block of the plurality of memory blocks comprises a first plurality of cell strings, the first plurality of cell strings comprises a first cell string, and the first cell string comprises a selected memory cell, an unselected memory cell, and a first monitoring unit; and a row decoder configured to: during a read operation, provide a first read voltage to a selected memory cell, provide a second read voltage to an unselected memory cell, and provide a monitoring voltage to the first monitoring unit, wherein the row decoder is further configured to adjust the monitoring voltage according to at least one of: characteristics of the selected memory cell, characteristics of unselected memory cells in the first cell string adjacent to the selected memory cell, and characteristics of the first memory block.

[0011] A nonvolatile memory device is provided herein, comprising: a memory cell array, wherein the memory cell array comprises a cell string, the cell string comprises a first memory cell, a plurality of memory cells connected in series, a monitoring cell, a string selection element, and a ground selection element, wherein the monitoring cell is located between the string selection element and the plurality of memory cells or between the ground selection element and the plurality of memory cells, and the cell string comprises a selected memory cell, an unselected memory cell, and a first monitoring cell; and a row decoder, wherein the row decoder is configured to provide voltages to the plurality of memory cells, the monitoring cell, the string selection element, and the ground selection element, wherein the row decoder is further configured to: when reading the first memory cell, provide a first read voltage to the first memory cell, provide a first unselected memory cell spaced apart from the first memory cell with a first read voltage, and provide a first read voltage to the first memory cell; A selected memory cell provides a second read voltage, a third read voltage is provided to an unselected memory cell adjacent to the first memory cell, and a first monitoring voltage is provided to a monitoring unit, and when reading the second memory cell, the first read voltage is provided to the second memory cell, a second read voltage is provided to a second unselected memory cell spaced apart from the second memory cell, a third read voltage is provided to a third unselected memory cell adjacent to the second memory cell, and a second monitoring voltage different from the first monitoring voltage is provided to the monitoring unit, wherein the third read voltage is greater than the second read voltage, the second read voltage is greater than the first read voltage, and the first monitoring voltage and the second monitoring voltage are greater than the second read voltage, wherein the non-volatile memory device is configured to determine whether to make a recycling request based on whether the monitoring unit is degraded.

[0012] A method for memory cell degradation detection is also provided herein, the method comprising: identifying a first weak memory cell in a cell string; identifying a non-weak memory cell, wherein the non-weak memory cell is a neighbor of the first weak memory cell in the cell string; identifying a second weak memory cell in the cell string; designating the second weak memory cell as a monitoring cell; when a first read operation reads the non-weak memory cell: applying an elevated pass voltage to the monitoring cell; when a second read operation reads the first weak memory cell: applying a non-elevated pass voltage to the monitoring cell; when a count of the read operations exceeds a threshold: checking degradation of the monitoring cell; based on the checking, when the monitoring cell has degraded: performing a recovery operation of the cell string; and based on the checking, when the monitoring cell has not degraded, not performing a recovery operation of the cell string.

[0013] According to aspects of the present disclosure, a nonvolatile memory device is provided, comprising: a memory cell array comprising a first cell string including a plurality of memory cells connected in series and a first monitoring unit, and a row decoder which, when reading a first memory cell among the memory cells, provides a first read voltage to the first memory cell and provides a first monitoring voltage to the first monitoring unit, and when reading a second memory cell among the memory cells that is different from the first memory cell, provides the first read voltage to the second memory cell and provides a second monitoring voltage that is different from the first monitoring voltage to the first monitoring unit.

[0014] According to another aspect of the present disclosure, a nonvolatile memory device is provided, comprising: a memory cell array comprising a plurality of memory blocks, wherein each of the memory blocks comprises a plurality of cell strings, wherein each cell string comprises a plurality of memory cells and a monitoring unit, and a row decoder, which during a read operation provides a first read voltage to a selected memory cell among the memory cells, provides a second read voltage to unselected memory cells, and provides a monitoring voltage to the monitoring unit, wherein the monitoring voltage is adjusted according to at least one of characteristics of the selected memory cell, characteristics of unselected memory cells adjacent to the selected memory cell, and characteristics of a memory block including the selected memory cell.

[0015] According to another aspect of the present disclosure, a nonvolatile memory device is provided, comprising: a memory cell array, comprising a cell string, the cell string comprising a plurality of memory cells connected in series, a monitoring cell, a string selection element, and a ground selection element, and a row decoder, which provides voltages to the memory cells, the monitoring cell, the string selection element, and the ground selection element, wherein the monitoring cell is located between the string selection element and the memory cells or between the ground selection element and the memory cells, and when a first memory cell among the memory cells is read, the row decoder provides a first read voltage to the first memory cell, provides a second read voltage to an unselected memory cell spaced apart from the first memory cell, and provides a second read voltage to an unselected memory cell adjacent to the first memory cell. The memory unit provides a third read voltage and provides a first monitoring voltage to the first monitoring unit, and when a second memory cell different from the first memory cell among the memory cells is read, the first read voltage is provided to the second memory cell, a second read voltage is provided to an unselected memory cell separated from the second memory cell, a third read voltage is provided to an unselected memory cell adjacent to the second memory cell, and a second monitoring voltage different from the first monitoring voltage is provided to the monitoring unit, wherein the third read voltage is greater than the second read voltage, the second read voltage is greater than the first read voltage, the first monitoring voltage and the second monitoring voltage are greater than the second read voltage, and whether a recycling request is made is determined based on whether the monitoring unit has degraded. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] These and / or other aspects will become apparent and more readily understood from the following description of example embodiments taken in conjunction with the accompanying drawings, in which:

[0017] Figure 1 is a block diagram of a storage device according to an embodiment;

[0018] Figure 2 is a block diagram of a nonvolatile memory device according to an embodiment;

[0019] Figure 3A and 3B yes Figure 2 A circuit diagram of a memory cell array;

[0020] Figure 4 and 5 is a diagram for explaining a method of driving a nonvolatile memory device according to a first embodiment;

[0021] Figure 6 It is used to explain the Figure 4 and 5 A diagram of a level of a monitoring voltage used in a method of a non-volatile memory device;

[0022] Figure 7 is a diagram for explaining a method of driving a nonvolatile memory device according to a second embodiment;

[0023] Figure 8 and 9 is a diagram for explaining a method of driving a nonvolatile memory device according to a third embodiment;

[0024] Fig.10 is used to explain Figure 8 and 9 A diagram of a level of a monitoring voltage used in a method of driving a nonvolatile memory device;

[0025] Fig.11 is a diagram for explaining a method of driving a nonvolatile memory device according to a fourth embodiment;

[0026] Fig.12 is a diagram for explaining a method of driving a nonvolatile memory device according to a fifth embodiment;

[0027] Fig.13 is a diagram for explaining a method of driving a nonvolatile memory device according to a sixth embodiment;

[0028] Fig.14 is a flowchart of a method for driving a nonvolatile memory device according to a seventh embodiment;

[0029] Fig.15 illustrates a process in which the threshold voltages of a plurality of monitoring cells are changed; and

[0030] Fig.16 is a flowchart illustrating a method of driving a nonvolatile memory device according to an eighth embodiment. DETAILED DESCRIPTION

[0031] Hereinafter, various embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0032] Figure 1 is a block diagram of a storage device according to an embodiment.

[0033] refer to Figure 1 , a memory device according to an embodiment includes a memory device 100 and a memory controller 200 .

[0034] The storage device may be implemented as, but not limited to, a smart card, a secure digital (SD) card, a multimedia card (MMC), an embedded MMC (eMMC), an embedded multi-chip package (eMCP), perfect page NAND (PPN), universal flash storage (UFS), a universal serial bus (USB) flash drive, a solid-state drive (SSD), or an embedded SSD (eSSD).

[0035] The memory device 100 may be, but is not limited to, a non-volatile memory (eg, NAND flash memory) based device.

[0036] The memory controller 200 controls the overall operation of the memory device 100. The memory controller 200 may interpret a command received from a host and control an operation (eg, a program, read, or erase operation) of the memory device 100 based on the interpretation result.

[0037] The memory controller 200 includes a reclaim controller 210. The reclaim controller 210 checks a monitoring cell (eg, Figure 3A Whether the monitoring unit has degraded and a recycling request is made based on the inspection result. That is, depending on whether the monitoring unit has degraded, data stored in a memory block (or page) including the monitoring unit can be transferred to and stored in another memory block (or page).

[0038] Figure 2 is a block diagram of a nonvolatile memory device 100 according to an embodiment. Figure 3A and 3B yes Figure 2 The circuit diagram of the memory cell array 110 is shown in FIG. 1 . ... Figure 2 , Figure 3A and Figure 3B , but the embodiment is not limited to this case.

[0039] First, refer to Figure 2 , the memory device 100 includes a memory cell array 110 and an access circuit 112 .

[0040] The memory cell array 110 may be a two-dimensional (2D) memory cell array or a three-dimensional (3D) memory cell array.

[0041] refer to Figure 3A, the memory cell array 110 may be a 2D memory cell array. In this case, the memory cell array 110 includes a plurality of cell strings STR0 to STRm. Each of the cell strings STR0 to STRm includes a plurality of memory cells C0 to Cn connected in series and a first monitoring cell MC0. In addition, each of the cell strings STR0 to STRm further includes a string selection element SST and a ground selection element GST. For example, the string selection element SST may be a transistor having a drain connected to one of the bit lines BL0 to BLm and a gate connected to the string selection line SSL. The ground selection element GST may be a transistor having a source connected to a common source line CSL and a gate connected to the ground selection line GSL. The memory cells C0 to Cn connected to a plurality of word lines WL0 to WLn, respectively, and the first monitoring cell MC0 connected to the monitoring line MWL0 are connected in series between the source of the string selection element SST and the drain of the ground selection element GST. As described above, in some embodiments, each memory cell includes a transistor. Each transistor has a source, a gate, and a drain terminal. The gate of any transistor is connected to one of the word lines. A memory cell being "turned on" (a conductive path exists between the source and drain of the transistor) means that the corresponding transistor is placed in a conductive state by applying a read voltage to the gate of the transistor.

[0042] Despite Figure 3A The first monitor cell MC0 is disposed between the ground selection element GST and the memory cell (eg, C0), but the embodiment is not limited to this case.

[0043] For example, Figure 3B As illustrated in , the monitoring cell MC1 may be additionally placed between the string selection element SST and the memory cell (e.g., Cn). Alternatively, the monitoring cell MC1 may be placed between the string selection element SST and the memory cell (e.g., Cn), and the first monitoring cell MC0 may not be placed between the ground selection element GST and the memory cell (e.g., C0).

[0044] Alternatively, the first monitoring cell MC0 may be located between the memory cells (eg, C7 and C8).A memory cell exhibiting a weak characteristic during a read operation may be designated as the first monitoring cell MC0, but the embodiment is not limited to this case.

[0045] The case where the memory cell array 110 is a 3D memory cell array will be briefly described as follows. In a 3D memory cell array, an array of memory cells may be formed monolithically at one or more physical levels, and circuits related to the operation of the memory cells may also be included. The term "monolithically" means that the layers at the array level are deposited directly on the layers of the lower level of the array. The 3D memory array may include vertical NAND strings that are vertically oriented so that at least one memory cell is located above other memory cells. In some embodiments, each NAND string consists of a string of transistors; in some embodiments, one memory cell is associated with one transistor. Each exemplary transistor has three terminals: a source, a gate, and a drain. At least one memory cell may include a charge trapping layer associated with a gate terminal. The 3D memory cell array may be implemented as a wafer stack, a chip stack, or a cell stack.

[0046] Reference again Figure 2 , the access circuit 112 may include a voltage generator 140 , a row decoder 150 , a control logic 160 , a column decoder 170 , a page buffer and sense amplifier block 120 , a Y gating circuit 130 , and an input / output (I / O) block 180 .

[0047] The control logic 160 controls the overall operation of the access circuit 112 according to the command CMD received from the memory controller 200. For example, the control logic 160 may control the access circuit 112 to sense memory read status information and provide read data to the memory controller 200 during a memory read operation.

[0048] The voltage generator 140 can generate the voltage required for the access operation according to the control code generated by the control logic 160. The voltage generator 140 generates the program voltage and the program verification voltage required to perform the program operation, generates the read voltage required to perform the read operation, and generates the erase voltage and the erase verification voltage required to perform the erase operation. In addition, the voltage generator 140 provides the row decoder 150 with the voltage required to perform each operation. The row decoder 150 decodes the row address XADD and selectively provides the read voltage, the program voltage, the program verification voltage, the erase voltage, and the erase verification voltage to the memory cell array 110.

[0049] Specifically, the read voltage generated by the voltage generator 140 may include a first read voltage (select read voltage) Vr, a second read voltage (non-select read voltage) Vread, a monitoring voltage Vm, a string selection voltage, and a ground selection voltage. The first read voltage Vr is a voltage provided to a memory cell to be read (i.e., a read target memory cell or a selected memory cell) through a selected word line. The second read voltage Vread is a voltage provided to a memory cell that will not be read through an unselected word line. The monitoring voltage Vm is a voltage provided to a monitoring cell (e.g., MC0) whenever a read operation is performed on a cell string (e.g., STR0) including the monitoring cell (e.g., MC0). The string selection voltage and the ground selection voltage are voltages for turning on the string selection element SST and the ground selection element GST electrically connected to the memory cell to be read.

[0050] In addition, the voltage generator 140 may further generate a third read voltage (adjacent non-selected read voltage) Vh. The third read voltage Vh is a voltage provided to an unselected memory cell adjacent to the memory cell to be read through an adjacent unselected word line. When the third read voltage Vh is used, the second read voltage Vread is provided to the unselected memory cell spaced apart from the memory cell to be read.

[0051] The third read voltage Vh is higher than the second read voltage Vread.

[0052] The second read voltage Vread is higher than the first read voltage Vr.

[0053] The monitoring voltage Vm is also higher than the first read voltage Vr. The first monitoring unit MC0 may not receive a monitoring voltage Vm of a fixed level, but may receive a monitoring voltage Vm adjusted according to at least one of the characteristics of a selected memory cell (i.e., a memory cell to be read), the characteristics of a memory cell adjacent to the selected memory cell, and the characteristics of a memory block to which the selected memory cell belongs. For example, the voltage generator 140 may generate a plurality of monitoring voltages (e.g., Vm0 to Vm2) having different levels, and the row decoder 150 may select one of the monitoring voltages (e.g., Vm2) by considering the row address XADD (i.e., considering the characteristics described above) and provide the selected monitoring voltage to the first monitoring unit MC0. In addition, the level of the monitoring voltage Vm may be determined by further reflecting the characteristics of the semiconductor chip including the selected memory cell.

[0054] Will refer to it later Figures 4 to 13 A method of providing the read voltages (the first read voltage Vr, the second read voltage Vread, the third read voltage Vh, and the monitor voltage Vm) during the read operation will be described in detail.

[0055] The column decoder 170 decodes the column address YADD under the control of the control logic 160 and provides a plurality of selection signals to the Y gating circuit 130 .

[0056] The page buffer and sense amplifier block 120 includes a plurality of page buffers PB. The page buffers PB are connected to a plurality of bit lines, respectively.

[0057] Each of the page buffers PB may operate as a driver for temporarily storing data read from the memory cell array 110 during a data read operation under the control of the control logic 160. In addition, each of the page buffers PB may operate as a sense amplifier capable of sensing and amplifying a voltage level of each of the bit lines during a read operation under the control of the control logic 160.

[0058] The Y gating circuit 130 may control transmission of data DATA between the page buffer and sense amplifier block 120 and the I / O block 180 in response to a selection signal received from the column decoder 170 .

[0059] The I / O block 180 may transmit data DATA received from the outside to the Y gating circuit or transmit data DATA output from the Y gating circuit 130 to the memory controller 200 through a plurality of I / O pins (or a data bus).

[0060] Figure 4 and 5 is a diagram for explaining a method of driving a nonvolatile memory device according to the first embodiment. Figure 6 It is used to explain the Figure 4 and 5 FIG. 1 is a diagram of a monitoring voltage level used in a method of a nonvolatile memory device. Specifically, Figure 6 is a diagram for explaining the level of a monitoring voltage when a memory cell is a single-level cell (SLC).

[0061] First, refer to Figure 4 , it is assumed that a first memory cell (eg, C7 ) among the plurality of memory cells C0 to Cn is a selected memory cell (ie, a memory cell to be read).

[0062] A string selection voltage is applied to the string selection line SSL to turn on the string selection element SST, and a ground selection voltage is applied to the ground selection line GSL to turn on the ground selection element GST.

[0063] A first read voltage (select read voltage) Vr is provided to the selected first memory cell C7 through the selected word line WL7, and a second read voltage (non-select read voltage) Vread is provided to the unselected memory cells C0 to C6 and C8 to Cn in the cell string STR0 through the unselected word lines WL0 to WL6 and WL8 to WLn.

[0064] The first monitoring cell MC0 is supplied with the first monitoring voltage Vm1 through the monitoring line MWL0 .

[0065] exist Figure 6 In FIG. 1 , the x-axis is labeled with “Vth”. The x-axis corresponds to the threshold voltage applied to the gate terminal of the exemplary memory cell. At the threshold voltage, the exemplary transistor of the memory cell is turned on. The charge on the charge trapping layer of the exemplary transistor gate changes the threshold voltage at which the transistor gate turns on. Therefore, “0” can be stored in the transistor by not depositing charge, and when Vr is applied ( Figure 6 The cell will turn on when enough charge is deposited to move the threshold above Vr ( Figure 6 The middle part of the transistor, labeled “0 (off)”, stores a “1” in the transistor.

[0066] Different memory cells turn on at different threshold voltages. Thus, for a given memory cell, there is uncertainty about the actual value of the threshold. Figure 6 The bell-shaped function in indicates the distribution of thresholds of many memory cells in the sample set. The peak in the distribution indicates the threshold at which many memory cells in the sample set will turn on. When no charge is stored in the charge trapping layer, there is a Figure 6 The narrow width of the bell-shaped function on the left shows the small range of threshold voltages.

[0067] When charge is stored in the charge trapping layer to represent a logical "0", there is a Figure 6 The distribution marked “0” in FIG.

[0068] Here, reference Figure 6 , the first read voltage Vr has a relatively low level, and the second read voltage Vread has a relatively high level.

[0069] As described above, the first read voltage Vr is greater than the threshold voltage of the memory cell having data '1' (i.e., an on cell) and less than the threshold voltage of the memory cell having data '0' (i.e., an off cell). That is, when the first read voltage Vr is provided to the memory cell C7, it is determined whether the memory cell will be turned on or off depending on whether the data stored in the memory cell C7 is 1 or 0.

[0070] The second read voltage Vread is higher than the threshold voltage of the memory cell having data '0' (i.e., a closed cell). Therefore, regardless of the data stored in the unselected memory cells C0 to C6 and C8 to Cn, the unselected memory cells C0 to C6 and C8 to Cn are all turned on. In this scenario, when Vr is applied, the amount of charge stored to put the memory cell in the closed state ("0") keeps the exemplary transistor off, but when Vread is applied, the stored charge will allow the exemplary transistor to turn on.

[0071] Therefore, the first monitor voltage Vm1 is also higher than the threshold voltage of the memory cell having data '0' (ie, a turned-off cell). Therefore, the first monitor cell MC0 is turned on by the first monitor voltage Vm1.

[0072] Therefore, when the first read voltage Vr, the second read voltage Vread, and the first monitoring voltage Vm1 are applied during a read operation, current may or may not flow from the bit line BL0 to the common source line CSL (ie, ground voltage) depending on whether the data stored in the memory cell C7 is 1 or 0.

[0073] Here, reference Figure 5 , assuming that a second memory cell (eg, C8 ) among the memory cells C0 to Cn is a selected memory cell (ie, a memory cell to be read).

[0074] A first read voltage (select read voltage) Vr is provided to the selected second memory cell C8 through the selected word line WL8, and a second read voltage (non-select read voltage) Vread is provided to the unselected memory cells C0 to C7 and C9 to Cn in the cell string STR0 through the unselected word lines WL0 to WL7 and WL9 to WLn.

[0075] The second monitor voltage Vm2 different from the first monitor voltage Vm1 is provided to the first monitor unit MC0 through the monitor line MWL0 .

[0076] Here, it is assumed that the first memory cell C7 is a memory cell showing a weak characteristic during a read operation (ie, a weak cell), and the second memory cell C8 is not a weak cell. An example of a weak characteristic is Figure 6 The tail of a distribution that expands to the right within the "1" distribution in . See also Fig.15 . This type of tail corresponds to Figure 6 The weak memory cells are turned on at the Vth values ​​within the right portion of the distribution marked as "1" in FIG. 1. For example, 0.1%, 1%, or 10% of the population of thresholds shown by the distribution correspond to weak cells.

[0077] Which cell in the memory cell array 110 is a weak cell or which memory block is a weak block can be identified by testing performed during the manufacture of the non-volatile memory device. Alternatively, which cell / block is a weak cell / weak block can be identified by using a non-volatile memory device. The location of the weak cell / weak block is stored in the non-volatile memory device (memory device 100). For example, the location of the weak cell / weak block can be stored in the control logic 160 or can be stored in a separate storage medium.

[0078] The level of the monitoring voltage Vm applied to the first monitoring cell MC0 can be adjusted according to the memory cell (C0 to Cn) to be read. In other words, the level of the monitoring voltage Vm can be adjusted according to the level of the voltage received by the weak cell (e.g., the first memory cell C7) in the cell string STR0 during the read operation.

[0079] You can Figure 6 The level of the monitoring voltage Vm is determined within the first voltage range V0 to V1 including the first reference voltage Vm0 as illustrated in FIG. Specifically, the first voltage range V0 to V1 may include the first reference voltage Vm0 and extend to both sides from the first reference voltage Vm0. Here, the level of the first reference voltage Vm0 is determined based on the level of the second read voltage Vread. For example, the level of the first reference voltage Vm0 and the level of the second read voltage Vread may be substantially equal. Vm0 may be referred to as a non-elevated value.

[0080] When a weak cell (eg, the first memory cell C7) is Figure 4 When the memory cell to be read in FIG. 1 is selected, the weak cell receives the first read voltage Vr having a relatively low level. Therefore, the first monitor cell MC0 receives the first monitor voltage Vm1 having a relatively low level.

[0081] On the other hand, when Figure 5 When a memory cell (i.e., the second memory cell C8) that is not a weak cell is a memory cell to be read, the non-weak memory cell (the second memory cell C8) receives the first read voltage Vr, and the weak cell (i.e., the first memory cell C7) receives the second read voltage Vread having a relatively high level. Therefore, the first monitoring cell MC0 receives the second monitoring voltage Vm2 having a relatively high level. The relatively high level may be referred to as an elevated value.

[0082] In summary, the first monitoring cell MC0 represents at least one weak cell located in the cell string STR0. The level of the monitoring voltage Vm provided to the first monitoring cell MC0 can be adjusted according to the level of the voltage provided to another weak cell in the same cell string STR0. As described above, the level of the monitoring voltage Vm can be higher than the level of the voltage provided to the weak cell (i.e., Vm1>Vr, Vm2>Vread). The application of Vread to C7 when reading C8 tends to leak electrons into the capture layer of C7 because they are neighbors. By imposing a similar effect on MC0 when reading C8, MC0 tends to track the degradation of the weak cell C7.

[0083] Therefore, it is possible to identify whether at least one weak cell (e.g., weak cell C7) of cell string STR0 has degraded by checking whether the first monitoring cell MC0 has degraded, because the capture layer of MC0 has been affected in a manner similar to the capture layer of weak cell C7. Therefore, it is possible to check whether the first monitoring cell MC0 has degraded (which implies that other weak cells of the same cell string have degraded) and make a recycling request based on the check result. In some embodiments, neighbor cell C7 and monitoring cell MC0 are not in the same cell string.

[0084] The check can be performed by writing a 1 to the memory cell (by not storing charge in the trapping layer of the exemplary transistor associated with the memory cell). The reading of the checked memory cell is then performed using a read voltage Vr (see Figure 6 and 15 ). In a cell that has not degraded, the threshold voltage will be below Vr. In a cell that has degraded, the threshold voltage will exceed Vr. If the memory cell indicates that a "0" is stored (ie, the threshold voltage exceeds Vr), then this check indicates that the memory cell has degraded.

[0085] Figure 7 is a diagram for explaining a method of driving a nonvolatile memory device according to the second embodiment. Figure 7 1 is a diagram for explaining the level of the monitoring voltage when the memory cell is a multi-level cell (MLC). For ease of description, the following will mainly describe the Figures 4 to 6 Features and aspects described.

[0086] refer to Figure 7, the read voltage Vr1 is greater than the threshold voltage of the memory cell with data '11' and less than the threshold voltage of the memory cell with data '10'. The read voltage Vr2 is greater than the threshold voltage of the memory cell with data '10' and less than the threshold voltage of the memory cell with data '00'. The read voltage Vr3 is greater than the threshold voltage of the memory cell with data '00' and less than the threshold voltage of the memory cell with data '01'. The non-select read voltage Vread is higher than the threshold voltage of the memory cell with data '01'.

[0087] A monitoring voltage Vm is applied to the first monitoring cell MC0 through the monitoring line MWL0. The level of the monitoring voltage Vm applied to the first monitoring cell MC0 can be adjusted according to the memory cell (C0 to Cn) to be read. In other words, the level of the monitoring voltage Vm can be adjusted according to the level of the voltage received by the weak cell (e.g., C7) in the cell string during the read operation.

[0088] During a read operation, when a read voltage Vr1 is applied to the weak cell C7, a monitoring voltage Vm1 may be applied to the first monitoring cell MC0. When a read voltage Vr2 is applied to the weak cell C7, a monitoring voltage Vm0 may be applied to the first monitoring cell MC0. When a read voltage Vr3 is applied to the weak cell C7, a monitoring voltage Vm2 may be applied to the first monitoring cell MC0. When a non-select read voltage Vread is applied to the weak cell C7, a monitoring voltage Vm3 may be applied to the first monitoring cell MC0.

[0089] Figure 8 and 9 FIG. 1 is a diagram for explaining a method of driving a nonvolatile memory device according to a third embodiment. Figures 4 to 6 Features and aspects described. Fig.10 is used to explain Figure 8 and 9 A diagram of a level of a monitoring voltage used in a method of driving a nonvolatile memory device. Specifically, Fig.10 The diagram shows the level of the monitoring voltage when the memory cell is an SLC.

[0090] First, refer to Figure 8, assuming that the first memory cell (e.g., C7) among the plurality of memory cells C0 to Cn is a selected memory cell (i.e., a memory cell to be read). A first read voltage (select read voltage) Vr is provided to the selected first memory cell C7 through the selected word line WL7. A second read voltage (non-select read voltage) Vread is provided to the unselected memory cells C0 to C5 and C9 to Cn spaced apart from the first memory cell C7 in the cell string STR0 through the unselected word lines WL0 to WL5 and WL9 to WLn. A third read voltage (adjacent non-select read voltage) Vh is provided to the unselected memory cells C6 and C8 adjacent to the selected first memory cell C7 through the unselected word lines WL6 and WL8. A third monitoring voltage Vm11 is provided to the first monitoring cell MC0 through the monitoring line MWL0.

[0091] Here, reference Fig.10 , the second read voltage Vread has a higher level than the first read voltage Vr. The third read voltage Vh has a higher level than the second read voltage (non-select read voltage) Vread. The third monitor voltage Vm11 has a higher level than the second read voltage Vread.

[0092] Here, reference Fig. 9 , assuming that the second memory cell (e.g., C8) among the memory cells C0 to Cn is the selected memory cell (i.e., the memory cell to be read). A first read voltage (select read voltage) Vr is provided to the selected second memory cell C8 through the selected word line WL8. A second read voltage (non-select read voltage) Vread is provided to the unselected memory cells C0 to C6 and C10 to Cn spaced apart from the second memory cell C8 in the cell string STR0 through the unselected word lines WL0 to WL6 and WL10 to WLn. A third read voltage (adjacent non-select read voltage) Vh is provided to the unselected memory cells C7 and C9 adjacent to the selected second memory cell C8 through the unselected word lines WL7 and WL9. A fourth monitoring voltage Vm12 is provided to the first monitoring cell MC0 through the monitoring line MWL0. The fourth monitoring voltage Vm12 has a higher level than the second read voltage Vread.

[0093] As described above, the third read voltage Vh higher than the second read voltage Vread is provided to the unselected memory cells C7 and C9 adjacent to the selected memory cell (e.g., C8). The high third read voltage Vh is provided so as to reliably turn on the unselected memory cells C7 and C9 adjacent to the selected memory cell C8 during the read operation. Because the relatively low first read voltage Vr is provided to the selected memory cell C8, the unselected memory cells C7 and C9 adjacent to the selected memory cell C8 may be affected by the first read voltage Vr due to parasitic capacitance, etc. Therefore, even if the second read voltage Vread is applied to the adjacent unselected memory cells C7 and C9, the adjacent unselected memory cells C7 and C9 are also driven by a voltage substantially lower than the second read voltage Vread. This is why the high third read voltage Vh is provided to the unselected memory cells C7 and C9 adjacent to the selected memory cell C8.

[0094] When the adjacent unselected memory cell (eg, C9) is a weak cell, it may be easily degraded by the third read voltage Vh.

[0095] The level of the monitoring voltage Vm applied to the first monitoring unit MC0 can be adjusted according to the memory cells (C0 to Cn) to be read. More specifically, the level of the monitoring voltage Vm can be adjusted according to whether the unselected memory cells (e.g., C7 and C9) next to the memory cells to be read (e.g., C8) are weak cells.

[0096] You can Fig.10 The level of the monitoring voltage Vm is determined within the second voltage range V10 to V11 including the second reference voltage Vm10 as illustrated in FIG. More specifically, the second voltage range V10 to V11 may extend to both sides from the second reference voltage Vm10. Here, the level of the second reference voltage Vm10 is determined based on the level of the third read voltage Vh. For example, the level of the second reference voltage Vm10 and the level of the third read voltage Vh may be substantially equal.

[0097] When Figure 8 When the adjacent unselected memory cells (eg, C6 and C8) in the second voltage range V10 to V11 are not weak cells, the first monitoring unit MC0 receives a relatively low third monitoring voltage Vm11.

[0098] On the other hand, when the adjacent unselected memory cell (e.g., C9) is Fig. 9 When the weak cell C9 is a weak cell, the weak cell C9 receives a relatively high third read voltage Vh. Therefore, the first monitor cell MC0 receives a fourth monitor voltage Vm12 having a high level within the second voltage range V10 to V11.

[0099] In summary, the first monitoring cell MC0 represents at least one weak cell located in the cell string STR0. The level of the monitoring voltage Vm provided to the first monitoring MC0 can be adjusted according to the level of the voltage provided to the weak cell. Therefore, it is possible to identify whether at least one weak cell of the cell string STR0 has degraded simply by checking whether the first monitoring cell MC0 has degraded. Therefore, it is possible to check whether the first monitoring cell MC0 has degraded and make a recycling request based on the check result.

[0100] Fig.11 FIG. 1 is a diagram for explaining a method of driving a nonvolatile memory device according to a fourth embodiment. Fig.10 Features and aspects described.

[0101] refer to Fig.11 , the level of the monitoring voltage Vm may be determined within a second voltage range V10 to V11 including the second reference voltage Vm10. Specifically, the second voltage range V10 to V11 may extend from the second reference voltage Vm10 to both sides. Here, the level of the second reference voltage Vm10 is determined based on the level of the third read voltage Vh. For example, the level of the second reference voltage Vm10 may be determined as an average value of the second read voltage Vread and the third read voltage Vh, but the embodiment is not limited to this case.

[0102] exist Fig.11 In the embodiment, the lower limit V10 of the second voltage range V10 to V11 is equal to the second read voltage Vread, and the upper limit V11 is equal to the third read voltage Vh, but the embodiment is not limited to this case.

[0103] Fig.12 is a diagram for explaining a method of driving a nonvolatile memory device according to a fifth embodiment. Fig.12 1 is a diagram for explaining the level of the monitoring voltage when the memory cell is an MLC. For the convenience of description, the following will mainly describe the Figures 8 to 11 Features and aspects described.

[0104] refer to Fig.12 , the read voltage Vr1 is greater than the threshold voltage of the memory cell with data '11' and less than the threshold voltage of the memory cell with data '10'. The read voltage Vr2 is greater than the threshold voltage of the memory cell with data '10' and less than the threshold voltage of the memory cell with data '00'. The read voltage Vr3 is greater than the threshold voltage of the memory cell with data '00' and less than the threshold voltage of the memory cell with data '01'. The non-select read voltage Vread is higher than the threshold voltage of the memory cell with data '01'.

[0105] The monitoring voltage Vm is applied to the first monitoring cell MC0 through the monitoring line MWL0. The level of the monitoring voltage Vm applied to the first monitoring cell MC0 may be adjusted depending on whether unselected memory cells (e.g., C7 and C9) adjacent to the memory cell to be read (e.g., C8) are weak cells.

[0106] During a read operation, when adjacent unselected memory cells (e.g., C7 and C9) to which the third read voltage Vh is applied are weak cells, a relatively high fourth monitor voltage Vm12 is applied. When all adjacent unselected memory cells (e.g., C7 and C9) to which the third read voltage Vh is applied are not weak cells, a relatively low third monitor voltage Vm11 is applied.

[0107] Fig.13 is a diagram for explaining a method of driving a nonvolatile memory device according to a sixth embodiment.

[0108] refer to Fig.13 , the level of the monitor voltage Vm may be adjusted according to the characteristics of a memory block including memory cells to be read.

[0109] Specifically, the nonvolatile memory device includes a first memory block BLK0 and a second memory block BLK1. The first cell string is located in the first memory block BLK0 and includes a plurality of memory cells and a first monitoring cell MC10. The second cell string is located in the second memory block BLK1 and includes a plurality of memory cells and a second monitoring cell MC11. The monitoring voltage (e.g., Vm11) provided to the first monitoring cell MC10 and the monitoring voltage (e.g., Vm12) provided to the second monitoring cell MC11 may be different from each other.

[0110] For example, when the second memory block BLK1 is a weak block, the monitoring voltage Vm12 provided to the second monitoring unit MC11 is relatively high by reflecting this. On the other hand, when the first memory block BLK0 is not a weak block, the monitoring voltage Vm11 provided to the first monitoring unit MC10 is relatively low by reflecting this.

[0111] Fig.14 is a diagram illustrating a method of driving a nonvolatile memory device according to a seventh embodiment. Fig.15 The diagram shows a process in which the threshold voltages of a plurality of monitoring cells are changed.

[0112] refer to Fig.14 , a read operation is performed at S10.

[0113] For example, when reading a first memory cell, a first read voltage Vr is provided to the first memory cell, a second read voltage Vread is provided to a memory cell spaced apart from the first memory cell, a third read voltage Vh is provided to an unselected memory cell adjacent to the first memory cell, and a first monitoring voltage is provided to the monitoring unit.

[0114] When reading a second memory cell different from the first memory cell, a first read voltage Vr is provided to the second memory cell, a second read voltage Vread is provided to a memory cell separated from the second memory cell, a third read voltage Vh is provided to an unselected memory cell adjacent to the second memory cell, and a second monitoring voltage different from the first monitoring voltage is provided to the monitoring unit.

[0115] As described above, when the adjacent memory cell receiving the third read voltage Vh is a weak cell, a relatively high monitoring voltage is provided to the monitoring cell. When the adjacent memory cell receiving the third read voltage Vh is not a weak cell, a relatively low monitoring voltage is provided to the monitoring cell.

[0116] The number of read operations performed on the cell string is counted at S20. That is, the number of read operations performed on each of the plurality of memory cells included in the cell string is counted.

[0117] It is checked at S30 whether the counted number of read operations has reached a reference number.

[0118] When the counted number of read operations reaches the reference number, the number of open cells or closed cells is counted by reading a plurality of monitoring cells connected to the monitoring line at S40. Based on the counted number of open cells or closed cells, it is determined whether the monitoring cell has degraded.

[0119] refer to Fig.15 , before performing the read operation, the threshold of the monitoring unit connected to the monitoring line may be lower than the first read voltage Vr. That is, the threshold voltage distribution 90 may be lower than the first read voltage Vr.

[0120] When the read operation is repeated, the monitoring cell is soft-programmed. An example of a mechanism of soft programming is that the pass voltage applied to the unselected cell during the read event causes electrons to be introduced into the capture layer little by little. Therefore, the threshold voltage of the monitoring cell gradually increases. That is, the threshold voltage distribution 92 gradually moves to the right. Therefore, the threshold voltage of some monitoring cells becomes higher than the first read voltage Vr. The number of turned-on cells can be gradually reduced, and the number of turned-off cells can be gradually increased.

[0121] For example, when the counted number of closed cells is equal to or greater than a reference number at S50, a recycling request is made at S60. Conversely, when the counted number of open cells is equal to or less than a reference number, a recycling request is made.

[0122] When the counted number of closed cells is equal to or less than the reference number at S50, no recycling request is made. Conversely, when the counted number of open cells is equal to or greater than the reference number, no recycling request is made.

[0123] Fig.16 is a diagram illustrating a method of driving a nonvolatile memory device according to an eighth embodiment.

[0124] Whether to make a reclaim request may be determined not only by counting the number of on-cells / off-cells but also by checking whether adjacent non-selected memory cells have degraded.

[0125] More specifically, refer to Fig.16 , even when the number of counted off cells is equal to or less than the reference number at S50, it is checked at S70 whether the unselected memory cells adjacent to the last read memory cell have degraded. That is, if the last read memory cell is C7, it is checked whether C6 and C8 have degraded. This is because the adjacent unselected memory cells receiving the third read voltage Vh having a high level can be easily degraded as described above.

[0126] When it is determined that the adjacent non-selected memory cells have degraded, a reclaim request is made at S60.

[0127] When it is determined that the adjacent non-selected memory cells are not degraded, no reclaim request is made.

[0128] Although the present disclosure has been specifically shown and described with reference to example embodiments, it will be appreciated by those skilled in the art that various changes in form and detail may be made thereto without departing from the spirit and scope of the present disclosure as defined in the appended claims. Therefore, the above example embodiments should be considered as merely illustrative and not restrictive.

Claims

1. A storage device, comprising: A non-volatile memory device (100), which is a NAND flash memory device, comprising: A memory cell array (110) comprising a first cell string (STR0) comprising a first plurality of memory cells connected in series and a first monitoring cell (MC0), wherein the first plurality of memory cells comprises a first memory cell and a second memory cell; A row decoder (150) configured to: When reading a first memory cell among a first plurality of memory cells, providing a first read voltage (Vr) to the first memory cell among the first plurality of memory cells and providing a first monitoring voltage (Vm1) to the first monitoring unit (MC0), and When reading a second memory cell among the first plurality of memory cells, the first read voltage (Vr) is provided to the second memory cell among the first plurality of memory cells and a second monitoring voltage (Vm2) different from the first monitoring voltage (Vm1) is provided to the first monitoring unit (MC0), wherein the first monitoring voltage (Vm1) or the second monitoring voltage (Vm2) is higher than the first read voltage (Vr), and The row decoder (150) is further configured to: When reading a first memory cell or a second memory cell among the first plurality of memory cells, a second read voltage (Vread) is provided to an unselected memory cell spaced apart from the first memory cell or the second memory cell among the first plurality of memory cells, and a third read voltage (Vh) is provided to an unselected memory cell adjacent to the first memory cell or the second memory cell among the first plurality of memory cells, and Wherein, the second read voltage (Vread) is higher than the first read voltage (Vr), Wherein, the third read voltage (Vh) is higher than the second read voltage (Vread), and A memory controller (200) comprising a reclaim controller (210); Wherein, the recycling controller (210) is configured as follows: checking whether the first monitoring unit (MC0) has degraded; and A recall request is made based on the inspection results.

2. The storage device according to claim 1, wherein: The first monitoring voltage (Vm1) or the second monitoring voltage (Vm2) is determined within a first voltage range including a first reference voltage (Vm0), and a level of the first reference voltage (Vm0) is determined based on a level of the second read voltage (Vread).

3. The storage device according to claim 1, wherein: The row decoder (150) is further configured to adjust the first monitoring voltage (Vm1) or the second monitoring voltage (Vm2) within a second voltage range, the second voltage range including a second reference voltage (Vm10), and Wherein, the level of the second reference voltage (Vm10) is determined based on the level of the third read voltage (Vh).

4. The storage device according to claim 1, wherein: The row decoder (150) is further configured to adjust a level of the first monitoring voltage (Vm1) or the second monitoring voltage (Vm2) according to whether an unselected memory cell adjacent to the first memory cell or the second memory cell among the first plurality of memory cells is a weak cell.

5. The storage device according to claim 1, wherein: The memory cell array (110) further comprises: a first memory block (BLK0); and The second memory block (BLK1), The first cell string (STR0) is located in the first memory block, the second cell string (STR1) is located in the second memory block, the second cell string (STR1) includes a second plurality of memory cells and a second monitoring cell (MC11), the second plurality of memory cells includes a first memory cell, a second memory cell and a third memory cell, wherein the row decoder (150) is further configured to, when reading a third memory cell among the second plurality of memory cells, provide the first read voltage (Vr) to the third memory cell among the second plurality of memory cells and provide a third monitoring voltage (Vm11) to the second monitoring unit (MC11), and The third monitoring voltage (Vm11) is different from the first monitoring voltage (Vm1).

6. The storage device according to claim 1, wherein: The recycling controller (210) is further configured to check by counting a first number of open cells or a second number of closed cells, wherein the counting of the first number of open cells or the second number of closed cells is performed by reading a plurality of first monitoring cells (MC0) connected to the monitoring line, and Wherein, the checking is based on the first quantity or the second quantity.

7. The storage device according to claim 1, wherein: The recycling controller (210) is further configured to perform the inspection by the following operations: counting a third number of read operations performed on the first cell string (STR0); and The third quantity is compared to a reference quantity.

8. The storage device according to claim 7, wherein: When the third number of read operations reaches the reference number, the recycling controller (210) is further configured to check whether unselected memory cells adjacent to the last read memory cell have degraded.

9. The storage device according to claim 1, wherein: The first cell string (STR0) further includes a string selection element and a ground selection element, the first plurality of memory cells are connected in series between the string selection element and the ground selection element, and the first monitoring unit (MC0) is located between the string selection element and the first plurality of memory cells or between the ground selection element and the first plurality of memory cells.

10. The storage device according to claim 1, comprising: The memory cell array (110) comprises a plurality of memory blocks, each of the plurality of memory blocks comprises a plurality of cell strings (STR0-STRm), each of the plurality of cell strings (STR0-STRm) comprises a plurality of memory cells and a monitoring unit (MC0, MC11), a first memory block (BLK0) of the plurality of memory blocks comprises a first plurality of cell strings (STR0-STRm), the first plurality of cell strings (STR0-STRm) comprises a first cell string (STR0), and the first cell string (STR0) comprises a selected memory cell, an unselected memory cell and a first monitoring unit (MC0); and The row decoder (150) is configured to: adjusting a monitoring voltage (Vm1) according to at least one of: a characteristic of the selected memory cell, a characteristic of unselected memory cells adjacent to the selected memory cell in the first cell string, and a characteristic of the first memory block (BLK0); as well as During a read operation, a first read voltage (Vr) is provided to the selected memory cells, a second read voltage (Vread) is provided to the unselected memory cells, and the monitoring voltage (Vm1) is provided to the first monitoring unit (MC0).

11. The storage device according to claim 10, wherein: When the selected memory cell is a weak cell, the monitoring voltage (Vm1) is a first level, and when the selected memory cell is not a weak cell, the monitoring voltage (Vm1) is a second level higher than the first level.

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