Semiconductor package

Abstract

A semiconductor package includes a mounting substrate, a first semiconductor chip located on the mounting substrate and electrically connected to the mounting substrate, a heat dissipation element located on an upper surface of the first semiconductor chip, wherein the heat dissipation element includes a side wall and an upper surface, the side wall includes an inclined surface, and the upper surface is directly connected to the inclined surface, and a package molding portion located on the mounting substrate and the inclined surface of the heat dissipation element. The package molding portion exposes at least a portion of the upper surface of the heat dissipation element, the upper surface of the heat dissipation element is parallel to an upper surface of the first semiconductor chip, and an angle formed by the upper surface of the heat dissipation element and the inclined surface of the heat dissipation element is obtuse.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0103432, filed with the Korean Intellectual Property Office on August 23, 2019, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to semiconductor packages, and more specifically, to semiconductor packages comprising a structure including a chip or thermal conductor exposed to the outside. Background Technology

[0004] With the rapid development of the electronics industry and the increasing demands of users, electronic devices are becoming smaller and lighter. Semiconductor packages used in electronic devices are not only being manufactured to be smaller and lighter, but also possess high performance and high capacity.

[0005] To achieve high performance, the structure of semiconductor packages is being continuously researched and developed to effectively dissipate the heat generated during the semiconductor packaging process. Summary of the Invention

[0006] Various aspects of this disclosure provide semiconductor packages that enhance the strength of semiconductor chips or heat dissipation elements exposed to the outside during the assembly of the semiconductor package.

[0007] According to one aspect of this disclosure, a semiconductor package is provided, comprising: a mounting substrate; a first semiconductor chip disposed on and electrically connected to the mounting substrate; a heat dissipation element disposed on an upper surface of the first semiconductor chip, wherein the heat dissipation element includes a sidewall having an inclined surface and an upper surface directly connected to the inclined surface; and a package molding portion disposed on the mounting substrate and on the inclined surface of the heat dissipation element. The package molding portion exposes at least a portion of the upper surface of the heat dissipation element, the upper surface of the heat dissipation element being parallel to the upper surface of the first semiconductor chip, and the angle formed by the upper surface of the heat dissipation element and the inclined surface of the heat dissipation element being an obtuse angle.

[0008] According to another aspect of this disclosure, a semiconductor package is provided, comprising: a mounting substrate; a first semiconductor chip located on the mounting substrate, the first semiconductor chip including an upper surface and a lower surface facing away from each other and a sidewall connecting the upper surface and the lower surface, wherein the first semiconductor chip is electrically connected to the mounting substrate; and a package molding portion located on the mounting substrate and on the sidewall of the first semiconductor chip, wherein the package molding portion exposes at least a portion of the upper surface of the first semiconductor chip, wherein the sidewall of the first semiconductor chip includes an inclined surface, and the angle formed by the upper surface of the first semiconductor chip and the inclined surface of the first semiconductor chip is an obtuse angle.

[0009] According to another aspect of this disclosure, a semiconductor package is provided, comprising: a mounting substrate; a first semiconductor chip located on the mounting substrate; a connection terminal electrically connecting the first semiconductor chip and the mounting substrate; a bottom filler portion located between the mounting substrate and the first semiconductor chip and located on the connection terminal; a second semiconductor chip located on a first portion of an upper surface of the first semiconductor chip; a heat dissipation element located on a second portion of an upper surface of the first semiconductor chip and a portion of an upper surface of the second semiconductor chip; and a package molding portion located on the mounting substrate, the first semiconductor chip, the second semiconductor chip, and the heat dissipation element, wherein the package molding portion exposes at least a portion of an upper surface of the heat dissipation element, wherein the heat dissipation element includes a first sidewall directly connected to the upper surface of the heat dissipation element, the package molding portion is located on the first sidewall of the heat dissipation element, and the angle formed by the upper surface of the heat dissipation element and the first sidewall of the heat dissipation element is in the range of 115 degrees to 170 degrees.

[0010] A semiconductor package includes: a mounting substrate; a first semiconductor chip located on and electrically connected to the mounting substrate; a second semiconductor chip located on and electrically connected to the mounting substrate; and a heat dissipation element located on the first semiconductor chip and the second semiconductor chip, wherein the heat dissipation element includes a sidewall having an inclined surface and an upper surface directly connected to the inclined surface, and wherein the angle formed by the upper surface of the heat dissipation element and the inclined surface of the heat dissipation element is an obtuse angle.

[0011] However, the aspects of this disclosure are not limited to the one set forth herein. These and other aspects of the disclosure will become more apparent to those skilled in the art upon reference to the detailed description of the disclosure given below. Attached Figure Description

[0012] Figure 1A Semiconductor packages according to some embodiments of the present disclosure are shown.

[0013] Figure 1B Semiconductor packages according to some embodiments of the present disclosure are shown.

[0014] Figure 2A Semiconductor packages according to some embodiments of the present disclosure are shown.

[0015] Figure 2B Semiconductor packages according to some embodiments of the present disclosure are shown.

[0016] Figure 3A Semiconductor packages according to some embodiments of the present disclosure are shown.

[0017] Figure 3B Semiconductor packages according to some embodiments of the present disclosure are shown.

[0018] Figure 4A Semiconductor packages according to some embodiments of the present disclosure are shown.

[0019] Figure 4B Semiconductor packages according to some embodiments of the present disclosure are shown.

[0020] Figure 5 Semiconductor packages according to some embodiments of the present disclosure are shown.

[0021] Figure 6 Semiconductor packages according to some embodiments of the present disclosure are shown.

[0022] Figure 7 Semiconductor packages according to some embodiments of the present disclosure are shown.

[0023] Figure 8 Semiconductor packages according to some embodiments of the present disclosure are shown.

[0024] Figure 9 The process steps for forming a semiconductor package according to some embodiments of the present disclosure are shown.

[0025] Figure 10 This is a graph used to illustrate a semiconductor package according to some embodiments of the present disclosure.

[0026] Figure 11 This is a graph used to illustrate a semiconductor package according to some embodiments of the present disclosure.

[0027] Throughout this text, the same numbers refer to the same elements. Therefore, other accompanying figures can be used to describe the same or similar numbers, even if these numbers are not mentioned or described in the corresponding figures. Additionally, other accompanying figures can be used to describe elements not indicated by the figure labels. Detailed Implementation

[0028] Figure 1A Semiconductor packages according to some embodiments of the present disclosure are shown.

[0029] refer to Figure 1A A semiconductor package according to some embodiments of the present disclosure may include a mounting substrate 100, external terminals 90, connection terminals 110, a first semiconductor chip 120, a second semiconductor chip 140, a package molding portion 160, and a heat dissipation element 150. It should be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms; rather, these terms are used only to distinguish one element from other elements. Therefore, the first element discussed may be referred to as the second element without departing from the scope of the present disclosure.

[0030] Mounting substrate 100 may be a package substrate, and may be, for example, one of a printed circuit board (PCB), an interposer substrate, and a redistribution layer (RDL) substrate, but this disclosure is not limited thereto. Mounting substrate 100 may include an upper surface 100a and a lower surface 100b corresponding to each other. Conductors, pads, connectors, etc., may be formed on the upper surface 100a and / or the lower surface 100b of mounting substrate 100. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0031] External terminals 90 may be disposed on the lower surface 100b of the mounting substrate 100. External terminals 90 can electrically connect the semiconductor package to an external device. External terminals 90 can provide electrical signals to the first semiconductor chip 120 and / or the second semiconductor chip 140, or can provide electrical signals from the first semiconductor chip 120 and / or the second semiconductor chip 140 to an external device.

[0032] The first semiconductor chip 120 and the second semiconductor chip 140 can be disposed on the mounting substrate 100. The first semiconductor chip 120 can be disposed between the second semiconductor chip 140 and the mounting substrate 100.

[0033] The width of the first semiconductor chip 120 and the width of the second semiconductor chip 140 may be the same or different.

[0034] In a semiconductor package according to some embodiments of the present disclosure, a first semiconductor chip 120 may be electrically connected to a mounting substrate 100. For example, the first semiconductor chip 120 and the mounting substrate 100 may be electrically connected via flip-chip bonding.

[0035] In a semiconductor package according to some embodiments of the present disclosure, a second semiconductor chip 140 may be electrically connected to a mounting substrate 100. For example, the second semiconductor chip 140 and the mounting substrate 100 may be electrically connected via wire bonding.

[0036] In a semiconductor package according to some embodiments of the present disclosure, a second semiconductor chip 140 may include a second chip pad 140P. The second chip pad 140P of the second semiconductor chip 140 may be electrically connected to a substrate pad 100P of a mounting substrate 100 via a second wire 140w.

[0037] For example, each of the first semiconductor chip 120 and the second semiconductor chip 140 can be a memory semiconductor chip. The memory semiconductor chip can be a volatile memory semiconductor chip such as dynamic random access memory (DRAM) or static random access memory (SRAM), or it can be a non-volatile memory semiconductor chip such as phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM), or resistive random access memory (RRAM).

[0038] In another example, the first semiconductor chip 120 may be a logic semiconductor chip, and the second semiconductor chip 140 may be a memory semiconductor chip. The first semiconductor chip 120 may also be a controller semiconductor chip that controls the operation (e.g., input / output operation) of the second semiconductor chip 140, which is electrically connected to the first semiconductor chip 120.

[0039] The connection terminal 110 may be disposed between the upper surface 100a of the mounting substrate 100 and the lower surface 120b of the first semiconductor chip 120. Although the connection terminal 110 is shown as spherical, this disclosure is not limited thereto. For example, the connection terminal 110 may also be in the shape of a solder bump, which is a combination of a pillar and a solder ball. Although not shown, the first semiconductor chip 120 may include pads made of a metallic material.

[0040] The column may be cylindrical and may comprise, for example, nickel (Ni), copper (Cu), palladium (Pd), platinum (Pt), gold (Au), or combinations thereof. According to embodiments, a diffusion barrier layer and / or an adhesive layer may be formed between the column and the solder layer. The diffusion barrier layer may comprise, for example, nickel (Ni), cobalt (Co), copper (Cu), or combinations thereof. The adhesive layer may comprise, for example, nickel (Ni), copper (Cu), palladium (Pd), cobalt (Co), platinum (Pt), gold (Au), or combinations thereof.

[0041] The bottom filling portion 115 can be in the space between the upper surface 100a of the mounting substrate 100 and the lower surface 120b of the first semiconductor chip 120, and in some embodiments, fills the space. The bottom filling portion 115 can redistribute the stress and deformation caused by the difference in the coefficients of thermal expansion between the first semiconductor chip 120 and the mounting substrate 100.

[0042] The bottom filling portion 115 is shown to partially cover the first sidewall 120c and the second sidewall 120d of the first semiconductor chip 120, but this disclosure is not limited to this case.

[0043] In a semiconductor package according to some embodiments of the present disclosure, a heat dissipation element 150 may be disposed on a first semiconductor chip 120. The heat dissipation element 150 may cover a portion of the upper surface 120a of the first semiconductor chip 120 and a portion of the upper surface 140a of the second semiconductor chip 140.

[0044] The upper surface 150a of the heat dissipation element 150 can be parallel to the upper surface 120a of the first semiconductor chip 120 and the upper surface 140a of the second semiconductor chip 140.

[0045] The heat dissipation element 150 may include a first lower surface 150b_1 and a second lower surface 150b_2.

[0046] The first lower surface 150b_1 of the heat dissipation element 150 can partially cover the upper surface 120a of the first semiconductor chip 120. In addition, the first lower surface 150b_1 of the heat dissipation element 150 can be parallel to the lower surface 120b of the first semiconductor chip 120 and the upper surface 140a of the second semiconductor chip 140.

[0047] The second lower surface 150b_2 of the heat dissipation element 150 can partially cover the upper surface 140a of the second semiconductor chip 140. In addition, the second lower surface 150b_2 of the heat dissipation element 150 can be parallel to the upper surface 120a of the first semiconductor chip 120 and the lower surface 140b of the second semiconductor chip 140.

[0048] The first lower surface 150b_1 and the second lower surface 150b_2 of the heat dissipation element 150 can also be parallel to the upper surface 100a of the mounting substrate 100, which is parallel to the upper surface 120a and the lower surface 120b of the first semiconductor chip 120.

[0049] In a semiconductor package according to some embodiments of the present disclosure, a heat dissipation element 150 may include a first sidewall 150c and a second sidewall 150d.

[0050] The first sidewall 150c of the heat dissipation element 150 may include a first inclined surface 150c_1.

[0051] The second sidewall 150d of the heat dissipation element 150 may include a second inclined surface 150d_1 and a first connecting sidewall 150d_2 extending from the second inclined surface 150d_1 to the upper surface 120a of the first semiconductor chip 120.

[0052] The third portion of the sidewall 150c_3 of the heat dissipation element 150 is a sidewall that extends from the second lower surface 150b_2 of the heat dissipation element 150 to the first lower surface 150b_1 of the heat dissipation element 150 along the second sidewall 140d of the second semiconductor chip 140. In some embodiments, the third portion of the sidewall 150c_3 is physically separated from the first sidewall 150c and the second sidewall 150d of the heat dissipation element 150 (e.g., the third portion of the sidewall 150c_3 is not directly connected to the first sidewall 150c and the second sidewall 150d of the heat dissipation element 150).

[0053] The third portion of the heat dissipation element 150 sidewall 150c_3 may be parallel to the first sidewall 120c and the second sidewall 120d of the first semiconductor chip 120, which are opposite to each other. In addition, the third portion of the heat dissipation element 150 sidewall 150c_3 may be parallel to the first connecting sidewall 150d_2 of the heat dissipation element 150.

[0054] In a semiconductor package according to some embodiments of the present disclosure, the first connection sidewall 150d_2 of the heat dissipation element 150 may be parallel to the first sidewall 140c of the second semiconductor chip 140 and the first sidewall 120c of the first semiconductor chip 120.

[0055] In a semiconductor package according to some embodiments of the present disclosure, the angle A1_1 formed by the first inclined surface 150c_1 of the heat dissipation element 150 and the upper surface 150a of the heat dissipation element 150 is an obtuse angle.

[0056] In some embodiments of the semiconductor package according to this disclosure, the angle A1_2 formed by the second inclined surface 150d_1 of the heat dissipation element 150 and the upper surface 150a of the heat dissipation element 150 is an obtuse angle. In some embodiments, angle A1_2 may be different from angle A1_1.

[0057] In a semiconductor package according to some embodiments of the present disclosure, the angle A1_3 formed by the second inclined surface 150d_1 of the heat dissipation element 150 and the first connecting sidewall 150d_2 of the heat dissipation element 150 can be an obtuse angle, but is not limited to an obtuse angle.

[0058] The range of obtuse angles will be referenced in this article. Figure 10 and Figure 11 Describe it.

[0059] In a semiconductor package according to some embodiments of the present disclosure, the slope of the first connecting sidewall 150d_2 of the heat dissipation element 150 may be different from the slope of the second inclined surface 150d_1 of the heat dissipation element 150. In a semiconductor package according to some embodiments of the present disclosure, the slope of the first inclined surface 150c_1 of the heat dissipation element 150 may be different from the slope of the second inclined surface 150d_1 of the heat dissipation element 150.

[0060] In a semiconductor package according to some embodiments of the present disclosure, a heat dissipation element 150 may partially cover the upper surface 120a of a first semiconductor chip 120 and partially cover the upper surface 140a of a second semiconductor chip 140.

[0061] In some embodiments, the heat dissipation element 150 may be a heat conductor or include a heat conductor. In some embodiments, the heat dissipation element 150 may be thermally connected to the first semiconductor chip 120 and / or the second semiconductor chip 140, and may be configured to remove heat generated by the first semiconductor chip 120 and / or the second semiconductor chip 140. For example, the heat dissipation element 150 may include at least one metallic material or alloy of metallic materials selected from silver (Ag), aluminum (Al), copper (Cu), platinum (Pt), zinc (Zn), nickel (Ni), and iron (Fe), but the embodiments of this disclosure are not limited thereto.

[0062] In a semiconductor package according to some embodiments of the present disclosure, a heat dissipation element 150 may be on and in some embodiments cover the second sidewall 130d of the adhesive layer 130 between the first semiconductor chip 120 and the second semiconductor chip 140.

[0063] An adhesive layer 130 may be disposed between a first semiconductor chip 120 and a second semiconductor chip 140. A portion of the upper surface 120a of the first semiconductor chip 120 may be connected to the lower surface 130b of the adhesive layer 130, and a portion of the lower surface 140b of the second semiconductor chip 140 may be connected to the entire upper surface 130a and / or a portion of the upper surface 130a of the adhesive layer 130. Figure 1A As shown, the second sidewall 130d of the adhesive layer 130 can contact and / or be coplanar with the third sidewall 150c_3 of the heat dissipation element 150.

[0064] In a semiconductor package according to some embodiments of the present disclosure, the height h2 from the upper surface 100a of the mounting substrate 100 to the first lower surface 150b_1 of the heat dissipation element 150 may be equal to, but is not limited to, the height h1 from the upper surface 100a of the mounting substrate 100 to the upper surface 120a of the first semiconductor chip 120.

[0065] The encapsulation molding part 160 may be provided on the upper surface 100a of the mounting substrate 100.

[0066] The package molding portion 160 may be located on the first semiconductor chip 120, the second semiconductor chip 140, the underfill portion 115, and / or the heat dissipation element 150, and in some embodiments, it may cover the first semiconductor chip 120, the second semiconductor chip 140, the underfill portion 115, and / or the heat dissipation element 150. The package molding portion 160 may increase the adhesion between the first semiconductor chip 120 and the second semiconductor chip 140 and the mounting substrate 100. In addition, the package molding portion 160 may maintain the appearance of the semiconductor package and protect the first semiconductor chip 120 and the second semiconductor chip 140 from external physical impacts, moisture, and other effects.

[0067] The encapsulation molding portion 160 can be formed by molding processes using, for example, any of epoxy molding compound (EMC), silicone resin, polyimide, and equivalents.

[0068] The first sidewall 120c of the first semiconductor chip 120 can be spaced apart from the sidewall 160c of the package molding portion 160 by a distance D1. The first sidewall 140c of the second semiconductor chip 140 can be spaced apart from the sidewall 160c of the package molding portion 160 by a distance D2.

[0069] In some embodiments of the semiconductor package according to this disclosure, the distance D1 from the sidewall 160c of the package molding portion 160 to the first sidewall 120c of the first semiconductor chip 120 may be greater than the distance D2 from the sidewall 160c of the package molding portion 160 to the first sidewall 140c of the second semiconductor chip 140. For example, in some embodiments, the first sidewall 120c of the first semiconductor chip 120 may not be coplanar with the first sidewall 140c of the second semiconductor chip 140.

[0070] Figure 1B Semiconductor packages according to some embodiments of the present disclosure are shown.

[0071] Regarding the above references Figure 1A Descriptions of elements and features that are substantially the same or similar will be omitted or given briefly, and the differences will be described in detail below.

[0072] Referring to 1B, the width of the adhesive layer 130 can be greater than the width of the second semiconductor chip 140. Specifically, the adhesive layer 130 can extend to cover the entire upper surface 120a of the first semiconductor chip 120. A portion of the adhesive layer 130 can be disposed between the heat dissipation element 150 and the first semiconductor chip 120. Therefore, the height h2 from the upper surface 100a of the mounting substrate 100 to the first lower surface 150b_1 of the heat dissipation element 150 can be greater than, but not limited to, the height h1 from the upper surface 100a of the mounting substrate 100 to the upper surface 120a of the first semiconductor chip 120.

[0073] Figure 2A Semiconductor packages according to some embodiments of the present disclosure are illustrated. For ease of description, the following description will focus on those referenced above. Figure 1A The differences in the components and features described.

[0074] refer to Figure 2A In a semiconductor package according to some embodiments of the present disclosure, a first semiconductor chip 120 can be electrically connected to a mounting substrate 100 via a first wire 120w.

[0075] Similar to the first semiconductor chip 120, the second semiconductor chip 140 can be electrically connected to the mounting substrate 100 via the second wire 140w.

[0076] The first semiconductor chip 120 and the second semiconductor chip 140 may each include a first chip pad 120P and a second chip pad 140P. The mounting substrate 100 may include a first substrate pad 100P_1 and a second substrate pad 100P_2. The first substrate pad 100P_1 is connected to the first chip pad 120P via a first wire 120w, and the second substrate pad 100P_2 is connected to the second chip pad 140P via a second wire 140w.

[0077] The adhesive layer 130 may include a first adhesive layer 130_1 and a second adhesive layer 130_2. The first adhesive layer 130_1 may be disposed between the first semiconductor chip 120 and the mounting substrate 100. The second adhesive layer 130_2 may be disposed between the first semiconductor chip 120 and the second semiconductor chip 140. (Reference) Figure 2A The width of the second adhesive layer 130_2 may be equal to the width of the second semiconductor chip 140, but the embodiments of this disclosure are not limited thereto.

[0078] In some embodiments of the semiconductor package according to the present disclosure, the distance D1 from the sidewall 160c of the package molding portion 160 to the first sidewall 120c of the first semiconductor chip 120 may be less than the distance D2 from the sidewall 160c of the package molding portion 160 to the first sidewall 140c of the second semiconductor chip 140.

[0079] The first sidewall 150c of the heat dissipation element 150 may include a first inclined surface 150c_1 and a second connecting sidewall 150c_2 extending from the first inclined surface 150c_1 of the heat dissipation element 150 to the upper surface 140a of the second semiconductor chip 140.

[0080] The slope of the first inclined surface 150c_1 of the heat dissipation element 150 may be different from the slope of the second connecting sidewall 150c_2 of the heat dissipation element 150. Specifically, the angle A1_4 formed by the first inclined surface 150c_1 and the second connecting sidewall 150c_2 of the heat dissipation element 150 may be an obtuse angle, but is not limited to an obtuse angle.

[0081] Figure 2B Semiconductor packages according to some embodiments of the present disclosure are shown. (Referring to the above references) Figure 2A The descriptions of elements and features that are the same will be omitted or given briefly; the differences will be described below.

[0082] refer to Figure 2BThe width of the second adhesive layer 130_2 may be greater than the width of the second semiconductor chip 140. The second adhesive layer 130_2 may extend to cover the entire upper surface 120a of the first semiconductor chip 120. Specifically, a portion of the second adhesive layer 130_2 may be disposed between the heat dissipation element 150 and the first semiconductor chip 120.

[0083] The encapsulation molding portion 160 may cover the second sidewall 130_2d of the second adhesive layer 130_2. Therefore, the height h2 from the upper surface 100a of the mounting substrate 100 to the first lower surface 150b_1 of the heat dissipation element 150 may be greater than, but not limited to, the height h1 from the upper surface 100a of the mounting substrate 100 to the upper surface 120a of the first semiconductor chip 120.

[0084] Figure 3A Semiconductor packages according to some embodiments of the present disclosure are shown. For ease of description, the following description will focus on the differences from the elements and features described above.

[0085] refer to Figure 3A The first semiconductor chip 120 can be electrically connected to the mounting substrate 100 via flip-chip bonding.

[0086] Since the first semiconductor chip 120 is flip-chip bonded, chip pads do not need to be formed on the upper surface 120a of the first semiconductor chip 120, and second chip pads 140P can be provided on the upper surface 140a of the second semiconductor chip 140.

[0087] In some embodiments of the semiconductor package according to the present disclosure, the distance D1 from the sidewall 160c of the package molding portion 160 to the first sidewall 120c of the first semiconductor chip 120 may be greater than, but not limited to, the distance D2 from the sidewall 160c of the package molding portion 160 to the first sidewall 140c of the second semiconductor chip 140.

[0088] A portion of the lower surface 130b of the adhesive layer 130 disposed between the first semiconductor chip 120 and the second semiconductor chip 140 may be covered by the package molding portion 160.

[0089] The first sidewall 150c of the heat dissipation element 150 may include a first inclined surface 150c_1 and a second connecting sidewall 150c_2 extending from the first inclined surface 150c_1 to the upper surface 140a of the second semiconductor chip 140.

[0090] The second sidewall 150d of the heat dissipation element 150 may include a second inclined surface 150d_1 and a first connecting sidewall 150d_2 extending to the upper surface 120a of the first semiconductor chip 120.

[0091] The slope of the second connecting sidewall 150c_2 of the heat dissipation element 150 may be different from the slope of the first inclined surface 150c_1 of the heat dissipation element 150.

[0092] The slope of the first connecting sidewall 150d_2 of the heat dissipation element 150 may be different from the slope of the second inclined surface 150d_1 of the heat dissipation element 150.

[0093] Figure 3B Semiconductor packages according to some embodiments of the present disclosure are shown. The following description will focus on... Figure 3A The differences.

[0094] refer to Figure 3B The width of the adhesive layer 130 can be greater than the width of the second semiconductor chip 140. Specifically, the adhesive layer 130 can extend to cover the entire upper surface 120a of the first semiconductor chip 120. Therefore, a portion of the adhesive layer 130 can be disposed between the heat dissipation element 150 and the first semiconductor chip 120. The height h2 from the upper surface 100a of the mounting substrate 100 to the first lower surface 150b_1 of the heat dissipation element 150 can be greater than, but not limited to, the height h1 from the upper surface 100a of the mounting substrate 100 to the upper surface 120a of the first semiconductor chip 120.

[0095] Figure 4A Semiconductor packages according to some embodiments of the present disclosure are shown. For ease of description, the following description will focus on the differences from the elements and features described above.

[0096] refer to Figure 4A In some embodiments of the semiconductor package according to the present disclosure, the distance D1 from the sidewall 160c of the package molding portion 160 to the first sidewall 120c of the first semiconductor chip 120 may be equal to the distance D2 from the sidewall 160c of the package molding portion 160 to the first sidewall 140c of the second semiconductor chip 140.

[0097] Figure 4B Semiconductor packages according to some embodiments of the present disclosure are shown. The following description will focus on... Figure 4A The differences.

[0098] refer to Figure 4BThe width of the adhesive layer 130 can be greater than the width of the second semiconductor chip 140. Specifically, the adhesive layer 130 can extend to cover the entire upper surface 120a of the first semiconductor chip 120. Therefore, a portion of the adhesive layer 130 can be disposed between the heat dissipation element 150 and the first semiconductor chip 120. The height h2 from the upper surface 100a of the mounting substrate 100 to the first lower surface 150b_1 of the heat dissipation element 150 can be greater than, but not limited to, the height h1 from the upper surface 100a of the mounting substrate 100 to the upper surface 120a of the first semiconductor chip 120.

[0099] Figure 5 Semiconductor packages according to some embodiments of the present disclosure are shown. For ease of description, the following description will focus on the differences from the elements and features described above.

[0100] refer to Figure 5 The first semiconductor chip 120 can be electrically connected to the mounting substrate 100 via the first wire 120w.

[0101] In a semiconductor package according to some embodiments of the present disclosure, the first sidewall 150c of the heat dissipation element 150 may include a first inclined surface 150c_1 extending from the upper surface 120a of the first semiconductor chip 120.

[0102] The second sidewall 150d of the heat dissipation element 150 may include a second inclined surface 150d_1 extending from the upper surface 120a of the first semiconductor chip 120. Figures 1A to 4B Unlike other heat dissipation elements, the first sidewall 150c and the second sidewall 150d of the heat dissipation element 150 may not include the connecting sidewall.

[0103] In a semiconductor package according to some embodiments of the present disclosure, the entire lower surface 150b of the heat dissipation element 150 may cover a portion of the upper surface 120a of the first semiconductor chip 120.

[0104] In a semiconductor package according to some embodiments of the present disclosure, a first semiconductor chip 120 may include a first chip pad 120P. A mounting substrate 100 may include a mounting substrate pad 100P. The first semiconductor chip 120 may be electrically connected to the mounting substrate 100 via a first wire 120W.

[0105] Figure 6 Semiconductor packages according to some embodiments of the present disclosure are shown. For ease of description, the following description will focus on the differences from the elements and features described above.

[0106] refer to Figure 6The third semiconductor chip 220 may include an upper surface 220a and a lower surface 220b facing away from each other on the mounting substrate 100. In a semiconductor package according to some embodiments of the present disclosure, the package molding portion 160 may cover the first sidewall 220c and the second sidewall 220d of the third semiconductor chip 220, but may not cover the upper surface 220a of the third semiconductor chip 220.

[0107] The bottom filler portion 115 may extend along the lower surface 220b of the third semiconductor chip 220 between the third semiconductor chip 220 and the mounting substrate 100. The bottom filler portion 115 may surround the connection terminal 110 disposed between the third semiconductor chip 220 and the mounting substrate 100. It should be understood that, as used herein, "element A surrounds element B" (or similar language) means that element A is at least partially around element B, but does not necessarily mean that element A completely encloses element B.

[0108] In some embodiments of this disclosure, the angle A2_1 formed by the upper surface 220a of the third semiconductor chip 220 and the first sidewall 220c of the third semiconductor chip 220 can be an obtuse angle.

[0109] In some embodiments of this disclosure, the angle A2_2 formed by the upper surface 220a of the third semiconductor chip 220 and the second sidewall 220d of the third semiconductor chip 220 can be an obtuse angle.

[0110] In some embodiments of this disclosure, the angle A2_1 formed by the upper surface 220a and the first sidewall 220c of the third semiconductor chip 220 and the angle A22 formed by the upper surface 220a and the second sidewall 220d of the third semiconductor chip 220 may be equal, but are not limited to, within the limits of the technical process used to manufacture the third semiconductor chip 220.

[0111] Figure 7 Semiconductor packages according to some embodiments of the present disclosure are shown. For ease of description, the following description will focus on those referenced above. Figure 6 The differences in the components and features described.

[0112] refer to Figure 7 The third semiconductor chip 220 and the fourth semiconductor chip 240 can be electrically connected to the mounting substrate 100 via flip-chip bonding.

[0113] Each of the third semiconductor chip 220 and the fourth semiconductor chip 240 can be a memory semiconductor chip. The memory semiconductor chip can be a volatile memory semiconductor chip such as DRAM or SRAM, or a non-volatile memory semiconductor chip such as PRAM, MRAM, FeRAM, or RRAM.

[0114] Additionally, although not shown, the third semiconductor chip 220 and the fourth semiconductor chip 240 can be stacked using chip packaging technology that employs through-silicon via (TSV) technology. Specifically, vias can be formed to penetrate the third semiconductor chip 220, and then the vias can be filled with a conductive material to ensure electrical connection channels within the third semiconductor chip 220. In some embodiments, the third semiconductor chip 220 may be a logic chip such as a central processing unit (CPU) or a graphics processing unit (GPU), or it may be DRAM, while the fourth semiconductor chip 240 may be DRAM.

[0115] In a semiconductor package according to some embodiments of the present disclosure, a first connection terminal 110_1 may be disposed between a mounting substrate 100 and a third semiconductor chip 220.

[0116] The first connection terminal 110_1 may be surrounded by a bottom filler portion 115 extending along the lower surface 220b of the third semiconductor chip 220. Although the first sidewall 220c and the second sidewall 220d of the third semiconductor chip 220 are shown as being partially covered by the bottom filler portion 115, this disclosure is not limited to this.

[0117] In a semiconductor package according to some embodiments of the present disclosure, a second connection terminal 110_2 may be disposed between a third semiconductor chip 220 and a fourth semiconductor chip 240.

[0118] The second connection terminal 110_2 can be surrounded by an inter-chip molding portion 230 extending along the lower surface 240b of the fourth semiconductor chip 240.

[0119] The first sidewall 240c of the fourth semiconductor chip 240 may include a third inclined surface 240c_1 and a third connecting sidewall 240c_2 extending to the lower surface 240b of the fourth semiconductor chip 240.

[0120] The second sidewall 240d of the fourth semiconductor chip 240 may include a fourth inclined surface 240d_1 and a fourth connecting sidewall 240d_2 extending to the lower surface 240b of the fourth semiconductor chip 240.

[0121] The bottom filling portion 115 and the inter-chip molding portion 230 may include, for example, an insulating material.

[0122] The slope of the third connecting sidewall 240c_2 of the fourth semiconductor chip 240 may be different from the slope of the third inclined surface 240c_1 of the fourth semiconductor chip 240.

[0123] The slope of the fourth connecting sidewall 240d_2 of the fourth semiconductor chip 240 may be different from the slope of the fourth inclined surface 240d_1 of the fourth semiconductor chip 240.

[0124] The angle A23 formed by the fourth inclined surface 240d_I of the fourth semiconductor chip 240 and the fourth connecting sidewall 240d_2 of the fourth semiconductor chip 240 can be an obtuse angle, but is not limited to an obtuse angle.

[0125] The third connection sidewall 240c_2 of the fourth semiconductor chip 240 can be parallel to the fourth connection sidewall 240d_2 of the fourth semiconductor chip 240.

[0126] Figure 8 Semiconductor packages according to some embodiments of the present disclosure are illustrated. For ease of description, the following description will focus on those referenced above. Figure 7 The differences in the components and features described.

[0127] refer to Figure 8 In a semiconductor package according to some embodiments of the present disclosure, the first sidewall 240c of the fourth semiconductor chip 240 may include only the third inclined surface 240c_1.

[0128] The second sidewall 240d of the fourth semiconductor chip 240 may consist only of the fourth inclined surface 240d_1.

[0129] Therefore, with Figure 7 Unlike other semiconductor chips, the first sidewall 240c and the second sidewall 240d of the fourth semiconductor chip 240 may not include the connecting sidewall.

[0130] Figure 9 The process steps for forming a semiconductor package according to some embodiments of the present disclosure are shown.

[0131] refer to Figure 9 The process of a grinder 900 colliding with a third semiconductor chip 220 and a fourth semiconductor chip 240 or a heat sink 150 in a semiconductor package according to some embodiments of the present disclosure is illustrated.

[0132] The polishing machine 900 is a wafer polishing device that prevents the wafer from deforming due to the rotation of the grinding wheel that contacts the wafer surface when polishing the wafer surface.

[0133] When the grinder 900 enters the semiconductor chip or heat sink in a horizontal direction, the angle formed between the sidewall of the semiconductor chip or heat sink and the horizontal direction of the grinder 900 is defined as the incident angle θ.

[0134] Figure 10 This is a diagram illustrating a semiconductor package according to some embodiments of the present disclosure.

[0135] refer to Figure 9 and Figure 10 The impulse transmitted during the polishing of a semiconductor chip with an inclined surface (e.g., the third semiconductor chip 220 and / or the fourth semiconductor chip 240 described herein) or a heat dissipation element (e.g., the heat dissipation element 150 described herein). Figure 10 The y-axis represents the rate of change of impulse, and the incident angle θ of the grinder 900 entering the semiconductor chip or heat sink is also relevant. Figure 10 The relationship between the x-axis and the x-axis is shown in Figure 10 middle.

[0136] According to the formula impulse = F × sinθ × Δt, the rate of change of impulse decreases proportionally to the sine value relative to the incident angle θ, where F is the force (N), θ is the incident angle, and Δt is the time change before and after the collision.

[0137] Compared to an incident angle θ of 65 degrees, in other words, theoretically compared to an angle A1_2 formed by the upper surface 150a and the second sidewall 150d of the heat sink 150 of 115 degrees, the rate of change of impulse is reduced to 90% or less. In some embodiments, the sum of θ and the obtuse angle A1_2 formed by the second sidewall 150d and the upper surface 150a of the heat sink 150 may not be 180 degrees. This also applies to the third semiconductor chip 220 or the fourth semiconductor chip 240.

[0138] Figure 11 This is a graph used to illustrate a semiconductor package according to some embodiments of the present disclosure.

[0139] refer to Figures 9 to 11 The rate of reduction of the exposed surface area of ​​the sample ( Figure 11 The area reduction ratio shown on the y-axis is related to the incident angle θ when the grinder 900 enters the semiconductor chip or heat sink. Figure 11 The relationship between the x-axis and the x-axis is shown in Figure 11 middle.

[0140] According to Q = k × A × (ΔT / L), when the incident angle θ is 10 degrees or less, the area of ​​the exposed surface of the semiconductor chip (e.g., the third semiconductor chip 220 and / or the fourth semiconductor chip 240 described herein) or the heat dissipation element (e.g., the heat dissipation element 150 described herein) decreases sharply (the area reduction rate increases sharply), resulting in a decrease in heat dissipation capacity. Here, Q is the heat flux (W), k is the thermal conductivity of the sample (W / (m × K)), and A is the area of ​​the sample (m²). 2 ), where L is the thickness of the sample (m), and ΔT is the absolute temperature difference (K).

[0141] Numerical limitations are important when the incident angle θ is in the range of 10 to 65 degrees. Within this range, the amount of impulse transmitted during the polishing of semiconductor chips or heat dissipation elements with inclined surfaces is reduced, but a sharp reduction in the exposed area does not occur.

[0142] In other words, numerical limitations can have significant benefits when the obtuse angle formed by the inclined surface of the heat sink (or semiconductor chip) and the upper surface of the heat sink (or semiconductor chip) is in the range of 115 to 170 degrees.

[0143] Therefore, it is possible to prevent physical forces generated during the assembly of semiconductor packages (especially grinding or cutting, transfer, transportation, etc.) from damaging heat dissipation components and semiconductor chips (e.g., cracking or splitting). However, this disclosure is not limited to angles.

[0144] Those skilled in the art will understand that many variations and modifications can be made to the exemplary embodiments without substantially departing from the scope of this disclosure as defined by the appended claims. Therefore, the embodiments of this disclosure are used in a general and descriptive sense only and not for limiting purposes.

Claims

1. A semiconductor package, comprising: Mounting substrate; A first semiconductor chip is located on the mounting substrate and is electrically connected to the mounting substrate; A heat dissipation element is located on the upper surface of the first semiconductor chip, wherein the heat dissipation element includes a sidewall, the sidewall including an inclined surface, and the heat dissipation element further includes an upper surface directly connected to the inclined surface; and A package molding portion is located on the mounting substrate and the inclined surface of the heat dissipation element, wherein the package molding portion exposes at least a portion of the upper surface of the heat dissipation element. Wherein, the upper surface of the heat dissipation element is parallel to the upper surface of the first semiconductor chip. Wherein, the angle formed by the upper surface of the heat dissipation element and the inclined surface of the heat dissipation element is an obtuse angle, and Wherein, in a direction perpendicular to the upper surface of the mounting substrate, the first sidewall of the first semiconductor chip does not overlap with the heat dissipation element and extends laterally relative to the heat dissipation element.

2. The semiconductor package according to claim 1, wherein, The angle formed by the upper surface of the heat dissipation element and the inclined surface of the heat dissipation element is in the range of 115 degrees to 170 degrees.

3. The semiconductor package according to claim 1 further includes a second semiconductor chip, the second semiconductor chip being electrically connected to the mounting substrate. in, The first semiconductor chip is located between the mounting substrate and the second semiconductor chip.

4. The semiconductor package according to claim 3, wherein, The second semiconductor chip includes a first sidewall and a second sidewall facing away from each other. The heat dissipation element is located on the second sidewall of the second semiconductor chip and does not overlap with the first sidewall of the second semiconductor chip in a direction perpendicular to the upper surface of the mounting substrate. The encapsulation molding portion is located on the first sidewall of the second semiconductor chip.

5. The semiconductor package according to claim 3, wherein, The first semiconductor chip is a flip chip bonded to the mounting substrate, and the second semiconductor chip is connected to the mounting substrate via wires.

6. The semiconductor package according to claim 3, wherein, The heat dissipation element is located on the upper surface of the second semiconductor chip.

7. The semiconductor package according to claim 3, wherein, The distance from the upper surface of the mounting substrate to the lower surface of the heat dissipation element is equal to or greater than the distance from the upper surface of the mounting substrate to the upper surface of the first semiconductor chip.

8. The semiconductor package according to claim 1, wherein, The sidewall of the heat dissipation element includes a connecting sidewall extending between the inclined surface of the heat dissipation element and the upper surface of the first semiconductor chip, and the slope of the connecting sidewall of the heat dissipation element is different from the slope of the inclined surface of the heat dissipation element.

9. The semiconductor package according to claim 1, wherein, The first semiconductor chip is connected to the mounting substrate via wires.

10. The semiconductor package according to claim 1, wherein, The heat dissipation element also includes a connecting sidewall extending from the inclined surface to the upper surface of the first semiconductor chip.

11. A semiconductor package, comprising: Mounting substrate; A first semiconductor chip is located on the mounting substrate; A connection terminal that electrically connects the first semiconductor chip and the mounting substrate; The bottom filling portion is located between the mounting substrate and the first semiconductor chip and is located on the connection terminal; The second semiconductor chip is located on the first portion of the upper surface of the first semiconductor chip; A heat dissipation element is located on a second portion of the upper surface of the first semiconductor chip and a portion of the upper surface of the second semiconductor chip; as well as A package molding portion is located on the mounting substrate, the first semiconductor chip, the second semiconductor chip, and the heat dissipation element, wherein the package molding portion exposes at least a portion of the upper surface of the heat dissipation element. The heat dissipation element includes a first sidewall that is directly connected to the upper surface of the heat dissipation element. The molded portion of the package is located on the first sidewall of the heat dissipation element. Wherein, the angle formed between the upper surface of the heat dissipation element and the first sidewall of the heat dissipation element is in the range of 115 degrees to 170 degrees, and Wherein, in a direction perpendicular to the upper surface of the mounting substrate, the first sidewall of the first semiconductor chip does not overlap with the heat dissipation element and extends laterally relative to the heat dissipation element.

12. The semiconductor package of claim 11, wherein, The first sidewall of the heat dissipation element includes an inclined surface directly connected to the upper surface of the heat dissipation element and a connecting sidewall extending from the inclined surface to the upper surface of the first semiconductor chip.

13. The semiconductor package of claim 11, further comprising an adhesive layer located between the first semiconductor chip and the second semiconductor chip.

14. The semiconductor package of claim 11, wherein, The first semiconductor chip is a flip chip bonded to the mounting substrate, and the second semiconductor chip is connected to the mounting substrate via wires.

15. A semiconductor package, comprising: Mounting substrate; A first semiconductor chip is located on the mounting substrate and is electrically connected to the mounting substrate; A second semiconductor chip is located on the first semiconductor chip and is electrically connected to the mounting substrate; as well as A heat dissipation element is located on the first semiconductor chip and the second semiconductor chip, wherein the heat dissipation element includes a sidewall, the sidewall including an inclined surface, and the heat dissipation element further includes an upper surface directly connected to the inclined surface, and Wherein, the angle formed by the upper surface of the heat dissipation element and the inclined surface of the heat dissipation element is an obtuse angle. The heat dissipation element includes a first lower surface and a second lower surface that is further away from the upper surface of the mounting substrate than the first lower surface. The first lower surface of the heat dissipation element is located on the portion of the upper surface of the first semiconductor chip that extends laterally beyond the second semiconductor chip.

16. The semiconductor package of claim 15, wherein, The angle formed by the upper surface of the heat dissipation element and the inclined surface of the heat dissipation element is in the range of 115 degrees to 170 degrees.

17. The semiconductor package of claim 15, wherein, The sidewall of the heat dissipation element is a first sidewall, and the inclined surface of the heat dissipation element is a first inclined surface. The heat dissipation element further includes a second sidewall, which includes a second inclined surface.

18. The semiconductor package of claim 17, wherein, The angle formed by the upper surface of the heat dissipation element and the first inclined surface of the heat dissipation element is a first angle, and Wherein, the second angle formed by the upper surface of the heat dissipation element and the second inclined surface of the heat dissipation element is a second obtuse angle.

19. The semiconductor package of claim 15, wherein, The second distance from the upper surface of the mounting substrate to the lower surface of the heat dissipation element is equal to or greater than the first distance from the upper surface of the mounting substrate to the upper surface of the first semiconductor chip.

20. The semiconductor package of claim 15, further comprising a package molding portion located on the mounting substrate. in, The molded portion of the package is located on the inclined surface of the heat dissipation element, but not on at least a portion of the upper surface of the heat dissipation element.

21. The semiconductor package of claim 15, wherein, The first sidewall of the first semiconductor chip and the second sidewall of the second semiconductor chip are not coplanar.

Images