semiconductor devices

Abstract

Embodiments of this disclosure relate to a semiconductor device. The semiconductor device includes: bonding pads formed in a first wiring layer; and first wiring and second wiring formed in a second wiring layer disposed below the first wiring layer. Here, a power supply potential and a reference potential are supplied to the respective first wiring and second wiring. Furthermore, in a perspective view, each of the first wirings is arranged adjacent to each other and at a first location in the second wiring layer, the first location overlapping the bonding region of the first bonding pad. Also, in a perspective view, the second wiring is arranged at a second location in the second wiring layer, the second location overlapping a first region located between the first bonding pad and the second bonding pad. Further, the width of each first wiring is smaller than the width of the second wiring.

Description

[0001] Cross-references to related applications

[0002] The disclosure of Japanese Patent Application No. 2019-151900, filed on August 22, 2019, includes a specification, drawings and an abstract, the entire contents of which are incorporated herein by reference. Background Technology

[0003] This invention relates to a semiconductor device, and for example, to a technique valuable for semiconductor devices comprising multiple bonding pads, the bonding pads including a power supply path for a power supply potential and a power supply path for a reference potential.

[0004] The publicly available technologies are listed below.

[0005] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2009-170763

[0006] [Patent Document 2] Japanese Unexamined Patent Application Publication No. 2013-206905

[0007] [Patent Document 3] WO 2017 / 145256

[0008] Patent document 1, patent document 2 and patent document 3 describe a semiconductor device in which multiple wires are arranged directly below the bonding pads. Summary of the Invention

[0009] In recent years, with the increasing performance of semiconductor devices, circuits formed within them transmit various electronic signals. Furthermore, as the speed of electrical signal transmission and the processing speed of circuits increase, the power consumption of the circuits also increases. In such semiconductor devices, the power supply path of the reference potential has multiple functions. The power supply path of the reference potential can act as a path to reduce noise components contained in various wiring paths (i.e., return paths of signal transmission paths), or as an electromagnetic shield to suppress the propagation of electromagnetic noise from inside or outside the semiconductor device. To improve the aforementioned functions of the power supply path of the reference potential, it is desirable to reduce the impedance of the power supply path of the reference potential.

[0010] Other objectives and novel features will become apparent from the description in this specification and the accompanying drawings.

[0011] A semiconductor device according to one embodiment includes: a plurality of bonding pads formed in a first wiring layer; a plurality of first wirings formed in a second wiring layer disposed below the first wiring layer; and one or more second wirings formed in the second wiring layer, wherein a power supply potential is supplied to each of the plurality of first wirings. Furthermore, a reference potential is supplied to the one or more second wirings. Moreover, in a perspective view, each of the first wirings is arranged adjacent to each other and positioned at a first location in the second wiring layer, the first location overlapping a bonding region of a first bonding pad. Furthermore, in a perspective view, the one or more second wirings are arranged such that the one or more second wirings extend along one of the plurality of first wirings at a second location in the second wiring layer, the second location overlapping a first region located between a first bonding pad and a second bonding pad. Further, the width of each of the plurality of first wirings is smaller than the width of the one or more second wirings. Attached Figure Description

[0012] Figure 1 This is a top view of a semiconductor package according to one embodiment.

[0013] Figure 2 It is along Figure 1 A cross-sectional view of line AA.

[0014] Figure 3 From Figure 2 The image shows a plan view of the semiconductor chip from the front.

[0015] Figure 4 yes Figure 3 An enlarged plan view of part A shown in the diagram.

[0016] Figure 5 It shows Figure 4 The diagram shows a perspective view of the positional relationship between the bonding pads and the wiring formed in the underlying wiring layer.

[0017] Figure 6 It is along Figure 4 Enlarged cross-sectional view of line AA.

[0018] Figure 7 It shows the location Figure 5 The diagram shows a perspective view of the wiring layer below the wiring layer.

[0019] Figure 8 It is along Figure 4 Enlarged cross-sectional view of the BB line.

[0020] Figure 9 It is along Figure 4 Enlarged cross-sectional view of the CC line.

[0021] Figure 10 It is shown in Figure 3 The enlarged plan view of part B shown is related to Figure 5 A magnified perspective view of an example of the wiring layout in the corresponding wiring layer.

[0022] Figure 11 It shows the location Figure 10 The diagram shows a perspective plan of the wiring layer below the wiring layer.

[0023] Figure 12 This is an illustrative diagram showing the assembly process of a semiconductor package according to one embodiment.

[0024] Figure 13 This shows connecting the wire to... Figure 4 The image shows a magnified plan view of the state after the bonding region.

[0025] Figure 14 It is along Figure 13 Enlarged cross-sectional view of line AA.

[0026] Figure 15 It shows Figure 10 An enlarged plan view of the modified example.

[0027] Figure 16 It shows Figure 5 An enlarged plan view of the modified example. Detailed Implementation

[0028] <Explanation of the descriptive forms, basic terms, and usages in this application>

[0029] In this application, for convenience, the description of embodiments is divided into multiple sections, etc., when necessary. Unless otherwise expressly stated, these sections are not independent of each other. Regardless of the order of description, in each part of a single example, one part is a partial detail of another part, or a modification example of part or all of another part. In principle, descriptions of similar parts are omitted. Moreover, each component in the embodiments is not essential, and unless otherwise expressly stated and obvious from the context, the number is theoretically limited.

[0030] Similarly, in the description of embodiments, etc., unless explicitly indicated otherwise or clearly apparent from the context, the phrase "X composed of A" regarding materials, composition, etc., does not exclude elements other than A. For example, regarding composition, it means "X including A as a main component," etc. For example, the term "silicon component," etc., is not limited to pure silicon, and it is self-evident that it also includes components containing SiGe (silicon-germanium) alloys, multi-element alloys containing silicon as their main component, other additives, etc. In addition, unless otherwise stated, gold plating, Cu plating, nickel plating, etc., include not only pure materials, but also components containing gold, Cu, nickel, etc., as main components, respectively.

[0031] Additionally, when referring to a specific value or quantity, the theoretical limit is that number, but it can also be greater or less than that specific value, unless otherwise explicitly stated or clearly not so from the context. In the following description, one value and another value may be referred to as "same" or "identical," but "same" or "identical" means both strictly identical and within a range that can be considered substantially equivalent, where there is a difference in quality.

[0032] In the accompanying drawings of the embodiments, the same or similar parts are represented by the same or similar symbols or reference numerals, and in principle, they will not be described repeatedly.

[0033] Additionally, in the accompanying drawings, section lines may be omitted when they become complex or when they are clearly distinguished from gaps, or even in cross-sections. In this respect, even if a hole in a plane is closed, but is evident according to the description, the outline of the background may be omitted. Furthermore, section lines or dotted patterns may be added to indicate that the area is not empty (even if it is not a cross-section) or to indicate the boundary of the area.

[0034] In this application, a structure having a semiconductor substrate and multiple wiring layers stacked on the semiconductor substrate, with bonding pads formed on the topmost layer of the wiring layers, is referred to as a "semiconductor chip." Additionally, a structure in which a semiconductor chip is mounted on a substrate (such as a wiring substrate or lead frame) and the bonding pads are electrically connected to external terminals of the substrate is referred to as a "semiconductor package." This structure is also referred to as a "semiconductor device," as a general term for both semiconductor chips and semiconductor packages. Therefore, when this structure is described as a "semiconductor device," it can be either a semiconductor chip or a semiconductor package.

[0035] Furthermore, a "bonding pad" is an external terminal of a semiconductor chip, such as a wire or a portion capable of bonding conductive components (such as bump electrodes). Within a bonding pad, the area of ​​the wire or conductive component (such as a bump electrode) to be bonded, as described above, on the exposed surface exposed from the insulating film covering the uppermost wiring layer, is called the bonding region. Therefore, the "bonding region" includes not only the bonding surface after the actual bonding of the conductive component, but also the portion that may be bonded due to effects during bonding (such as mechanical accuracy).

[0036] Semiconductor Packaging

[0037] First, refer to Figures 1 to 3 This embodiment describes a construction example of the semiconductor package PKG1. Figure 1 This is a top view of the semiconductor package according to this embodiment. Figure 2 It is along Figure 1 A cross-sectional view of line AA.

[0038] In the following description, as an example of a semiconductor package configuration, the wires are metal wires connected to bonding pads exposed on the surface of the semiconductor chip. The wires and bonding pads disposed around the semiconductor chip are connected via the wires, describing a leadframe-type semiconductor package. However, various modifications exist in the embodiments of packaged semiconductor chips described below. For example, the semiconductor chip may be mounted on a wiring substrate instead of a leadframe. Further, for example, the bonding pads of the semiconductor chip may be mounted on the wiring substrate facing the wiring substrate, so that the bonding pads can be electrically connected to the wiring substrate via bump electrodes.

[0039] like Figures 1 to 3 As shown, the semiconductor package PKG1 includes a semiconductor chip CP (see...). Figure 2 and 3 ), multiple leads (terminals, external terminals) LD and multiple wires BW (see Figure 2 The plurality of leads serve as external terminals disposed around the semiconductor chip CP, and the plurality of wires serve as conductive components for electrically connecting the semiconductor chip CP to the plurality of leads LD. The semiconductor chip CP and the plurality of wires BW are sealed by a sealing body (resin body) MR. The inner lead portion ILD of each lead in the plurality of leads LD is sealed by the sealing body MR, and the outer lead portion OLD of each lead in the plurality of leads LD is exposed from the sealing body MR.

[0040] like Figure 1 As shown in the diagram, the hermetically sealed body MR in the plan view of the semiconductor package PKG1 has a rectangular shape. The hermetically sealed body MR includes an upper surface MRt and a lower surface (rear surface, mounting surface) MRb opposite the upper surface MRt (see [reference]). Figure 2), and multiple (in) located between the upper surface MRt and the lower surface MRb Figure 1 The middle part consists of four side surfaces MR.

[0041] Furthermore, in the semiconductor package PKG1, a plurality of leads LDs are arranged along each of the four sides of the hermetically sealed body MR, which is composed of a rectangular shape. The plurality of leads LDs are made of metal, and in this embodiment, the leads LDs are, for example, metal components primarily made of copper (Cu). A semiconductor package, such as this embodiment, in which a plurality of leads LDs are arranged along each of the four sides of the hermetically sealed body MR is referred to as a QFP (Quad Flat Package). Although not shown, the following semiconductor package is referred to as an SOP (Small Outline Package): a plurality of leads LDs are arranged along two opposite sides of the four sides of the hermetically sealed body MR, and no leads LDs are arranged on the other two sides of the hermetically sealed body MR. This embodiment illustrates an example applied to the semiconductor package PKG1 as a QFP; however, as described above, various modified examples exist.

[0042] like Figure 2 As shown, the outer lead portions (OLDs) of the multiple lead LDs protrude outwards from the side surfaces (MRs) of the hermetically sealed MR. In the case of QFP or SOP, the outer lead portions (OLDs) protrude from the side surfaces (MRs) of the hermetically sealed MR and have a shape that bends towards the mounting surface. Although not shown, as a modified example of the semiconductor package PKG1, there also exists a so-called non-lead type semiconductor package in which each lead of the multiple lead LDs is exposed on the lower surface (MRb) of the hermetically sealed MR.

[0043] The semiconductor chip CP is sealed inside a sealant MR. The semiconductor chip CP has a surface (upper surface, main surface) CPt and a back surface CPb opposite to the surface CPt (see...). Figure 2 The semiconductor chip CP is located on the side surface between the surface CPt and the back surface CPb in the thickness direction of the semiconductor chip CP in the cross-sectional view. On the front surface CPt of the semiconductor chip CP, a plurality of bonding pads PD are arranged in two rows along each of the four sides constituting the outer edge of the front surface CPt. Further, the semiconductor chip CP (specifically, the semiconductor substrate) is made of, for example, silicon (Si). Although not shown, a plurality of semiconductor elements (circuit elements) are formed on the main surface of the semiconductor chip CP (particularly on the semiconductor element formation area disposed on the upper surface of the semiconductor substrate of the semiconductor chip CP). The plurality of bonding pads PD are then electrically connected to the semiconductor elements through wiring formed in the wiring layer (not shown) to be disposed inside the semiconductor chip CP (specifically, between the surface CPt and the semiconductor element formation area (not shown)). That is, the plurality of bonding pads PD are electrically connected to the circuit formed in the semiconductor chip CP.

[0044] Furthermore, an insulating film covering the substrate and wiring of the semiconductor chip CP is formed on the surface CPt of the semiconductor chip CP. Through openings formed in the insulating film, each surface of a plurality of bonding pads PD is exposed from the insulating film. The bonding pads PD are made of metal, and in this embodiment, the bonding pads PD are made of, for example, aluminum (Al).

[0045] The semiconductor chip CP is mounted on the die pad DP, which serves as the chip mounting portion. For the semiconductor package PKG1, the die pad (chip mounting portion) DP is located inside the hermetically sealed body MR, and the semiconductor chip CP is mounted on the upper surface (surface, main surface, chip mounting surface) DPt of the die pad DP.

[0046] Furthermore, such as Figure 2 The semiconductor chip CP shown is mounted on the die pad DP by a die bonding material (adhesive) DB when the back surface CPb faces the upper surface DPt of the die pad DP. That is, multiple bonding pads PD formed by the so-called face-up mounting method have their surfaces (main surfaces) CPt opposite each other (back surface CPb) to the chip mounting surface (upper surface DPt). The die bonding material DB is an adhesive material used for die bonding the semiconductor chip CP, and is, for example, a thermosetting resin based on epoxy resin or a conductive resin adhesive or solder containing multiple conductive particles (e.g., silver particles) within a thermosetting resin based on epoxy resin.

[0047] Multiple lead LDs are disposed around the semiconductor chip CP (in other words, around the die pads DP). Multiple bonding pads (electrodes) PD exposed on the surface CPt of the semiconductor chip CPt are electrically connected via internal lead portions ILDs of the multiple lead LDs located inside the hermetically sealed body MR and multiple conductors (conductive members) BWs. One end of the conductor BW is bonded to the bonding pad PD, and the other end is bonded to a portion (bonding area) of the internal lead portion ILD.

[0048] Semiconductor Chips

[0049] Next, a detailed description will be provided. Figure 2 The semiconductor chip CP shown is shown. Figure 3 From Figure 2 The image shows a plan view of the semiconductor chip from the front. Figure 4 yes Figure 3 An enlarged plan view of part A shown in the diagram. Figure 5 It shows Figure 4 The diagram shows a perspective view of the positional relationship between the bonding pads and the wiring formed in the underlying wiring layer. Figure 6 It is along Figure 4 Enlarged cross-sectional view of line AA. Figure 7It shows the location Figure 5 The diagram shows a perspective view of the wiring layer below the wiring layer. Figure 8 It is along Figure 4 Enlarged cross-sectional view of the BB line. Figure 9 It is along Figure 4 A magnified cross-sectional view of the CC line. Although Figure 5 yes Figure 6 The diagram shows a plan view of routing layer CL2, but to clearly show the positional relationship between the routing layers formed on CL2 and the bonding pads PD and bonding areas (bonding regions) PDr1, these outlines are shown with dashed lines. Although Figure 7 yes Figure 6 The diagram shows a plan view of routing layer CL3, but to illustrate the positional relationship between the routing formed in routing layer CL3 and the routing formed in routing layer CL2 in the plan view, the outline of the routing formed in routing layer CL2 is shown with dashed lines. Figure 8 and 9 It shows Figure 6 The diagram shows the layers of each of the multiple wiring layers CL1 to CL3, but not the layers of each of the wiring layers CL4 to CL10.

[0050] Semiconductor chip CP includes: semiconductor substrate SS (see Figure 6 Multiple wiring layers CL stacked on the main surface SSt of the semiconductor substrate SS (see...) Figure 6 ), covering the insulating film (protective film) PV of the wiring layer CL1 at the top (see Figure 6 ) and multiple bonding pads PD formed in the wiring layer CL1.

[0051] The main surface SSt of the semiconductor substrate SS (see Figure 6 In a plan view, it consists of rectangular shapes and has a direction in the X direction (see...). Figure 3 Edge CPs1 extending from ) (see Figure 3 ), and the side CPs2 extending in the Y direction and intersecting the X direction (perpendicular to the X direction) (see Figure 3 ), located on the side CPs3 opposite to edge CPs1 (see Figure 3 ) and the side CPs4 located on the opposite side of side CPs2 (see Figure 3 The main surface SSt of the semiconductor substrate SS (see...) Figure 6 ) is the formation of multiple semiconductor elements Q1 (see Figure 6 The semiconductor element forms a surface. The semiconductor substrate SS, which serves as the base material for the semiconductor chip CP, is, for example, composed of silicon (Si) as its main component.

[0052] Furthermore, such as Figure 6 As shown, multiple wiring layers CL are stacked on the main surface SSt of the semiconductor substrate SS. Figure 6 As shown, multiple routing layers CL have a fine layer FNL and a global layer GBL formed on the fine layer FNL. Figure 6 As shown, the global layer GBL has routing layers CL2 and CL3. Figure 6 As shown, the fine layer FNL has wiring layers CL4, CL5, CL6, CL7, CL8, CL9, and CL10. Here, the thickness of each wiring formed in the wiring layers CL2 and CL3 constituting the global layer GBL is greater than the thickness of each wiring formed in the wiring layers CL4, CL5, CL6, CL7, CL8, CL9, and CL10 constituting the fine layer FNL. Further, the width (thickness) of each wiring formed in the wiring layers CL2 and CL3 constituting the global layer GBL is greater than the width (thickness) of each wiring formed in the wiring layers CL4, CL5, CL6, CL7, CL8, CL9, and CL10 constituting the fine layer FNL. Multiple bonding pads PD are formed on the uppermost wiring layer CL1 of the multiple wiring layers CL. Each bonding pad in the multiple bonding pads PD is connected to a semiconductor device (e.g., a semiconductor device formed on the main surface SSt of the semiconductor substrate SS via a conductor pattern CWP formed in the multiple wiring layers CL. Figure 6 The semiconductor device Q1 is electrically connected.

[0053] Each of the multiple wiring layers CL has multiple conductor patterns (wiring patterns) CWP. An insulating layer CIL is inserted between the multiple conductor patterns CWP. The conductor patterns CWP are embedded in openings formed in the insulating layer CIL. The multiple conductor patterns CWP adjacent to each other are insulated by the insulating layer CIL. That is, each insulating layer CIL formed in the multiple wiring layers CL serves as an insulating material to insulate the multiple conductor patterns CWP formed in each wiring layer from each other. In this embodiment, the insulating layer CIL is, for example, an inorganic film made of silicon oxide. Further, the conductor patterns CWP of each wiring layer CL are electrically connected to the conductor patterns CWP of the wiring layer CL adjacent to the wiring layer CL in which the conductor patterns CWP are formed. The conductor patterns CWP formed in the upper wiring layer CL and the conductor patterns CWP formed in the lower wiring layer CL are electrically connected via vias CVW.

[0054] In a multi-layer wiring system CL, the topmost wiring layer CL1 is covered by an insulating film (protective film) PV. The insulating film PV has the surface (top surface, main surface) CPt of the semiconductor chip CP. The insulating film PV has multiple openings PVk. A portion of each bonding pad PD is exposed from the insulating film PV at the openings PVk. For example... Figure 4As shown, in this embodiment, the exposed surface of the bonding pad PD exposed from the insulating film P includes a bonding region PDr1 and a probe region (probe area) PDr2. The bonding region PDr1 is the conductive component to be bonded (such as a wire BW (see...)). Figure 2 The region is called the bonding region. Conductive components (such as wires BWs) are bonded somewhere in the bonding region PDr1. Moreover, when performing on the semiconductor substrate SS (see... Figure 6 During continuity testing of the integrated circuit formed on the ), the test pins are connected to a portion of the probe area PDr2. Incidentally, the insulating film PV not only insulates the multiple bonding pads PD formed in the uppermost wiring layer CL1 from each other, but also serves as a protective film for protecting the semiconductor chip CP. Therefore, as... Figure 6 As shown, multiple wiring layers CL (particularly wiring layer CL1) are covered by an insulating film PV. This PV is composed of a material different from the aforementioned insulating layer CIL. In this embodiment, the insulating film PV is, for example, an inorganic film made of silicon oxide, an organic film made of polyimide, or a laminate of an inorganic film made of silicon oxide and an organic film made of polyimide.

[0055] exist Figure 6 The conductor pattern CWP formed in each wiring layer CL from wiring layer CL2 to wiring layer CL10 shown is formed, for example, by a metal mainly composed of copper. On the other hand, each of the multiple bonding pads PD formed in wiring layer CL1 is formed, for example, by a metal containing aluminum as the main component.

[0056] exist Figure 6 In the example shown, the portion exposed from the insulating film PV at the opening PVk of the bonding pad PD constitutes part of the surface CPt of the semiconductor chip CP. However, as Figure 6 In a modified example, a portion of the insulating film PV exposed at the opening PVk of the bonding pad PVk may be covered by a metal film (not shown) (e.g., over-pad metal or under-bump metal). In this case, the metal film stacked on the bonding pad PD is considered part of the bonding pad PD. Conductors or bump electrodes are electrically connected to the bonding pad PD through the metal film.

[0057] Figure 4 Each of the multiple bonding pads PD shown in the diagram is along... Figure 3 The edge CPs1 arrangement is shown in the diagram. Figure 3 As shown in the figure, the multiple bonding pads PD included in the semiconductor chip CP in this embodiment are arranged in two rows along each of the edges CPs1, CPs2, CPs3 and CPs4 of the semiconductor chip CP. Figure 4The bonding pads PD in the first row, relatively close to edge CPs1, are shown. The layout of the bonding pads PD in the second row, relatively farther from edge CPs1, will be described later.

[0058] Figure 4 The bonding pads PD shown include bonding pad PD1 and bonding pad PD2. Figure 4 In the embodiment shown, bonding pad PD1 is bonding pad PDv to which a power potential is to be supplied (see [reference]). Figure 5 Bond pad PD2 is the bond pad PDg to which a reference potential is to be supplied (see [link]). Figure 5 Bond pads PD1 and PD2 are arranged such that they are adjacent to each other in the X direction, in other words, along the X direction. Figure 3 The edge CPs1 shown is adjacent.

[0059] Furthermore, such as Figure 5 As shown, multiple wirings CW1 and one or more wirings CW2 are formed in the wiring layer CL2, extending in the Y direction that intersects the X direction. Figure 5 In the example shown, multiple wirings CW2 extending in the Y direction are formed in wiring layer CL2. Each of the multiple wirings CW2 extends along wiring CW1. Each of the multiple wirings CW1 is arranged adjacent to each other in the X direction. A power supply potential is supplied to each of the multiple wirings CW1. The power supply potential is the potential used to drive the circuitry formed in the semiconductor chip CP. On the other hand, a reference potential is supplied to each of the multiple wirings CW2. The reference potential is a potential different from the power supply potential and is, for example, a ground potential.

[0060] <Power supply path for power supply potential and reference potential>

[0061] As the functionality of semiconductor chips (CPs) increases, the power supply path for the reference potential serves, for example, as a path to reduce noise components contained in various wiring paths (i.e., return paths of signal transmission paths), or as an electromagnetic shield to suppress the propagation of electromagnetic noise from inside or outside the semiconductor device. From the viewpoint of improving the aforementioned functional characteristics, it is preferable to reduce the impedance of the power supply path for the reference potential. In this embodiment, a structure for reducing the impedance of the power supply path for the reference potential and realizing the enhanced functionality of the power supply path for the reference potential, as illustrated above, will be described.

[0062] As described above, the bonding pad PD and in such Figure 6 The diagram illustrates the electrical connections formed in the conductor patterns CWP within the multiple wiring layers CL. In the multiple wiring layers CL, this is achieved by considering the conductive components (such as wires BW) (see...). Figure 2The stress caused by the connection to the bonding pad PD needs to be arranged in the conductor pattern CWP formed in the wiring layer CL2, which is the uppermost layer and forms the bonding pad PD. That is, because the distance between the wiring layer CL2 and the bonding pad PD is short, the wiring layer CL2 is easily affected by the stress generated at the bonding pad PD.

[0063] For example, in Figure 5 The diagram illustrates a wiring configuration formed according to conventional wiring rules, directly below the bonding region PDr1. When the tip of the conductor BW is bonded to the bonding region PDr1, a spherical portion formed on the tip of the conductor BW is pressed against the bonding region PDr1, for example, by applying heat and ultrasound to bond the spherical portion to the bonding pad PD. At this time, because an external force is applied to the bonding pad PD, a relatively larger stress propagates in the area directly below the bonding region PDr1 within the bonding pad PD compared to the surrounding area. As described above, in the wiring layer CL2, if wiring is formed directly below the bonding region PDr1, the wiring is susceptible to damage under the stress generated in the bonding region PDr1. This stress generation is not limited to conductor bonding. For example, when forming a cylindrical protruding electrode called a copper pillar on the bonding pad PD, the protruding electrode can be formed by electroplating. In this case, no large external force is applied to the bonding pad PD when forming the protruding electrode. However, when a semiconductor chip with protruding electrodes is mounted on such a wiring substrate (not shown), a strong external force is applied to the bonding pads PD through the protruding electrodes. As a result, greater stress propagates in the region directly beneath the bonding region PDr1 compared to the surrounding area.

[0064] Therefore, it is preferable not to form wiring at the location overlapping the bonding region PDr1, which is connected to conductive components (such as wires or protruding electrodes).

[0065] However, according to the inventors' research, it has been found that, Figure 6 In the wiring layer CL2 shown, even at locations where it overlaps with the bonding area PDr1 of the bonding pad PD, damage to the wiring can be suppressed when multiple wirings, each with a narrow width, are arranged close to each other.

[0066] like Figure 5 As shown, as from the insulating film PV (see...) Figure 6In the perspective plan view of the upper surface of the semiconductor chip CP according to this embodiment, each of the plurality of wirings CW1 is arranged adjacent to each other. Further, at the location overlapping with the bonding region PDr1 of the bonding pad PD1, each of the plurality of wirings CW1 is arranged such that each of the plurality of wirings CW1 extends in the Y direction intersecting the X direction. In other words, in the perspective plan view, a wiring group CWg1 composed of the plurality of wirings CW1 arranged adjacent to each other is arranged at the location (region) overlapping with the bonding region PDr1 of the bonding pad PD1. Further, as... Figure 5 As shown, in the routing layer CL2, the routing CW2 is arranged such that at a location (region) overlapping with the region (region) R1 between the bonding pads PD1 and PD2, the routing CW2 extends along one of the multiple routing CW1.

[0067] The width W1 of each of the plurality of wirings CW1 is smaller than the width W2 of wiring CW2, for example, 1.0 μm or less. The width W2 of wiring CW2 is, for example, about 5 μm to 10 μm. Because the width of each of the plurality of wirings CW1 is narrower, it has a high property of reducing applied stress compared to wider wirings. Furthermore, when the plurality of wirings CW1 are arranged adjacent to each other, each of the plurality of wirings CW1 serves as a reinforcing member for enhancing the strength of subsequently arranged wirings CW1. Therefore, in the wiring layer CL2, each of the plurality of wirings CW1 in this embodiment has a structure that is almost undamaged, even when positioned at the location of the overlapping bonding region PDr1.

[0068] From the viewpoint of improving the function of the multiple wirings CW1 as reinforcing components, it is particularly preferable that the distance (interval) P1 between the multiple wirings CW1 is equal to or less than the width W1 of each of the multiple wirings CW1. Figure 5 In the example shown, the distance P1 between adjacent wirings CW1 is, for example, 0.50 μm. The width W1 of each of the plurality of wirings CW1 is preferably 1.0 μm or less. Further, the distance P1 between the plurality of wirings CW1 is preferably 0.55 μm or less.

[0069] For this embodiment, as Figure 5 As shown, multiple interconnects CW1 are placed in the area overlapping the bonding region PDr1 of the bonding pad PD1. These multiple interconnects CW1 serve as power supply paths for the power supply potential. Therefore, the area around the bonding region PDr1 can be used as a power supply path for the reference potential. In other words, according to this embodiment, the bonding pad PD is formed in the wiring layer CL2 adjacent to the wiring layer CL1 (see...). Figure 6 This can increase the area of ​​the conductive pattern CWP supplying the reference potential (see...). Figure 6Therefore, the impedance of the power supply path to the reference potential can be reduced.

[0070] For example, such as Figure 5 As shown, the interconnect CW2 supplying the reference potential is positioned at a location overlapping with the region (area) R1 between at least the bonding pad PD1 and the bonding pad PD2. Figure 5 In the embodiment shown, two wirings CW2 are arranged at a location overlapping region R1. For Figure 5 In the example shown, because each of the multiple narrow-width traces CW1 and multiple wide-width traces CW2 is arranged with a narrow spacing, an upper limit is set on the width of the relatively wide traces CW2 from the viewpoint of improving processing accuracy. Two traces CW2 located at a position overlapping with region R1 pass each other through traces CW4 formed in the trace layer CL3 (see...). Figure 8 Electrically connected to each other (see) Figure 8 However, as Figure 5 As a further modification example, a wider wiring CW2 can be arranged by integrating two wiring CW2s set at a location overlapping with region R1.

[0071] Furthermore, in Figure 5 In the example shown, in the X direction, wiring CW2 supplying each reference potential is arranged on both sides of a wiring group CWg1 consisting of multiple wirings CW1. In other words, multiple wirings CW2 extending along one of the multiple wirings CW1 are formed in the wiring layer CL2, and the wiring group CWg1 consisting of multiple wirings CW1 arranged adjacent to each other is sandwiched between the multiple wirings CW2. In this case, the interaction between the multiple wirings CW1 and the surrounding conductive pattern CWP (see...) can be reduced. Figure 6 Electromagnetic effects between ( ).

[0072] Each of the plurality of traces CW1 positioned overlapping the bonding pad PD1 is electrically connected to the bonding pad PD1 via a via CVW. Further, the plurality of traces CW2 (in...) Figure 5 A portion of the two (in the middle) overlaps with the bonding pad PD1, but does not overlap with the bonding region PDr1 of the bonding pad PD1.

[0073] Furthermore, in Figure 5In the example shown, a routing group CWg1 consisting of multiple routing traces CW1 is provided at the location overlapping each of the plurality of bonding pads PD. Multiple routing traces CW1 are arranged at the locations overlapping the corresponding bonding regions PDr1 of bonding pads PD1 and PD2. Further, routing traces CW2 extending along one of the multiple routing traces CW1 are provided on both sides adjacent to the bonding region PDr1 of bonding pad PD1 and on both sides adjacent to the bonding region PDr1 of bonding pad PD2. The bonding pad PD2 is electrically connected to the multiple routing traces CW2 and is supplied with a reference potential.

[0074] As described above, a reference potential is supplied at the location where the bonding region PDr1 overlaps with the bonding pad PD2. When multiple traces CW1 to be supplied with the power potential are arranged, wide traces CW2 can be arranged around the bonding region PDr1 at the overlapping location for the reference potential. Multiple traces CW2 are provided at the location overlapping with the bonding pad PD2, and each of the multiple traces CW2 is electrically connected to the bonding pad PD2 via multiple vias CVW. Figure 5 A modified example, where a reference potential is supplied at a location overlapping the bonding region PDr1 of the bonding pad PD2, exhibits the following condition: routing for multiple reference potentials is arranged with the same routing width and spacing as multiple routing CW1. Figure 5 In the embodiment shown, the impedance of the power supply path for the reference potential in the interconnect layer CL2 can be reduced compared to the modified example described above.

[0075] Furthermore, multiple traces CW1 are disposed at locations overlapping the bonding region PDr1 of the bonding pad PD2, each of the multiple traces CW1 being separate from the bonding pad PD2. Additionally, each of the multiple traces CW1 disposed at locations overlapping the bonding region PDr1 of the bonding pad PD2 is connected via a trace layer CL3 (see...) Figure 9 The wiring CW3 formed in ) (see Figure 9 The wiring is electrically connected to each of the plurality of wirings CW1 arranged at a location overlapping the bonding area PDr1 of the bonding pad PD1. As in this embodiment, when power potential is supplied through a plurality of narrow wirings CW1, there is a concern about increased impedance of the power supply path. Therefore, in the wiring layer CL2 and at the corresponding bonding area PDr1 of the plurality of bonding pads PD (see...), the impedance of the power supply path is increased. Figure 5 Multiple wiring CW1s are installed at overlapping locations (see...) Figure 5 ),like Figure 7 As shown, the impedance increase of the power supply path of the power supply potential can be suppressed by electrically connecting the locations that do not overlap with the bonding region PDr1 through the wiring CW3 formed in the wiring layer CL3.

[0076] like Figure 7 As shown, a routing layer CL3 is disposed below routing layer CL2 (see...). Figure 5 This includes wiring CW3, which is electrically connected to multiple wirings CW1. Furthermore, power potential will be supplied to wiring CW3. Moreover, in the perspective plan view, wiring CW3 is along edge CPs1 (see...). Figure 3 The wiring layer CL3 extends to intersect with each of the multiple wirings CW1 and CW2. Further, the wiring layer CL3 includes wiring CW4 electrically connected to the multiple wirings CW2. Moreover, a reference potential will be supplied to wiring CW4. Furthermore, in the perspective plan view, wiring CW4 extends along edge CPs1 (see...). Figure 3 () Extends to cross with each of the multiple wirings CW1 and CW2.

[0077] via the wiring layer CL2 (see Figure 5 The wiring CW4 formed in the wiring layer CL3 below connects multiple wiring CW2 to each other. When charge is concentrated in a portion of the multiple wiring CW2, the charge in that portion of the multiple wiring CW2 can be dispersed through the wiring CW4. Therefore, the electromagnetic shielding function of the power supply path, which serves as a reference potential, can be enhanced.

[0078] Furthermore, via the wiring layer CL2 (see...) Figure 5 The wiring CW3 formed in the wiring layer CL3 in a lower layer connects multiple wiring groups CWg1 to each other. When there is a sudden power demand, charge can be supplied through wiring CW3, which is a part of the multiple wiring groups CWg1. Therefore, the power supply can be stabilized through the power supply path of the power supply potential.

[0079] exist Figure 7 The example shown illustrates two wirings CW3 and one wiring CW4. Wirings CW3 and CW4 are arranged alternately in the Y direction. Furthermore, Figure 4 Each of the bonding pads PD1 and PD2 shown is connected to Figure 7 Each of the wirings CW3 and CW4 shown overlaps. Figure 3 The semiconductor chip CP shown includes multiple bonding pads PD, which include multiple bonding pads PDv supplying power potential (see...). Figure 5 And multiple bonding pads PDg supplying reference potential (see) Figure 5 If each of the multiple bonding pads (PDs) arranged in the X direction is connected to... Figure 7 As shown, the wiring CW3 overlaps, allowing multiple bonding pads PDv used for power supply potential to be electrically connected to each other. Furthermore, if each of the multiple bonding pads PD arranged in the X direction is connected to... Figure 7If the wiring CW4 shown overlaps, then multiple bonding pads PDg used for reference potential can be electrically connected to each other.

[0080] Furthermore, two wires CW3, spaced apart from each other by wire CW4, are electrically connected to each other by wire CW1 formed in the wiring layer CL2 that constitutes the global layer GBL. Therefore, the supply of power potential can be further stabilized.

[0081] Furthermore, each of the widths W3 and W4 of the wiring CW3 is greater than the width W1 of the plurality of wirings CW1 (see [reference]). Figure 5 Width. If the width W3 of interconnect CW3 is wide, the impedance of the power supply path for the power supply potential can be reduced. Furthermore, if the width W4 of interconnect CW4 is wide, the impedance of the power supply path for the reference potential can be reduced.

[0082] Furthermore, such as Figure 3 As shown, the multiple bonding pads PDs disposed in the semiconductor chip CP include bonding pad PD1 (see...). Figure 4 ) and bonding pad PD2 (see Figure 4 The plurality of bonding pads PDs include a plurality of first row pads PDL1 arranged along the edge CPs1. The plurality of bonding pads PDs include a plurality of second row pads PDL2 disposed at a position further away from the edge CPs1 than the plurality of first row pads PDL1. Figure 10 It is shown in Figure 3 The enlarged plan view of part B shown, and Figure 5 A magnified perspective view of an example of the wiring layout in the corresponding wiring layer. Figure 11 It shows the location Figure 10 The diagram shows a perspective plan of the wiring layer below the wiring layer.

[0083] exist Figure 10 In the plurality of wirings CW1 shown, each wiring CW1 located at a position overlapping the bonding region PDr1 of the bonding pad PD1 is electrically connected to the bonding pad PD1 and one of the plurality of second column bonding pads PDL2. Further, Figure 10 Each of the multiple wirings CW2 shown is electrically connected to one of the bonding pads PD2 and multiple second row bonding pads PDL2.

[0084] exist Figure 10In the example shown, a plurality of second-row bond pads include bond pad PD3, which is adjacent to bond pad PD1 in the Y direction, and bond pad PD4, which is adjacent to bond pad PD2 in the Y direction. Bond pads PD1 and PD3 are electrically connected via a plurality of traces CW1. Further, bond pads PD2 and PD4 are electrically connected via traces CW2. In other words, a plurality of second-row bond pads PDL2 include bond pad PD3, which is electrically connected to bond pad PD1 via a plurality of traces CW1. In the perspective view, a plurality of traces CW1 are arranged at each overlapping location of the bonding region PDr1 of bond pad PD3 and bond pad PD1, such that each of the plurality of traces CW1 extends in the Y direction.

[0085] Therefore, by electrically connecting any one of the multiple second row pads PDL2 to one of the multiple first row pads PDL1, the number of power supply paths for the power supply potential or reference potential can be increased. Thus, the power supply potential or reference potential can be stably supplied.

[0086] Furthermore, such as Figure 10 As shown, multiple wirings CW2 are formed in wiring layer CL2, extending along any one of the multiple wirings CW1. A wiring group CWg1, consisting of multiple wirings CW1 arranged adjacent to each other, is sandwiched between the multiple wirings CW2. Figure 11 The wiring layer CL3 shown is supplied with a reference potential and is along edge CPs1 in the perspective view (see...). Figure 3The routing layer CL3 extends along edge CPs1 in the perspective view to intersect with each of routing CW1 and CW2, and is electrically connected to multiple routing CW2. Multiple first row bonding pads PD1 overlapping with routing CW4 are also arranged. Further, routing layer CL3 is supplied with a reference potential and extends along edge CPs1 in the perspective view to intersect with each of routing CW1 and CW2, and is electrically connected to multiple routing CW2. Multiple second row bonding pads overlapping with routing CW5 are also arranged. In other words, each of the multiple routing CW2 extending in the Y direction in routing layer CL2 is electrically connected through routing CW4 and CW5 extending in the X direction in routing layer CL3. That is, the multiple routing CW4 and CW5, which are separate from each other in routing layer CL3, are each electrically connected to each other through routing CW2 formed in routing layer CL2, which constitutes the global layer GBL. In this case, in the perspective view, because the reference potential supply circuit is formed in a grid shape, when local charge is concentrated in a portion of the power supply path of the reference potential, it is easily dispersed to the surrounding area. Furthermore, multiple wirings CW4 and CW5 are electrically connected to each other by forming wirings with greater thickness and width in the wiring layer constituting the global layer GBL compared to the wiring layers constituting the fine layer FNL, which can make the supply of reference potential more stable.

[0087] Furthermore, Figure 11 The wiring layer CL3 shown is supplied with power potential and is along edge CPs1 in the perspective view (see...). Figure 3 The routing layer CL3 extends to intersect with each of routing CW1 and CW2, and is electrically connected to multiple routing CW1s, and provides multiple first row bonding pads PD1 that overlap with routing CW3. Further, the routing layer CL3 is supplied with a power potential and extends along edge CPs1 in the perspective view to intersect with each of routing CW1 and CW2, and is electrically connected to multiple routing CW1s, and provides multiple second row bonding pads that overlap with routing CW6. In other words, each of the multiple routing CW1s extending in the Y direction in routing layer CL2 is electrically connected to routing CW3 and routing CW6 extending in the X direction in routing layer CL3. That is, the multiple routing CW3s and CW6s that are separate from each other in routing layer CL3 are electrically connected to each other through routing CW1s formed in routing layer CL2, which constitutes the global layer GBL. In this case, because the power supply circuit is formed as a grid shape in the perspective view, when there is a sudden power demand, charge can be supplied via wiring CW3 and wiring CW6 in part of the power supply path. Furthermore, multiple wirings CW3 and CW6 are electrically connected to each other by forming wirings with greater thickness and width in the wiring layer constituting the global layer GBL compared to the wiring layers constituting the fine layer FNL, which makes the power supply more stable.

[0088] Furthermore, such as Figure 11 As shown, each of the widths W4 and W5 of routing CW4 is wider than the corresponding widths W1 of the plurality of routing CW1 shown in the figure. Therefore, the impedance of the power supply path for the reference potential in routing layer CL3 can be reduced. Furthermore, each of the widths W3 and W6 of routing CW3 is wider than the corresponding widths W1 of the plurality of routing CW1 shown in the figure. Therefore, the impedance of the power supply path for the power supply potential in routing layer CL3 can be reduced.

[0089] Methods for Manufacturing Semiconductor Devices

[0090] Next, we will describe Figure 1 The manufacturing method of the PKG1 shown is illustrated. The semiconductor packaged PKG1 of this embodiment is based on... Figure 12 It is manufactured according to the assembly process shown. Figure 12 This is an explanatory diagram illustrating the assembly process of a semiconductor package according to this embodiment.

[0091] exist Figure 12 In the substrate preparation step shown, a lead frame (substrate) (not shown) is prepared. The lead frame prepared in this process includes... Figure 2 The diagram shows a die pad DP and multiple leads LDs arranged around the die pad DP. During execution... Figure 12 Prior to the lead-forming process shown, the leads LD are connected to each other. Further, in Figure 12 In the lead formation process shown, before the lead LD is bent, each of the multiple lead LDs, for example, is... Figure 2 The cross-section shown extends linearly along the X direction. Multiple leads LD are arranged around the die pad DP, forming a configuration that extends outwards in all four directions.

[0092] <Semiconductor chip fabrication>

[0093] Furthermore, in Figure 12 In the semiconductor chip preparation steps shown, a reference is prepared. Figures 3 to 11 The semiconductor chip CP is described. In this step, for example, on the main surface SSt of a semiconductor wafer made of silicon (not shown) (see... Figure 6 On the ), it is prepared to consist of multiple semiconductor elements Q1 (see Figure 6 ) and electrically connected to (see Figure 6 A semiconductor wafer is formed by the wiring layer CL of semiconductor components. Further, in... Figure 6 The top layer of the wiring layer CL shown forms multiple bonding pads PD (see...). Figure 3 ).

[0094] Furthermore, an insulating film PV is formed (see...) Figure 6 This covers the topmost wiring layer CL, which has multiple bonding pads PD. Subsequently, multiple openings PVk are formed in the insulating film PV (see...). Figure 3 This exposes at least a portion of each of the multiple bonding pads PD. After forming the semiconductor wafer as described above, the semiconductor wafer is cut along the dicing lines to obtain the multiple semiconductor chips CP shown in the figure.

[0095] Incidentally, before dicing a semiconductor wafer, wafer testing is performed. Wafer testing includes, for example, electrical testing to verify the continuity or characteristics of circuits formed within the semiconductor wafer. When performing electrical testing on a semiconductor wafer, the pins used for testing (probe pins) are connected to... Figure 4 This is a portion of the probe region PDr2 shown.

[0096] <Naked Film Bonding>

[0097] Next, in Figure 12 In the die bonding step (semiconductor chip mounting step) shown, as Figure 2 As shown, a semiconductor chip CP is mounted onto a die pad DP. The semiconductor chip CP has a back surface CPb located on the opposite side of a surface CPt, and a plurality of bonding pads PD are formed on the surface CPt. In this step, the back surface CPb of the semiconductor chip CP and the die pad DP are bonded and fixed together via a die bonding material DB. The semiconductor chip CP is mounted on the die pad DP using a so-called face-up mounting method, such that the back surface CPb faces the upper surface DPt, which is the chip mounting surface of the die pad DP. The die bonding material DB is a bonding member used to bond and fix the semiconductor chip CP and the die pad DP. Examples of die bonding materials DB include resin adhesives, solder, etc.

[0098] <Wire bonding>

[0099] Next, in Figure 12 In the wire bonding process shown, as Figure 2 As shown, multiple bonding pads PD formed on the surface CPt of the semiconductor chip CP are electrically connected to multiple leads LD arranged around the semiconductor chip CP through multiple wires (conductive components) of BW. Figure 13 This shows connecting the wire to... Figure 4 The image shows a magnified plan view of the state after the bonding region is shown. Figure 14 It is along Figure 13 Enlarged cross-sectional view of line AA.

[0100] In this step, for example, one end of the wire BW made of a metallic material (such as copper (Cu) or gold (Au)) Figure 14 The spherical portion (BWB) shown is bonded to the pad (PD) of the semiconductor chip, and the other end (the pin portion (not shown)) is bonded to... Figure 2 The internal lead portion ILD of the lead LD is shown in the diagram. Therefore, the pads PD and lead LD of the semiconductor chip CP are electrically connected via the wire BW.

[0101] Figure 13 The bonding region PDr1 shown is the area of ​​the spherical portion BWB of the conductor BW (conductive member) to be bonded. Therefore, the spherical portion BWB is bonded to a portion of the bonding region PDr1. In other words, the bonding region PDr1 includes the area that does not overlap with the spherical portion BWB after the wire bonding process. Further, as described above, the probe region PDr2 is the area used to connect test pins during wafer testing, and the spherical portion BWB is not bonded to this area.

[0102] When bonding the ball-shaped portion (BWB) and the bonding pad (PD), after pressing the ball-shaped portion (BWB) onto the bonding pad and performing an erasure operation (mechanical vibration to remove the oxide film at the bonding interface), ultrasonic waves are applied to the ball-shaped portion (BWB). This results in an alloy forming at the bonding interface between the metal constituting the ball-shaped portion (BWB) and the metal constituting the bonding pad (PD), which improves bond strength.

[0103] In the wire bonding step, as described above, an external force is applied to the bonding pad PD via the spherical portion BWB. Therefore, the external force applied to the bonding pad PD easily propagates in the thickness direction of the semiconductor chip CP. For this embodiment, as described above, the wiring width ( Figure 5 As shown, multiple narrow traces CW1 with a width of W1 are arranged adjacent to each other in the routing layer CL2. Therefore, even when external forces propagate from the bonding pads PD, damage to the multiple traces CW1 formed in the routing layer CL can be prevented.

[0104] <Sealed>

[0105] Next, in Figure 12 During the sealing process shown, Figure 2 The internal lead portion ILD, multiple wires BW, and multiple leads LD of the semiconductor chip CP shown are each sealed with resin to form a seal body MR.

[0106] In this step, with the lead frame positioned within a molded die (not shown) including a cavity (not shown), resin is supplied into the space formed by the cavity, and then the resin is cured to form a seal (resin body) MR. This method of forming a seal MR is called transfer molding.

[0107] <Leader Formation>

[0108] Next, in Figure 12 During the lead formation process shown, as Figure 2 As shown, multiple leaded LDs are formed. In this step, the outer lead portion OLD is cut, and each lead in the multiple leaded LDs is separated from the lead frame. Therefore, each lead in the multiple leaded LDs is separated from each other. Further, in this step, after cutting the leaded LDs, multiple leaded LDs are formed, and the following is performed: Figure 2 The bending process shown in the figure.

[0109] <cutting>

[0110] Next, in Figure 12 In the segmentation step shown, the support is cut separately. Figure 2 The bare die pad DP shown has multiple floating leads (not shown) to separate the semiconductor package.

[0111] Following this process, necessary inspections and tests are performed, such as visual inspection and electrical testing, and results are obtained. Figure 1 and 2 The semiconductor package shown is a completed semiconductor package PKG1. The semiconductor package PKG1 is shipped or mounted on a mounting substrate (not shown).

[0112] <Modification Example 1>

[0113] While some modification examples have been described above, typical modification examples other than those described above are described below. Figure 15 It shows Figure 10 An enlarged plan view of the modified example. Figure 15 The perspective view of the semiconductor chip CP2 shown below, where the difference is... Figure 10 The semiconductor chip CP shown has multiple wirings CW1 positioned at a location that overlaps with the bonding area PDr1 of the bonding pad PD1 but does not overlap with the bonding area PDr1 of the multiple second row bonding pads PDL2.

[0114] For semiconductor chip CP2, each of the bonding pads PD3 and PD4, which are adjacent to bonding pad PD1 along the Y direction and adjacent to bonding pad PD2 along the Y direction, serves as a signal terminal for inputting or outputting electrical signals. In this case, bonding pads PD1 and PD3 cannot be electrically connected. Furthermore, bonding pads PD2 and PD4 cannot be electrically connected.

[0115] For semiconductor chip CP2, in region (area) R2, multiple wirings CW1 that overlap with the bonding area PDr1 of bonding pad PD1 and multiple wirings CW1 that overlap with the bonding area PDr1 of bonding pad PD2 are connected to each other between the first row of pads PDL1 and the second row of pads PDL2.

[0116] Furthermore, a routing CW7 is provided between bonding pads PD3 and PD4 in the plurality of second-row bonding pads PDL2. The routing CW7, which extends along the long side of bonding pad PD3 in the Y direction, is connected to each of the plurality of routing CW1.

[0117] Although not shown, but as in Figure 11 In the example shown, the wiring layer CL3 is located one layer below the wiring layer CL2 of the semiconductor chip CP2 (see...). Figure 6 Each of them sets its own wiring CW3, CW4, CW5 and CW6 extending along the Y direction. Figure 10 The wiring CW7 shown is connected via a via (not shown) to... Figure 11 The wiring shown is CW6 electrical connection.

[0118] In addition to the differences mentioned above, Figure 15 The semiconductor chip CP2 shown is Figure 10 The semiconductor chips shown are identical (CP). Therefore, redundant descriptions are omitted.

[0119] <Modification Example 2>

[0120] Figure 16 It shows Figure 5 An enlarged plan view of the modified example. Figure 16 In order to illustrate the positional relationship between the spherical portion BWB, which is bonded to multiple wirings CW1, and the bonding region PDr1 in the plan view, it is shown with dashed lines. Figure 4 The outlines of the bonding pad PD, the opening PVk, and the spherical portion BWB are shown in the figure.

[0121] In the perspective plan, Figure 16 The semiconductor chip CP3 shown is Figure 5 The difference in the semiconductor chip CP shown is that a portion of the wiring CW2 overlaps with a portion of the bonding pad PD. Figure 16 In the example shown, each of the plurality of interconnects CW2 overlaps with either bonding pad PD1 or bonding pad PD2. However, each of the plurality of second wirings CW2 does not overlap with the area of ​​the ball portion (conductive member) BWB to be bonded in each of the bonding pads PD1 and PD2.

[0122] From the perspective of preventing damage to wiring CW2 and its surrounding components, such as Figure 5 As shown, it is particularly preferred that the plurality of wirings CW2 do not overlap with the bonding area PDr1 of the bonding pads PD exposed from the insulating film (protective film) PV. However, since the bonding area PDr1 is the area where the spherical portion BWB is to be bonded, a certain margin is allowed. Therefore, if the spherical portion BWB and the wiring CW2 do not overlap, damage to the wiring CW2 can be prevented. Therefore, as Figure 16 As shown, it is permissible for the spherical portion BWB and the wiring CW2 to be slightly larger, even if the wiring CW2 and the bonding pad PD are slightly larger, as long as the spherical portion BWB and the wiring CW2 do not overlap.

[0123] In addition to the differences mentioned above Figure 16 The semiconductor chip CP3 shown is the same as the semiconductor chip CP shown in the figure. Therefore, redundant descriptions are omitted.

[0124] Although the present invention has been specifically described based on embodiments, it is not limited to the embodiments described above, and it is self-evident that various modifications can be made without departing from its spirit.

Claims

1. A semiconductor device, comprising: A semiconductor substrate having a main surface, the main surface having a first side extending along a first direction; Multiple wiring layers are stacked on the main surface of the semiconductor substrate; A protective film covers the first wiring layer among the plurality of wiring layers, wherein the first wiring layer is disposed on the topmost layer of the plurality of wiring layers; Multiple bonding pads are formed in the first wiring layer; Multiple first wirings are formed in a second wiring layer, which is disposed below the first wiring layer, and a power potential is supplied to each of the multiple first wirings; as well as One or more second wirings are formed in the second wiring layer, and a reference potential will be supplied to the one or more second wirings. Each of the plurality of bonding pads has a bonding area exposed from the protective film at the opening formed in the protective film. The plurality of bonding pads includes a first bonding pad and a second bonding pad arranged along the first side of the main surface. In the perspective view taken from the upper surface of the protective film: Each of the plurality of first wirings is arranged adjacent to each other, and at a first location in the second wiring layer, such that each of the plurality of first wirings extends along a second direction, the second direction intersecting the first direction, and the first location overlapping the bonding area of ​​the first bonding pad. The one or more second wirings are arranged at a second location on the second wiring layer such that the one or more second wirings extend along one of the plurality of first wirings, the second location overlapping with a first region located between the first bonding pad and the second bonding pad, and The width of each of the plurality of first wirings is less than the width of the one or more second wirings.

2. The semiconductor device according to claim 1, The second wirings, each extending along one of the plurality of first wirings, are formed in the second wiring layer, and The plurality of first wirings arranged adjacent to each other are located between the second wirings.

3. The semiconductor device according to claim 2, in, In the perspective plan: The plurality of first wirings are arranged at each of the following locations: a first location overlapping the bonding area of ​​the first bonding pad, and a third location overlapping the bonding area of ​​the second bonding pad, and The second wirings, each extending along one of the plurality of first wirings, are respectively arranged on both sides of the bonding area of ​​the first bonding pad and on both sides of the bonding area of ​​the second bonding pad.

4. The semiconductor device according to claim 3, The first bonding pad is electrically connected to each of the plurality of first wirings located at the first position overlapping the bonding area of ​​the first bonding pad, and The second bonding pad is electrically connected to the second wiring and electrically disconnected from the plurality of first wirings located at the third position overlapping the bonding area of ​​the second bonding pad.

5. The semiconductor device according to claim 4, The plurality of wiring layers includes a third wiring layer disposed below the second wiring layer. A third wiring electrically connected to the plurality of first wirings is arranged in the third wiring layer, the power potential of which is supplied to the third wiring, and in the perspective plan, the third wiring extends along the first side to intersect each of the plurality of first wirings and the second wiring. Each of the plurality of first wirings arranged at each of the following locations is electrically connected to each other via the third wiring: the first location overlapping the bonding area of ​​the first bonding pad, and the third location overlapping the bonding area of ​​the second bonding pad.

6. The semiconductor device according to claim 2, The plurality of wiring layers includes a third wiring layer disposed below the second wiring layer, and The third wiring layer includes: A third wiring is electrically connected to the plurality of first wirings, the power potential of which will be supplied to the third wiring, and in the perspective plan, the third wiring extends along the first side to intersect with each of the plurality of first wirings and the second wiring. A fourth wiring is electrically connected to the second wiring, the reference potential is supplied to the fourth wiring, and in the perspective plan, the fourth wiring extends along the first side to intersect each of the plurality of first wirings and the second wiring.

7. The semiconductor device according to claim 6, The width of the third wiring and the width of the fourth wiring are greater than the width of each of the plurality of first wirings.

8. The semiconductor device according to claim 1, The plurality of bonding pads include: Multiple first row pads, including first bonding pads and second bonding pads, are arranged along the first side, and Multiple second row pads are arranged further away from the first side compared to the multiple first row pads.

9. The semiconductor device according to claim 8, Each of the second wirings extending along one of the plurality of first wirings is formed in the second wiring layer. The plurality of first wirings arranged adjacent to each other are located between the second wirings. The plurality of wiring layers includes a third wiring layer disposed below the second wiring layer, and The third wiring layer includes: A fourth wiring, electrically connected to the second wiring, is supplied with the reference potential. In a perspective view, the fourth wiring extends along the first side to intersect each of the plurality of first wirings and the second wiring, and overlaps with the plurality of first row pads. The fifth wiring is electrically connected to the second wiring, and the reference potential will be supplied to the fifth wiring. In the perspective view, the fifth wiring extends along the first side to intersect each of the plurality of first wirings and the second wiring, and the fifth wiring overlaps with the plurality of second row pads.

10. The semiconductor device according to claim 9, The width of the fourth wiring and the width of the fifth wiring are greater than the width of each of the plurality of first wirings.

11. The semiconductor device according to claim 10, The plurality of second row pads include third bonding pads, the third bonding pads being electrically connected to the first bonding pads via the plurality of first wirings, and in, In the perspective view, each of the plurality of first wirings extends along the second direction to overlap with the bonding area of ​​the first bonding pad and the bonding area of ​​the third bonding pad.

12. The semiconductor device according to claim 10, in, In the perspective view, each of the plurality of first wirings is arranged to overlap with the bonding area of ​​the first bonding pad, but not with the plurality of second row pads.

13. The semiconductor device according to claim 8, Each of the plurality of first wirings arranged at the first position overlapping the bonding area of ​​the first bonding pad is electrically connected to one of the first bonding pad and the plurality of second row pads.

14. The semiconductor device according to claim 1, The distance between the plurality of first wires arranged adjacent to each other is equal to or less than the width of each of the plurality of first wires.

15. The semiconductor device according to claim 1, The width of each of the plurality of first wirings is 1.0 μm or less, and The distance between the plurality of first wirings is 0.55 μm or less.

16. The semiconductor device according to claim 1, in, In the perspective view, the second wiring overlaps with at least one of the first and second bonding pads, but does not overlap with the bonding area of ​​each of the first and second bonding pads.

17. The semiconductor device according to claim 1, The conductive component is connected to each of the first bonding pad and the second bonding pad, and in, In the perspective view, the second wiring overlaps with at least one of the first and second bonding pads, but does not overlap with the contact surface of the conductive member connected to each of the first and second bonding pads.

18. A semiconductor device, comprising: Semiconductor substrate, having a main surface; Multiple wiring layers are stacked on the main surface of the semiconductor substrate; as well as A protective film covers the plurality of wiring layers. The first wiring layer of the plurality of wiring layers includes a plurality of bonding pads, and the first wiring layer is disposed on the topmost layer of the plurality of wiring layers. Each of the plurality of bonding pads has a bonding region. The bonding region is exposed from the protective film at the opening formed in the protective film. The second wiring layer, which is disposed in a layer below the first wiring layer, includes: Multiple first wirings, in a perspective view taken from the upper surface side of the protective film, are located in a first region overlapping the bonding region, and Multiple second wirings are located in a second region that does not overlap with the bonding region in a perspective view taken from the upper surface side of the protective film. The width of each of the plurality of first wirings is smaller than the width of each of the plurality of second wirings. The distance between the plurality of first wires arranged adjacent to each other is equal to or less than the width of each of the plurality of first wires. The power potential will be supplied to each of the plurality of first wirings, and The reference potential will be supplied to each of the plurality of second wirings.

19. The semiconductor device according to claim 18, The plurality of bonding pads have the bonding area and the probe area. The bonding region and the probe region are exposed from the protective film at the opening formed in the protective film, and The second wiring layer includes: The plurality of first wirings, in a perspective view taken from the upper surface side of the protective film, are located at the first region overlapping each of the bonding region and the probe region, and The plurality of second wirings, in a perspective view taken from the upper surface side of the protective film, are located in a second region that does not overlap with each of the bonding region and the probe region.

20. The semiconductor device according to claim 19, The main surface of the semiconductor substrate has a first side extending along a first direction. The third wiring layer, which is disposed in a layer below the second wiring layer, includes: A third wiring, extending along the first side in a perspective view from the upper surface side of the protective film, will have the power potential supplied to the third wiring. A fourth wiring, extending along the first side in a perspective view from the upper surface side of the protective film, provides the reference potential to the fourth wiring. A fifth wiring, extending along the first side in a perspective view taken from the upper surface side of the protective film, supplies the reference potential to the fifth wiring. In the perspective view taken from the upper surface side of the protective film, the third wiring is arranged between the fourth and fifth wirings. The width of each of the plurality of first wirings and the width of the wiring included in the wiring layer located below the third wiring layer are smaller than the width of each of the plurality of second wirings, the width of the third wiring, the width of the fourth wiring, and the width of the fifth wiring. In a perspective view taken from the upper surface of the protective film, each of the plurality of second wirings extends along a second direction intersecting the first direction. The fourth wiring is electrically connected to the fifth wiring via at least one of the plurality of second wirings.

21. The semiconductor device according to claim 20, The plurality of bonding pads include: Multiple first row pads are arranged along the first side, and Multiple second row pads are arranged along the first side and are located further away from the first side compared to the multiple first row pads. The plurality of first row pads include: The first bonding pad is electrically connected to each of the plurality of first wirings, and The second bonding pad is electrically connected to at least one of the first wirings in the plurality of second wirings, and The plurality of second row pads include: The third bonding pad is electrically connected to each of the plurality of first wirings, and The fourth bonding pad is electrically connected to at least one of the plurality of second wirings.

22. The semiconductor device according to claim 21, The second region is the region that overlaps with the region between the plurality of first row pads arranged adjacent to each other in a perspective view taken from the upper surface side of the protective film. The plurality of first wirings are interconnected in areas of the second wiring layer other than the first area and the second area.

23. The semiconductor device according to claim 21, The second region is the region that overlaps with the region between the plurality of first row pads arranged adjacent to each other in a perspective view taken from the upper surface side of the protective film. The plurality of second wirings are interconnected in areas of the second wiring layer other than the first area and the second area.

Images