Semiconductor device

Abstract

A semiconductor device includes a substrate including a first active region and a second active region; a first source / drain pattern on the first active region; a second source / drain pattern on the second active region; a separation dielectric pattern on the substrate between the first source / drain pattern and the second source / drain pattern; and a first contact pattern on the first source / drain pattern, wherein the first contact pattern includes a first metal pattern; a first barrier pattern between the first metal pattern and the first source / drain pattern; and a second barrier pattern between the first barrier pattern and the first source / drain pattern, wherein the first barrier pattern contacts the separation dielectric pattern and extends along a sidewall of the first metal pattern adjacent to the separation dielectric pattern.

Description

TECHNICAL FIELD

[0001] The present inventive concepts relate to semiconductor devices, and more particularly, to semiconductor devices having improved reliability. BACKGROUND

[0002] Semiconductor devices can include integrated circuits formed with metal oxide semiconductor field effect transistors (MOSFETs). MOSFETs are a type of insulated gate field effect transistor that are manufactured by controlled oxidation of a semiconductor, typically silicon. As semiconductor devices including MOSFETs become highly integrated, MOSFETs are also scaled down in proportion; however, this can cause deterioration in operating characteristics of the semiconductor devices. Accordingly, various technologies are being developed to manufacture semiconductor devices having MOSFETs with excellent performance and high integration. SUMMARY

[0003] According to an example embodiment of the present inventive concepts, a semiconductor device can include a substrate including a first active region and a second active region; a first source / drain pattern on the first active region; a second source / drain pattern on the second active region; a separation dielectric pattern on the substrate between the first source / drain pattern and the second source / drain pattern; and a first contact pattern on the first source / drain pattern, wherein the first contact pattern includes a first metal pattern; a first barrier pattern between the first metal pattern and the first source / drain pattern; and a second barrier pattern between the first barrier pattern and the first source / drain pattern, wherein the first barrier pattern contacts the separation dielectric pattern and extends along a sidewall of the first metal pattern adjacent to the separation dielectric pattern.

[0004] According to an example embodiment of the present inventive concepts, a semiconductor device can include a first active fin protruding in a vertical direction from a top surface of a substrate; a first source / drain pattern on the first active fin; an interlayer dielectric layer on the substrate and covering the first source / drain pattern; and a first contact pattern in the interlayer dielectric layer and contacting the first source / drain pattern, wherein the first contact pattern includes a first metal pattern; a first barrier pattern between the first metal pattern and the first source / drain pattern; and a second barrier pattern between the first barrier pattern and the first metal pattern, wherein the second barrier pattern is disposed along a sidewall of the first metal pattern, and wherein a portion of the second barrier pattern is exposed by the first barrier pattern.

[0005] According to an example embodiment of the inventive concept, a semiconductor device can include: a plurality of active fins protruding from a top surface of a substrate and extending in a first direction, the active fins adjacent to each other; a gate pattern extending across the active fins in a second direction, the second direction crossing the first direction; a first source / drain pattern on the active fins at a first side of the gate pattern; and a first contact pattern on the first source / drain pattern, wherein the first contact pattern includes: a first metal pattern; and a first barrier pattern covering first and second sidewalls of the first metal pattern, wherein the first barrier pattern includes a first portion covering the first sidewall of the first metal pattern and a second portion covering the second sidewall of the first metal pattern, wherein the first portion includes a single layer, and wherein the second portion includes a plurality of layers. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 A top view showing a semiconductor device according to an example embodiment of the inventive concept is illustrated.

[0007] Figure 2A A cross-sectional view taken along line I-I' of the top view showing a semiconductor device according to an example embodiment of the inventive concept is illustrated. Figure 1

[0008] Figure 2B A cross-sectional view taken along line II-II' of the top view showing a semiconductor device according to an example embodiment of the inventive concept is illustrated. Figure 1

[0009] Figure 2C A cross-sectional view taken along line III-III' of the top view showing a semiconductor device according to an example embodiment of the inventive concept is illustrated. Figure 1

[0010] Figure 3 A cross-sectional view taken along line III-III' of the top view showing a semiconductor device according to an example embodiment of the inventive concept is illustrated. Figure 1

[0011] Figure 4A A cross-sectional view taken along line I-I' of the top view showing a semiconductor device according to an example embodiment of the inventive concept is illustrated. Figure 1

[0012] Figure 4B A cross-sectional view taken along line II-II' of the top view showing a semiconductor device according to an example embodiment of the inventive concept is illustrated. Figure 1

[0013] Figure 4C A cross-sectional view taken along line II-II' of the top view showing a semiconductor device according to an example embodiment of the inventive concept is illustrated. Figure 1 ​​​​​​cross-sectional view taken along line III-III' of FIG. 3.

[0014] Figure 5 shows a plan view showing a semiconductor device according to an example embodiment of the present inventive concept.

[0015] Figure 6A shows a cross-sectional view taken along line II-II' of FIG. 2 showing a semiconductor device according to an example embodiment of the present inventive concept. Figure 5

[0016] Figure 6B shows a cross-sectional view taken along line III-III' of FIG. 3 showing a semiconductor device according to an example embodiment of the present inventive concept. Figure 5

[0017] Figure 6C shows a cross-sectional view taken along line IV-IV' of FIG. 4 showing a semiconductor device according to an example embodiment of the present inventive concept. Figure 5

[0018] Figure 7 shows a plan view showing a semiconductor device according to an example embodiment of the present inventive concept.

[0019] Figure 8A shows a cross-sectional view taken along line IV-IV' of FIG. 4 showing a semiconductor device according to an example embodiment of the present inventive concept. Figure 7

[0020] Figure 8B shows a cross-sectional view taken along line V-V' of FIG. 5 showing a semiconductor device according to an example embodiment of the present inventive concept. Figure 7

[0021] Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16 , Figure 17A and Figure 18A shows a cross-sectional view taken along line I-I' of FIG. 1 showing a method of manufacturing a semiconductor device according to an example embodiment of the present inventive concept. Figure 1

[0022] Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 17B and​​​​​​Figure 18B The illustration shows a method for manufacturing a semiconductor device according to an exemplary embodiment of the concept of the present invention. Figure 1 The sectional view taken from line II-II'.

[0023] Figure 9C , Figure 10C , Figure 11C , Figure 12C , Figure 13C , Figure 14C , Figure 15C , Figure 17C and Figure 18C The illustration shows a method for manufacturing a semiconductor device according to an exemplary embodiment of the concept of the present invention. Figure 1 The sectional view taken from line III-III'.

[0024] Figure 19A and Figure 19B The illustration shows a method for manufacturing a semiconductor device according to an exemplary embodiment of the concept of the present invention. Figure 1 A sectional view taken by line I-I'. Detailed Implementation

[0025] Figure 1 A top view is shown illustrating an exemplary embodiment of a semiconductor device according to a concept conceived in this invention. Figure 2A The diagram illustrates an exemplary embodiment of a semiconductor device according to a concept of the present invention. Figure 1 A sectional view taken by line I-I'. Figure 2B The diagram illustrates an exemplary embodiment of a semiconductor device according to a concept of the present invention. Figure 1 The sectional view taken from line II-II'. Figure 2C The diagram illustrates an exemplary embodiment of a semiconductor device according to a concept of the present invention. Figure 1 The sectional view taken from line III-III'. Figure 3 The diagram illustrates an exemplary embodiment of a semiconductor device according to a concept of the present invention. Figure 1 The sectional view taken from line III-III'.

[0026] Reference Figure 1 , Figure 2A , Figure 2B and Figure 2CA device isolation layer 101 can be disposed in the substrate 100. The device isolation layer 101 can define active regions 100a and 100b of the substrate 100. The active regions 100a and 100b can include a first active region 100a and a second active region 100b. The first active region 100a and the second active region 100b can be spaced apart from each other in a second direction Y that crosses the first direction X. For example, the first active region 100a can be an n-type metal oxide semiconductor (NMOS) region, and the second active region 100b can be a p-type metal oxide semiconductor (PMOS) region. As another example, the first active region 100a and the second active region 100b can be NMOS regions. As another example, the first active region 100a and the second active region 100b can be PMOS regions. As another example, the first active region 100a can be a PMOS region, and the second active region 100b can be an NMOS region. The device isolation layer 101 can include a dielectric material (e.g., a silicon oxide layer or a silicon nitride layer). The active fins AF1 and AF2 can protrude from a top surface of the substrate 100 in a vertical direction (e.g., a third direction Z). The active fins AF1 and AF2 can extend in the first direction X that crosses the third direction Z and can be arranged in the second direction Y. The active fins AF1 and AF2 can include a first active fin AF1 and a second active fin AF2. The first active fin AF1 can be disposed on the first active region 100a of the substrate 100, and the second active fin AF2 can be disposed on the second active region 100b of the substrate 100.

[0027] The gate pattern GP can extend in the second direction Y across the first active fin AF1 and the second active fin AF2. The gate pattern GP can be spaced apart from each other in the first direction X. Top surfaces and sidewalls of the first active fin AF1 and the second active fin AF2 can be exposed by the device isolation layer 101 and covered by the gate pattern GP. For example, the top surfaces and sidewalls of the first active fin AF1 and the second active fin AF2 can protrude into the gate pattern GP. The gate pattern GP can include a metal (e.g., tungsten, copper, or aluminum) or a metal nitride (e.g., a titanium nitride layer or a tantalum nitride layer).

[0028] A spacer 103 can be disposed on a sidewall of each of the gate pattern GP. The spacer 103 can cover the sidewall of the gate pattern GP. The spacer 103 can include a dielectric material (e.g., a silicon oxide layer or a silicon nitride layer). A gate dielectric layer 105 can be disposed between each of the gate pattern GP and the first and second active fins AF1 and AF2. The gate dielectric layer 105 can extend from between the gate pattern GP and the first and second active fins AF1 and AF2 to an area between the gate pattern GP and a top surface of the device isolation layer 101. The gate dielectric layer 105 can be interposed between the gate pattern GP and the spacer 103. The gate dielectric layer 105 can include, for example, a silicon oxide layer or a thermal oxide layer.

[0029] The cap pattern 107 can be disposed on each of the gate patterns GP. For example, the cap pattern 107 can be disposed on the top surface of the gate pattern GP, the top surface of the gate dielectric layer 105, and the top surface of the spacer 103. The cap pattern 107 can have a bottom surface protruding convexly toward the top surface of the substrate 100, and a top surface parallel to the top surface of the substrate 100. The cap pattern 107 can include a dielectric material, such as a silicon nitride layer or a silicon oxynitride layer.

[0030] The first source / drain pattern SDP1 can be disposed on the first active fin AF1 between the gate patterns GP. The top surface of the first active fin AF1 between the gate patterns GP can be located at a level lower than the top surface of the first active fin AF1 under the gate patterns GP. The first source / drain pattern SDP1 can have its top surface at a level higher than the top surface of the first active fin AF1 under the gate patterns GP. Alternatively, as shown, the first source / drain pattern SDP1 can have its top surface coplanar with the top surface of the first active fin AF1 under the gate patterns GP. The first source / drain pattern SDP1 can be a single pattern in which a plurality of epitaxial patterns disposed on the first active fins AF1 adjacent to each other in the second direction Y are merged. For example, the first source / drain pattern SDP1 can be shaped like a combination of a plurality of pentagonal epitaxial patterns. The first source / drain pattern SDP1 can have a zigzag shape at its top surface. The first source / drain pattern SDP1 can be doped with an N-type or P-type impurity. Figure 3

[0031] The second source / drain pattern SDP2 can be disposed on the second active fin AF2 between the gate patterns GP. The second active fin AF2 between the gate patterns GP can have its top surface at a level lower than the top surface of the second active fin AF2 under the gate patterns GP. The second source / drain pattern SDP2 can be a single pattern in which a plurality of epitaxial patterns disposed on the second active fins AF2 adjacent to each other in the second direction Y are merged. For example, the second source / drain pattern SDP2 can be shaped like a combination of a plurality of pentagonal epitaxial patterns. The second source / drain pattern SDP2 can have a zigzag shape at its top surface. The second source / drain pattern SDP2 can be doped with an N-type or P-type impurity.

[0032] ​A first interlayer dielectric layer ILD1 can be disposed on the first and second source / drain patterns SDP1 and SDP2. The first interlayer dielectric layer ILD1 can cover top surfaces of the first and second source / drain patterns SDP1 and SDP2 and sidewalls of the spacers 103. The first interlayer dielectric layer ILD1 can have a top surface that is coplanar with a top surface of the cap pattern 107. The first interlayer dielectric layer ILD1 can include a dielectric material (e.g., a silicon oxide layer). A second interlayer dielectric layer ILD2 can be disposed on the first interlayer dielectric layer ILD1. The second interlayer dielectric layer ILD2 can cover a top surface of the first interlayer dielectric layer ILD1 and a top surface of the cap pattern 107. The second interlayer dielectric layer ILD2 can include a dielectric material (e.g., a silicon oxide layer).

[0033] A first contact pattern CP1 can be disposed on the first active region 100a of the substrate 100. The first contact pattern CP1 can be disposed on the first source / drain patterns SDP1 between the gate patterns GP adjacent to each other in the first direction X. The first contact pattern CP1 can be in contact with a top surface of the first source / drain patterns SDP1. The first contact pattern CP1 can extend across the first active fin AF1 in the second direction Y. A second contact pattern CP2 can be disposed on the second active region 100b of the substrate 100. The second contact pattern CP2 can be disposed on the second source / drain patterns SDP2 between the gate patterns GP adjacent to each other in the first direction X. The second contact pattern CP2 can be in contact with a top surface of the second source / drain patterns SDP2. The second contact pattern CP2 can extend across the second active fin AF2 in the second direction Y. The first and second contact patterns CP1 and CP2 can be spaced apart from each other in the second direction Y. For example, as shown in FIG. 1, the first and second contact patterns CP1 and CP2 can be spaced apart from each other in the second direction Y without any of the first and second active regions 100a and 100b disposed therebetween. Figure 1

[0034] A separation dielectric pattern SP can be disposed between the first and second contact patterns CP1 and CP2. The separation dielectric pattern SP can penetrate the second interlayer dielectric layer ILD2 and the first interlayer dielectric layer ILD1 and can be disposed in an upper portion of the device isolation layer 101. The separation dielectric pattern SP can physically separate the first and second contact patterns CP1 and CP2 from each other. The separation dielectric pattern SP can include a dielectric material (e.g., a silicon oxide layer).

[0035] ​Each of the first contact pattern CP1 and the second contact pattern CP2 can include a first barrier pattern 120, a second barrier pattern 122, a metal pattern 124, and an interface pattern 126. The metal pattern 124 can penetrate the second interlayer dielectric layer ILD2, and can be disposed in the first interlayer dielectric layer ILD1. The metal pattern 124 can be spaced apart from the separation dielectric pattern SP. For example, the second barrier pattern 122 can be disposed between the metal pattern 124 and the separation dielectric pattern SP. The metal pattern 124 can include one or more of tungsten (W), cobalt (Co), and ruthenium (Ru). The metal pattern 124 of each of the first contact pattern CP1 and the second contact pattern CP2 can have a first sidewall SW1, a second sidewall SW2, a third sidewall SW3, and a fourth sidewall SW4. The first sidewall SW1 and the second sidewall SW2 can be disposed spaced apart from each other in the first direction X, and can be parallel to the second direction Y. The third sidewall SW3 and the fourth sidewall SW4 can be disposed spaced apart from each other in the second direction Y, and can be parallel to the first direction X. The fourth sidewall SW4 of the metal pattern 124 can be adjacent to the separation dielectric pattern SP.

[0036] The second barrier pattern 122 can be disposed on a sidewall of the metal pattern 124. The second barrier pattern 122 of the first contact pattern CP1 can be interposed between the metal pattern 124 and the first source / drain pattern SDP1, and the second barrier pattern 122 of the second contact pattern CP2 can be interposed between the metal pattern 124 and the second source / drain pattern SDP2. The second barrier pattern 122 can completely surround the sidewall of the metal pattern 124. For example, in a top view, the second barrier pattern 122 can surround the first sidewall SW1, the second sidewall SW2, the third sidewall SW3, and the fourth sidewall SW4 of the metal pattern 124. The second barrier pattern 122 can be in contact with one sidewall of the separation dielectric pattern SP. For example, the second barrier pattern 122 can be disposed between the one sidewall of the separation dielectric pattern SP and the fourth sidewall SW4 of the metal pattern 124. The second barrier pattern 122 can have a top surface that is coplanar with a top surface of the metal pattern 124 and a top surface of the separation dielectric pattern SP. When viewed in a top view, the second barrier pattern 122 can have a rectangular ring shape. The second barrier pattern 122 can include one or more of titanium (Ti) and titanium nitride (TiN).

[0037] The first barrier pattern 120 can be disposed on sidewalls of the second barrier pattern 122. The first barrier pattern 120 of the first contact pattern CP1 can be interposed between the second barrier pattern 122 and the first source / drain pattern SDP1, and the first barrier pattern 120 of the second contact pattern CP2 can be interposed between the second barrier pattern 122 and the second source / drain pattern SDP2. In a top view, the first barrier pattern 120 can cover at least one sidewall of the second barrier pattern 122, and can expose the remaining sidewalls of the second barrier pattern 122. For example, the first barrier pattern 120 can cover the sidewalls of the second barrier pattern 122, which are located in positions corresponding to the first sidewall SW1, the second sidewall SW2, and the third sidewall SW3 of the metal pattern 124. The first barrier pattern 120 can expose the sidewall of the second barrier pattern 122, which is located in a position corresponding to the fourth sidewall SW4 of the metal pattern 124. In other words, the first barrier pattern 120 can not be disposed in a position corresponding to the fourth sidewall SW4 of the metal pattern 124.

[0038] In an exemplary embodiment of the inventive concept, a second distance W2 in the second direction Y between the first barrier pattern 120 of the first contact pattern CP1 and the first barrier pattern 120 of the second contact pattern CP2 can be substantially the same (W1=W2) as a first distance W1 in the second direction Y between the second barrier pattern 122 of the first contact pattern CP1 and the second barrier pattern 122 of the second contact pattern CP2. The second distance W2 can correspond to a thickness of the separation dielectric pattern SP in the second direction Y between the first barrier pattern 120 of the first contact pattern CP1 and the first barrier pattern 120 of the second contact pattern CP2. The first distance W1 can correspond to a thickness of the separation dielectric pattern SP in the second direction Y between the second barrier pattern 122 of the first contact pattern CP1 and the second barrier pattern 122 of the second contact pattern CP2. The first barrier pattern 120 and the second barrier pattern 122 can have respective sidewalls S1 and S2 that contact the separation dielectric pattern SP, and the sidewalls S1 and S2 can be aligned with each other.

[0039] The first barrier pattern 120 can include first sections P1 and second sections P2 when viewed in a top view. The first sections P1 can be parallel to the second direction Y and can be spaced apart from each other in the first direction X. The second sections P2 can contact first ends of the first sections P1 and can connect the first ends to each other. The first ends of the first sections P1 of the first barrier pattern 120 can be spaced apart from the separation dielectric pattern SP, the second ends of the first sections P1 of the first barrier pattern 120 can be adjacent to and in contact with the separation dielectric pattern SP, the second ends of the first sections P1 of the first barrier pattern 120 being opposite the first ends of the first sections P1 of the first barrier pattern 120. The first barrier pattern 120 can have a U shape when viewed in a top view. The first barrier pattern 120 can include one or more of titanium (Ti) and titanium nitride (TiN).

[0040] In an example embodiment of the inventive concept, the portion of the barrier pattern disposed on the first, second, and third sidewalls SW1, SW2, and SW3 of the metal pattern 124 of each of the first and second contact patterns CP1 and CP2 can include multiple layers. The barrier pattern can include a first portion PA1, a second portion PA2, a third portion PA3, and a fourth portion PA4. The first portion PA1 can be the portion of the barrier pattern on the first sidewall SW1 of the metal pattern 124. The second portion PA2 can be the portion of the barrier pattern on the second sidewall SW2 of the metal pattern 124. The third portion PA3 can be the portion of the barrier pattern on the third sidewall SW3 of the metal pattern 124. The fourth portion PA4 can be the portion of the barrier pattern on the fourth sidewall SW4 of the metal pattern 124. For example, the first, second, and third portions PA1, PA2, and PA3 of the barrier pattern can include the first barrier pattern 120 and the second barrier pattern 122. In this case, the first, second, and third portions PA1, PA2, and PA3 of the barrier pattern can include multiple layers. The fourth portion PA4 of the barrier pattern can be a single layer. For example, the fourth portion PA4 of the barrier pattern can include the second barrier pattern 122. The first, second, and third portions PA1, PA2, and PA3 of the barrier pattern can each be thicker than the fourth portion PA4 of the barrier pattern.

[0041] The interface pattern 126 can be disposed between the first source / drain pattern SDP1 and the first barrier pattern 120 and between the second source / drain pattern SDP2 and the first barrier pattern 120. The interface pattern 126 can cover top surfaces of the first and second source / drain patterns SDP1 and SDP2. The interface pattern 126 can include a material formed by chemical bonding of a semiconductor material and a metallic material. The interface pattern 126 can include, for example, TiSi2.

[0042] A third contact pattern CP3 can be disposed on the first and second source / drain patterns SDPl and SDP2 between adjacent gate patterns GP. The third contact pattern CP3 can be disposed on the first and second active regions 100a and 100b of the substrate 100 and can extend across the first and second active fins AF1 and AF2 in the second direction Y. The third contact pattern CP3 can contact the first and second source / drain patterns SDPl and SDP2. The third contact pattern CP3 can be spaced apart from the first and second contact patterns CPI and CP2 in the first direction X. For example, the gate patterns GP can be disposed between the third contact pattern CP3 and both of the first and second contact patterns CPI and CP2. The third contact pattern CP3 can include a first barrier pattern 130, a second barrier pattern 132, a metal pattern 134, and an interface pattern 136. The metal pattern 134 can penetrate the second interlayer dielectric layer ILD2 and can be disposed in the first interlayer dielectric layer ILD1. The metal pattern 134 can include one or more of tungsten (W), cobalt (Co), and ruthenium (Ru). The metal pattern 134 can have a fifth sidewall SW5, a sixth sidewall SW6, a seventh sidewall SW7, and an eighth sidewall SW8. The fifth and sixth sidewalls SW5 and SW6 can be spaced apart from each other in the first direction X and can be parallel to the second direction Y. The fifth and sixth sidewalls SW5 and SW6 can be parallel to the first and second sidewalls SW1 and SW2 of the metal pattern 124. The seventh and eighth sidewalls SW7 and SW8 can be spaced apart from each other in the second direction Y and can be parallel to the first direction X. The seventh and eighth sidewalls SW7 and SW8 can be parallel to the third and fourth sidewalls SW3 and SW4 of the metal pattern 124.

[0043] The second barrier pattern 132 can cover sidewalls of the first metal pattern 134, and can be interposed between the metal pattern 134 and the first source / drain pattern SDP1 and between the metal pattern 134 and the second source / drain pattern SDP2. The second barrier pattern 132 can surround the sidewalls of the metal pattern 134. For example, the second barrier pattern 132 can completely surround the fifth sidewall SW5, the sixth sidewall SW6, the seventh sidewall SW7, and the eighth sidewall SW8 of the metal pattern 134. When viewed in a top view, the second barrier pattern 132 can have a rectangular ring shape. The second barrier pattern 132 can include one or more of, for example, titanium (Ti) and titanium nitride (TiN). The first barrier pattern 130 can cover sidewalls of the second barrier pattern 132, and can be interposed between the second barrier pattern 132 and the first source / drain pattern SDP1 and between the second barrier pattern 132 and the second source / drain pattern SDP2. The first barrier pattern 130 can completely surround the sidewalls of the second barrier pattern 132. When viewed in a top view, the first barrier pattern 130 can have a rectangular ring shape. The first barrier pattern 130 can include one or more of, for example, titanium (Ti) and titanium nitride (TiN). The interface pattern 136 of the third contact pattern CP3 can be disposed between the first barrier pattern 130 and the first source / drain pattern SDP1 and between the first barrier pattern 130 and the second source / drain pattern SDP2. The interface pattern 136 can include a material formed by a chemical combination of a semiconductor material and a metallic material. For example, the interface pattern 136 can include TiSi2.

[0044] In an example embodiment of the inventive concept, the barrier pattern on the fifth sidewall SW5, the sixth sidewall SW6, and the seventh sidewall SW7 of the metal pattern 134 of the third contact pattern CP3 can include multiple layers. The barrier pattern can include a fifth portion PA5, a sixth portion PA6, a seventh portion PA7, and an eighth portion PA8. The fifth portion PA5 can be a portion of the barrier pattern on the fifth sidewall SW5 of the metal pattern 134. The sixth portion PA6 can be a portion of the barrier pattern on the sixth sidewall SW6 of the metal pattern 134. The seventh portion PA7 can be a portion of the barrier pattern on the seventh sidewall SW7 of the metal pattern 134. The eighth portion PA8 can be a portion of the barrier pattern on the eighth sidewall SW8 of the metal pattern 134. For example, the fifth portion PA5, the sixth portion PA6, the seventh portion PA7, and the eighth portion PA8 of the barrier pattern can include the first barrier pattern 130 and the second barrier pattern 132. In this case, the fifth portion PA5, the sixth portion PA6, the seventh portion PA7, and the eighth portion PA8 can include multiple layers. The fifth portion PA5, the sixth portion PA6, the seventh portion PA7, and the eighth portion PA8 can have the same thickness.

[0045] Figure 4A shows a cross-sectional view taken along the line I-I' of a semiconductor device showing an exemplary embodiment in accordance with the inventive concept. Figure 1 Figure 4B shows a cross-sectional view taken along the line II-II' of a semiconductor device showing an exemplary embodiment in accordance with the inventive concept. Figure 1 Figure 4C shows a cross-sectional view taken along the line III-III' of a semiconductor device showing an exemplary embodiment in accordance with the inventive concept. Figure 1

[0046] With reference to Figure 4A , Figure 4B and Figure 4C , a second distance W2 in the second direction Y between the first barrier pattern 120 of the first contact pattern CP1 and the first barrier pattern 120 of the second contact pattern CP2 can be different from a first distance W1 in the second direction Y between the second barrier pattern 122 of the first contact pattern CP1 and the second barrier pattern 122 of the second contact pattern CP2. For example, the second distance W2 can be smaller than the first distance W1 (W2 < W1). The first barrier pattern 120 and the second barrier pattern 122 can have respective sidewalls S1 and S2 of the contact separation dielectric pattern SP, and the sidewalls S1 and S2 can be misaligned with respect to each other. For example, the sidewall S1 of the first barrier pattern 120 can protrude into the separation dielectric pattern SP. The first barrier pattern 120 can have a top surface, portions of which are exposed by the second barrier pattern 122 and covered by the separation dielectric pattern SP.

[0047] Figure 5 shows a top view of a semiconductor device showing an exemplary embodiment in accordance with the inventive concept. Figure 6A shows a cross-sectional view taken along the line I-I' of a semiconductor device showing an exemplary embodiment in accordance with the inventive concept. Figure 5 Figure 6B shows a cross-sectional view taken along the line II-II' of a semiconductor device showing an exemplary embodiment in accordance with the inventive concept. Figure 5 Figure 6C shows a cross-sectional view taken along the line III-III' of a semiconductor device showing an exemplary embodiment in accordance with the inventive concept. Figure 5

[0048] With reference to Figure 5 , Figure 6A , Figure 6B and Figure 6C ​​​​​​The first active fin AF1 can be disposed on the first active region 100a of the substrate 100, and the second active fin AF2 can be disposed on the second active region 100b of the substrate 100. The first active fin AF1 and the second active fin AF2 can protrude in the third direction Z from a top surface of the substrate 100. The first active patterns AP1 can be spaced apart from each other in the third direction Z on the first active fin AF1, and the second active patterns AP2 can be spaced apart from each other in the third direction Z on the second active fin AF2. The gate pattern GP can extend in the second direction Y and can extend across the first active fin AF1 and the second active fin AF2. The gate pattern GP can fill spaces between the first active fin AF1 and the lowermost first active pattern AP1, between the first active patterns AP1 adjacent to each other in the third direction Z, between the second active fin AF2 and the lowermost second active pattern AP2, and between the second active patterns AP2 adjacent to each other in the third direction Z. The gate pattern GP can be disposed on the uppermost first active pattern AP1 and the uppermost second active pattern AP2. The gate pattern GP can surround the first active patterns AP1 and the second active patterns AP2. The gate dielectric pattern 105a can be interposed between the gate pattern GP and the first active fin AF1, between the gate pattern GP and the second active fin AF2, between the gate pattern GP and the first active pattern AP1, and between the gate pattern GP and the second active pattern AP2. The gate dielectric pattern 105a can extend between the device isolation layer 101 and the gate pattern GP.

[0049] For example, the spacer pattern 260 can be disposed between the first active fin AF1 and the lowermost first active pattern AP1, between the first active patterns AP1 adjacent to each other in the third direction Z, between the second active fin AF2 and the lowermost second active pattern AP2, between the second active patterns AP2 adjacent to each other in the third direction Z, and between the sidewalls of the first and second source / drain patterns SDP1 and SDP2 and the sidewalls of the portions of the gate pattern GP between the second active patterns AP2 adjacent to each other in the third direction Z and between the first active patterns AP1 adjacent to each other in the third direction Z. The spacer pattern 260 can contact the sidewalls of the first source / drain pattern SDP1 and the sidewalls of the second source / drain pattern SDP2. The spacer pattern 260 can include a dielectric material, such as a silicon nitride layer or a silicon oxynitride layer. For example, the gate dielectric pattern 105a can extend between the first active fin AF1 and the lowermost first active pattern AP1, between the first active patterns AP1 adjacent to each other in the third direction Z, between the second active fin AF2 and the lowermost second active pattern AP2, between the second active patterns AP2 adjacent to each other in the third direction Z, and between the sidewalls of the spacer pattern 260 and the sidewalls of the portions of the gate pattern GP between the second active patterns AP2 adjacent to each other in the third direction Z and between the first active patterns AP1 adjacent to each other in the third direction Z.

[0050] The spacer 103 can be disposed on each of the uppermost first active pattern AP1 and the uppermost second active pattern AP2 and can cover the sidewalls of the gate pattern GP. The spacer 103 can be disposed between the gate pattern GP and the first interlayer dielectric layer ILD1.

[0051] Figure 7 A top view showing a semiconductor device according to an exemplary embodiment of the present inventive concept is illustrated. Figure 8A A cross-sectional view taken along line IV-IV' of Figure 7 showing a semiconductor device according to an exemplary embodiment of the present inventive concept is illustrated. Figure 8B A cross-sectional view taken along line V-V' of Figure 7 showing a semiconductor device according to an exemplary embodiment of the present inventive concept is illustrated.

[0052] Reference is made to Figure 7 , Figure 8A and Figure 8BThe substrate 100 can include a first active region 100a and a second active region 100b defined by the device isolation layer 101. The first active region 100a and the second active region 100b can be spaced apart from each other in the second direction Y. A gate pattern GP can be disposed on the first active region 100a and the second active region 100b. The gate pattern GP can extend in the second direction Y and can extend across the first active region 100a and the second active region 100b. A gate dielectric layer 105 can be disposed between the gate pattern GP and the first and second active regions 100a and 100b. A cap pattern 107 can be disposed on a top surface of the gate pattern GP. Spacers 103 can cover sidewalls of the gate pattern GP, sidewalls of the gate dielectric layer 105, and sidewalls of the cap pattern 107.

[0053] A first source / drain pattern SDP1 can be disposed in or on the first active region 100a exposed by the gate pattern GP. The first source / drain pattern SDP1 can be an epitaxial pattern formed by using the substrate 100 as a seed. The first source / drain pattern SDP1 can be an impurity region formed by doping the substrate 100 with an impurity. A second source / drain pattern SDP2 can be disposed in or on the second active region 100b exposed by the gate pattern GP. The second source / drain pattern SDP2 can be an epitaxial pattern formed by using the substrate 100 as a seed. The second source / drain pattern SDP2 can be an impurity region formed by doping the substrate 100 with an impurity.

[0054] A first interlayer dielectric layer ILD1 can be disposed on the substrate 100. The first interlayer dielectric layer ILD1 can cover top surfaces of the first source / drain pattern SDP1 and the second source / drain pattern SDP2, a top surface of the device isolation layer 101, and sidewalls of the spacers 103. The first interlayer dielectric layer ILD1 can have a top surface that is coplanar with a top surface of the cap pattern 107. A second interlayer dielectric layer ILD2 can cover a top surface of the cap pattern 107 and a top surface of the first interlayer dielectric layer ILD1.

[0055] The first contact pattern CP1 can penetrate the first interlayer dielectric layer ILD1 and the second interlayer dielectric layer ILD2 to contact a top surface of the first source / drain pattern SDP1. The second contact pattern CP2 can penetrate the first interlayer dielectric layer ILD1 and the second interlayer dielectric layer ILD2 to contact a top surface of the second source / drain pattern SDP2. The first contact pattern CP1 and the second contact pattern CP2 can be spaced apart from each other in the second direction Y. Each of the first contact pattern CP1 and the second contact pattern CP2 can include the first barrier pattern 120, the second barrier pattern 122, the metal pattern 124, and the interface pattern 126. The separation dielectric pattern SP can be disposed between the first contact pattern CP1 and the second contact pattern CP2. The separation dielectric pattern SP can be in direct contact with a side surface of each of the first contact pattern CP1 and the second contact pattern CP2. Descriptions of the first contact pattern CP1, the second contact pattern CP2, and the separation dielectric pattern SP are the same as those discussed above with reference to FIGS. 1A to 1C, and thus will be omitted. Figure 1 、 Figure 2A 、 Figure 2B and Figure 2C

[0056] Figures 9A-15A 、 Figure 16 、 Figure 17A and Figure 18A FIG. 1D illustrates a cross-sectional view taken along line I-I' of FIG. 1A, showing a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept. Figure 1 Figures 9B-15B 、 Figure 17B and Figure 18B FIG. 2D illustrates a cross-sectional view taken along line II-II' of FIG. 2A, showing a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept. Figure 1 Figures 9C-15C 、 Figure 17C and Figure 18C FIG. 3D illustrates a cross-sectional view taken along line III-III' of FIG. 3A, showing a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept. Figure 1

[0057] Referring to Figure 9A 、 Figure 9B and Figure 9C ​​​​A device isolation layer 101 can be formed in the substrate 100. The device isolation layer 101 can be formed by etching an upper portion of the substrate 100 to form a trench and then filling the trench with a dielectric material, such as silicon oxide. The device isolation layer 101 can define a first active region 100a and a second active region 100b of the substrate 100. The first active region 100a and the second active region 100b can be spaced apart from each other in the second direction Y. A first active fin AF1 can be formed on the first active region 100a, and a second active fin AF2 can be formed on the second active region 100b. The first active fin AF1 and the second active fin AF2 can protrude from a top surface of the substrate 100 in the third direction Z. The device isolation layer 101 can expose upper sidewalls and a top surface of the first active fin AF1 and the second active fin AF2.

[0058] A sacrificial dielectric layer SL can cover the top surfaces and sidewalls of the first active fin AF1 and the second active fin AF2 that are exposed by the device isolation layer 101. The sacrificial dielectric layer SL can conformally cover the top surfaces and sidewalls of the first active fin AF1 and the second active fin AF2. The sacrificial layer SL can include an oxide layer or a nitride layer.

[0059] A sacrificial gate layer CG can be formed on the sacrificial dielectric layer SL. The sacrificial gate layer CG can cover a top surface of the sacrificial dielectric layer SL. The sacrificial gate layer CG can fill a gap between the first active fin AF1 and the second active fin AF2. The sacrificial gate layer CG can include at least one layer that is etch-selective with respect to the sacrificial dielectric layer SL. The sacrificial gate layer CG can include, for example, polysilicon.

[0060] A first mask pattern 210 can be formed on the sacrificial gate layer CG. The first mask pattern 210 can be spaced apart from each other on the sacrificial gate layer CG along the first direction X and can extend in the second direction Y. The first mask pattern 210 can occupy an area in which the gate pattern GP discussed above with reference to FIG. 1A is to be disposed. The first mask pattern 210 can include a silicon oxide layer or a silicon nitride layer. Figure 1

[0061] Figure 10A Figure 10B Figure 10C ​​​​A patterning process in which the first mask pattern 210 is used can be performed to sequentially pattern the sacrificial gate layer CG and the sacrificial dielectric layer SL. Thus, the sacrificial dielectric pattern SLa and the sacrificial gate pattern CGa can be sequentially formed on the substrate 100. The patterning process can be performed using wet etching or dry etching. The sacrificial dielectric pattern SLa, the sacrificial gate pattern CGa, and the first mask pattern 210 can be arranged on the substrate 100 along the first direction X and can extend in the second direction Y. The sacrificial dielectric pattern SLa, the sacrificial gate pattern CGa, and the first mask pattern 210 can expose top surfaces of the device isolation layer 101 between the first mask pattern 210 and can also expose portions of the first active fin AF1 and the second active fin AF2 between the first mask pattern 210.

[0062] A spacer 103 can be formed on sidewalls of the sacrificial dielectric pattern SLa, sidewalls of the sacrificial gate pattern CGa, and sidewalls of the first mask pattern 210. The spacer 103 can be formed by forming and etching a dielectric layer that conformally covers top surfaces of the first mask pattern 210, sidewalls of the sacrificial dielectric pattern SLa, sidewalls of the sacrificial gate pattern CGa, and sidewalls of the first mask pattern 210. The spacer 103 can expose the top surfaces of the first mask pattern 210. The spacer 103 can include a dielectric material such as a silicon oxide layer or a silicon nitride layer.

[0063] Referring to Figure 11A , Figure 11B and Figure 11C An etching process can be performed to etch portions of the first active fin AF1 and the second active fin AF2 exposed by the sacrificial dielectric pattern SLa, the sacrificial gate pattern CGa, the first mask pattern 210, and the spacer 103. Thus, top surfaces of the first active fin AF1 and the second active fin AF2 disposed between the first mask pattern 210 can be recessed from top surfaces of the first active fin AF1 and the second active fin AF2 disposed under the sacrificial dielectric pattern SLa. The etching process can be performed by employing dry etching.

[0064] Referring to Figure 12A , Figure 12B and Figure 12CA first source / drain pattern SDP1 can be formed on the first active fin AF1 exposed by the first mask pattern 210, and a second source / drain pattern SDP2 can be formed on the second active fin AF2 exposed by the first mask pattern 210. The first source / drain pattern SDP1 can be formed by performing an epitaxial growth process in which a portion of the first active fin AF1 exposed by the device isolation layer 101 on the first active region 100a and the first mask pattern 210 is used as a seed crystal. For example, the first source / drain pattern SDP1 can be an epitaxial layer grown from the portion of the first active fin AF1. The first source / drain pattern SDP1 can be a single pattern in which a plurality of epitaxial patterns formed on the portion of the first active fin AF1 exposed by the device isolation layer 101 on the first active region 100a and the first mask pattern 210 are merged. The epitaxial patterns can have a pentagonal shape, and the first source / drain pattern SDP1 can have a shape in which the pentagonal epitaxial patterns are merged with each other in the second direction Y. For example, the first source / drain pattern SDP1 can have a top surface at a level higher than a level of a top surface of the first active fin AF1 disposed under the sacrificial dielectric pattern SLa. As another example, as shown in FIG. 2B, the first source / drain pattern SDP1 can have a top surface coplanar with a top surface of the first active fin AF1 disposed under the sacrificial dielectric pattern SLa. The first source / drain pattern SDP1 can fill a recessed region of the substrate 100 between the first mask pattern 210 on the first active region 100a of the substrate 100. Figure 3

[0065] ​The second source / drain pattern SDP2 can be formed by performing an epitaxial growth process in which the portions of the second active fin AF2 exposed by the device isolation layer 101 on the second active region 100b of the substrate 100 and the first mask pattern 210 are used as seeds. For example, the second source / drain pattern SDP2 can be an epitaxial layer grown from the portions of the second active fin AF2. The second source / drain pattern SDP2 can be a single pattern in which a plurality of epitaxial patterns formed on the portions of the second active fin AF2 exposed by the device isolation layer 101 on the second active region 100b and the first mask pattern 210 are merged. The epitaxial patterns can have a pentagonal shape, and the second source / drain pattern SDP2 can have a shape in which the pentagonal epitaxial patterns are merged with each other in the second direction Y. For example, the second source / drain pattern SDP2 can have a top surface at a level higher than a level of the top surface of the second active fin AF2 disposed under the sacrificial dielectric pattern SLa. As another example, the second source / drain pattern SDP2 can have a top surface that is coplanar with the top surface of the second active fin AF2 disposed under the sacrificial dielectric pattern SLa. The second source / drain pattern SDP2 can fill the recessed regions of the substrate 100 between the first mask pattern 210 on the second active region 100b. The first source / drain pattern SDP1 and the second source / drain pattern SDP2 can be formed simultaneously with each other. A gap can be formed between the first source / drain pattern SDP1 and the second source / drain pattern SDP2 in the second direction Y.

[0066] A first interlayer dielectric layer ILD1 can be formed on the first source / drain pattern SDP1 and the second source / drain pattern SDP2. The first interlayer dielectric layer ILD1 can fill the spaces between the first mask pattern 210 and can cover the top surface of the first mask pattern 210. The first interlayer dielectric layer ILD1 can include a dielectric material, such as a silicon oxide layer or a silicon nitride layer.

[0067] An etching process can be performed such that the first interlayer dielectric layer ILD1 and the first mask pattern 210 are etched until the top surface of the sacrificial gate pattern CGa is exposed. Thus, the sacrificial gate pattern CGa can be exposed at its top surface, and the spacer 103 can also be exposed at its top surface. The top surface of the sacrificial gate pattern CGa can be coplanar with the top surface of the spacer 103 and the top surface of the first interlayer dielectric layer ILD1. A chemical mechanical polishing process can be employed as the etching process.

[0068] Referring to Figure 13A , Figure 13B and Figure 13CThe gate recess region GRR can be formed by removing the sacrificial dielectric pattern SLa and the sacrificial gate pattern CGa exposed by the first interlayer dielectric layer ILD1. The gate recess region GRR can partially expose the first active fin AF1 between the first source / drain patterns SDP1 adjacent to each other in the first direction X, and can also expose the second active fin AF2 between the second source / drain patterns SDP2 adjacent to each other in the first direction X. The gate recess region GRR can expose the inner sidewall of the spacer 103. The sacrificial dielectric pattern SLa and the sacrificial gate pattern CGa can be selectively removed using an etching recipe that has etching selectivity with respect to the spacer 103 and the substrate 100.

[0069] The gate dielectric layer 105 can conformally cover the top surface and sidewall of the first active fin AF1 exposed to the gate recess region GRR, the top surface and sidewall of the second active fin AF2 exposed to the gate recess region GRR, and the inner sidewall of the spacer 103 exposed to the gate recess region GRR. The gate dielectric layer 105 can include, for example, a silicon oxide layer or a high-k dielectric layer (e.g., HfO2, HfSiO, HfSiON, HfON, HfAlO, HfLaO, or TaO2).

[0070] A gate pattern GP can be formed in the gate recess region GRR in which the gate dielectric layer 105 is formed. The gate pattern GP can be formed by forming a metal layer to fill the gate recess region GRR and cover the top surface of the first interlayer dielectric layer ILD1, and performing an etching process until the top surface of the gate pattern GP is recessed from the top surface of the first interlayer dielectric layer ILD1. In other words, the top surface of the gate pattern GP is below the top surface of the first interlayer dielectric layer ILD1. When etching the gate pattern GP, the upper portion of the spacer 103 and the upper portion of the gate dielectric layer 105 can be etched. The etching process can be performed by employing wet etching or dry etching. The gate pattern GP can include one or more of a metal nitride material (e.g., TiN, TaN, AlN, WN, or MoN), a metal (e.g., W, Al, or Cu), and a semiconductor material (e.g., Si).

[0071] A cap pattern 107 can be disposed on the top surface of the gate pattern GP, the top surface of the spacer 103, and the top surface of the gate dielectric layer 105. The cap pattern 107 can fill the upper portion of the gate recess region GRR. The cap pattern 107 can be formed by forming a dielectric layer to fill the upper portion of the gate recess region GRR and cover the top surface of the first interlayer dielectric layer ILD1, and performing an etching process until the top surface of the first interlayer dielectric layer ILD1 is exposed. The etching process to form the cap pattern 107 can be performed by employing chemical mechanical polishing or dry etching. The cap pattern 107 can include a dielectric material (e.g., a silicon nitride layer or a silicon oxide layer).

[0072] A second interlayer dielectric layer ILD2 can be formed over the cap pattern 107. The second interlayer dielectric layer ILD2 can expose a top surface of the first interlayer dielectric layer ILD1 formed on top surfaces of the first source / drain pattern SDP1 and the second source / drain pattern SDP2. The second interlayer dielectric layer ILD2 can be formed to extend along the second direction Y on a top surface of the cap pattern 107. The second interlayer dielectric layer ILD2 can include a dielectric material, such as a silicon oxide layer.

[0073] Referring to Figure 14A , Figure 14B and Figure 14C , an etching process can be performed such that the second interlayer dielectric layer ILD2 is used as an etching mask to etch the first interlayer dielectric layer ILD1. Accordingly, a contact recess region CRR can be formed to expose the top surfaces of the first source / drain pattern SDP1 and the second source / drain pattern SDP2 between the cap patterns 107. The etching process can use an etching recipe that has etching selectivity with respect to the cap pattern 107 and the spacers 103. For example, neither the cap pattern 107 nor the spacers 103 can be etched when etching the first interlayer dielectric layer ILD1. Accordingly, the contact recess region CRR can be formed when the first interlayer dielectric layer ILD1 is selectively removed from spaces between the cap patterns 107 adjacent to each other in the first direction X and between the spacers 103 adjacent to each other in the first direction X. A dry etching process can be employed as the etching process for forming the contact recess region CRR. For example, in the etching process, an upper portion of the first source / drain pattern SDP1 and the second source / drain pattern SDP2 can not be etched. As another example, in the etching process, an upper portion of the first source / drain pattern SDP1 and the second source / drain pattern SDP2 can be etched.

[0074] A first metal barrier layer 241 can be formed in the contact recess region CRR. For example, the first metal barrier layer 241 can conformally cover the top surfaces of the first source / drain pattern SDP1 and the second source / drain pattern SDP2 exposed to the contact recess region CRR, and can also conformally cover a top surface of the second interlayer dielectric layer ILD2 as well as a bottom surface and sidewalls of the contact recess region CRR. The first metal barrier layer 241 can be formed to be in contact with the top surfaces of the first source / drain pattern SDP1 and the second source / drain pattern SDP2. The first metal barrier layer 241 can include one or more of, for example, titanium (Ti) and titanium nitride (TiN).

[0075] Referring to Figure 15A , Figure 15B and Figure 15CThe sacrificial contact pattern 243 and the first preliminary barrier pattern 120a can be formed in the contact recessed region CRR. The formation of the sacrificial contact pattern 243 and the first preliminary barrier pattern 120a can include forming a sacrificial layer to fill the contact recessed region CRR and cover a top surface of the first metal barrier layer 241, forming a plurality of second mask patterns 245 on the sacrificial layer spaced apart from each other in the second direction Y, and performing an etching process in which the sacrificial layer and the first metal barrier layer 241 are etched using the second mask patterns 245 as etching masks. The etching process can also etch portions of the first interlayer dielectric layer ILD1 between the first preliminary barrier patterns 120a adjacent to each other in the second direction Y. The etching process can form separation openings SN between the first preliminary barrier patterns 120a adjacent to each other in the second direction Y and between the sacrificial contact patterns 243 adjacent to each other in the second direction Y. The separation openings SN can be formed between the first active region 100a and the second active region 100b of the substrate 100. For example, the separation openings SN can be formed in a gap between the first source / drain pattern SDP1 and the second source / drain pattern SDP2 in the second direction Y. The first preliminary barrier patterns 120a and the sacrificial contact patterns 243 can be formed on the first active region 100a and the second active region 100b of the substrate 100. The second mask patterns 245 can include a dielectric material (e.g., a silicon nitride layer). The sacrificial contact patterns 243 can include, for example, a spin-on hard mask (SOH) layer. The etching process can include an anisotropic etching process.

[0076] Referring to Figure 16 A separation dielectric pattern SP can be formed in the separation openings SN. The separation dielectric pattern SP can be formed by forming a separation dielectric layer to fill the separation openings SN and cover a top surface of the second mask patterns 245, and then performing an etching process on the separation dielectric layer until the top surface of the second mask patterns 245 is exposed. The separation dielectric pattern SP can be formed between the first active region 100a and the second active region 100b of the substrate 100. The separation dielectric pattern SP can be formed to have a top surface that is coplanar with the top surface of the second mask patterns 245. The separation dielectric pattern SP can include a dielectric material (e.g., a silicon oxide layer or a silicon nitride layer). The etching process for forming the separation dielectric pattern SP can be performed by employing chemical mechanical polishing, dry etching, or wet etching.

[0077] Referring to Figure 17A , Figure 17B and Figure 17CAn etch process can be performed to selectively remove the second mask pattern 245 and the sacrificial contact pattern 243. As a result, a top surface of the first preliminary barrier pattern 120a can be exposed, and sidewalls of the spacer dielectric pattern SP can be exposed inside the contact recess region CRR. The etch process can include a strip process. The etch process can be performed using an etch recipe that has etch selectivity with respect to the first preliminary barrier pattern 120a and the spacer dielectric pattern SP.

[0078] Referring back to Figure 18A , Figure 18B and Figure 18C A second metal barrier layer 250 can be conformally formed on the top surface of the first preliminary barrier pattern 120a and on the sidewalls and top surface of the spacer dielectric pattern SP. The second metal barrier layer 250 can cover the sidewalls and top surface of the spacer dielectric pattern SP. The second metal barrier layer 250 can include one or more of titanium (Ti) and titanium nitride (TiN). A metal layer 251 can be formed on the second metal barrier layer 250. The metal layer 251 can cover a top surface of the second metal barrier layer 250 and can fill the contact recess region CRR. The metal layer 251 can include at least one metallic material (e.g., tungsten (W), cobalt (Co), or ruthenium (Ru)).

[0079] Referring back to Figure 2A , Figure 2B and Figure 2CA polishing process can be performed on the metal layer 251, the second metal barrier layer 250, the first preliminary barrier pattern 120a, and the separation dielectric pattern SP. The polishing process can continue until a top surface of the second interlayer dielectric layer ILD2 is exposed. The first preliminary barrier pattern 120a, the second metal barrier layer 250, and the metal layer 251 formed on the top surface of the second interlayer dielectric layer ILD2 can be etched to form the first contact pattern CP1, the second contact pattern CP2, and the third contact pattern CP3 in the contact recessed region CRR. The first contact pattern CP1 and the second contact pattern CP2 can be spaced apart from each other in the second direction Y with the separation dielectric pattern SP therebetween and between the gate patterns GP adjacent to each other in the first direction X. The first contact pattern CP1 can be formed on the first source / drain pattern SDP1, and the second contact pattern CP2 can be formed on the second source / drain pattern SDP2. Each of the first contact pattern CP1 and the second contact pattern CP2 can include a first barrier pattern 120 formed by etching the first preliminary barrier pattern 120a, a second barrier pattern 122 formed by etching the second metal barrier layer 250, a metal pattern 124 formed by etching the metal layer 251, and an interface pattern 126 formed by a chemical bond between the first barrier pattern 120 and each of the first and second source / drain patterns SDP1 and SDP2. The interface pattern 126 can be formed between the first barrier pattern 120 and each of the first and second source / drain patterns SDP1 and SDP2.

[0080] The third contact pattern CP3 can be formed on the first source / drain pattern SDP1 and the second source / drain pattern SDP2 between the gate patterns GP adjacent to each other in the first direction X. The third contact pattern CP3 can be disposed spaced apart from the first contact pattern CP1 and the second contact pattern CP2 in the first direction X. The third contact pattern CP3 can include a first barrier pattern 130 formed by etching the first preliminary barrier pattern 120a, a second barrier pattern 132 formed by etching the second metal barrier layer 250, a metal pattern 134 formed by etching the metal layer 251, and an interface pattern 136 formed by a chemical bond between the first barrier pattern 130 and the first and second source / drain patterns SDP1 and SDP2.

[0081] According to an exemplary embodiment of the inventive concept, after formation of the separation dielectric pattern SP, which physically separates the first preliminary barrier pattern 120a on the first source / drain pattern SDP1 from the first preliminary barrier pattern 120a on the second source / drain pattern SDP2, a second metal barrier layer 250 can be formed on the first preliminary barrier pattern 120a, and then, the first barrier pattern 120 and the second barrier pattern 122 can be formed by performing a polishing process on the first preliminary barrier pattern 120a and the second metal barrier layer 250. Thus, it is not necessary to perform a lift-off process on the first ILD layer ILD1 and a stripping process on the barrier metal layer to form the first barrier pattern 120 and the second barrier pattern 122 on the first source / drain pattern SDP1 and the second source / drain pattern SDP2. As a result, formation of unnecessary layers (due to the lift-off and stripping processes) that increase the electrical resistance between the first barrier pattern 120 and the interface pattern 126 including the semiconductor material can be prevented.

[0082] Figure 19A and Figure 19B shows a cross-sectional view taken along the line I-I' of a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept. Figure 1

[0083] Referring to Figure 15A and Figure 19A , a horizontal expansion process can be performed on the separation openings SN. In other words, the size of the separation openings SN in the second direction Y can be increased. The horizontal expansion process can include an etching process of etching the sidewalls of the separation openings SN. The etching process can use the etching gas used to etch the sacrificial contact patterns 243. When etching portions of the sacrificial contact patterns 243, portions of the second mask pattern 245 can also be etched. The etching process can be an anisotropic etching process. During the horizontal expansion process, the first preliminary barrier patterns 120a can not be etched due to their etching selectivity to the etching gas. Thus, the separation openings SN can partially expose the top surfaces of the first preliminary barrier patterns 120a. The horizontal expansion process can be performed such that the distance between the sacrificial contact patterns 243 adjacent to each other in the second direction Y can be greater than the distance between the first preliminary barrier patterns 120a adjacent to each other in the second direction Y.

[0084] In an exemplary embodiment of the inventive concept, the horizontal expansion process can control the width of the first contact pattern CP1 and the second contact pattern CP2 to be formed later in the second direction Y. Thus, the capacitance between the first contact pattern CP1 and the second contact pattern CP2 can be adjusted.

[0085] Referring to Figure 19B ​A separation dielectric pattern SP can be formed in the separation opening SN. The separation dielectric pattern SP can fill the separation opening SN. The separation dielectric pattern SP can partially cover a top surface of the first preliminary barrier pattern 120a exposed to the separation opening SN.

[0086] The subsequent processes thereafter are the same as or substantially similar to the processes discussed with reference to Figure 17A 、 Figure 18A and Figure 2A the processes discussed with reference to the exemplary embodiments of the inventive concept, and thus repetitive descriptions are omitted for the sake of brevity.

[0087] According to the exemplary embodiments of the inventive concept, it is not necessary to perform a lift-off process on the barrier metal layer and to perform a stripping process on the interlayer dielectric layer to form the barrier pattern on the first source / drain pattern and the second source / drain pattern. Thus, it is possible to prevent formation of unnecessary layers, which can cause an increase in electrical resistance between the barrier pattern and the semiconductor-containing interface pattern, due to the stripping process and the lift-off process.

[0088] Although the inventive concept has been described with reference to the exemplary embodiments of the inventive concept, those skilled in the art will appreciate that various modifications and changes can be made thereto without departing from the scope of the inventive concept.

[0089] This application claims priority to Korean Patent Application No. 10-2019-0101855, filed on August 20, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

Claims

1. A semiconductor device, comprising: The substrate includes a first active region and a second active region; The first source / drain pattern is on the first active region; The second source / drain pattern is on the second active region; An interlayer dielectric layer is provided on the substrate and covers the first source / drain pattern and the second source / drain pattern. A separating dielectric pattern is formed on the substrate between the first source / drain pattern and the second source / drain pattern, and the separating dielectric pattern penetrates the interlayer dielectric layer. as well as The first contact pattern is on the first source / drain pattern. The first contact pattern includes: First metal pattern; A first barrier pattern is located between the first metal pattern and the first source / drain pattern; and The second blocking pattern is located between the first blocking pattern and the first source / drain pattern. The first blocking pattern contacts the separating dielectric pattern and extends along the sidewall of the first metal pattern adjacent to the separating dielectric pattern.

2. The semiconductor device according to claim 1, wherein... The first blocking pattern completely surrounds the first metal pattern, and The second blocking pattern exposes a portion of the first blocking pattern.

3. The semiconductor device of claim 1, further comprising a second contact pattern on the second source / drain pattern, The second contact pattern includes: Second metal pattern; A third barrier pattern is located between the second metal pattern and the second source / drain pattern; as well as A fourth blocking pattern is located between the third blocking pattern and the second source / drain pattern. The third blocking pattern contacts the separating dielectric pattern and extends along the sidewall of the second metal pattern adjacent to the separating dielectric pattern.

4. The semiconductor device of claim 3, wherein the distance between the second blocking pattern of the first contact pattern and the fourth blocking pattern of the second contact pattern is different from the distance between the first blocking pattern of the first contact pattern and the third blocking pattern of the second contact pattern.

5. The semiconductor device of claim 3, wherein the distance between the second blocking pattern of the first contact pattern and the fourth blocking pattern of the second contact pattern is the same as the distance between the first blocking pattern of the first contact pattern and the third blocking pattern of the second contact pattern.

6. The semiconductor device according to claim 1, wherein The second blocking pattern covers the top surface of the first source / drain pattern. The first blocking pattern covers the top surface of the second blocking pattern, and The first metal pattern covers the top surface of the first blocking pattern.

7. The semiconductor device of claim 1, wherein the top surface of the first metal pattern and the top surface of the first barrier pattern are coplanar with the top surface of the separating dielectric pattern.

8. The semiconductor device according to claim 1, wherein The first active region and the second active region are spaced apart from each other in a first direction. When viewed from above, the second blocking pattern includes: Multiple first segments are spaced apart from each other in a second direction that intersects the first direction; as well as The second segment connects the first ends of the first segments to each other and is parallel to the second direction. The second segment is spaced apart from the separating dielectric pattern, and The second end of the first segment is in contact with the separating dielectric pattern, and the second end is opposite to the first end.

9. The semiconductor device according to claim 1, The substrate further includes: The first active fin protrudes vertically from the top surface of the first active region; as well as The second active fin protrudes vertically from the top surface of the second active region, wherein The first active fin and the second active fin extend in a first direction. The first source / drain pattern is disposed on the first portion of the first active fin, and The second source / drain pattern is disposed on the first portion of the second active fin. The semiconductor device further includes: Multiple first active patterns are spaced apart from each other in the vertical direction on the top surface of the second portion of the first active fin; A plurality of second active patterns are spaced apart from each other in the vertical direction on the top surface of the second portion of the second active fin; and A gate pattern surrounds the first active pattern and the second active pattern, and extends in a second direction on the second portion of the first active fin and the second portion of the second active fin, the second direction intersecting the first direction.

10. A semiconductor device, comprising: The first active fin protrudes from the top surface of the substrate in the vertical direction; The first source / drain pattern is on the first active fin; An interlayer dielectric layer is placed on the substrate and covers the first source / drain pattern; The first contact pattern is located in the interlayer dielectric layer and contacts the first source / drain pattern. The first contact pattern includes: First metal pattern; A first barrier pattern is located between the first metal pattern and the first source / drain pattern; and A second blocking pattern is located between the first blocking pattern and the first metal pattern; and A separating dielectric pattern is formed on the substrate on one side of the first active fin, the separating dielectric pattern penetrating the interlayer dielectric layer. The second blocking pattern is arranged along the sidewall of the first metal pattern, and A portion of the second blocking pattern is exposed by the first blocking pattern.

11. The semiconductor device of claim 10, wherein the first blocking pattern covers at least one sidewall of the second blocking pattern.

12. The semiconductor device of claim 10, wherein the second blocking pattern is between the separating dielectric pattern and the first metal pattern.

13. The semiconductor device of claim 10, wherein the sidewalls of the second barrier pattern and the sidewalls of the first barrier pattern are in contact with the separating dielectric pattern. The sidewall of the first blocking pattern that contacts the separating dielectric pattern and the sidewall of the second blocking pattern that contacts the separating dielectric pattern are aligned with each other.

14. The semiconductor device of claim 10, wherein the sidewalls of the second barrier pattern and the sidewalls of the first barrier pattern are in contact with the separating dielectric pattern. The sidewall of the second blocking pattern that contacts the separating dielectric pattern and the sidewall of the first blocking pattern that contacts the separating dielectric pattern are not aligned with each other.

15. The semiconductor device of claim 10, further comprising: A second active fin protrudes from the top surface of the substrate in the vertical direction, and the second active fin is adjacent to the first active fin; A second source / drain pattern is formed on the second active fin and is covered by the interlayer dielectric layer. as well as The second contact pattern is located in the interlayer dielectric layer and contacts the second source / drain pattern. The second contact pattern includes: Second metal pattern; A third barrier pattern is located between the second metal pattern and the second source / drain pattern; and A fourth blocking pattern is located between the third blocking pattern and the second metal pattern. The distance between the first blocking pattern and the third blocking pattern is the same as the distance between the second blocking pattern and the fourth blocking pattern.

16. The semiconductor device of claim 10, further comprising: A second active fin protrudes from the top surface of the substrate in the vertical direction, and the second active fin is adjacent to the first active fin; A second source / drain pattern is formed on the second active fin and is covered by the interlayer dielectric layer. as well as The second contact pattern is located in the interlayer dielectric layer and contacts the second source / drain pattern. The second contact pattern includes: Second metal pattern; A third barrier pattern is located between the second metal pattern and the second source / drain pattern; and A fourth blocking pattern is located between the third blocking pattern and the second metal pattern. The distance between the first blocking pattern and the third blocking pattern is different from the distance between the second blocking pattern and the fourth blocking pattern.

17. A semiconductor device, comprising: Multiple active fins protrude from the top surface of the substrate and extend in a first direction, the active fins being adjacent to each other; A gate pattern extends across the active fin in a second direction, which intersects the first direction; A first source / drain pattern is on the active fin on a first side of the gate pattern; as well as The first contact pattern is on the first source / drain pattern. The first contact pattern includes: First metal pattern; as well as A first blocking pattern covers the first and second sidewalls of the first metal pattern. The first blocking pattern includes a first portion covering the first sidewall of the first metal pattern and a second portion covering the second sidewall of the first metal pattern. The first part comprises a single layer. The second part includes multiple layers, and The first sidewall and the second sidewall are parallel to the first direction.

18. The semiconductor device of claim 17, wherein the first blocking pattern comprises a third portion covering a third sidewall of the first metal pattern and a fourth portion covering a fourth sidewall of the first metal pattern. The third sidewall and the fourth sidewall are parallel to the second direction, and The third and fourth parts comprise multiple layers.

19. The semiconductor device of claim 17, further comprising: A second source / drain pattern is provided on the active fin on a second side of the gate pattern, the second side being opposite to the first side; as well as The second contact pattern is on the second source / drain pattern. The second contact pattern includes: Second metal pattern; as well as The second blocking pattern covers the first and second sidewalls of the second metal pattern. The first sidewall and the second sidewall of the second metal pattern are parallel to the first sidewall and the second sidewall of the first metal pattern. The second blocking pattern includes a third portion covering the first sidewall of the second metal pattern and a fourth portion covering the second sidewall of the second metal pattern. The third portion of the second blocking pattern comprises multiple layers, and The fourth part of the second blocking pattern comprises multiple layers.

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