Integrated assembly having vertically spaced channel material segments and method of forming the same

Abstract

The present application relates to an integrated assembly having vertically spaced channel material segments, and a method of forming the integrated assembly. The conductive level includes a control gate region and a second region proximate to the control gate region. A high-k dielectric structure is directly adjacent to the control gate region and extends completely across the insulating level. A charge blocking material is adjacent to the high-k dielectric structure. A charge storage material is adjacent to the charge blocking material. The charge storage material is configured as segments that are stacked vertically above and below each other and are vertically spaced apart from each other. A gate dielectric material is adjacent to the charge storage material. A channel material extends vertically along the stack and is adjacent to the gate dielectric material.

Description

Technical Field

[0001] Integrated assemblies (eg, integrated NAND memories) having vertically spaced channel material segments, and methods of forming the integrated assemblies. Background Art

[0002] Memory provides data storage for electronic systems. Flash memory is a type of memory and has many uses in modern computers and devices. For example, a modern personal computer may have a BIOS stored on a flash memory chip. As another example, it is increasingly common for computers and other devices to utilize flash memory in solid-state drives instead of conventional hard disk drives. As another example, flash memory is popular in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized and can provide the ability to remotely upgrade devices to enhance features.

[0003] NAND may be the basic architecture of flash memory, and may be configured to include vertically stacked memory cells.

[0004] Before describing NAND in detail, it may be helpful to more broadly describe the relationship of a memory array in an integrated arrangement. Figure 1A block diagram of a prior art device 1000 is shown that includes a memory array 1002 having a plurality of memory cells 1003 arranged in rows and columns and access lines 1004 (e.g., word lines to conduct signals WL0 to WLm) and first data lines 1006 (e.g., bit lines to conduct signals BL0 to BLn). Access lines 1004 and first data lines 1006 may be used to transfer information to and from memory cells 1003. Row decoders 1007 and column decoders 1008 decode address signals A0 to AX on address lines 1009 to determine which of the memory cells 1003 are to be accessed. Sense amplifier circuits 1015 operate to determine the value of information read from memory cells 1003. I / O circuits 1017 transfer the value of information between memory array 1002 and input / output (I / O) lines 1005. Signals DQ0 to DQN on I / O lines 1005 may represent the value of information read from or to be written to memory cells 1003. Other devices may communicate with device 1000 through I / O lines 1005, address lines 1009, or control lines 1020. Memory control unit 1018 is used to control memory operations to be performed on memory cells 1003 and utilizes signals on control lines 1020. Device 1000 may receive supply voltage signals Vcc and Vss on first power lines 1030 and second power lines 1032, respectively. Device 1000 includes selection circuit 1040 and input / output (I / O) circuit 1017. Selection circuit 1040 may respond to signals CSEL1 to CSELn via I / O circuit 1017 to select signals on first data lines 1006 and second data lines 1013, which may represent the value of information to be read from or programmed into memory cells 1003. Column decoder 1008 may selectively activate CSEL1 through CSELn signals based on A0 through AX address signals on address line 1009. Selection circuit 1040 may select signals on first and second data lines 1006, 1013 to provide communication between memory array 1002 and I / O circuit 1017 during read and program operations.

[0005] Figure 1 The memory array 1002 may be a NAND memory array, and Figure 2 Display can be used Figure 1Schematic diagram of a three-dimensional NAND memory device 200 of a memory array 1002 of FIG. The device 200 includes a plurality of strings of charge storage devices. In a first direction (ZZ′), each string of charge storage devices may include, for example, thirty-two charge storage devices stacked on top of each other, wherein each charge storage device corresponds to, for example, one of thirty-two layers (e.g., layer 0 to layer 31). The charge storage devices of the respective strings may share a common channel region, such as formed in one of respective semiconductor material (e.g., polysilicon) pillars around which the string of charge storage devices is formed. In a second direction (XX′), each first group of a plurality of strings, such as sixteen first groups, may include, for example, eight strings that share a plurality (e.g., thirty-two) access lines (i.e., “global control gate (CG) lines,” also referred to as word lines, WL). Each of the access lines may couple the charge storage devices within a layer. When each charge storage device includes a cell capable of storing two bits of information, the charge storage devices coupled by the same access line (and therefore corresponding to the same layer) may be logically grouped into, for example, two pages, such as P0 / P32, P1 / P33, P2 / P34, etc. In the third direction (YY′), for example, each second group of a plurality of strings of eight second groups may include sixteen strings coupled by corresponding ones of eight data lines. The size of the storage block may include 1,024 pages and a total of approximately 16 MB (e.g., 16 WLs×32 layers×2 bits=1,024 pages / block, block size=1,024 pages×16KB / page=16MB). The size of the strings, layers, access lines, data lines, first groups, second groups, and / or pages may be larger than Figure 2 Those shown in are larger or smaller.

[0006] Figure 3 exhibit Figure 2 A cross-sectional view of a memory block 300 of a 3D NAND memory device 200 in the XX′ direction, including Figure 2Fifteen charge storage device strings in one of the sixteen first group strings described. The multiple strings of the memory block 300 may be grouped into multiple subsets 310, 320, 330 (e.g., block columns), such as block column I, block column j, and block column K, where each subset (e.g., block column) includes a "partial block" of the memory block 300. A global drain-side select gate (SGD) line 340 may be coupled to the SGD of the multiple strings. For example, the global SGD line 340 may be coupled to a plurality of (e.g., three) sub-SGD lines 342, 344, 346 via a corresponding one of a plurality of (e.g., three) sub-SGD drivers 332, 334, 336, where each sub-SGD line corresponds to a respective subset (e.g., block column). Each of the sub-SGD drivers 332, 334, 336 may simultaneously couple or disconnect the SGD of the strings of the corresponding partial block (e.g., block column) independently of those of the other partial blocks. A global source side select gate (SGS) line 360 ​​may be coupled to the SGS of a plurality of strings. For example, the global SGS line 360 ​​may be coupled to a plurality of sub-SGD lines 362, 364, 366 via a corresponding one of a plurality of sub-SGS drivers 322, 324, 326, wherein each sub-SGS line corresponds to a corresponding subset (e.g., a block column). Each of the sub-SGS drivers 322, 324, 326 may simultaneously couple or cut off the SGS of the strings of the corresponding partial block (e.g., a block column) independently of those of the other partial blocks. A global access line (e.g., a global CG line) 350 may couple the charge storage devices of the corresponding layers of each of the plurality of strings. Each global CG line (e.g., a global CG line 350) may be coupled to a plurality of sub-access lines (e.g., sub-CG lines) 352, 354, 356 via a corresponding one of the plurality of sub-string drivers 312, 314, and 316. Each of the substring drivers may be coupled or disconnected simultaneously to the charge storage devices corresponding to the respective partial blocks and / or layers independently of those of the other partial blocks and / or other layers. The charge storage devices corresponding to the respective subsets (e.g., partial blocks) and respective layers may include a "partial layer" (e.g., a single "block") of charge storage devices. The strings corresponding to the respective subsets (e.g., partial blocks) may be coupled to a respective one of the sub-sources 372, 374, and 376 (e.g., a "block source"), each of which is coupled to a respective power supply.

[0007] refer to Figure 4 The schematic illustration of instead describes a NAND memory device 200 .

[0008] The memory array 200 includes word lines 202 1 To 202 N , and bit line 228 1 To 228 M .

[0009] The memory array 200 also includes NAND strings 206. 1 To 206 M Each NAND string includes a charge storage transistor 208 1 To 208 N The charge storage transistor may use a floating gate material (eg, polysilicon) to store charge, or may use a charge trapping material (eg, silicon nitride, metal nanodots, etc.) to store charge.

[0010] The charge storage transistor 208 is located at the intersection of the word line 202 and the string 206. The charge storage transistor 208 represents a non-volatile memory cell for storing data. The charge storage transistor 208 of each NAND string 206 is connected in series from source to drain between a source select device (e.g., source side select gate, SGS) 210 and a drain select device (e.g., drain side select gate, SGD) 212. Each source select device 210 is located at the intersection of the string 206 and the source select line 214, and each drain select device 212 is located at the intersection of the string 206 and the drain select line 215. The select devices 210 and 212 can be any suitable access devices, and are generally used. Figure 4 Description of the box in .

[0011] The source of each source selection device 210 is connected to the common source line 216. The drain of each source selection device 210 is connected to the source of the first charge storage transistor 208 of the corresponding NAND string 206. For example, the source selection device 210 1 The drain is connected to the corresponding NAND string 206 1 The charge storage transistor 208 1 The source selection device 210 is connected to the source selection line 214.

[0012] The drain of each drain select device 212 is connected to a bit line (ie, digit line) 228 at a drain contact. For example, the drain select device 212 1 The drain is connected to the bit line 228 1 The source of each drain select device 212 is connected to the drain of the last charge storage transistor 208 of the corresponding NAND string 206. For example, the drain select device 212 1 The source is connected to the corresponding NAND string 206 1 The charge storage transistor 208 N of the drain.

[0013] The charge storage transistor 208 includes a source 230, a drain 232, a charge storage region 234, and a control gate 236. The charge storage transistor 208 has its control gate 236 coupled to the word line 202. A column of charge storage transistors 208 are those transistors within the NAND string 206 that are coupled to a given bit line 228. A row of charge storage transistors 208 are those transistors that are coupled in common to a given word line 202.

[0014] It is desirable to develop improved NAND architectures and improved methods for making NAND architectures. Summary of the invention

[0015] One aspect of the present invention relates to an integrated structure comprising: a vertical stack of alternating insulating levels and conductive levels; the conductive levels having a terminal region and having a non-terminal region proximate the terminal region; a high-k dielectric material adjacent to the terminal region and extending vertically across the insulating levels; a charge blocking material adjacent to the terminal region; a charge storage material arranged into vertically stacked, spaced-apart segments adjacent to the charge blocking material; a gate dielectric material adjacent to the charge storage material; and a channel material adjacent to the gate dielectric material.

[0016] Another aspect of the present invention relates to a NAND memory array comprising: a vertical stack of alternating insulating levels and conductive levels; the conductive levels including a control gate region and a second region proximate the control gate region; a high-k dielectric structure directly against the control gate region and extending completely across the insulating levels; a charge blocking material adjacent to the high-k dielectric structure; a charge storage material adjacent to the charge blocking material; the charge storage material being configured into segments, the segments being vertically stacked one above the other and the segments being vertically spaced apart from each other; a gate dielectric material adjacent to the charge storage material; and a channel material extending vertically along the stack and adjacent to the gate dielectric material.

[0017] Another aspect of the present invention relates to a method of forming an integrated structure, the method comprising: forming a vertical stack of alternating first and second levels; the first level comprising a first material and the second level comprising a second material; forming an opening to extend through the stack; making the first level concave relative to the second level; the second level having a terminal extending beyond the concave first level; the terminal having a surface of the second material; the concave first level having a surface of the first material; the surfaces of the first and second materials forming a first wavy sidewall surface of the opening; forming a dielectric material along the wavy sidewall surface; the dielectric material wrapping around the terminal; the dielectric material having a first portion along the surface of the first material and having a second portion along the surface of the second material; the outer surface of the dielectric material being the second wavy sidewall surface of the opening; forming a third material adjacent to the dielectric material and along the second wavy sidewall surface ; the outer surface of the third material is the third wavy sidewall surface of the opening, the third wavy sidewall surface has a peak area along the second level and has a cavity along the first level; a fourth material is formed in the cavity; a charge storage material is selectively formed along the third material relative to the fourth material to form segments of the charge storage material along the peak area, such segments are vertically spaced apart from each other by gaps adjacent to the fourth material; a tunneling material is formed adjacent to the charge storage material; a channel material is formed adjacent to the tunneling material; the second material is removed to leave a gap; the third material is oxidized with an oxidant flowing into the gap, the oxidation forming a charge blocking material from the third material; and a conductive level is formed in the gap; the conductive level has a terminal area adjacent to the dielectric material and has a non-terminal area close to the terminal area; the dielectric material is adjacent to the terminal area and not adjacent to the non-terminal area. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A block diagram of a prior art memory device having a memory array with memory cells is shown.

[0019] Figure 2 Demonstrated as a 3D NAND memory device Figure 1 Schematic diagram of a prior art memory array.

[0020] Figure 3 exhibit Figure 2 FIG. 1 is a cross-sectional view of a prior art 3D NAND memory device along the XX′ direction.

[0021] Figure 4 FIG. 1 is a schematic diagram of a NAND memory array in the prior art.

[0022] Figure 5 and 6 is a diagrammatic cross-sectional side view of a region of an integrated assembly shown at an example sequential processing stage of an example method for forming an example NAND memory array.

[0023] Fig. 6A for Figure 6 A diagrammatic top view of a portion of an integrated assembly.

[0024] Figures 7 to 15 The example method for forming an example NAND memory array is shown at an example sequential processing stage. Figure 5 A diagrammatic cross-sectional side view of a region of an integrated assembly. Figure 7 The processing phase follows Figure 6 processing stage.

[0025] Fig.16 For the replacement Fig.15 The processing stage of the example processing stage is shown at Figure 5 A diagrammatic cross-sectional side view of a region of an integrated assembly.

[0026] Fig.17 For the replacement Fig.15 Another example of a processing stage of the processing stage shown at Figure 5 A diagrammatic cross-sectional side view of a region of an integrated assembly.

[0027] Figures 18 to 20 is a diagrammatic cross-sectional side view of a region of an integrated assembly shown at an example sequential processing stage of an example method for forming an example NAND memory array. Fig.18 The processing stage can be followed by Fig.13 processing stage.

[0028] Fig.21 For the replacement Fig. 20 The processing stage of the example processing stage is shown at Fig.18 A diagrammatic cross-sectional side view of a region of an integrated assembly. DETAILED DESCRIPTION

[0029] The operation of a NAND memory cell includes the movement of charge between a channel material and a charge storage material. For example, programming a NAND memory cell may include moving charge (i.e., electrons) from the channel material into the charge storage material, and then storing the charge in the charge storage material. Erasing a NAND memory cell may include moving holes into the charge storage material to recombine with the electrons stored in the charge storage material, and thereby releasing charge from the charge storage material. The charge storage material may include a charge trapping material (e.g., silicon nitride, metal dots, etc.). A problem with conventional NAND may be that the charge trapping material extends across multiple memory cells of a memory array, and this may cause charge to migrate from one memory cell to another. Charge migration may cause data retention issues. Some embodiments include a NAND architecture having breaks in the charge trapping material in the area between memory cells. And such breaks may advantageously hinder charge migration between memory cells. Reference Figures 5 to 21 To describe example embodiments.

[0030] refer to Figure 5 , a construction (integrated assembly, integrated structure) 10 includes a vertical stack 12 of alternating first levels 14 and second levels 16. The first level 14 includes a first material 60, and the second level 16 includes a second material 62. The first material and the second material may include any suitable composition, and have different compositions relative to each other. In some embodiments, the first material 60 may include, consist essentially of, or consist of silicon dioxide; and the second material 62 may include, consist essentially of, or consist of silicon nitride. Levels 14 and 16 may be of any suitable thickness; and may be the same thickness as each other, or different thicknesses relative to each other. In some embodiments, levels 14 and 16 may have a vertical thickness in a range from about 10 nanometers (nm) to about 400 nm. In some embodiments, levels 14 and 16 may have a thickness in a range from about 10 nm to about 50 nm.

[0031] Stack 12 is shown supported above pedestal 18. Pedestal 18 may include semiconductor material; and, for example, may include, consist essentially of, or consist of single crystal silicon. Pedestal 18 may be referred to as a semiconductor substrate. The term "semiconductor substrate" refers to any structure including semiconductor material, including but not limited to bulk semiconductor material, such as semiconductor wafers (alone or in an assembly including other materials) and layers of semiconductor material (alone or in an assembly including other materials). The term "substrate" refers to any supporting structure, including but not limited to the semiconductor substrates described above. In some applications, pedestal 18 may correspond to a semiconductor substrate containing one or more materials associated with integrated circuit manufacturing. Such materials may include, for example, one or more of refractory metal materials, barrier materials, diffusion materials, insulator materials, etc.

[0032] A gap is provided between the stack 12 and the base 18 to indicate that other components and materials may be provided between the stack 12 and the base 18. Such other components and materials may include additional levels of the stack, source line levels, source side select gates (SGS), and the like.

[0033] refer to Figure 6 , forming an opening 64 to extend through the stack 12. The opening 64 has a sidewall 65 extending along the first material 60 and the second material 62. When viewed from above (such as in Fig. 6A ), the opening 64 may have a closed shape (circular, elliptical, polygonal, etc.), and Figure 6 The side wall 65 shown in the cross section of FIG. 64 may be part of a single continuous side wall that extends around the closed shape of the opening 64 (as in FIG. Fig. 6A ). The opening 64 may be shown in Figure 6 A plurality of substantially identical openings formed during a processing stage of and used to fabricate NAND memory cells of a NAND memory array. The term "substantially identical" means identical within reasonable fabrication and measurement tolerances.

[0034] refer to Figure 7 , the first level 14 is recessed relative to the second level 16 along the sidewalls 65 of the opening 64. After the recess, the second level 16 has a protruding terminal end 66 that extends beyond the recessed first level 14. The terminal end 66 has a surface 67 of the second material 62. The recessed first level 14 has a surface 69 of the first material 60. The cavity (gap) 68 is vertical between the terminal ends 66. The surface 69 can be considered to be along the inner edge of the cavity 68.

[0035] exist Figure 7 At the processing stage , surfaces 67 and 69 together form a wavy sidewall surface 65 of opening 64 . Figure 7 The wavy sidewall surface 65 may be referred to as a first wavy sidewall surface.

[0036] refer to Figure 8, a dielectric material 70 is formed along the wavy sidewall surface 65. The dielectric material 70 may include any suitable composition. In some embodiments, the dielectric material 70 may include silicon dioxide. In some embodiments, the dielectric material 70 may be a high-k dielectric material. The term "high-k" refers to a dielectric constant that is greater than the dielectric constant of silicon dioxide. In some embodiments, dielectric material 70 may be a high-k dielectric material that includes, consists essentially of, or consists of one or more of aluminum oxide (AlO), hafnium oxide (HfO), hafnium silicate (HfSiO), zirconium oxide (ZrO), and zirconium silicate (ZrSiO); wherein the chemical formula indicates the major components rather than a specific stoichiometry.

[0037] The dielectric material 70 has a substantially uniform thickness along the entire wavy sidewall 65; wherein the term "substantially uniform" means uniform within reasonable manufacturing and measurement tolerances. The dielectric material 70 can be formed to any suitable thickness; and in some embodiments, can be formed to a thickness in the range of about 1 nanometer (nm) to about 6 nm.

[0038] The dielectric material 70 wraps around the terminal ends 66. In the illustrated embodiment, the terminal ends 66 have generally upper corners, and the dielectric material 70 extends around such generally upper corners. In other embodiments, the corners may be more rounded.

[0039] The dielectric material 70 can be considered to have a first portion 72 along the first material 60 (i.e., along the surface 69), and a second portion 74 along the second material 62 (i.e., along the surface 67). The second portion 74 has generally horizontal sections 73 along the upper and lower surfaces of the terminal 66, and has generally vertical sections 75 along the front surface (i.e., the sidewall surface) of the terminal 66. The generally vertical sections 75 extend between the generally horizontal sections 73. The term "generally vertical" means vertical within reasonable manufacturing and measurement tolerances; and the term "generally horizontal" means horizontal within reasonable manufacturing and measurement tolerances.

[0040] The dielectric material 70 has an outer surface 71 having a wavy topography. The outer surface 71 of the dielectric material 70 can be considered as a second wavy sidewall surface of the opening 64 , wherein such second wavy sidewall surface is formed above the first wavy sidewall surface 65 .

[0041] refer to Fig. 9, material 74 is formed adjacent to dielectric material 70 and along second non-concave surface 71. Material 74 may be referred to as a third material to distinguish it from first material 60 and second material 62. Third material 74 has a wavy topography, which may be considered a third wavy sidewall surface 77 of opening 64. The third wavy sidewall surface has a peak region 78 along second level 16, and has a valley region (or cavity) 76 along first level 14.

[0042] Dielectric material 74 may include any suitable composition. For example, in some embodiments, the third material may include, consist essentially of, or consist of silicon nitride or silicon (eg, polysilicon).

[0043] refer to Fig.10 , forming material 80 within cavity 76. Material 80 may be referred to as a fourth material to distinguish it from first material 60, second material 62, and third material 74. The fourth material may include any suitable composition; and in some embodiments, may include, consist essentially of, or consist of silicon dioxide.

[0044] refer to Fig.11 , the charge storage material 38 is selectively formed along the third material 74 relative to the fourth material 80. Thus, the charge storage material 38 is formed in vertically stacked segments 40. The segments 40 are along the peak regions 78 of the surface 77. The segments 40 are vertically spaced apart from each other by gaps 82 adjacent to the fourth material 80.

[0045] Charge storage material 38 may include any suitable composition. In some embodiments, charge storage material 38 may include a charge trapping material; for example, silicon nitride, silicon oxynitride, conductive nanodots, etc. For example, in some embodiments, charge storage material 38 may include, consist essentially of, or consist of silicon nitride. In alternative embodiments, charge storage material 38 may be configured to include a floating gate material (e.g., polysilicon).

[0046] exist Fig.11 In the illustrated embodiment of the present invention, each section 40 of charge storage material 38 has a flat configuration (or substantially flat configuration). The term "flat configuration" means that the material 38 of the section 40 has a substantially continuous thickness and extends substantially vertically straight as opposed to wavy. The term "substantially flat" means flat within reasonable manufacturing and measurement tolerances.

[0047] The charge storage material 38 may be selectively formed along the third material 74 relative to the fourth material 80 using any suitable process. In some embodiments, a blocking material (also referred to herein as an inhibiting material) may be selectively formed along the fourth material 80 relative to the third material 74 to prevent subsequent formation of the charge storage material 38 along the surface of the fourth material 80, and then the charge storage material 38 may be formed by a suitable deposition process (e.g., atomic layer deposition, chemical vapor deposition, etc.). The blocking material may include any suitable composition; and in some embodiments may include N,N-dimethylaminotrimethylsilane, bis(N,N-dimethylamino)dimethylsilane, ethylenediamine, 1-trimethylsilylpyrrolidine, 1-trimethylsilylpyrrole, 3,5-dimethyl-1-trimethylsilyl, and R1-(C-OH)-R2; wherein R1 and R2 are organic moieties.

[0048] refer to Fig.12 , a tunneling material (ie, gate dielectric material, charge passing material) 42 is formed adjacent to the charge storage material 38, a channel material 44 is formed adjacent to the tunneling material, and an insulating material 46 is formed adjacent to the channel material.

[0049] Tunneling material 42 may include any suitable composition. In some embodiments, tunneling material 42 may include, for example, one or more of silicon dioxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, etc. Tunneling material 42 may be bandgap engineered to achieve desired electrical properties; and thus may include a combination of two or more different materials.

[0050] Channel material 44 includes a semiconductor material; and may include any suitable composition or combination of compositions. For example, channel material 44 may include one or more of silicon, germanium, a III / V semiconductor material (e.g., gallium phosphide), a semiconductor oxide, etc.; wherein the term III / V semiconductor material refers to a semiconductor material including elements selected from Groups III and V of the periodic table (wherein Groups III and V are old terms and are now referred to as Groups 13 and 15). In some embodiments, semiconductor material 44 may include, consist essentially of, or consist of silicon.

[0051] Insulating material 46 may comprise any suitable composition; and in some embodiments, may comprise, consist essentially of, or consist of silicon dioxide.

[0052] exist Fig.12 In the illustrated embodiment of , the channel material 44 is configured as an annular ring surrounding the insulating material 46. This configuration of the channel material may be considered to include a hollow channel configuration because, in the annular shaped channel configuration, the insulating material 46 is disposed within the “hollow.” In other embodiments (not shown), the channel material may be configured as a solid columnar configuration.

[0053] refer to Fig.13 , the second material 62( Fig.12 ) is removed to leave void 84. Void 84 may be referred to as a first void to distinguish it from other voids formed in subsequent process stages.

[0054] refer to Fig.14 , the third material 74( Fig.13 ) is oxidized to convert the third material into the charge blocking material 34. The oxidation of the third material 74 may utilize an oxidant 86 flowing into the gap 84. The oxidant 86 may include, for example, oxygen, ozone, and the like.

[0055] The charge blocking material 34 may include any suitable composition. For example, if the third material 74 ( Fig.13 ) includes silicon nitride, then charge blocking material 34 may include, consist essentially of, or consist of silicon oxynitride. As another example, if third material 74 ( Fig.13 ) includes silicon (e.g., polysilicon), then charge blocking material 34 may include, consist essentially of, or consist of silicon dioxide.

[0056] refer to Fig.15 , in the first gap 84 ( Fig.14 ) to line the first gap, and then form the conductive region 22 in the lined gap.

[0057] High-k dielectric material 28 may include, consist essentially of, or consist of one or more of aluminum oxide, hafnium oxide, hafnium silicate, zirconium oxide, and zirconium silicate. In some embodiments, both materials 70 and 28 may be high-k dielectric materials. In such embodiments, materials 70 and 28 may include the same composition as one another, or may include different compositions relative to one another. If both materials 70 and 28 include high-k dielectric materials, one of the materials may be referred to as a first high-k dielectric material and the other material may be referred to as a second high-k dielectric material in order to distinguish materials 70 and 28 from one another.

[0058] High-k dielectric material 28 has a substantially uniform thickness ( Fig.14 ). High-k dielectric material 28 may be formed to any suitable thickness; and in some embodiments, may be formed to a thickness in a range of approximately 1 nm to approximately 5 nm.

[0059] Conductive region 22 may include two or more conductive materials; and in the illustrated embodiment includes a pair of conductive materials 24 and 26. Conductive materials 24 and 26 may include any suitable conductive composition; for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.). Conductive materials 24 and 26 differ from one another in composition. In some embodiments, core material 24 may include one or more metals (e.g., may include tungsten), and outer conductive material 26 may include one or more metal nitrides (e.g., may include titanium nitride).

[0060] In the illustrated embodiment, high-k dielectric material 28 is directly against conductive material 26 .

[0061] Level 16 Fig.15 The processing stage of can be considered as a conductive level (or word line level), where the conductive level 16 includes the conductive region 22. In some embodiments, Fig.15 The configuration of may be considered as a vertical stack 12 having alternating conductive levels (NAND word line levels) 16 and insulating levels 14.

[0062] Conductive region 22 has terminal region 88 and non-terminal region 90 adjacent to the terminal region. Terminal region 88 is between non-terminal region 90 and dielectric material 70. In some embodiments, dielectric material 70 can be considered to be adjacent to terminal region 88 and not adjacent to non-terminal region 90.

[0063] The conductive region 22 of the word line level 16 includes a control gate region 92 within the terminal region 88 and includes a second region (word line region) 94 proximate to the control gate region 92 .

[0064] In some embodiments, material 70 may be a high-k dielectric material that is adjacent to terminal region 88 and that extends vertically across insulating level 14. In some embodiments, materials 28 and 70 may be considered together and incorporated into a high-k dielectric structure 96, where such a structure is directly against control gate region 92 and extends across insulating level 14. If materials 28 and 70 are identical to one another, high-k dielectric material structure 96 will include a single homogeneous high-k material 28 / 70. If materials 28 and 70 are different compositions relative to one another, high-k dielectric material structure 96 will include a laminated region (portion) 98 along terminal region 88 of conductive level 16, and will include a non-laminated region (portion) 100 along insulating level 14. In the illustrated embodiment, laminated region 98 includes a laminate of two high-k dielectric materials 28 and 70. In other embodiments, the laminate may include more than two high-k dielectric materials (e.g., material 70 may include two or more materials rather than the single material illustrated). As shown, the thicknesses of the high-k dielectric materials of the laminate may be approximately the same as one another (where the term "approximately the same" means the same within reasonable fabrication and measurement tolerances); or may include different thicknesses relative to one another.

[0065] Control gate region 92 may be considered to include terminals 93 within conductive level 16. Each terminal 93 has a top surface 83, a bottom surface 85, and sidewall surfaces (or front surfaces) 87 extending between the top and bottom surfaces. Fig.15 In the illustrated embodiment of , laminated portion 98 of high-k dielectric structure 96 wraps around control gate region 92 ; and specifically, along top and bottom surfaces 83 , 85 of terminal 93 , and along front surface 87 of terminal 93 .

[0066] exist Figure 1 5, high-k dielectric structure 96 can be considered to have a portion 98 along control gate region 92 of conductive level 16, and have another portion 102 along second region 94 of conductive level 16. In some embodiments, portions 98, 100, and 102 of high-k dielectric structure 96 can be considered to be first, second, and third portions of such high-k dielectric structure. First portion 98 includes a laminate of materials 28 and 70, second portion 100 includes only material 70, and third portion 102 includes only material 28. Thus, first portion 98 is thicker than second portion 100 and third portion 102. In some embodiments, first portion 98 can be at least approximately twice as thick as second portion 100 and third portion 102.

[0067] exist Fig.15In the illustrated embodiment, the high-k dielectric structure 96 can be considered to be directly contacting the terminal region 88 of two vertically adjacent conductive levels (e.g., conductive levels labeled 16a and 16b) to each other, and extending completely across an insulating level (e.g., insulating level labeled 14a) between the vertically adjacent conductive levels.

[0068] The NAND memory cell 52 includes a dielectric barrier material 28 / 70, a charge blocking material 34, a charge storage material 38, a gate dielectric material 42, and a channel material 44. The illustrated NAND memory cell 52 forms part of a vertically extending string of memory cells. Such a string may represent a large number of substantially identical NAND strings (where the term "substantially identical" means identical within reasonable manufacturing and measurement tolerances) formed during the fabrication of a NAND memory array.

[0069] The charge storage material 38 within the memory cell 52 is configured as segments 40 that are vertically stacked one above the other and that are vertically spaced apart from one another. The tunneling material 42 and the channel material 44 are configured as layers that extend vertically along (through) the stack 12 .

[0070] Each NAND memory cell 52 includes a control gate region 92 within the conductive level 16. The control gate region 92 includes a gate region similar to that described above with reference to Figures 1 to 4 The control gates are those described above.

[0071] In some embodiments, high-k dielectric material 28 may be omitted. Alternatively, material 70 may be the only high-k dielectric material within NAND memory cell 52. Examples of such embodiments are described in Fig.16 As shown in FIG. 10a, it is obvious that Fig.16 In the embodiment of the present invention, there is no high-k dielectric material extending along the non-terminal region 90 of the conductive level 16 (i.e., the high-k dielectric material does not extend along the second region 94 of the word line level 16), and the high-k dielectric structure 96 includes a single homogenous composition having a uniform thickness along the levels 16 and 14 (i.e., there is no high-k dielectric material extending along the non-terminal region 90 of the conductive level 16). Fig.15 of the laminated portion 98). Fig.16 The high-k dielectric material 70 of the assembly 10a directly contacts the conductive material 26 of the vertically adjacent wordline levels 16a and 16b and extends completely across the insulating level 14a between the vertically adjacent wordline levels 16a and 16b.

[0072] exist Fig.15 and 16 In the embodiment of FIG. 8 , the charge blocking material 34 wraps around the terminal region 88 of the conductive level 16 and does not extend along the non-terminal region 90 . The charge blocking material 34 extends vertically across the insulating level 14 .

[0073] exist Fig.15 and 16 In the embodiment of the present invention, the insulating level 14 is completely filled with insulating materials 60, 70 and 80 in the vertical regions between the conductive materials of the level 16. In other embodiments, gaps may be formed within the insulating level 14. For example, Fig.17 Shows something like Fig.15 10b, but in which at least some of the insulating material 60 is replaced by voids 104. Voids 104 are covered by insulating material 106. Voids 104 may be filled with air or any other suitable gas. Insulating material 106 may include any suitable composition; and in some embodiments, may include, consist essentially of, or consist of silicon dioxide. Voids 104 may be referred to as second voids to distinguish them from the second voids described above with reference to FIG. Fig.13 The depicted first gap 84 is distinguished.

[0074] Fig.17 An advantage of a configuration of (ie a configuration having a gap within the insulating level 14) is that this can mitigate capacitive coupling between vertically adjacent materials in situations where such capacitive coupling is found to be problematic.

[0075] In embodiments where material 70 comprises a high-k dielectric material, it may be difficult to Fig.14 The third material 74 is oxidized at a processing stage with an oxidant flowing into the void 84. In such embodiments, it may be advantageous to remove some of the material 70 before flowing the oxidant into the void. Fig.18 Display available at Fig.13 Assembly 10 c at a later processing stage. A section of material 70 has been removed from the end of void 84 .

[0076] refer to Fig.19 , shown in a similar Fig.14 The oxidant 86 flows into the gap 84 and is used to convert the third material 74 ( Fig.18 ) is converted to charge blocking material 34 along second level 16. Although all of the third material is shown as being converted to charge blocking material, it should be understood that in some embodiments, only a portion of the third material may be converted to charge blocking material (e.g., after converting the third material to charge blocking material 34 along second level 16, there may still be some portion of the third material remaining along first level 14).

[0077] refer to Fig. 20 , in the gap 84( Fig.19 ) forms a conductive region 22. Fig. 20The assembly 10c has a second high-k dielectric material 28 extending along the top surface 83, the bottom surface 85, and the sidewall surface 87 of the terminal region 88 of the conductive level 16; and has a first high-k dielectric material 70 only along the top surface 83 and the bottom surface 87 of the terminal region 88. In addition, the second dielectric material 28 extends along the non-terminal region 90 of the conductive level 16, while the first dielectric material 70 does not extend along such non-terminal region. In some embodiments, Fig. 20 The configuration is considered to include a stacked high-k structure 108 along the top surface 83 and the bottom surface 85 of the terminal region 88 (wherein the laminate includes a first high-k dielectric material 70 and a second high-k dielectric material 28), and includes a non-laminated high-k structure 110 along the sidewall surface (front surface) 87 of the terminal region 88, and such non-laminated high-k structure includes the high-k dielectric material 28.

[0078] In some embodiments, Fig. 20 At least some of the insulating material 60 may be replaced by voids. For example, Fig.21 Shows something like Fig. 20 The assembly 10c of FIG. 1 is an assembly 10d of FIG. 1 , but some of the insulating material 60 has been replaced by voids 104, and wherein such voids are covered by insulating material 106. The voids 104 and insulating material 106 may be similar to those described above with reference to FIG. Fig.17 The void 104 and the insulating material 106 are depicted.

[0079] In operation, the charge storage material 38 can be configured to store information in the memory cells 52 of the various embodiments described herein. The value of the information stored in a single memory cell (where the term "value" refers to one or more bits) can be based on the amount of charge (e.g., the number of electrons) stored in the charge storage region of the memory cell. The amount of charge in a single charge storage region can be controlled (e.g., increased or decreased) based at least in part on the value of the voltage applied to the associated gate 92 and / or based on the value of the voltage applied to the channel material 44.

[0080] Tunneling material 42 forms a tunneling region of memory cell 52. Such tunneling region may be configured to allow for the desired migration (e.g., transport) of charge (e.g., electrons) between charge storage material 38 and channel material 44. Tunneling region may be configured (i.e., engineered) to achieve selected criteria such as, but not limited to, equivalent oxide thickness (EOT). EOT quantifies the electrical properties (e.g., capacitance) of the tunneling region in terms of a representative physical thickness. For example, EOT may be defined as the thickness of a theoretical silicon dioxide layer that would be required to have the same capacitance density as a given dielectric, while neglecting leakage current and reliability considerations.

[0081] The charge blocking material 34 adjacent to the charge storage material 38 may provide a mechanism to prevent charge from flowing from the charge storage material 38 to the associated gate 92 .

[0082] Backward tunneling of charge carriers from gate 92 toward charge storage material 38 may be inhibited by dielectric barrier material (high-k material) 28, 70, or 28 / 70 disposed between charge blocking material 34 and associated gate 92. In some embodiments, dielectric barrier material 28, 70, or 28 / 70 may be considered to form a dielectric barrier region within memory cell 52.

[0083] The assemblies and structures discussed above may be used within integrated circuits (where the term "integrated circuit" refers to an electronic circuit supported by a semiconductor substrate); and may be incorporated into electronic systems. Such electronic systems may be used, for example, in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multi-layer multi-chip modules. The electronic system may be any of a wide range of systems, such as cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0084] Unless otherwise specified, the various materials, substances, compositions, etc. described herein may be formed by any suitable method now known or yet to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0085] The terms "dielectric" and "insulating" may be used to describe materials with insulating electrical properties. The terms are considered synonymous in this disclosure. The use of the term "dielectric" in some cases and the term "insulating" (or "electrically insulating") in other cases may be used to provide language changes within the present disclosure to simplify the premise basis in the subsequent claims and is not intended to indicate any significant chemical or electrical differences.

[0086] The terms "electrically connected" and "electrically coupled" may both be used in the present invention. The terms are considered synonymous. The use of one term in certain circumstances and another term in other circumstances may provide language variation in the context of the present invention to simplify the premise basis in the appended claims.

[0087] The specific orientations of the various embodiments in the drawings are for illustration purposes only, and in some applications, the embodiments may be rotated relative to the orientation shown. The description provided herein and the claims that follow are directed to any structure having the described relationships between the various features, regardless of whether the structure is in a specific orientation in the drawings or rotated relative to such orientation.

[0088] To simplify the drawings, the cross-sectional views of the accompanying illustrations show only features within the plane of the cross-section and do not show material behind the plane of the cross-section unless otherwise indicated.

[0089] When a structure is referred to above as being "on," "adjacent," or "against" another structure, it may be directly on the other structure, or intervening structures may also be present. Conversely, when a structure is referred to as being "directly on," "directly adjacent," or "directly against" another structure, there are no intervening structures. The terms "directly below," "directly over," and the like do not indicate direct physical contact (unless expressly stated otherwise), but rather indicate upright alignment.

[0090] Structures (eg, layers, materials, etc.) may be referred to as "vertically extending" to indicate that the structures extend generally upward from an underlying base (eg, substrate). Vertically extending structures may extend substantially perpendicularly relative to an upper surface of the base, or may not extend at all.

[0091] Some embodiments include an integrated structure having a vertical stack of alternating insulating levels and conductive levels. The conductive levels have a terminal region and have a non-terminal region proximate the terminal region. A high-k dielectric material is adjacent to the terminal region and extends vertically across the insulating levels. A charge blocking material is adjacent to the terminal region. A charge storage material is arranged in a vertical stack of spaced-apart segments. The segments are adjacent to the charge blocking material. A gate dielectric material is adjacent to the charge storage material. A channel material is adjacent to the gate dielectric material.

[0092] Some embodiments include a vertically stacked NAND memory array having alternating insulating levels and conductive levels. The conductive levels include a control gate region and a second region proximate the control gate region. A high-k dielectric structure is directly adjacent to the control gate region and extends completely across the insulating levels. A charge blocking material is adjacent to the high-k dielectric structure. A charge storage material is adjacent to the charge blocking material. The charge storage material is configured as segments that are stacked vertically above and below each other and are vertically spaced apart from each other. A gate dielectric material is adjacent to the charge storage material. A channel material extends vertically along the stack and is adjacent to the gate dielectric material.

[0093] Some embodiments include a method of forming an integrated structure. A vertical stack of alternating first and second levels is formed. The first level includes a first material and the second level includes a second material. An opening is formed to extend through the stack. The first level is recessed relative to the second level. The second level has a terminal that extends beyond the recessed first level. The terminal has a surface of the second material. The recessed first level has a surface of the first material. The surfaces of the first material and the second material form a first wavy sidewall surface of the opening. A dielectric material is formed along the wavy sidewall surface. The dielectric material wraps around the terminal. The dielectric material has a first portion along the surface of the first material and has a second portion along the surface of the second material. An outer surface of the dielectric material is a second wavy sidewall surface of the opening. A third material is formed adjacent to the dielectric material and along the second wavy sidewall surface. An outer surface of the third material is a third wavy sidewall surface of the opening. The third wavy sidewall surface has a peak region along the second level and has a cavity along the first level. A fourth material is formed within the cavity. A charge storage material is selectively formed along the third material relative to the fourth material to form a segment of the charge storage material along the peak region. The segments are vertically spaced apart from each other by gaps adjacent to the fourth material. A tunneling material is formed adjacent to the charge storage material. A channel material is formed adjacent to the tunneling material. The second material is removed to leave a void. The third material is oxidized with an oxidant flowing into the void. The oxidation forms a charge blocking material from the third material. A conductive level is formed within the void. The conductive level has a terminal region adjacent to the dielectric material and has a non-terminal region proximate to the terminal region. The dielectric material is adjacent to the terminal region and not adjacent to the non-terminal region.

[0094] In compliance with the statute, the subject matter disclosed herein has been described in language more or less specific with respect to structural and methodological features. However, it is to be understood that since the methods disclosed herein include example embodiments, the claims are not limited to the specific features shown and described. Therefore, the claims are to be given the full scope by the literal wording and appropriately interpreted in accordance with the doctrine of equivalents.

Claims

1. An integrated structure, wherein include: Vertical stacking of alternating insulating and conducting layers; The conductive layer has a terminal area and a non-terminal area close to the terminal area; a high-k dielectric material adjacent to the terminal region and extending vertically across the insulating level; a charge blocking material adjacent to the terminal region; a charge storage material arranged in vertically stacked spaced-apart segments; the segments being adjacent to the charge blocking material and laterally spaced from the conductive level, a portion of the segments extending through the conductive level to be laterally spaced from the insulating level; a gate dielectric material adjacent to the charge storage material; a channel material adjacent to the gate dielectric material; and The high-k dielectric material directly contacts terminal regions of two of the conductive levels that are vertically adjacent to each other and extends completely across one of the insulating levels between the vertically adjacent conductive levels.

2. The integrated structure of claim 1, wherein the high-k dielectric material comprises one or more of aluminum oxide, hafnium oxide, hafnium silicate, zirconium oxide, and zirconium silicate.

3. An integrated structure according to claim 1, wherein the high-k dielectric material is adjacent to the terminal area and not along the non-terminal area; wherein the terminal area has a top surface and a bottom surface, and has a vertically extending sidewall surface between the top surface and the bottom surface; wherein the high-k dielectric material extends along the top surface and the bottom surface of the terminal area but not along the sidewall surface of the terminal area; and wherein the high-k dielectric material is a first high-k dielectric material; and the integrated structure further includes a second high-k dielectric material between the first high-k dielectric material and the conductive level; the second high-k dielectric material wraps around the terminal area and extends along the non-terminal area; the second high-k dielectric material has a different composition from the first high-k dielectric material.

4. The integrated structure of claim 3, wherein the second high-k dielectric material comprises one or more of aluminum oxide, hafnium oxide, hafnium silicate, zirconium oxide, and zirconium silicate.

5. The integrated structure of claim 3, wherein the charge blocking material wraps around the terminal region of the conductive level and does not extend along the non-terminal region; and wherein the charge blocking material extends vertically across the insulating level.

6. The integrated structure of claim 1, wherein the high-k dielectric material wraps around the terminal region; wherein The terminal region has a top surface and a bottom surface, and has a vertically extending sidewall surface between the top surface and the bottom surface; wherein the high-k dielectric material extends along the top surface, the bottom surface and the sidewall surface of the terminal region; and is a first high-k dielectric material; wherein the first high-k dielectric material is not along the non-terminal region; and the integrated structure further includes a second high-k dielectric material between the first high-k dielectric material and the conductive layer; the second high-k dielectric material wraps around the terminal region and extends along the non-terminal region; the second high-k dielectric material has a different composition from the first high-k dielectric material.

7. The integrated structure of claim 6, wherein the first high-k dielectric material and the second high-k dielectric material are approximately the same thickness as each other.

8. The integrated structure of claim 6, wherein the charge blocking material wraps around the terminal region of the conductive level and does not extend along the non-terminal region; and wherein the charge blocking material extends vertically across the insulating level.

9. The integrated structure of claim 1, wherein the high-k dielectric material wraps around the terminal region; wherein The terminal region has a top surface and a bottom surface, and a vertically extending sidewall surface between the top surface and the bottom surface; and wherein the high-k dielectric material extends along the top surface, the bottom surface and the sidewall surface of the terminal region, and does not extend along the non-terminal region.

10. A NAND memory array, wherein include: Vertical stacking of alternating insulating and conducting layers; The conductive level includes a control gate region and a second region proximate to the control gate region; a high-k dielectric structure directly contacting the control gate region of two of the conductive levels vertically adjacent to each other and extending completely across one of the insulating levels between the vertically adjacent conductive levels; a charge blocking material adjacent to the high-k dielectric structure; a charge storage material adjacent to the charge blocking material and laterally spaced from the conductive level; The charge storage material is configured as segments, the segments are vertically stacked one above the other, the segments are vertically spaced apart from each other, a portion of the segments extends through the conductive level to be laterally spaced apart from the insulating level; a gate dielectric material adjacent to the charge storage material; and A channel material extends vertically along the stack and adjacent to the gate dielectric material.

11. The NAND memory array of claim 10, wherein the high-k dielectric structure comprises one or more of aluminum oxide, hafnium oxide, hafnium silicate, zirconium oxide, and zirconium silicate.

12. The NAND memory array of claim 10, wherein the high-k dielectric structure comprises only a single homogeneous high-k dielectric material.

13. The NAND memory array of claim 10, wherein at least a portion of the high-k dielectric structure comprises a laminate of two or more different high-k dielectric materials.

14. The NAND memory array of claim 13 wherein the high-k dielectric materials of the laminates are approximately the same thickness as one another.

15. The NAND memory array of claim 13, wherein the control gate region has a terminal end, and wherein the laminate wraps around the terminal end of the control gate region.

16. The NAND memory array of claim 13, wherein the control gate region has a terminal having a top surface, a bottom surface, and sidewall surfaces extending from the top surface to the bottom surface, and wherein the laminate is along the top and bottom surfaces of the terminal of the control gate region but not along the sidewall surfaces of the terminal.

17. The NAND memory array of claim 10 wherein the high-k dielectric structure is adjacent to the control gate region and is not adjacent to the second region.

18. The NAND memory array of claim 10 wherein the high-k dielectric structure is adjacent to the control gate region and the second region.

19. The NAND memory array of claim 10 including voids within the insulating levels.

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