Hysteretic Control of Boost Converter

Abstract

The present invention relates to a boost converter. The boost converter includes a clock generator, a switching converter, a hysteresis controller and a power tracking module. The clock generator is configured to output a clock signal; the switching converter is configured to operate at a frequency based on the clock signal. The hysteresis controller is configured to adjust an intermediate output from the switching converter. The power tracking module is configured to change a frequency control signal sent to the clock generator, the change in frequency is based on a current flowing into an output capacitor, so that the charging time of the capacitor is minimized when the current is maximized.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Application Serial No. 62 / 889,509, filed on August 20, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention generally relates to systems and methods for operating hysteretic control feedback of a boost converter. Background Art

[0004] Energy harvesters have transducers that convert physical energy such as vibration, light or temperature differences into electrical energy. This electrical energy is often generated at a voltage different from that required to charge a battery or capacitor. Switching voltage converters are often used to step up / down the voltage.

[0005] Energy harvesting systems often utilize hysteretic control to regulate output voltage due to its simplicity and low power implementation. However, in energy-constrained applications, tracking the maximum output power under different inputs is challenging. The present disclosure describes an improved modified hysteretic controller with higher efficiency that also provides a control signal for tracking output power. Summary of the invention

[0006] The boost converter includes a clock generator, a switching converter, a hysteretic controller, and a power tracking module. The clock generator is configured to output a clock signal; the switching converter is configured to operate at a frequency based on the clock signal. The hysteretic controller is configured to regulate an intermediate output from the switching converter. The power tracking module is configured to change a frequency control signal sent to the clock generator, the change in frequency being based on a current flowing into an output capacitor so that the charging time of the capacitor is minimized when the current is maximized. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram of a battery powered sensor node.

[0008] Figure 2 is a block diagram of an energy harvesting sensor node.

[0009] Figure 3 is a block diagram of an exemplary energy harvesting image sensor node.

[0010] Figure 4 is a block diagram of an energy harvesting system powered by image sensor pixels.

[0011] Figure 5 is a block diagram of an output voltage regulator using a switched capacitor (SC) boost converter with ping-pong hysteretic control.

[0012] Figure 6 is used for Figure 5 A graphical illustration of the control signals for ping-pong hysteretic control of an SC boost converter is shown.

[0013] Figure 7 is a block diagram of a non-overlapping clock phase generator.

[0014] Figure 8 yes Figure 7 Graphical illustration of the control and intermediate signals of a non-overlapping clock phase generator.

[0015] Fig. 9 is a block diagram of a clock generator using interleaved oscillators with power-gated buffers.

[0016] Fig.10 is a block diagram of a buffered high speed ring oscillator.

[0017] Fig.11 is a block diagram of a buffered high speed current hungry ring oscillator.

[0018] Fig. 12A is a block diagram of a first exemplary non-overlapping two-phase clock generator with frequency-independent delays.

[0019] Fig. 12B is a block diagram of a second exemplary non-overlapping two-phase clock generator with frequency-independent delays.

[0020] Fig.13 is a block diagram of a two-phase clock generator with interleaved ring oscillators.

[0021] Fig.14 is a block diagram of an interleaved current-starved ring oscillator with power-gated buffers.

[0022] Fig.15 is a block diagram of an interleaved current starved ring oscillator with power gated buffers and ungated buffers.

[0023] Fig.16 is a block diagram of a state machine based multiple non-overlapping clock phase generator.

[0024] Fig.17 is a block diagram of the energy harvesting system.

[0025] Fig.18 is a block diagram of a maximum output power tracking regulator that controls the switching frequency or duty cycle.

[0026] Fig.19 is a block diagram of an alternative embodiment of a maximum input power tracking regulator that controls the switching frequency or duty cycle.

[0027] Fig. 20It is a schematic diagram of the system model of the switching frequency regulator.

[0028] Fig.21 is a block diagram of a regulator with a switched capacitor converter, a maximum output power tracking regulator, and a ping-pong hysteretic controller.

[0029] Fig. 22 is a graphical representation of the output voltage versus time of a regulator with a switched capacitor converter and ping-pong hysteretic control.

[0030] Fig.23A is a schematic diagram of a hysteresis controller.

[0031] Fig. 23B is a graphical representation of the output voltage and control signal versus time.

[0032] Fig.24A is a schematic diagram of a ping-pong hysteresis controller.

[0033] Fig. 24B is a graphical representation of the output voltage and control signal versus time.

[0034] Fig.25 is a flow chart of a hill climbing algorithm for minimizing the output capacitor charging time.

[0035] Fig.26 is a graphical representation of charging time and switching frequency versus time.

[0036] Fig. 27 It is a block diagram of an asynchronous maximum output power tracking circuit.

[0037] Fig.28 is a graphical representation of the measured peak efficiency and tracking efficiency versus time for a system using maximum power point tracking.

[0038] Fig.29 is a perspective view of an image sensor having peripheral diodes configured to capture light adjacent to an image field of view.

[0039] Fig.30 is a block diagram of an auxiliary energy harvesting diode configured to power a system via a DC-DC converter with a low frequency (LF) oscillator.

[0040] Fig.31 is a block diagram of an image sensor in energy harvesting mode using a DC-DC converter with a high frequency (HF) oscillator.

[0041] Fig.32 is a schematic diagram of a diode stack arranged adjacent to an image sensor.

[0042] Fig.33is a cross-sectional view of an embodiment of two semiconductor structures configured to capture light.

[0043] Fig.34 is a cross-sectional view of an alternative embodiment of two semiconductor structures configured to capture light.

[0044] Fig.35 is a schematic diagram of an image sensor node with a peripheral diode that captures nearby light for a cold start sequence of a self-powered energy harvester.

[0045] Fig.36 is a schematic diagram of a comparator with a built-in reference threshold for power-on reset (POR).

[0046] Fig.37 is a schematic diagram of a hysteresis comparator where the reference voltage is generated by an isolated photodiode.

[0047] Fig.38 is a graphical representation of measured voltage and logic levels versus time for a cold-start image sensor using a peripheral diode.

[0048] Fig.39 is a graphical representation of typical image sensor applications based on image capture rate relative to time. DETAILED DESCRIPTION

[0049] As required, detailed embodiments of the present invention are disclosed herein; however, it should be understood that the disclosed embodiments are merely examples of the present invention, which may be implemented in various and alternative forms. The figures are not necessarily to scale; some features may be enlarged or reduced to show the details of a particular component. Therefore, the specific structural and functional details disclosed herein should not be interpreted as limiting, but merely as a representative basis for teaching those skilled in the art to adopt the present invention in various ways.

[0050] The term "substantially" may be used herein to describe the disclosed or claimed embodiments. The term "substantially" may modify a value or relative property disclosed or claimed in the present disclosure. In this case, "substantially" may mean that the value or relative property it modifies is within ±0%, 0.1%, 0.5%, 1%, 2%, 3%, 4%, 5%, or 10% of the value or relative property.

[0051] Using distributed sensor nodes that employ energy harvesting techniques can improve battery life and form factor. Using the sensor itself as an energy harvesting element is an attractive option to further reduce the cost and footprint of such nodes. CMOS image sensors are an example of a pixel array that can be reconfigured to collect incident light. Several applications, including warehouse inventory tracking and structural fault detection, can capture images at a slow rate, such as once every 2-5 minutes, and are therefore compatible with ultra-low energy harvesting power levels. However, a key challenge with this circuit configuration is to ensure robust cold start and efficient operation over a wide range of light intensities.

[0052] Energy harvesting from the imager pixel array utilizes the pixel array to generate energy when it is not being used to capture an image. However, the pixel array needs to be modified to multiplex between the energy harvesting mode and the image capture mode. These modifications result in a low fill factor and a large pixel pitch (i.e., reduced image resolution). In addition, the system modifications require a battery or an off-chip inductor to start up (i.e., cold start). Furthermore, for energy-efficient operation under varying light intensities, prior art designs employ maximum input power point tracking (MPPT). However, this does not necessarily result in maximum power delivery to the load.

[0053] Other related work in this area has explored more general energy harvesters with power management capabilities. A dedicated charge pump was used to enable cold start, but this came with a significant area overhead. The design used off-chip solar cells, which added additional cost and footprint to the sensor node.

[0054] Figure 1 1 is a block diagram of a battery powered sensor node 100. The sensor node 100 includes at least a sensor 102, such as an imaging sensor, a microphone, a humidity sensor, a pressure sensor, an infrared sensor, a magnetic sensor, a temperature sensor, or a combination thereof. The output of the sensor 102 may then be converted from an analog signal to a digital signal via an analog-to-digital converter (ADC) 104, and the digital signal may then be processed by a central processing unit (CPU) 106. The sensor node also includes a communication node 108. The communication node 108 may be a wireless node configured to communicate via a wireless protocol, such as cellular, 802.11 (Wi-Fi), 802.15, optical (e.g., via fiber optics), infrared (e.g., IrDA), or acoustic (e.g., ultrasonic). Here, the sensor node 100 is powered by a battery 110, or alternatively connected to a power grid, for example, via an AC / DC converter.

[0055] Figure 21 is a block diagram of an energy harvesting sensor node 200. The sensor node 200 includes at least one sensor 202, such as an imaging sensor, a microphone, a humidity sensor, a pressure sensor, an infrared sensor, a magnetic sensor, a temperature sensor, or a combination thereof. The output of the sensor 202 may then be converted from an analog signal to a digital signal via an analog-to-digital converter (ADC) 204, and the digital signal may then be processed by a central processing unit (CPU) 106. The sensor node also includes a communication node 208. The communication node 208 may be a wireless node configured to communicate via a wireless protocol, such as cellular, 802.11 (Wi-Fi), 802.15, optical (e.g., via fiber), infrared (e.g., IrDA), or acoustic (e.g., ultrasonic). Here, the sensor node 200 is powered by the sensor 202, which includes an energy harvesting system, or alternatively may be selectively configured as an energy harvesting system.

[0056] Figure 3 is a block diagram of an exemplary energy harvesting sensor node 300. The sensor node 300 includes an integrated circuit (IC) 302 including a pixel array 304 and a DC / DC converter 306. The integrated circuit 302 is shown configured to operate the pixel array 304 as a voltage source to power the DC / DC converter that generates at least one voltage level, or in an imaging mode where a digital signal of a captured image is sent to an image readout circuit 308 that can be used to generate a remote image 310.

[0057] For example, consider a fully integrated energy harvester IC that uses a conventional 4-T image sensor pixel with a constant fill factor or pixel pitch arranged as a QVGA (320x240) pixel array. Figure 3 , the image sensor is configured in imaging mode (I M ) or energy harvesting mode (EH). The design includes a DC / DC converter 306, such as a switched capacitor (S C ) boost converter, which increases the pixel array voltage (V IN ) to generate two output voltages for standard imager readout (A VDD and D VDD ). In this prototype, the readout circuitry is not included in a monolithic manner, but since the pixel structure is not changed, such integration should be relatively simple.

[0058] Next, we will describe the IC chip architecture and its key building blocks, followed by circuit details, and finally end with measurement results from a prototype fabricated in a sub-500 nm CMOS image sensor (CIS) process, however, the concepts disclosed in this application are not limited to these technologies.

[0059] Figure 4 4 is a block diagram of an energy harvesting image sensor system 400. The sensor system 400 includes an image area 402 having an image / pixel array 404 and an auxiliary photodiode. The array 404 is coupled to a DC / DC converter 406 and a voltage regulator 408, where the regulated output is fed back to the DC / DC converter 406 via an MPPT controller 401 and an oscillator 412. The QVGA pixel array is forward biased when configured in energy harvesting (EH) mode. When illuminated, the pixel array 404 harvests energy and generates a V between 0.25-0.4 V depending on the light intensity. IN . This voltage (V IN ) is stepped up to digital (D VDD ) and simulation (A VDD ) supply, using a hysteresis control circuit, the digital (D VDD ) and simulation (A VDD ) supplies are regulated to 0.6 V and 1.8 V. The SC converters operate using non-overlapping clocks from an oscillator. The oscillator frequency is set by an MPPT algorithm to maximize the power delivered to the load under varying light and load conditions. Auxiliary photodiodes adjacent to the pixel array capture edge light at the periphery of the imager pixel array to enable a cold start.

[0060] The QVGA pixel array consists of conventional 4-T pixels. Fig.33 and 34 As shown, each pixel is embedded in a shared P-well and deep N-well. During imaging (IM) mode, the P-well-N diffusion (PD1) junction is reverse biased, while the P-well-deep N-well (PD2) junction is shorted. The junction depth of PD1 does not change and therefore has a negligible impact on image quality.

[0061] During EH mode, the NMOS transfer gate and reset transistor of the 4-T pixel bias the N diffusion to GND. The forward-biased PD1 and PD2 junctions harvest energy from light at different wavelengths, generating a positive VIN at the P-well node. The entire array can be configured to share a set of reconfiguration switches external to the array to multiplex it between IM and EH modes. This approach is independent of the pixel pitch and does not sacrifice fill factor. As a result, this work achieves a high reported pixel fill factor (60.4%) and small pitch (e.g., 5 μm) for EH pixels.

[0062] Each unit photodiode in the auxiliary array may have a structure similar to that in the pixel array and is placed in its own N-well. The photodiodes may be configured in series, in parallel, or in a combination thereof. For example, the photodiodes may be arranged in series in 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, or 15 arrangements to produce a photodiode string of the desired voltage, which may then be connected in parallel with other photodiode strings to achieve the desired current. The test chip was constructed with nine photodiodes stacked in series (see Fig.32 The stack generates an unregulated auxiliary supply rail (V AUX ), which can reach about 1.8 V. The diode size is gradually increased (4x to 35x) to compensate for the reverse photocurrent loss at the deep N-well-P substrate junction (i.e., I s,leak ). This dimensioning greatly enhances V AUX rail output drive capability.

[0063] Figure 5 is a block diagram of an output voltage regulator 500 using a switched capacitor (SC) boost converter with ping-pong hysteretic control. The voltage regulator 500 uses a modified Dickson topology for a fully integrated SC boost conversion. This topology enables step charging of the capacitors, thereby reducing conduction losses across the switches. This topology also ensures that the voltage excursion across the top and bottom plate parasitic capacitors is minimal to reduce losses. The SC Boost-1 and SC Boost-2 converters are daisy-chained to generate the (unregulated) V DIG and V ANA These outputs are then regulated using hysteresis control to generate D VDD and A VDD SC boost-1 at frequency f HF The following operates on non-overlapping clocks (φ1 and φ2) with a frequency of f HF is provided by a high frequency oscillator. When SC Boost-2 takes input from SC Boost-1, it generates a DIV Operates on a gated clock. MPPT control adjusts f HF and f DIV , to maximize the output power delivered by each stage. Figure 6 is used for Figure 5 A graphical illustration of the control signals for an SC boost converter is shown.

[0064] The test setup has a boost converter with 10 stages, each containing a 200 pF cell fly capacitor. The converter can be programmed to tap the two outputs from any two different stages, which provides the flexibility to change the conversion ratio independently. Figure 5 , after stage 2, nominally tapping V from SC boost converter 1 DIG output, and taps V from SC boost converter 2 after stage 6 ANA Output. The clocks to unused stages are turned off to save power.

[0065] Voltage regulation occurs via ping-pong hysteretic control. Two output capacitors, C1 and C2, buffer the boost converter output in opposite phases. While one capacitor delivers energy to the load, the other buffers the boosted output. The charge enable signal QEN1 charges C1, while the load enable signal LEN2 connects C2 to the load. Likewise, once both QEN1 and LEN2 have been disabled, QEN2 and LEN1 begin to be in phase. The voltage across C1 and C2 is compared to V refL and V refH The comparison allows independent control of charge and discharge times.

[0066] Depends on A VDD and D VDD Under load, the switching frequency f HF Typically in the range from 0.5 to 10 kHz, and f DIV / f HF The ratio of varies from 0.75 to 1. The clock generator and drivers for the SC boost converter switches are often the main source of energy loss in the energy harvester. This is addressed via the improved interleaved ring oscillator (IRO) design described below.

[0067] The chip's oscillator operates at 82 Hz (LF for cold start; see below) and 10 kHz (HF). Fig.14 and 15, discloses an ultra-low power interleaved ring oscillator (IRO) that generates two non-overlapping clock phases. The IRO draws a current proportional to its frequency due to a special circuit configuration that minimizes the shoot-through current in its preceding buffer stage (which would otherwise cause a disproportionate overhead). The IRO employs two interleaved ring oscillator chains that operate at the same operating frequency, but out of phase. Each chain consists of an odd number (e.g., five in this embodiment) of current-starved stages to control the oscillation frequency. The current source in each stage is gated to control the phase of charging and discharging. Stage outputs 1-5 and 1'-5' control the gated control in the other chain. This results in i and i' (1≤I≤5) being out of phase. In order to minimize the shoot-through current in the buffer following the ring oscillator, specific i and i' nodes are used for power gating. Six gated buffer stages are used to recover small transition times and consume mainly dynamic switching current. A conventional clock driver follows the gated buffer and drives the boost converter switch.

[0068] At the lowest operating frequency of 82 Hz, the measured IRO current consumption of the test device is 2.1 nA / kHz, with shoot-through current negligible. The current source biasing the ring oscillator sets the oscillator frequency. The non-overlap delay is proportional to the rise and fall times of the stage nodes, which relaxes the clock driver requirements.

[0069] Here, circuit techniques are disclosed for generating ultra-low power clock phases for signal processing and power conversion.This disclosure describes the generation of non-overlapping clocks over a very wide frequency range with very low power consumption.

[0070] Most signal processing or power conversion ICs use switched capacitor or inductor circuits, however in energy-constrained applications such as energy harvesting devices, wireless sensor nodes or implantable devices, a significant source of energy consumption is the generation of these non-overlapping clocks. In these and other applications, the clock generator needs to operate over a wide frequency range depending on the operating mode or available power.

[0071] A conventional on-chip non-overlapping clock generator consists of the blocks in the dashed rectangle, followed by Figure 7 and 8 The indicated clock driver.

[0072] Figure 7 is a block diagram of a non-overlapping clock phase generator 700. The clock generator 700 includes an oscillator 702, a buffer 706, a two-phase non-overlapping generator 708, and a clock driver 710. Figure 8 yes Figure 7 Graphical illustration of the control and intermediate signals of a non-overlapping clock phase generator.

[0073] Fig. 9is a block diagram of a clock generator 900 having a buffered two-phase interleaved oscillator 902. The buffered two-phase interleaved oscillator 902 includes an interleaved oscillator 904 having a power-gated buffer 906. The buffered two-phase interleaved oscillator 902 provides an input to a clock driver 908.

[0074] Fig.10 1 is a block diagram of a buffered high speed ring oscillator 1000. The buffered high speed ring oscillator 1000 includes a ring oscillator 1002, a buffer 1004, and a non-overlapping generator 1006. The ring oscillator 1002 is shown as a 5-stage ring oscillator, however the ring oscillator can be any odd number of stages, such as 5, 7, 9, 11, 21, 31, 41, 51, etc. In addition, the buffer 1004 is shown as a single buffer, however this can be implemented as multiple buffers arranged in series or parallel or a combination thereof.

[0075] Current-starved ring oscillators or relaxation oscillators are often used to generate variable frequency clocks with lower power. When the clock frequency is reduced beyond a certain limit, the oscillator output (ɸ OSC ) rise time (T r ) and fall time (T f ) increases. This results in higher shoot-through current in the buffer following the oscillator, and any power reduction gained by reducing the oscillator frequency is lost.

[0076] Fig.11 1 is a block diagram of a buffered current hungry high speed ring oscillator 1100. The buffered high speed ring oscillator 1100 includes a ring oscillator 1102, a buffer 1104, and a non-overlapping generator 1106. The ring oscillator 1102 is shown as a 5-stage ring oscillator, however the ring oscillator can be any odd number of stages, such as 5, 7, 9, 11, 21, 31, 41, 51, etc. In addition, the buffer 1104 is shown as a single buffer, however this can be implemented as multiple buffers arranged in series or parallel or a combination thereof.

[0077] To reduce the number of clock drivers and repeaters in the chip, the non-overlapping cycles (T nov ) must be large. The non-overlapping period depends on the delay introduced in the non-overlapping generator. Conventionally, increasing the length of the delay also increases the power consumption of the non-overlapping generator.

[0078] To overcome these critical issues at lower power supplies, we propose a novel interleaved oscillator to generate non-overlapping clocks (ɸA and ɸB) without the need for additional non-overlapping generator circuitry. The non-overlap period increases with decreasing frequency, thereby enabling reduced clock drivers in energy-constrained applications. To reduce the rise and fall times of the clocks, we propose novel power-gated buffers to avoid shoot-through current.

[0079] Conventional ring oscillators have an odd number of inverter stages. The oscillator output is buffered before being driven by the clock driver. To reduce the power through the oscillator, the inverters in the oscillator are made weaker (smaller W / L size). This increases the rise and fall times of the ring oscillator output, resulting in large shoot-through currents in the buffer.

[0080] A current-starved ring oscillator is used to tune the frequency using a programmable current source in series with an inverter. Fig.11 As shown, the output of the current-starved oscillator also has large rise and fall times to achieve low-frequency clocking. However, at lower frequencies, the shoot-through current in the buffer following the current-starved ring oscillator dominates the overall power consumption.

[0081] Fig. 12A is a block diagram of a first exemplary CMOS logic circuit non-overlapping two-phase clock generator 1200 with frequency independent delay. Fig. 12B 1 is a block diagram of a second exemplary CMOS logic circuit non-overlapping two-phase clock generator 1250 with frequency-independent delay. Here, the delay stage I A1 to I AN ,I B1 to I BN and I1 to I N This can be any number of inverters or similar logic structures.

[0082] For low power, low frequency applications, it is desirable to have larger non-overlapping phases. This enables the use of a reduced number of buffer stages while tolerating larger clock skews. However, the larger delay comes at the expense of power consumption of these delay stages.

[0083] For high frequency clocks generated by current hungry ring oscillators, the rise and fall times are small and therefore, a small non-overlapping phase is sufficient to ensure two-phase operation. Smaller non-overlapping phases ensure greater on-time in high frequency applications. This improves the transient stability behavior of switched capacitor or inductor circuits.

[0084] Therefore, it would be desirable to make the delay between non-overlapping clock phases proportional to their frequency.

[0085] Fig.13is a block diagram of a two-phase clock generator 1300 having an interleaved ring oscillator 1302. The interleaved ring oscillator 1302 includes a first current starved ring oscillator 1304 and a second current starved ring oscillator 1306, which are coupled such that the output of the first current starved ring oscillator 1304 is an input to the second current starved ring oscillator 1306, and the second current starved ring oscillator 1306 is an input to the first current starved ring oscillator 1304. The first current starved ring oscillator 1304 and the second current starved ring oscillator 1306 send signals to power gated buffers 1308 and 1310. The output of the first current starved ring oscillator 1304 is an input to the first power gated buffer 1308, and the gating control for the first power gated buffer 1308 is the output of the second current starved ring oscillator 1306. Similarly, the output of the second current starving ring oscillator 1306 is the input to the second power gated buffer 1310, and the gate control for the second power gated buffer 1310 is the output of the first current starving ring oscillator 1304. The time period or clock frequency may be based on a programmable current source in a current starving inverter.

[0086] Interleaving the ring oscillator helps generate clock phases at half the original phase difference. These intermediate clock phases are used as gating control signals to prevent shoot-through current in power-gated buffers, such as Fig.13 shown.

[0087] Once the edges of the clocks are sharp enough after passing through several stages of power-gated buffers, conventional buffers or clock drivers help drive the non-overlapping clocks.

[0088] This approach also inherently introduces a delay between clock phases, which is also proportional to the frequency. Therefore, low-power, low-frequency operation can be implemented using fewer clock repeater stages.

[0089] At higher available power, the clock frequency can be increased depending on the operating mode, and the non-overlapping periods are smaller. This feature helps improve the stabilization of the switched capacitor voltage.

[0090] Fig.14is a block diagram of an interleaved current hungry ring oscillator with a power gated buffer system 1400. The interleaved ring oscillator 1402 includes a first current hungry ring oscillator 1404 and a second current hungry ring oscillator 1406 that are coupled such that the output of the first stage of the first current hungry ring oscillator 1404 gates the first stage of the second current hungry ring oscillator 1406, and the first stage of the second current hungry ring oscillator 1406 gates the first stage of the first current hungry ring oscillator 1404. The third current hungry ring oscillator 1404 and the second current hungry ring oscillator 1406 send signals to power gated buffers 1408 and 1410. The output of the first current hungry ring oscillator 1404 is an input to the first power gated buffer 1408, and the gating control for the first power gated buffer 1408 is the output of the second current hungry ring oscillator 1406. Similarly, the output of the second current starving ring oscillator 1406 is an input to the second power gated buffer 1410 , and the gating control for the second power gated buffer 1410 is the output of the first current starving ring oscillator 1404 .

[0091] The ring oscillators 1404, 1406 are shown as 5-stage ring oscillators, however the ring oscillators may be any odd number of stages, such as 5, 7, 9, 11, 21, 31, 41, 51, etc. Additionally, the buffers 1108, 1410 are shown as double buffers, however this may be implemented as multiple buffers arranged in series or parallel or a combination thereof.

[0092] Furthermore, each internal stage of the first ring oscillator 1404 is interleaved and used to gate an internal stage of the second ring oscillator 1406, and each internal stage of the second ring oscillator 1406 is interleaved and used to gate an internal stage of the first ring oscillator 1404. A1 The output A1 of the first inverter stage is used to gate the second ring oscillator I B1 The first inverter stage, and to the second ring oscillator I B1 The output B1 of the first inverter stage is used to gate the first ring oscillator I A1 This continues with each stage of each ring oscillator.

[0093] The power consumed by the interleaved ring oscillator and the power-gated buffer is linearly proportional to the clock frequency, which indicates that there is no shoot-through current even at very low clock frequencies. In addition, the power of the non-overlapping clock phase generator is linearly proportional to the supply voltage.

[0094] Fig.14Two interleaved current starved ring oscillators are shown, each with 5 stages. The current source in each stage helps control the frequency.

[0095] Each current starved inverter in Ring Oscillator-A is gated by the switch output (B1-B5) of the corresponding inverter in Oscillator-B. Similarly, the inverters in Oscillator-B are gated by the switch outputs (A1-A5) from Oscillator-A.

[0096] These interleaved ring oscillators produce clock phases that are 18 degrees out of phase with each other and produce outputs that are 180 degrees out of phase. The outputs from these oscillators have the same frequency.

[0097] Taking the outputs from nodes A5 and B5, we get non-overlapping clocks with opposite phases. However, at low clock frequencies, the rise and fall times are very large transition times.

[0098] These large transition times will result in large shoot-through currents in the subsequent buffers. We solve this problem using power-gated buffers. The power-gating signal for the buffer is selected to be one of the appropriate oscillator phases A1-A5 and B1-B5 that have been generated. This Fig.14 As shown in FIG. 1 , the first power gated buffer B A1 The first ring oscillator I A2 The output of the second inverter stage is gated, and the first power gated buffer B B1 The second ring oscillator I B2 In this example, a second power gated buffer is used, where the second power gated buffer B A2 The first ring oscillator I A3 The output of the third inverter stage is gated, and the second power gated buffer B B2 The second ring oscillator I B3 The output of the third inverter stage is gated.

[0099] As an example, if A5 goes high, the output of the first inverter after it will transition from high → low. Therefore, to avoid shoot-through current in this inverter, it is gated by clock phase B2. This results in the output having a lower transition time without any shoot-through current loss.

[0100] Generating sharper clock phases in this way results in a clock with a non-overlapping period proportional to the slow rise and fall times of the interleaved ring oscillator. At lower supply voltage levels and lower clock frequencies, we obtain a larger non-overlapping period. On the other hand, at faster clock frequencies, the non-overlapping period decreases.

[0101] Fig.15is a block diagram of an interleaved current starved ring oscillator with power gated buffers and ungated buffer system 1500 .

[0102] Fig.15 is a block diagram of an interleaved current hungry ring oscillator with a power gated buffer system 1500. The interleaved ring oscillator 1502 includes a first current hungry ring oscillator 1504 and a second current hungry ring oscillator 1506 that are coupled such that the output of the first stage first current hungry ring oscillator 1504 gates the first stage second current hungry ring oscillator 1506, and the first stage second current hungry ring oscillator 1506 gates the first stage first current hungry ring oscillator 1504. The third current hungry ring oscillator 1504 and the second current hungry ring oscillator 1506 send signals to power gated buffers 1508 and 1510. The output of the first current hungry ring oscillator 1504 is an input to the first power gated buffer 1508, and the gating control for the first power gated buffer 1508 is the output of the second current hungry ring oscillator 1506. Similarly, the output of the second current starving ring oscillator 1506 is an input to the second power gated buffer 1510 , and the gating control for the second power gated buffer 1510 is the output of the first current starving ring oscillator 1504 .

[0103] Conventional clock driver buffers increase the drive strength of these non-overlapping clocks. A simple state machine using a multiplexer to pass one of the two clocks can generate any number of non-overlapping clock phases, such as Fig.16 shown.

[0104] Fig.16 1 is a block diagram of a multiple non-overlapping clock phase generator 1600 based on a state machine. The clock generator includes a state machine 1602 and a multiplexer. In this exemplary block diagram, there are three multiplexers (a first multiplexer 1604, a second multiplexer 1606, and a third multiplexer 1608) for generating a three-phase clock. However, more or fewer multiplexers can be used to generate the desired number of phases. For example, if only two phases are required, only the first multiplexer 1604, the second multiplexer 1606, and the third multiplexer 1608 can be removed. If more phases are required, additional multiplexers can be added.

[0105] Energy harvesters have transducers that convert physical energy such as vibration, light or temperature differences into electrical energy. This electrical energy is often generated at a voltage different from that required to charge a battery or capacitor. Switching voltage converters are often used to step up / down the voltage.

[0106] Tracking the maximum output power at varying inputs is challenging in energy-constrained applications. This disclosure outlines an analog maximum output power tracking scheme that uses a hill climbing (also known as perturb and observe) algorithm to adjust the switching frequency of a voltage regulator at very low energies. The proposed method adjusts the switching frequency to change the input and output impedance of the voltage regulator. This impedance matching helps deliver maximum power output from the harvester.

[0107] Energy harvesting systems typically utilize hysteretic control to regulate the output voltage due to its simplicity and low power implementation. The present disclosure describes an improved modified hysteretic control with higher efficiency that also provides a control signal for tracking the output power.

[0108] A typical energy harvesting system has a transducer that converts energy such as light, pressure or heat into electrical energy. The electrical energy from the transducer is at a voltage V IN This requires the voltage to be stepped up / down before it can be delivered to the load R LOAD or stored in capacitor C LOAD middle.

[0109] Fig.17 1700 is a block diagram of an energy harvesting system 1700. The energy harvesting system 1700 includes a clock generator 1702, a transducer 1704, a switching voltage converter 1706, a voltage regulator 1708, and a resistor load R LOAD and / or capacitor C LOAD The transducer 1704 includes an imaging sensor, a microphone, a humidity sensor, a pressure sensor, an infrared sensor, a magnetic sensor, a temperature sensor, or a combination thereof.

[0110] The switching voltage converter is at voltage V OUT The converter requires a clock to periodically turn its switch on and off. The power delivered from the source to the load is regulated by varying the switching frequency or duty cycle. The feedback loop senses the output power and modulates the switching frequency or duty cycle, as Fig.18 shown.

[0111] Fig.18 1 is a block diagram of an energy harvesting system 1800 with a switching frequency regulator. The energy harvesting system 1800 includes a clock generator 1802, a transducer 1804, a switching voltage converter 1806, a voltage regulator 1808, and a load resistor R LOAD and / or load capacitance C LOAD The load and the maximum output power tracking module 1810. The transducer 1804 includes an imaging sensor, a microphone, a humidity sensor, a pressure sensor, an infrared sensor, a magnetic sensor, a temperature sensor or a combination thereof.

[0112] Sensing output power requires sensing the output voltage and current and taking their product to adjust the switching frequency. This is extremely challenging in energy-constrained applications such as harvesting energy from ambient sources.

[0113] Fig.19 A method of maximizing power in an energy harvesting system is shown. Fig.19 1 is a block diagram of an energy harvesting system 1900 with a switching frequency regulator. The energy harvesting system 1900 includes a clock generator 1902, a transducer 1904, a switching voltage converter 1906, a voltage regulator 1908, and a load resistor R LOAD and / or load capacitance C LOAD The load and the maximum output power tracking module 1910. The transducer 1904 includes an imaging sensor, a microphone, a humidity sensor, a pressure sensor, an infrared sensor, a magnetic sensor, a temperature sensor or a combination thereof.

[0114] Each source has a well-defined characteristic in its operating region where its power can be maximized. For example, a thermoelectric generator (TEG) delivers maximum power when the voltage across it is half of the voltage under no-load conditions. Similarly, a photovoltaic cell or solar cell delivers maximum power when the voltage across it is approximately 0.8 times the voltage under no-load conditions.

[0115] A simple and relatively low power implementation of measuring the source voltage under no-load conditions leads to Fig.19 The feedback control system shown in Figure 1 regulates the voltage delivered by the source (V IN ), so that the maximum power can be extracted from the source. The function of this system can be obtained from Fig. 20 is better described in the overall system model shown. Fig. 20 2000 is a schematic diagram of a system model of a switching frequency regulator. The transducer source 2002 can be modeled as a Thevenin voltage source Vs with an equivalent impedance Rs. The switching voltage converter 2004 is modeled as having a ratio of 1:N and a switching frequency f CLK The equivalent output impedance is inversely proportional to the voltage converter. And the load 2006 is modeled as a load resistor R LOAD and load capacitance C LOAD .

[0116] controls the frequency or duty cycle of the clock, to see the converter (R IN ) is modulated so that V IN V according to the energy source IN Under this condition, R INbecomes equal to Rs and extracts maximum power from the energy source. Hence, optimizing the clock to have impedance matching in matching network-1 results in suboptimal operation of matching network-2. This results in lower overall power output from the voltage converter.

[0117] The present disclosure relates to regulating the clock to maximize the total power output from a voltage converter. The main advantage of this scheme is that it enables the maximum power delivered from the energy harvesting system and is not limited to extracting the maximum power from the source. Some novel points include:

[0118] Some key aspects of this maximum power tracking system include:

[0119] The system can measure and maximize output power in energy-constrained applications (eg, energy harvesting), but embodiments are not limited to maximizing power from an energy source.

[0120] A method of sensing output power by measuring current from an output voltage regulator while consuming very low energy is implemented.

[0121] Current measurement from a voltage regulator does not require a series resistor or replica generation. The current output from the voltage regulator is measured by measuring the charge time of an intermediate capacitor in the voltage regulator.

[0122] The charging time of the intermediate capacitor is measured by converting a small bias current into a corresponding voltage and using a voltage regulator to compare the charging time at different clocks.

[0123] A novel multiplexed ping-pong hysteretic output voltage regulator scheme is disclosed that improves efficiency but maintains the simplicity of conventional hysteretic control.

[0124] Fig.21 21 is a block diagram of a system 2100 having a regulator with a switched capacitor converter and ping-pong hysteresis control. The energy harvesting system 2100 includes a clock generator 2102, a transducer 2104, a switching voltage converter 2106 such as a switched capacitor converter, a ping-pong hysteresis controlled voltage regulator 2108, a load resistor R LOAD and / or load capacitance C LOAD The load, and the maximum output power tracking module 2110. The transducer 2104 includes an imaging sensor, a microphone, a humidity sensor, a pressure sensor, an infrared sensor, a magnetic sensor, a temperature sensor, or a combination thereof.

[0125] In one embodiment, system 2100 is a fully integrated switched capacitor converter with hysteresis control. The system can adjust the output power by changing the switching frequency of the switched capacitor converter 2106. The output voltage is adjusted using a novel ping-pong hysteresis controller 2108, which can improve the efficiency of the voltage regulator. The technology described here is not limited to the type of voltage regulator. The feedback control variable is also not limited to the switching frequency, and can include any other variable by which the duty cycle or voltage regulator impedance can be controlled. The output power is the product of the output voltage and the current, and the output power can be expressed as equation 1.

[0126] Pout = Vout * Iout (1)

[0127] The ability to sense the output voltage and output current to determine the product is challenging for low energy systems. The output voltage is regulated within the hysteresis band, e.g. Fig. 22 shown. Fig. 22 2200 is a graphical representation of output voltage 2202 of a regulator having a switched capacitor converter and ping-pong hysteretic control versus time 2204. In the graphical representation 2200, the output voltage waveform 2206 swings back and forth between a high output voltage at time 2208 and a low output voltage at time 2210 with a period between time 2208 and 2212.

[0128] V OUT (=V OUT , HIGH –V OUT , LOW ) is designed to be small, where the output voltage remains essentially constant, and therefore the output power is proportional to the output current. To maximize the output power, the output current from the converter needs to be maximized.

[0129] To sense the output current, the current is measured by measuring the voltage across a series resistor or using a replica current mirror. However, these require additional circuitry and consume power to sense the current.

[0130] Here, the time taken to charge the output capacitor in the hysteretic controller is used as an estimate of the output current, as Fig.23A As shown. Fig.23A is a schematic diagram 2300 of a hysteretic controller using a Schmitt trigger 2302 . Fig. 23B is a graphical representation 2350 of the output voltage 2352 and the control signals 2354, 2356 versus time 2358. The higher the charging current, the shorter the charging time.

[0131] When QEN (charge-enable) is high, the output current from the converter charges the output capacitor Co. When QEN is low, Co discharges to deliver power to the load. When delivering power to the load, the energy from the disconnected converter is not utilized, resulting in inefficient operation.

[0132] To correct this problem, Fig.24A A ping-pong hysteresis control technology is disclosed. Fig.24A is a schematic diagram of a ping-pong hysteretic controller 2400 that includes combinational logic 2402 that generates control signals. Fig. 24B is a graphical representation 2450 of output voltage 2452 and control signals 2454, 2456, 2458, and 2460 versus time 2462. Two capacitors are used to store the output from the converter before it is delivered to the load. When the first capacitor C O1 When charging from the converter, the second capacitor C O2 discharge to deliver power to the load. Connect each node to V OUT,HIGH Or V OUT,LOW The comparison gives independent control over the charging time.

[0133] This ping-pong operation of the two capacitors delivers output power during load delivery without wasting converter energy, making it more efficient than conventional hysteretic control.In other embodiments, 3 or more capacitors may be used, with charge provided to each capacitor in a round robin fashion.

[0134] To measure the output current from the converter, the charge time in one or both capacitors can be observed. A hill climbing or perturb and observe algorithm is used to adjust the switching frequency of the clock so that the charge time of the output capacitors is minimized. Fig.25 The algorithm is explained in the flowchart in Figure .

[0135] Fig.25 25 is a flow chart of a hill climbing algorithm 2500 for minimizing the output capacitor charging time. Here, the controller begins operation at step 2502. At step 2504, the controller initializes the minimum charging time to an initial value, such as a maximum value based on the capacitor value and output load conditions. At step 2506, the controller decreases the switching frequency (f CLK ), the reduction amount can be a fixed amount or a variable amount. At step 2508, the controller monitors the charging time.

[0136] At step 2510, the controller compares the charge time with the minimum charge time. If the charge time is less than the minimum charge time, the controller sets the minimum charge time as the current charge time in step 2512 and branches back to step 2506. If the charge time is greater than or equal to the minimum charge time, the controller branches to step 2514. At step 2514, the controller increases the switching frequency (f CLK ), and proceeds to step 2516, where the controller monitors the charging time.

[0137] At step 2518, the controller compares the charging time with the minimum charging time. If the charging time is less than the minimum charging time, the controller sets the minimum charging time as the current charging time in step 2520 and branches back to step 2514. If the charging time is greater than or equal to the minimum charging time, the controller branches to step 2522. At step 2522, the controller sets the switching frequency (f CLK ) is reduced to the previous value and the loop is exited at step 2524.

[0138] Fig.26 is a graphical representation 2600 of charging time 2602 and switching frequency 2604 versus time 2606. The switching frequency changes over a period of time as shown in FIG. Fig.26 As an example case, the algorithm decreases the switching frequency from f1 to f2 and the observed charging time increases. Therefore, the frequency update direction is reversed and we keep increasing the switching frequency from f2 to f5 and observe a continuous decrease in the charging time. This indicates that we are operating our complete system to deliver more output power from the converter. If we increase the switching frequency further to f6, the charging time increases and we stop the hill climbing algorithm. We select the second to last switching frequency value (f5 in this case) as the optimal value.

[0139] The charge time is detected by converting it into a proportional voltage so that it can be compared using a conventional voltage comparator. Fig. 27 As shown, the small bias current I BIAS Used to charge the capacitor (C X or C Y )Charge.

[0140] Fig. 27is a block diagram of an asynchronous maximum output power tracking circuit 2700. The asynchronous maximum output power tracking circuit 2700 includes a capacitor group 2702, a Schmitt trigger comparator 2704, and a hill climbing logic 2706 that can be used to control the charging and resetting of the capacitors in the capacitor group 2702. The hill climbing logic 2706 feeds an up / down counter 2708, which then has a bias control 2710 to set the frequency of at least one oscillator 2712.

[0141] Initially, C X Charge to supply V AUX , while C Y The charging time corresponding to the current frequency f1 is stored. The frequency decreases from f1 to f2, and I BIAS Give C X The charging process lasts for an increased charging time. Therefore, the voltage comparator determines V X Greater than V Y We retain C Y The minimum value in C X The hill climbing logic asserts causing the frequency to increment, and the up / down counter sets the bias control to the new switching frequency f3. In our example case, I BIAS C X The recharge is performed for a reduced charge time, and the voltage comparator determines V X Less than V Y . C Y It is now reset, and frequency updates continue until the charging time starts to increase again.

[0142] The circuit proposed here can be designed as an asynchronous circuit that switches only at the end of a charging cycle. This prevents power loss at each clock.

[0143] Maximum Power Point Tracking (MPPT) control regulates the boost converter clock frequency generated by the IRO. The switching frequency of the boost converter modulates the input and output impedances of the converter. By interfacing with finite source and load impedances, MPPT control maximizes load current delivery at the regulated output voltage. Minimizing the QEN1 / QEN2 pulse width maximizes the load current and, therefore, the output power delivered to the load.

[0144] exist Fig. 27 In the circuit, the small bias current (I BIAS ) to the capacitor (C X or C Y ) and converts the charging time of QEN1 into a voltage. Comparing V X and V Y This is useful for comparing charging times at different frequencies. During power-up, V XInitialized to V AUX , and V Y is initialized to GND. The hill climbing logic block selects C A or C B to hold the smaller voltage and to cover the larger voltage after resetting it. Thus, the switching frequency is gradually reduced or increased until the QEN1 pulse width begins to increase. This is established using an increment or decrement signal to the up / down counter that controls the bias of the HF oscillator, see again Fig. 27 .

[0145] The hill climbing logic is implemented as custom event-triggered logic that evaluates the new state only on the falling edge of QEN1. This slow evaluation enables ultra-low power operation and provides ample time for updating the HF oscillator frequency. Therefore, each QEN1 pulse width corresponds to a different switching frequency.

[0146] Fig.28 is a graphical representation 2800 of measured peak efficiency 2802 and tracking efficiency versus time 2806 for a system using a maximum power point 2804 .

[0147] Fig.28 The maximum boost converter efficiency and tracking efficiency at various light intensities are shown. The measurements were made at D VDD 2-12 MΩ load and A VDD The tests were performed with 27-530 MΩ loads on the MOSFET (the load resistance is lower under brighter lighting). The maximum boost converter efficiency was found by sweeping the switching frequency around the MPPT predicted value. The MPPT tracking efficiency is the ratio of the efficiency predicted by the MPPT loop to the maximum efficiency found by sweeping. Under indoor lighting conditions of 430 lux, the boost converter can operate at a maximum efficiency of 52.4%. Under low light conditions of 52 lux, the boost converter has an efficiency of 38.2% at a minimum input power of 79.1 nW. The MPPT output power tracking efficiency is over 96%.

[0148] For self-powered transducers such as image sensors, the power rails must be charged to the required voltage before the image sensor can begin capturing an image. This is achieved using a DC-DC converter to generate these supply rails from incident light. However, operating such a DC-DC converter also requires stable supply rails.

[0149] The present disclosure solves the cold start of the DC-DC converter using incident light near the edge of the image sensor. The present disclosure illustrates how to convert the very low level of light to a higher voltage and establish a stable power rail, after which a conventional DC-DC converter can maintain the power rail and the sensor can then be used to capture images.

[0150] Light from an object passes through a lens or lens system and falls on the image sensor. Some portion of the light that passes through the lens or lens system also falls on the peripheral area around the image sensor. This marginal light energy is used to cold-start the DC-DC converter to generate the power rail for the imager.

[0151] In the present disclosure, the peripheral area is populated with photodiodes arranged in series, parallel, and combinations thereof, configured to collect an unregulated voltage Vaux that is high enough to allow operation of the circuit, but has very limited current drive capability. The auxiliary voltage (Vaux) enables / powers the operation of a low frequency (LF) oscillator that drives a DC-DC converter used to generate the main supply voltage.

[0152] Fig.29 2904 and a peripheral region 2906 having a diode. The image sensor is configured to capture light from an object that is collected via a lens 2908 or lens system. The peripheral region 2906 is configured to capture peripheral light 2910 that is incident on the IC 2902 through the lens 2908 and is adjacent to the image sensor 2904.

[0153] Fig.30 is a block diagram of an auxiliary energy harvesting system 3000 having an auxiliary diode 3008 proximate to an image sensor 3004 and configured to provide power via a DC-DC converter 3006 having a LF oscillator 3002 .

[0154] Fig.31 is a block diagram of an auxiliary energy harvesting system 3100 having an image sensor 3104 that uses a DC-DC converter 3106 clocked by an HF oscillator 3102 to feed a voltage regulator 3108 in an energy harvesting mode to generate a supply voltage V sup .

[0155] The primary input voltage (energy) to the DC-DC converter 3006 is generated by the image sensor 3004 which is configured as an energy harvester. Using the LF oscillator 3002, the energy from Vaux is used to boost the voltage on Vsup to a sufficient level to allow the secondary high frequency (HF) oscillator 3102 to take over. Once in this normal operating configuration, the cold start is complete and the energy can be stored or used to drive a load (R load ),like Fig.31 Conventional operation can generate much more energy from the imager sensor 3004 , 3104 because it uses the high frequency oscillator 3102 to drive the DC-DC converter 3006 , 3106 .

[0156] During startup from complete power failure, light first falls on the image sensor while all supply voltage rails are essentially at ground potential. Once these rails reach threshold voltage levels, conventional conversion using the HF oscillator can begin, such as Fig.31 shown.

[0157] Fig.32 32 is a schematic diagram of an imaging system 3200 including an integrated circuit 3200 having a pixel array 3204 and a diode stack 3206 arranged adjacent to the pixel array 3204. The diode stack has: a first diode D1, wherein the anode is a P-well (PW) and the cathode is a deep N-well (DNW); a second diode D2, wherein the anode is a P-well (PW) and the cathode is a deep N-well (DNW), and the second diode D2 is connected in series with D1; and a series of series diodes is formed until the Nth diode D n , where the anode is a P-well (PW) and the cathode is a deep N-well (DNW). The current through D1 is I1, and the current through D2 is I2, which is equal to the current through I1 and the current through the substrate diode D R1 The leakage current I R1 In addition, through D n The current is I n , which is equal to the current through I2 (I1 + I R1 ) and through the substrate diode D R2 The leakage current I R2 .

[0158] Fig.32 One embodiment of an arrangement of auxiliary photodiode stacks around an energy harvesting (EH) image sensor based on a test IC is shown. The test IC is configured with nine photodiodes stacked to form a series connection. In other embodiments, the auxiliary diode arrangement may not be around the entire circumferential portion of the pixel array, but may be on one side of the pixel array, or on multiple sides of the pixel array. In addition, the test chip combines the pixel array and the auxiliary diodes in a monolithic manner, while in other embodiments, the auxiliary diodes may be on a separate chip such that the two chips are combined in a multi-chip module (MCM).

[0159] Fig.33 3300 is a cross-sectional view of an embodiment of two monolithic semiconductor structures S0 and S1 configured to capture light. The first structure S0 has three junctions, J11 between the N region and the P well (PW), J21 between the PW and the deep N well (DNW), and J31 between the P substrate (PSUB) and the DNW. These three junctions form three diodes D 01 , D 02 , D 03The structure includes interconnections such that D 03 and D 02 In parallel, and D 01 Reverse bias.

[0160] Fig.34 is a cross-sectional view 3400 of an alternative embodiment of two semiconductor structures S0 and S1 configured to capture light. Fig.33 The structure has a first structure S0 having three junctions, J11 between the N region and the P well (PW), J21 between the PW and the deep N well (DNW), and J31 between the P substrate (PSUB) and the DNW. These three junctions form three diodes D 01 , D 02 , D 03 The structure includes interconnections such that D 03 is forward biased, and D 02 and D 01 is reverse biased.

[0161] In the test chip, each photodiode in the stack is located in a dedicated individual deep N-well, such as Fig.33 and 34 The cross section of the structure in is shown in Figure 1. To account for the reverse saturation leakage current at each deep N-well-P substrate junction (I2, I3), the photodiodes lower in the stack are made larger. As we go up in the stack, the size of the photodiodes decreases, as shown in Figure 1. Fig.32 The lowest photodiode is larger because it must carry a larger (I1+I2+I3) current than the photodiode above it which carries the (I1+I2) current. Fig.32 The pyramid structure of the entire nine photodiode stack is shown in the schematic diagram of , and greatly improves the current drive capability of the generated Vaux supply range.

[0162] The diodes are sized approximately geometrically rounded to the nearest integer. Each photodiode in the stack consists of a group of unit cells. This allows for a high degree of flexibility in the layout of the stack in the peripheral area while maintaining the geometric ratio.

[0163] Fig.35 35 is a schematic diagram of an image sensor node 3500 having a peripheral diode 3502 and an image sensor 3504. The peripheral diode 3502 is configured to collect energy from light at the periphery of the image sensor 3504. The image sensor 3504 is configured to collect energy and capture an image. The system 3500 uses a low frequency (LF) oscillator 3506 to a DC-DC converter 3508 during cold start, and then switches to a high frequency (HF) oscillator during normal operation once sufficient power is achieved.

[0164] However, the power sequence must follow a clear order to prevent any unwanted leakage through the chip and ensure correct functionality. This is the sequence of steps for a cold start, such as Fig.35 shown.

[0165] To achieve energy autonomous operation, the IC is built so that the System 3500 starts using V when light first shines on the chip. AUX Supply rail. The test device delivered approximately 25 nW at 1.8 V in dim room lighting conditions (25 lux). Fig.35 The four-phase cold start sequence shown is described as follows:

[0166] First, the entire chip 3500 is power gated until V AUX rises above a certain threshold and asserts V AUXGD (V AUX _ GOOD )Signal.

[0167] Second, when V IN exceeds the open circuit voltage of the isolated pixel (V OC ) part, by V AUX The comparator that supplies power asserts V INGD (V IN_GOOD ). In other words, when V IN When the threshold level is exceeded.

[0168] Third, the ultra-low power, low frequency (LF) oscillator 3506 from V AUX The SC boost converter operates from the same rail as the SC boost converter.

[0169] Fourth, the SC boost converter converts V IN Raised to A VDD and D VDD Once the output rail is within regulation (e.g., 1%, 2%, 3%, 4%, 5% of the desired output voltage), the COLDST (Cold Start Complete) signal is asserted to start normal operation with the HF oscillator and the same boost converter. Fig.35 Normally open wake-up comparator A in IS Can have built-in weights or offsets to implement a built-in reference. AUX V asserts when it exceeds the threshold (~1.8 V) generated by the offset AUXGD . V AUXGD The associated PMOS load device introduces hysteresis.

[0170] A more detailed process follows these four steps:

[0171] Step 1: With incident light, Vaux from the photodiode stack climbs to a higher voltage. When it crosses some minimum threshold, the Vaux_Good signal is asserted. This turns on the power gate switch, and power from Vaux_Gated reaches all other parts of the chip. Until Vaux_Good is asserted, the rest of the chip does not get any power, and therefore, the only power consuming block in the entire chip is the ultra-low power Vaux comparator.

[0172] Step 2: After Vaux_Good is asserted, the input voltage of Vin from the imager pixel is compared to some reference. Once Vin reaches a stable voltage above some minimum value, Vin_Good is asserted.

[0173] Step 3: The assertion of both Vaux_Good and Vin_Good implies that we can run the bias current and LF oscillator from the Vaux_Gated supply at very low current and very low frequency.

[0174] Step 4: These low frequency clocks then drive the DC-DC converter to generate the output Vsup voltage. Vsup reaches the minimum defined value and asserts the cold start complete signal. This assertion then enables the normal high efficiency conversion mode using the HF oscillator.

[0175] Vin is continuously converted to Vsup with much higher efficiency and enables output load delivery. The output Vsup is regulated within a certain voltage band.

[0176] The advantage of this system and method is that it enables a cold start of a self-powered image sensor. This is achieved without using any additional batteries, supercapacitors, inductors or charge pumps in the circuit, and thus has cost and size advantages.

[0177] Each photodiode has two vertically stacked PN junctions that collect light: N diffusion-P well and P well-deep N well. Each photodiode is located in its own deep N well.

[0178] like Fig.32 , 33 As shown in Figures 34, there is a reverse photocurrent loss at each deep N-well-P substrate junction. In another embodiment, the size of the photodiodes in the stack is set in an approximately geometric series to solve the reverse current junction leakage between two consecutive photodiodes. This enables higher current delivery from the Vaux supply.

[0179] The photodiode size ratio is chosen to be <2 to supply deep N-well-P-substrate photocurrent losses while still keeping the area of ​​the auxiliary photodiode stack small enough to fit in the periphery of the pixel array.

[0180] Several small unit photodiodes are placed in parallel to create a larger photodiode. Smaller photodiodes can be placed in Fig.32 In a peripheral ring outside the pixel array shown.

[0181] This cold-start scheme ensures that each supply rail reaches its defined voltage level under all lighting conditions without any leakage current or loss of functionality.

[0182] When light first strikes the chip, there is no reference voltage to compare to Vaux, so Fig.36 A new skew comparator with an offset that can act as a reference is disclosed.

[0183] Also, a portion of the open circuit voltage (Voc) of the isolation photodiode is used as a reference for comparison with Vin, as Fig.37 shown.

[0184] Fig.35 The cold start sequence shown begins with Vaux generation, which has the following four steps.

[0185] Step 1: Vaux is the supply and input to the skew comparator, as Fig.36 shown. Fig.36 is a schematic diagram of a comparator 3600 with a built-in reference threshold for power-on reset (POR). When light first falls on the photodiode, Vaux is close to ground, and I L ~I R ~0. Due to the skewing dimension setting, a small Vaux is initially used. However, when Vaux climbs above a certain voltage level, I L >I R In this way, the reference voltage is built into the comparator.

[0186] Ultra-low power operation is achieved by a tail current source biased in deep subthreshold. Hysteresis in the threshold is introduced by skewing the load of the comparator according to the current Vaux_Good value. In the test chip, to provide an offset for the step in the comparator, V IN1 is set to 3*V AUX / 8, V IN2 is set to 5*V AUX / 8, and V BIAS is set to V AUX / 8, so that 0 < V BIAS < V IN1 < V IN2 < V AUX.

[0187] Step 2: When Vaux_Good is asserted, the power-gated Vaux_Gated supply enables the comparator to check the V IN The reference voltage for Vin_Good generation is implemented using a portion of the open circuit voltage (Voc) of the isolated photodiode, such as Fig.37 Voc is the maximum voltage reached by no-load Vin.

[0188] Fig.37 is a schematic diagram 3700 of a hysteresis comparator in which the reference voltage is generated by an isolated photodiode D1. The first comparator 3702 and the second comparator 3704 have reference voltage inputs from a voltage divider 3708 that is used to generate the reference voltage from the diode D1 voltage. The output of the first comparator 3702 is used to enable the flip-flop (Flip-Flop), while the output from the second comparator 3704 is used to drive the active low RESET of the flip-flop.

[0189] Step 3: After Vaux_Good and Vin_Good assert, low power current bias generation is implemented followed by non-overlapping clock generation using the LF oscillator.

[0190] Step 4: These non-overlapping clocks drive the DC-DC converter to generate a stable Vsup power rail. Once this rail is established, normal operation of the HF oscillator is used to deliver power to the load at a regulated voltage level.

[0191] Fig.38 is a graphical representation 3800 of measured voltage 3802 and logic level 3804 versus time for a cold started image sensor using a peripheral diode.

[0192] Fig.38 The figure shows the measured cold start sequence waveform. Once V AUX When it rises above 1.8 V, V AUXGD , and when V IN More than 0.7 V OC When V INGD Once DV is asserted DDGD and AV DDGD , the chip starts to operate normally and provides a regulated output voltage.

[0193] The program code that specifically implements the algorithms and / or methods described herein can be distributed separately or together as a program product in various different forms. The program code can be distributed using a computer-readable storage medium having computer-readable program instructions thereon to enable a processor to implement various aspects of one or more embodiments. Inherently non-transitory computer-readable storage media may include volatile and non-volatile, and removable and non-removable tangible media implemented in any method or technology for storing information, such as computer-readable instructions, data structures, program modules, or other data. Computer-readable storage media may also include RAM, ROM, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other solid-state storage technology, portable compact disk read-only memory (CD-ROM) or other optical storage devices, cassettes, tapes, disk storage devices or other magnetic storage devices, or any other medium that can be used to store the desired information and can be read by a computer. Computer-readable program instructions can be downloaded from a computer-readable storage medium to a computer, another type of programmable data processing device, or another device, or downloaded to an external computer or external storage device via a network.

[0194] Computer-readable program instructions stored in a computer-readable medium may be used to instruct a computer, other types of programmable data processing equipment, or other devices to operate in a particular manner so that the instructions stored in the computer-readable medium produce an article of manufacture including instructions for implementing the functions, actions, and / or operations specified in the flowchart or figure. In certain alternative embodiments, the functions, actions, and / or operations specified in the flowchart and figure may be reordered, processed serially, and / or processed concurrently consistent with one or more embodiments. In addition, any flowchart and / or figure may include more or fewer nodes or blocks than those illustrated consistent with one or more embodiments.

[0195] Although the entirety of the present invention has been illustrated by the description of various embodiments, and although these embodiments have been described in considerable detail, the applicant does not intend that the scope of the appended claims be constrained or in any way limited to such details. Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the present invention in its broader aspects is not limited to the specific details, representative devices and methods, and illustrative examples shown and described. Therefore, such details may be deviated from without departing from the spirit or scope of the general concept of the present invention.

Claims

1. A boost converter, comprising: a clock generator configured to output a clock signal; a switching converter configured to operate at a frequency based on a clock signal; a hysteretic controller configured to regulate outputs from SC Boost-1 and SC Boost-2 converters of the boost converter to generate an output voltage, the SC Boost-1 and SC Boost-2 converters being connected in a daisy-chain manner; and A power tracking module is configured to change a frequency control signal sent to the clock generator, the change in frequency being based on the current flowing into the output capacitor so that the charging time of the capacitor is minimized when the current is maximized.

2. The boost converter according to claim 1, wherein: The switching converter is a switched capacitor converter. 3 . The boost converter of claim 1 , further comprising a charging time-to-voltage converter configured to change a frequency control signal inversely to a change in charging time until a minimum charging time of the capacitor is detected.

4. The boost converter according to claim 3, wherein: The charge time-to-voltage converter includes first and second capacitors that are alternately charged such that the second capacitor buffers a boosted output while the first capacitor delivers charge to a load.

5. The boost converter of claim 4 further comprising asynchronous hill climbing logic, perturb and observe logic, and an up / down counter.

6. A method for adjusting a boost converter clock, comprising: Through the controller, Initialize the charging time variable; reducing a switching frequency of the boost converter; In response to the current charging time being less than the charging time variable, updating the charging time variable to continuously reduce the switching frequency of the boost converter until the current charging time exceeds the charging time variable; increasing the switching frequency of the boost converter; and In response to the current charging time being less than the charging time variable, the charging time variable is updated to continuously increase the switching frequency of the boost converter until the current charging time exceeds the charging time variable.

7. The method according to claim 6, wherein: The method includes the steps of alternately charging first and second capacitors such that the second capacitor buffers the boosted output while the first capacitor delivers charge to a load.

8. The method according to claim 6, wherein: The method includes varying a frequency control signal in response to a capacitor charging time.

9. The method according to claim 8, wherein: The frequency control signal changes inversely to the change in charging time until a minimum charging time of the capacitor is detected.

10. An apparatus for operating a hysteresis control feedback of a boost converter, comprising: a clock generator configured to output a clock signal; a switching converter configured to operate at a frequency based on the clock signal; a hysteretic controller configured to regulate outputs from SC Boost-1 and SC Boost-2 converters of the boost converter to generate an output voltage, the SC Boost-1 and SC Boost-2 converters being connected in a daisy-chain manner; and A power tracking module is configured to vary a frequency control signal sent to the clock generator.

11. The device according to claim 10, wherein: The apparatus includes a boost converter, which is a switched capacitor boost converter.

12. The device according to claim 10, wherein: The apparatus includes a boost converter including a first capacitor and a second capacitor configured to buffer the boost converter output in opposite phases.

13. The apparatus according to claim 10, wherein: The apparatus includes a boost converter including a voltage regulator configured to utilize a modified Dickson topology.

14. The apparatus according to claim 10, wherein: The device includes a boost converter, the boost converter including an asynchronous maximum output power tracking circuit, the asynchronous maximum output power tracking circuit including a capacitor group, a Schmitt trigger comparator and a hill climbing logic, the hill climbing logic configured to control the charging and resetting of capacitors in the capacitor group.

15. The device according to claim 14, wherein: The asynchronous maximum output power tracking circuit is configured to switch when a charging cycle ends.

16. The apparatus according to claim 10, wherein: The frequency variation is based on the current flowing into the output capacitor such that when the current is maximized, the charging time of the capacitor is minimized.

17. The apparatus according to claim 10, wherein: The device includes a transducer modeled as a Thevenin voltage source with an equivalent impedance.

18. The apparatus according to claim 10, wherein: The hysteresis controller is a ping-pong hysteresis controller.

19. The apparatus according to claim 10, wherein: The clock generator includes a state machine and one or more multiplexers.

20. The apparatus of claim 10, wherein: The power tracking module is a maximum output power tracking module.

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