Multi - stage driving data transmission circuit and data transmission method

Abstract

The present invention discloses a multi-stage drive data transmission circuit and a data transmission method. The multi-stage drive data transmission circuit includes: a first drive module and a second drive module; wherein, the first drive module includes: a first signal generation unit and a first tri-state driver; the second drive module includes: a second tri-state driver; a first input end of the second tri-state driver is coupled to an output end of the first tri-state driver; the first signal generation unit includes: a first input end, a second input end and an output end; an output end of the first signal generation unit is coupled to a second input end of the first tri-state driver; the first signal generation unit is configured to receive a first signal through its first input end, receive a first feedback signal of the first signal from the second drive module through its second input end, generate a first control signal with an effective signal width wider than that of the first signal according to the first signal and the first feedback signal, and provide the first control signal to the first tri-state driver.

Description

Technical Field

[0001] The present invention relates to three-state drive bus transmission technology, and more particularly, to a multi-level drive data transmission circuit and a data transmission method. Background Art

[0002] In semiconductor integrated circuits, it is a common technique to connect a three-state driver to a bus and use the three-state driver to drive the bus transmission.

[0003] The three-state output of the three-state driver is controlled by a control signal. When the control signal is valid, the device outputs in a normal logic state, that is, the input data is directly sent to the output terminal; when the control signal is invalid, the output is in a high-impedance state, which is equivalent to being disconnected from the connected circuit.

[0004] However, due to the variations in different processes, voltages, and temperatures, the control signal of the three-state driver may change significantly, resulting in too short an output drive time, an incomplete output signal, or chaos in consecutive data with different beats.

[0005] The above information disclosed in the background art section is only used to enhance the understanding of the background of the present invention, and thus it may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0006] In view of this, the present invention provides a multi-level drive data transmission circuit and a data transmission method.

[0007] Other features and advantages of the present invention will become apparent from the following detailed description, or will be learned in part through the practice of the present invention.

[0008] According to an aspect of the present invention, there is provided a multi-level drive data transmission circuit, including: a first drive module and a second drive module; wherein, the first drive module includes: a first signal generation unit and a first three-state driver; the second drive module includes: a second three-state driver; a first input end of the second three-state driver is coupled to an output end of the first three-state driver; the first signal generation unit includes: a first input end, a second input end, and an output end; the output end of the first signal generation unit is coupled to a second input end of the first three-state driver; the first signal generation unit is configured to receive a first signal through its first input end, receive a first feedback signal of the first signal from the second drive module through its second input end, generate a first control signal with an effective signal width wider than the first signal according to the first signal and the first feedback signal, and provide the first control signal to the first three-state driver.

[0009] According to an embodiment of the present invention, the first signal generating unit includes: a first RS latch, a first input terminal of the first signal generating unit is a set terminal of the first RS latch, a second input terminal of the first signal generating unit is a reset terminal of the first RS latch, and an output terminal of the first signal generating unit is a first output terminal of the first RS latch.

[0010] According to an embodiment of the present invention, the first signal generating unit includes: a first D flip-flop, a first input terminal of the first signal generating unit is a clock input terminal of the first D flip-flop, a second input terminal of the first signal generating unit is a reset terminal of the first D flip-flop, and an output terminal of the first signal generating unit is an output terminal of the first D flip-flop.

[0011] According to an embodiment of the present invention, the second driving module further includes: a signal shaping unit, including: an input terminal and an output terminal; the signal shaping unit is configured to receive the first signal through its input terminal, shape the first signal, and generate and output the first feedback signal through its output terminal.

[0012] According to an embodiment of the present invention, the signal shaping unit includes: an even number of cascaded first inverters.

[0013] According to an embodiment of the present invention, the first driving module further includes: a pulse signal generating unit, including: an input terminal and an output terminal, coupled to the first input terminal of the first signal generating unit through its output terminal, configured to receive the first signal, generate a pulse signal according to a rising edge of the first signal, and provide the pulse signal to the first signal generating unit through the first input terminal of the first signal generating unit.

[0014] According to an embodiment of the present invention, the pulse signal generating unit includes: an odd-stage gate circuit, a NAND gate, and a second inverter; wherein, the odd-stage gate circuit receives the first signal through its input terminal; the NAND gate receives the first signal through its first input terminal, is coupled to the output terminal of the odd-stage gate circuit through its second input terminal to receive the output signal of the odd-stage gate circuit, and is coupled to the input terminal of the second inverter through its output terminal; an output terminal of the second inverter is coupled to the first input terminal of the first signal generating unit.

[0015] According to an embodiment of the present invention, it further includes: a third driving module, including: a third tri-state driver; a first input end of the third tri-state driver is coupled to an output end of the second tri-state driver; the second driving module further includes: a second signal generating unit; the second signal generating unit includes: a first input end, a second input end and an output end; an output end of the second signal generating unit is coupled to a second input end of the second tri-state driver; the second signal generating unit is configured to receive the first signal through its first input end, receive a second feedback signal of the first signal from the third driving module through its second input end, generate a second control signal whose effective signal width is wider than that of the first signal according to the first signal and the second feedback signal, and provide the second control signal to the second tri-state driver.

[0016] According to an embodiment of the present invention, the second signal generating unit includes: a second RS latch, a first input end of the second signal generating unit is a set end of the second RS latch, a second input end of the second signal generating unit is a reset end of the second RS latch, and an output end of the second signal generating unit is a first output end of the second RS latch.

[0017] According to an embodiment of the present invention, the second signal generating unit includes: a second D flip-flop, a first input end of the second signal generating unit is a clock input end of the second D flip-flop, a second input end of the second signal generating unit is a reset end of the second D flip-flop, and an output end of the second signal generating unit is an output end of the second D flip-flop.

[0018] According to another aspect of the present invention, a multi-stage driving data transmission method is provided, including: respectively receiving a first signal and a feedback signal of the first signal from a next-stage driving module; and generating a control signal whose effective signal width is wider than that of the first signal according to the first signal and the feedback signal, and providing the control signal to a tri-state driver in the current-stage driving module.

[0019] According to an embodiment of the present invention, generating a control signal whose effective signal width is wider than that of the first signal according to the first signal and the feedback signal includes: respectively inputting the first signal and the feedback signal to a set end and a reset end of an RS latch, and using a signal at a first output end of the RS latch as the control signal.

[0020] According to an embodiment of the present invention, generating a control signal with an effective signal width wider than that of the first signal based on the first signal and the feedback signal includes: respectively inputting the first signal and the feedback signal to the clock input terminal and the reset terminal of a D flip-flop, using the signal output from the output terminal of the D flip-flop as the control signal, and inputting a fixed voltage signal to the data terminal of the D flip-flop.

[0021] According to an embodiment of the present invention, before receiving the feedback signal, the method further includes: in the next-stage driving module, shaping the first signal to obtain and output the feedback signal.

[0022] According to an embodiment of the present invention, before receiving the first signal, the method further includes: generating a pulse signal according to the rising edge of the first signal, and using the pulse signal as the first signal output.

[0023] According to the multi-stage driving data transmission circuit and the multi-stage driving data transmission method of the present invention, the control signal input to the tri-state driver can be processed. After sending the original control signal to the next-stage driving module, it is then fed back to the driving module of this stage. Due to the existence of the feedback path, a new control signal with an effective signal width wider than the original control signal can be generated based on the feedback control signal and the original control signal, thereby avoiding the problem that the data cannot be completely transmitted to the next-stage driving module due to insufficient effective time of the control signal.

[0024] It should be understood that the above general description and the following detailed description are only exemplary and do not limit the present invention. Brief Description of the Drawings

[0025] By referring to the accompanying drawings and describing its exemplary embodiments in detail, the above and other objects, features, and advantages of the present invention will become more apparent.

[0026] Figure 1 is a block diagram of a multi-stage driving data transmission circuit shown according to an exemplary embodiment.

[0027] Figure 2 is a schematic diagram of the first signal generation unit 101 shown according to an exemplary embodiment.

[0028] Figure 3 is a schematic diagram of the second signal generation unit 201 shown according to an exemplary embodiment.

[0029] Figure 4 is a block diagram of a pulse signal generation unit shown according to an exemplary embodiment.

[0030] Figure 5It is a flowchart of a multi - stage drive data transmission method shown according to an exemplary embodiment.

[0031] Figure 6 It is a schematic diagram of signal timing shown according to an example.

[0032] Figure 7 It is a schematic diagram of another first signal generation unit 101 shown according to an exemplary embodiment. Detailed implementation manners

[0033] Now, example embodiments will be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this invention will be more thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The drawings are only schematic illustrations of the present invention and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus their repeated description will be omitted.

[0034] In addition, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of the embodiments of the present invention. However, those skilled in the art will realize that the technical solutions of the present invention can be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, well - known structures, methods, devices, implementations, or operations are not shown or described in detail to avoid obscuring the various aspects of the present invention.

[0035] In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features.

[0036] As described above, the three - state driver is turned on during the valid period of the control signal to output the input data; it is turned off during the invalid period of the control signal, and the output is in a high - impedance state, and the data on the bus is held by the holding circuit. However, if the effective width of the control signal becomes too narrow due to reasons such as manufacturing process, operating voltage, and temperature, the turn - on time of the three - state driver may not be sufficient to transfer the data completely to the next - stage drive module, resulting in errors.

[0037] The embodiment of the present invention provides a multi-level drive data transmission circuit and a multi-level drive data transmission method, which can process the control signal input to the three-state driver, send the original control signal to the next-level drive module, and then feed it back to the drive module of this level. Due to the existence of the feedback path, a new control signal with an effective signal width wider than the original control signal can be generated according to the feedback control signal and the original control signal, thereby avoiding the problem that the data cannot be completely transmitted to the next-level drive module due to insufficient effective time of the control signal.

[0038] The following first describes the multi-level driving data transmission circuit provided by the embodiment of the present invention.

[0039] Figure 1 is a block diagram of a multi-stage driving data transmission circuit according to an exemplary embodiment.

[0040] refer to Figure 1 The multi-stage driving data transmission circuit 1 includes: a first driving module 10 and a second driving module 20 .

[0041] The first driving module 10 includes: a first signal generating unit 101 and a first three-state driver 102 . The second driving module 20 includes: a second three-state driver 202 .

[0042] The output terminal 102 c (data output terminal) of the first tri-state driver 102 is coupled to the first input terminal 202 a (data input terminal) of the second tri-state driver 202 via the bus Bus, and outputs the data output by the first driving module 10 to the second driving module 20 via the bus Bus.

[0043] The first signal generation unit 101 includes: a first input terminal 101a, a second input terminal 101b, and an output terminal 101c. The output terminal 101c of the first signal generation unit 101 is coupled to the second input terminal 102b (control signal input terminal) of the first tri-state driver 102. The first input terminal 101a of the first signal generation unit 101 is used to receive a first signal (such as a control signal in the data transmission circuit 1), and the second input terminal 101b is used to receive a first feedback signal of the first signal from the second driving module 20. That is, the leading edge of the original control signal (first signal) is used to turn on the first tri-state driver 102 to send a data signal. At the same time, the control signal is sent out together using the same signal line. After the first signal and the data signal are simultaneously transmitted to the second driving module 20, the first signal is fed back to the second input terminal 101b of the first signal generation unit 101 in the first driving module 10. After the first signal generation unit 101 receives the first signal and its feedback signal respectively, it generates a first control signal with an effective signal width wider than the first signal according to the first signal and its feedback signal, and provides it to the first tri-state driver 102 to control data transmission of the first tri-state driver 102.

[0044] Figure 2 is a schematic diagram of the first signal generation unit 101 shown according to an exemplary embodiment. As Figure 2 shown, in some embodiments, the first signal generation unit 101 can be implemented as an RS latch.

[0045] Among them, the first input terminal 101a of the first signal generation unit 101 is, for example, the set terminal (i.e., S terminal) of the RS latch, the second input terminal 101b is, for example, the reset terminal (i.e., R terminal) of the RS latch, and the output terminal 101c is, for example, the first output terminal (i.e., Q terminal) of the RS latch.

[0046] Due to the existence of the feedback path, even if the effective signal width of the first signal (such as the duration of 1) is not sufficient to completely transmit the data signal to the next driving module (such as the second driving module 20), but because a feedback signal is also input to the other input terminal of the RS latch, as long as the feedback signal is still 0, the RS latch will not be reset, so that the RS latch can still continue to output an effective signal, enabling the first tri-state driver 102 to continue to be in an open state, thereby ensuring the complete transmission of the data signal.

[0047] Figure 6 is a signal timing schematic diagram shown according to an example. As Figure 6As shown, when the effective width of the first signal is relatively narrow (such as t1 to t2 shown in the figure), since the feedback signal is 0 at the time of t2 to t3, the first control signal output from the first output terminal remains 1 at the time of t2 to t3, thereby extending the effective width of the first signal (as shown in the figure, the effective signal width is t1 to t3).

[0048] Figure 7 is a schematic diagram of another first signal generation unit 101 shown according to an exemplary embodiment. As Figure 7 shown, in some embodiments, the first signal generation unit 101 can also be implemented as a D flip-flop.

[0049] Among them, the first input terminal 101a of the first signal generation unit 101 is, for example, the clock signal terminal of the D flip-flop (i.e., the CLK terminal in the figure), and is used to receive the first signal; the second input terminal 101b is, for example, the reset terminal of the D flip-flop (i.e., the RESET terminal in the figure), and is used to receive the feedback signal; the output terminal 101c is, for example, the output terminal of the D flip-flop (i.e., the Q terminal in the figure), and outputs the first control signal.

[0050] In addition, a fixed voltage signal VDD can be input to the data terminal 101d (i.e., the DATA terminal in the figure) of the D flip-flop.

[0051] Similarly, due to the existence of the feedback path, even if the effective signal width of the first signal (such as the duration of being 1) is not sufficient to enable the data signal to be completely transmitted to the next driving module (such as the second driving module 20), but because the feedback signal is also input to the RESET input terminal of the D flip-flop, still taking Figure 6 as an example, at the time of t2 to t3, the feedback signal is 0 and the D flip-flop cannot be reset (RESET), that is, the current output state of the D flip-flop is latched. Therefore, the first control signal output from the first output terminal remains 1 at the time of t2 to t3, thereby extending the effective width of the first signal, and further ensuring the complete transmission of the data signal. Continuing to refer to Figure 1 , in some embodiments, the second driving module 20 may further include: a signal shaping unit 203. The signal shaping unit 203 includes: an input terminal 203a and an output terminal 203b, and is used to receive the first signal through its input terminal, shape the first signal, and then generate a first feedback signal output through its output terminal 203b. Since the quality of the first signal will become worse after a long bus transmission, shaping it through the signal shaping unit 203 can improve its signal quality, so as to ensure that the feedback signal has better signal quality when it is fed back to the first driving module 10.

[0052] In some embodiments, the signal shaping unit 203 may be implemented as an even number of cascaded inverters, which act as a buffer. After the first signal is transmitted through the bus, it is shaped by the buffer. Those skilled in the art should understand that Figure 1 The positions of the two cascaded inverters in Figure 1 are only examples. An even number of cascaded inverters can be cascaded together or can be cascaded at different positions in the second driving module 20 through wires, and are used to shape the received first signal.

[0053] It should be noted that when other driving modules are also coupled before the first driving module 10, the first driving module 10 also includes a signal shaping unit to provide a feedback signal of the shaped first signal to the previous-level driving module.

[0054] If it is a multi-level transmission path, in each level of the driving module, a signal generation unit as described above can be coupled to the control signal input terminal of the three-state driver. Refer to Figure 1 , in some embodiments, the data transmission circuit 1 may further include: a third driving module 30. The third driving module 30 includes: a third three-state driver 302. The first input terminal 302a (data input terminal) of the third three-state driver 302 is coupled to the output terminal 202c (data output terminal) of the second three-state driver 202 through a bus.

[0055] The second driving module 20 may further include: a second signal generation unit 201. The second signal generation unit 201 includes: a first input terminal 201a, a second input terminal 201b, and an output terminal 201c. The output terminal 201c of the second signal generation unit 201 is coupled to the second input terminal 202b (control signal input terminal) of the second three-state driver 202, and is used to receive the first signal through its first input terminal 201a and receive the second feedback signal of the first signal from the third driving module 30 through its second input terminal 201b, that is, after the first signal and the data signal are simultaneously transmitted to the third driving module 30, the first signal is fed back to the second input terminal 201b of the second signal generation unit 201 in the second driving module 20. After the second signal generation unit 201 receives the first signal and its feedback signal respectively, it generates a second control signal with an effective signal width wider than that of the first signal according to the first signal and its feedback signal, and is used to provide it to the second three-state driver 202 to control the data transmission of the second three-state driver 202.

[0056] Figure 3 FIG. is a schematic diagram of the second signal generation unit 201 shown according to an exemplary embodiment. As Figure 3 shown, in some embodiments, the second signal generation unit 201 can also be implemented as an RS latch.

[0057] Among them, if the first input terminal 201a of the second signal generation unit 201 is the set terminal (i.e., S terminal) of an RS latch, the second input terminal 201b is the reset terminal (i.e., R terminal) of the RS latch, and the output terminal 201c is the first output terminal (i.e., Q terminal) of the RS latch.

[0058] Due to the existence of the feedback path, even if the effective signal width (e.g., the duration of being 1) of the first signal is not sufficient to enable the data signal to be completely transmitted to the next driving module (e.g., the second driving module 20), but because a feedback signal is also input to the other input terminal of the RS latch, as long as the feedback signal remains 0, the RS latch will not be reset, so that the RS latch can still continue to output an effective signal, enabling the second tri-state driver 202 to continue to be in an open state, thus ensuring the complete transmission of the data signal.

[0059] Similarly, as Figure 6 shown, when the effective width of the second signal is relatively narrow (as shown as t1 - t2 in the figure), since the feedback signal remains 0 at the time of t2 - t3, the new second control signal output by the first output terminal remains 1 at the time of t2 - t3, thus extending the effective width of the second signal (as shown in the figure, the effective signal width is t1 - t3).

[0060] In addition, the second signal generation unit 201 can also be implemented as Figure 7 the D flip-flop shown, and its connection relationship and working principle will not be elaborated here.

[0061] Similarly, the third driving module 30 can further include: a signal shaping unit 303. The signal shaping unit 303 includes: an input terminal 303a and an output terminal 303b, and is used to receive the first signal through its input terminal, shape the first signal, and then generate a second feedback signal output through its output terminal 303b. Since the quality of the first signal will become worse after a long bus transmission, shaping it through the signal shaping unit 303 can improve its signal quality, so as to ensure that the second feedback signal has better signal quality when it is fed back to the second driving module 20.

[0062] In some embodiments, the signal shaping unit 303 can also be implemented as two coupled inverters, which act as a buffer. After the first signal passes through the bus transmission, it is shaped by the buffer.

[0063] In addition, as Figure 1 shown in, the third driving module 30 can also include the signal generation unit as described above, and its output is coupled to the second input terminal 302b (control signal input terminal) of the third tri-state driver 302. For the sake of simplifying the drawings, the signal generation unit is not shown in the figure.

[0064] It should be noted that Figure 1 in the data transmission circuit 1 in Figure 1 , the example where multiple driving modules are serially connected is taken, but the present invention is not limited thereto. For example, it can also be that two parallel connection branches of driving modules are serially connected to the next-level driving module through a bus, etc.

[0065] In some embodiments, in order to prevent the first signal input from having too large a width and causing abnormal operation of the RS latch, a pulse signal can be generated according to the rising edge of the first signal and used as the input to the first input terminal (101a or 201a) in the signal generating unit (101 or 201).

[0066] Figure 4 is a block diagram of a pulse signal generating unit shown according to an exemplary embodiment. With reference to Figure 1 and Figure 4 , the first driving module 10 may further include: a pulse signal generating unit 104. The pulse signal generating unit 104 includes: an input terminal 104a and an output terminal 104b, and is coupled to the first input terminal 101a of the first signal generating unit 101 through its output terminal 104b, for receiving the first signal, generating a pulse signal according to the rising edge of the first signal, and providing the pulse signal to the first signal generating unit 101 through the first input terminal 101a of the first signal generating unit 101.

[0067] As Figure 4 shown, the pulse signal generating unit 104 may, for example, include: an odd-stage gate circuit 1041, a NAND gate 1042, and an inverter 1043. Among them, the odd-stage gate circuit 1041 receives the first signal through its input terminal 1041a; the NAND gate 1042 receives the first signal through its first input terminal 1042a, is coupled to the output terminal 1041b of the odd-stage gate circuit 1041 through its second input terminal 1042b to receive the output signal of the odd-stage gate circuit 1041, and is coupled to the input terminal 1043a of the inverter 1043 through its output terminal 1042c; the output terminal 1043b of the inverter 1043 is coupled to the first input terminal 101a of the first signal generating unit 101.

[0068] Among them, the delay of the odd-stage gate circuit 1041 is the width of the pulse signal. By using this pulse signal generating unit 104 to generate a pulse signal as the input, the problem that the RS latch operates abnormally due to the too large width of the input first signal can be prevented.

[0069] Similarly, the above-mentioned pulse signal generating unit may also be included in the second driving module 20 and the third driving module 30. For the sake of simplifying the drawings, Figure 1 it is not shown in Figure 1 and will not be elaborated here.

[0070] In addition, the first signal generation unit 101 can also be implemented as a combination of an inverter and a falling-edge detection circuit, for example. The falling-edge detection circuit can be implemented, for example, by replacing the NAND gate 1042 shown in Figure 4 with a NOR gate and removing the inverter 1043. At the same time, in order to detect the rising edge of the first signal and generate a pulse signal based on the rising edge, an inverter needs to be added before the falling-edge detection circuit, so that the rising edge of the received first signal becomes a falling edge.

[0071] It should be clearly understood that the present invention describes how to form and use specific examples, but the principles of the present invention are not limited to any details of these examples. On the contrary, based on the teachings of the disclosed content of the present invention, these principles can be applied to many other embodiments.

[0072] The following are method embodiments of the present invention, which can be applied to the device embodiments of the present invention. For details not disclosed in the method embodiments of the present invention, please refer to the device embodiments of the present invention.

[0073] Figure 5 is a flowchart of a multi-level drive data transmission method shown according to an exemplary embodiment. Figure 5 The multi-level drive data transmission method shown can be applied to the above multi-level drive data transmission circuit.

[0074] Referring to Figure 5 , the multi-level drive data transmission method 2 includes:

[0075] In step S22, the first signal and the feedback signal of the first signal from the next-level drive module are received respectively.

[0076] For example, through Figure 1 the first signal generation unit 101 or the second signal generation unit 201 in

[0077] receive the first signal and the feedback signal of the first signal from the second drive module 20 or the third drive module 30.

[0078] In step S24, according to the first signal and the feedback signal, a control signal with an effective signal width wider than the first signal is generated, and the control signal is provided to the tri-state driver in the current-level drive module. Figure 1 For example, through the first signal generation unit 101 or the second signal generation unit 201 shown in

[0079] Due to the existence of the feedback path, a new control signal with a wider effective signal width than the original control signal can be generated based on the feedback control signal and the original control signal, thereby avoiding the problem that the data cannot be completely transmitted to the next-level driving module due to insufficient effective time of the control signal.

[0080] In some embodiments, step S24 can be further implemented through the following embodiments: respectively input the first signal and the feedback signal to the set terminal and the reset terminal of the RS latch, and use the signal at the first output terminal of the RS latch as the control signal.

[0081] In some embodiments, step 24 can be implemented through the following embodiments: respectively input the first signal and the feedback signal to the clock input terminal and the reset terminal of the D flip-flop, use the signal output from the output terminal of the D flip-flop as the control signal, and input a fixed voltage signal VDD to the data terminal of the D flip-flop.

[0082] In some embodiments, before step S22 of the multi-stage driving data transmission method 1, it can further include: in the next-level driving module, shaping the received first signal to obtain and output the feedback signal. For example, it can be shaped by the signal shaping unit 203 or the signal shaping unit 303 as shown in Figure 1 to shape the received first signal, so as to provide the first feedback signal or the second feedback signal to the first signal generation unit 101 or the second signal generation unit 102.

[0083] In some embodiments, before step S22 of the multi-stage driving data transmission method 1, it can further include: generating a pulse signal according to the rising edge of the first signal, and using the pulse signal as the first signal output.

[0084] In addition, it should be noted that the above-mentioned drawings are only schematic illustrations of the processes included in the method according to the exemplary embodiments of the present invention, rather than for limiting purposes. It is easy to understand that the processes shown in the above-mentioned drawings do not indicate or limit the time sequence of these processes. Additionally, it is also easy to understand that these processes can be executed synchronously or asynchronously in, for example, multiple modules.

[0085] The above specifically shows and describes the exemplary embodiments of the present invention. It should be understood that the present invention is not limited to the detailed structures, setting manners or implementation methods described herein; on the contrary, the present invention is intended to cover various modifications and equivalent settings included within the spirit and scope of the appended claims.

Claims

1. A multi-stage drive data transmission circuit, characterized in that it includes: A first drive module, including: a first signal generation unit and a first tri-state driver; and A second drive module, including: a second tri-state driver; the second drive module further includes: a signal shaping unit, including: an input end and an output end; the signal shaping unit is used to receive the first signal through its input end and shape the first signal; Wherein, the first input end of the second tri-state driver is coupled to the output end of the first tri-state driver; The first signal generation unit includes: a first input end, a second input end and an output end; the output end of the first signal generation unit is coupled to the second input end of the first tri-state driver; the first signal generation unit is used to receive a first signal through its first input end, receive a first feedback signal of the first signal from the second drive module through its second input end, generate a first control signal with an effective signal width wider than the first signal according to the first signal and the first feedback signal, and provide the first control signal to the first tri-state driver; The first drive module further includes: a pulse signal generation unit, including: an input end and an output end, coupled to the first input end of the first signal generation unit through its output end, used to receive the first signal, and provide a pulse signal to the first signal generation unit through the first input end of the first signal generation unit, the pulse signal generation unit includes an odd number of gate circuits, used to delay the first signal, the delay is the width of the pulse signal, the first signal is respectively transmitted to at least the pulse signal generation unit and the signal shaping unit, one transmission path enters the first input end of the first signal generation unit after passing through the pulse signal generation unit, and the other transmission path enters the second input end of the first signal generation unit after passing through the signal shaping unit.

2. The multi-stage drive data transmission circuit according to claim 1, characterized in that The first signal generation unit includes: a first RS latch, the first input end of the first signal generation unit is the set end of the first RS latch, the second input end of the first signal generation unit is the reset end of the first RS latch, and the output end of the first signal generation unit is the first output end of the first RS latch.

3. The multi-stage drive data transmission circuit according to claim 1, characterized in that The first signal generation unit includes: a first D flip-flop, the first input end of the first signal generation unit is the clock input end of the first D flip-flop, the second input end of the first signal generation unit is the reset end of the first D flip-flop, and the output end of the first signal generation unit is the output end of the first D flip-flop.

4. The multi-stage drive data transmission circuit according to any one of claims 1-3, characterized in that The signal shaping unit generates and outputs the first feedback signal through its output end.

5. The multi-stage drive data transmission circuit according to claim 1, characterized in that The signal shaping unit includes: an even number of first inverters connected in series with each other.

6. The multi-stage driving data transmission circuit according to any one of claims 1-3, wherein The pulse signal generating unit generates a pulse signal according to the rising edge of the first signal.

7. The multi-stage driving data transmission circuit according to claim 1, wherein The pulse signal generating unit further includes: a NAND gate and a second inverter; wherein, the odd-stage gate circuit receives the first signal through its input terminal; the NAND gate receives the first signal through its first input terminal, is coupled to the output terminal of the odd-stage gate circuit through its second input terminal to receive the output signal of the odd-stage gate circuit, and is coupled to the input terminal of the second inverter through its output terminal; the output terminal of the second inverter is coupled to the first input terminal of the first signal generating unit.

8. The multi-stage driving data transmission circuit according to any one of claims 1-3, wherein It further includes: A third driving module, including: a third tri-state driver; the first input terminal of the third tri-state driver is coupled to the output terminal of the second tri-state driver; the second driving module further includes: a second signal generating unit; the second signal generating unit includes: a first input terminal, a second input terminal and an output terminal; the output terminal of the second signal generating unit is coupled to the second input terminal of the second tri-state driver; the second signal generating unit is configured to receive the first signal through its first input terminal, receive a second feedback signal of the first signal from the third driving module through its second input terminal, generate a second control signal with an effective signal width wider than that of the first signal according to the first signal and the second feedback signal, and provide the second control signal to the second tri-state driver.

9. A multi-stage driving data transmission method, wherein It includes: Receiving a first signal and a feedback signal of the first signal from a next-stage driving module respectively; And Generating a control signal with an effective signal width wider than that of the first signal according to the first signal and the feedback signal, and providing the control signal to a tri-state driver in the current-stage driving module; Before receiving the feedback signal, the method further includes: shaping the first signal in the next-stage driving module to obtain and output the feedback signal; Before receiving the first signal, the method further includes: generating a pulse signal according to the rising edge of the first signal, and outputting the pulse signal as the first signal, the first signal is transmitted to at least a pulse signal generating unit and a signal shaping unit respectively, the pulse signal generating unit includes an odd-stage gate circuit for delaying the first signal, the delay is the width of the pulse signal, one transmission path enters the first input terminal of the first signal generating unit after passing through the pulse signal generating unit, and the other transmission path enters the second input terminal of the first signal generating unit after passing through the signal shaping unit.

10. The multi-stage driving data transmission method according to claim 9, wherein Generating a control signal with an active signal width wider than that of the first signal based on the first signal and the feedback signal, including: respectively inputting the first signal and the feedback signal to the set terminal and the reset terminal of an RS latch, and using the signal at the first output terminal of the RS latch as the control signal.

11. The multi-stage driving data transmission method according to claim 9, wherein Generating a control signal with an active signal width wider than that of the first signal based on the first signal and the feedback signal, including: respectively inputting the first signal and the feedback signal to the clock input terminal and the reset terminal of a D flip-flop, using the signal output from the output terminal of the D flip-flop as the control signal, and inputting a fixed voltage signal to the data terminal of the D flip-flop.

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