Semiconductor device and method of forming the same

Abstract

Various embodiments of the present disclosure relate to a semiconductor device and a method of forming the same. The semiconductor device includes an interconnect structure disposed over a semiconductor substrate. A dielectric structure is disposed over the interconnect structure. A first cavity and a second cavity are disposed in the dielectric structure. A microelectromechanical system (MEMS) substrate is disposed over the dielectric structure, wherein the MEMS substrate includes a first movable diaphragm overlying the first cavity and a second movable diaphragm overlying the second cavity. A first functional structure overlies the first movable diaphragm, wherein the first functional structure includes a first material having a first chemical composition. A second functional structure overlies the second movable diaphragm, wherein the second functional structure is laterally spaced from the first functional structure, and wherein the second functional structure includes a second material having a second chemical composition different from the first chemical composition.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a semiconductor device and a method of forming the same. Background Art

[0002] Microelectromechanical systems (MEMS) is a technology that integrates miniaturized mechanical and electromechanical components on an integrated chip. Micro-fabrication techniques are typically used to manufacture MEMS devices. In recent years, MEMS devices have been widely used. For example, MEMS devices are present in mobile phones (e.g., accelerometers, gyroscopes, digital compasses), pressure sensors, microfluidic components (e.g., valves, pumps), optical switches (e.g., (reflective) mirrors), imaging devices (e.g., micromachined ultrasonic transducers (MUT)), etc. Summary of the Invention

[0003] Embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes an interconnect structure disposed on a semiconductor substrate. A first dielectric structure is disposed on the interconnect structure. A first cavity is disposed in the first dielectric structure. A second cavity is disposed in the first dielectric structure and is laterally spaced apart from the first cavity. A microelectromechanical system (MEMS) substrate is disposed on the first dielectric structure, wherein the MEMS substrate includes a first movable diaphragm covering the first cavity and a second movable diaphragm covering the second cavity. A first functional structure covers the first movable diaphragm and the first cavity, wherein the first functional structure includes a first material having a first chemical composition. A second functional structure covers the second movable diaphragm and the second cavity, wherein the second functional structure is laterally spaced apart from the first functional structure, and wherein the second functional structure includes a second material having a second chemical composition different from the first chemical composition.

[0004] Embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes an interconnect structure disposed on a semiconductor substrate. A dielectric structure is disposed on the interconnect structure. A first cavity is disposed in the dielectric structure. A second cavity is disposed in the dielectric structure and is laterally spaced apart from the first cavity. A microelectromechanical systems (MEMS) substrate is disposed on the dielectric structure, wherein the MEMS substrate includes a first movable diaphragm covering the first cavity and a second movable diaphragm covering the second cavity. A sensing structure covers the first movable diaphragm and the first cavity, wherein a physical property of the sensing structure changes in response to an external stimulus. A passivation layer is disposed on the MEMS substrate, wherein the sensing structure vertically separates a first bottom surface of the passivation layer from an upper surface of the first movable diaphragm, and wherein a second bottom surface of the passivation layer covers the second movable diaphragm and is vertically disposed between the first bottom surface and the upper surface of the first movable diaphragm.

[0005] Embodiments of the present disclosure provide a method for forming a semiconductor device. The method includes: receiving an integrated circuit (IC) structure, wherein the IC structure includes an interconnect structure disposed on a semiconductor substrate of the IC structure. Forming a dielectric structure on the interconnect structure. Forming a first opening in the dielectric structure. Forming a second opening in the dielectric structure that is laterally spaced apart from the first opening. Bonding a microelectromechanical systems (MEMS) substrate to the dielectric structure, wherein bonding the MEMS substrate to the dielectric structure covers the first opening and the second opening, thereby forming a first cavity and a second cavity respectively. Forming a first functional structure on the MEMS substrate that covers the first cavity. Forming a second functional structure on the MEMS substrate that covers the second cavity, wherein the second functional structure has a different chemical composition from the first functional structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the embodiments of the present invention will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figure 1 A cross-sectional view showing some embodiments of a semiconductor device including different types of microelectromechanical systems (MEMS) devices.

[0008] Figure 2 Shows Figure 1 A cross-sectional view of some more detailed embodiments of the semiconductor device shown.

[0009] Figure 3 Shows Figure 2 Cross-sectional views of some other embodiments of semiconductor devices are shown.

[0010] Figure 4 Show Figure 2 Cross-sectional views of some other embodiments of semiconductor devices are shown.

[0011] Figures 5A to 5B Show Figure 4 Various views of some embodiments of regions of a semiconductor device are shown.

[0012] Figures 6A to 6B Show Figure 4 Various views of some other embodiments of regions of a semiconductor device are shown.

[0013] Figure 7 Show Figure 2 Cross-sectional views of some other embodiments of semiconductor devices are shown.

[0014] Figure 8 Show Figure 2 Cross-sectional views of some other embodiments of semiconductor devices are shown.

[0015] Figure 9 Show Figure 2 Cross-sectional views of some other embodiments of semiconductor devices are shown.

[0016] Figure 10 Show Figure 2 Simplified layout diagrams of some embodiments of semiconductor devices are shown.

[0017] Figures 11 to 22 Shown for forming Figure 4 A series of cross-sectional views illustrating some embodiments of methods of some embodiments of semiconductor devices are shown.

[0018] Figure 23 Flowcharts illustrating some embodiments of methods for forming semiconductor devices, including different types of micro-electromechanical systems (MEMS) devices.

[0019] [Explanation of Symbols]

[0020] 100: Semiconductor devices

[0021] 102: Integrated Circuit (IC) Structure

[0022] 104: Semiconductor substrate

[0023] 106: IC device

[0024] 108: Source / drain region

[0025] 110: Gate dielectric

[0026] 112: Gate electrode

[0027] 114: Inner structure

[0028] 116: First dielectric structure

[0029] 118: First conductive contact

[0030] 119: Second dielectric structure

[0031] 120: First via

[0032] 121: Second via

[0033] 122: First conductive line

[0034] 123a: Third conductive line

[0035] 123b: fourth conductive line

[0036] 124: Third dielectric structure

[0037] 126: Third via

[0038] 128a: First electrode

[0039] 128b: Second electrode

[0040] 130: Fourth dielectric structure

[0041] 132: First dielectric layer

[0042] 134: Second dielectric layer

[0043] 136: Microelectromechanical systems (MEMS) substrates

[0044] 138: Third dielectric layer

[0045] 140a: fifth conductive hole

[0046] 140b: sixth conductive hole

[0047] 142a: First through hole opening

[0048] 142b: Second through hole opening

[0049] 144a: Third conductive contact

[0050] 144b: fourth conductive contact

[0051] 146a: First MEMS device

[0052] 146b: Second MEMS device

[0053] 148a: First cavity

[0054] 148b: Second cavity

[0055] 148c1: Third cavity

[0056] 148c2: Fourth cavity

[0057] 148d1: Fifth cavity

[0058] 148d2: Sixth cavity

[0059] 150a: First movable diaphragm

[0060] 150b: Second movable diaphragm

[0061] 150c1: Third movable diaphragm

[0062] 150c2: Fourth movable diaphragm

[0063] 150d1: Fifth movable diaphragm

[0064] 150d2: Sixth movable diaphragm

[0065] 152a: First functional structure

[0066] 152b: Second functional structure

[0067] 152c1: Third functional structure

[0068] 152c2: Fourth functional structure

[0069] 152d1: Fifth functional structure

[0070] 152d2: Sixth functional structure

[0071] 202: Fourth dielectric layer

[0072] 204: Fifth dielectric layer

[0073] 206: Sixth dielectric layer

[0074] 208: First anti-degassing layer

[0075] 210: Seventh dielectric layer

[0076] 212: Eighth dielectric layer

[0077] 214: Ninth dielectric layer

[0078] 216: Second anti-degassing layer

[0079] 217: First MEMS structure

[0080] 218: Second MEMS structure

[0081] 220: Isolation trench

[0082] 222: First passivation layer

[0083] 224: Second passivation layer

[0084] 226: Getter structure

[0085] 302: Fluid communication channel

[0086] 402: Vent hole

[0087] 404: Plug

[0088] 406: Region

[0089] 602: Third passivation layer

[0090] 802: First doped region

[0091] 804: Second doped region

[0092] 1002a1: First MEMS unit

[0093] 1002a2: Second MEMS unit

[0094] 1002b1: Third MEMS unit

[0095] 1002b2: Fourth MEMS unit

[0096] 1202a: First opening

[0097] 1202b: Second opening

[0098] 1302a: First cavity opening

[0099] 1302b: Second cavity opening

[0100] 1304: Fluid communication channel opening

[0101] 1602: Second plurality of openings

[0102] 1902a: Third opening

[0103] 1902b: Fourth opening

[0104] 2300: Flowchart

[0105] 2302, 2304, 2306, 2308, 2310, 2312, 2314: Actions

[0106] A - A: Line

[0107] D: Minimum dimension

[0108] T: Thickness

[0109] Θ: Angle Detailed implementation manners

[0110] Embodiments of the present invention will now be described with reference to the drawings, where the same reference numerals are used throughout to refer to the same elements, and the structures shown are not necessarily drawn to scale. It should be understood that this detailed implementation manner and the corresponding drawings in no way limit the scope of the present disclosure, and the detailed implementation manner and the drawings merely provide several examples to illustrate some ways in which the concepts of the embodiments of the present invention can be implemented.

[0111] The present disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature on or above a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. Additionally, the present disclosure may reuse reference numerals and / or letters in various examples. This reuse is for the purposes of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0112] Furthermore, in this document, for ease of description, spatial relative terms such as "beneath", "below", "lower", "above", "upper", etc. may be used to describe the relationship of one element or feature shown in the drawings to another (other) element or feature. The spatial relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the drawings. The device may also have other orientations (rotated 90 degrees or other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0113] In some embodiments, a semiconductor device (e.g., an integrated chip) includes a microelectromechanical systems (MEMS) device. The MEMS device includes a cavity and a movable diaphragm. The configuration (e.g., the structural configuration) of the MEMS device depends on the type of the MEMS device. For example, if the MEMS device is a capacitive micromachined ultrasonic transducer (CMUT), the MEMS device has a first configuration corresponding to the CMUT, while on the other hand, if the MEMS device is a piezoelectric micromachined ultrasonic transducer (PMUT), the MEMS device has a second configuration corresponding to the PMUT that is different from the first configuration. It should be understood that CMUTs and PMUTs are not the only types of MEMS devices that have different configurations, but there can be differences among many other types of MEMS devices, where the other types of MEMS devices include, for example, CMUTs, PMUTs, contact ultrasonic MEMS sensors (e.g., fingerprint sensors), non-contact ultrasonic MEMS sensors (e.g., gesture sensors), resonant mechanical MEMS devices (e.g., radio frequency (RF) switches, RF filters, etc.), pressure sensors, humidity sensors, fluid sensors (e.g., gas composition sensors), biosensors (e.g., MEMS-based glucose sensors), IR sensors (e.g., IR detection sensors, IR image sensors, etc.).

[0114] One difference in the configurations of different types of MEMS devices is the difference in the chemical composition of the functional structure overlying the movable diaphragm. For example, if the MEMS device is an infrared (IR) sensor, the MEMS device may have a first functional structure with a first chemical composition overlying the movable diaphragm of the MEMS device. On the other hand, if the MEMS device is a PMUT, the MEMS device may have a second functional structure with a second chemical composition different from the first chemical composition overlying the movable diaphragm of the MEMS device. It should be understood that the differences in the configurations among different types of MEMS devices are not limited to the differences in the chemical composition of the functional structure, but there can be other types of differences among different types of MEMS devices, such as the difference in the doping concentration of the movable diaphragm, the presence or absence of the functional structure, etc.

[0115] Generally, a semiconductor device only includes multiple MEMS devices of the same type. For example, if a semiconductor device includes CMUTs, the semiconductor device will only include CMUTs. On the other hand, if a semiconductor device includes PMUTs, the semiconductor device will only include PMUTs. Therefore, it is desirable to make a single semiconductor device that includes different types of MEMS devices to reduce manufacturing costs, reduce package size, reduce power consumption, etc.

[0116] Various embodiments of the present disclosure relate to a semiconductor device that includes different types of MEMS devices. The semiconductor device includes an interconnect structure disposed over a semiconductor substrate. A dielectric structure is disposed over the interconnect structure. A microelectromechanical system (MEMS) substrate is disposed over the dielectric structure. A first MEMS device is disposed over the semiconductor substrate. The first MEMS device includes a first cavity disposed in the dielectric structure and a first movable diaphragm of the MEMS substrate that overlies the first cavity. In addition, the first MEMS device includes a first functional structure that overlies the first movable diaphragm and the first cavity. The first functional structure includes a first material having a first chemical composition. A second MEMS device is disposed over the semiconductor substrate and is laterally spaced from the first MEMS device. The second MEMS device includes a second cavity disposed in the dielectric structure and a second movable diaphragm of the MEMS substrate that overlies the second cavity. In addition, the second MEMS device includes a second functional structure that overlies the second movable diaphragm and the second cavity. The second functional structure includes a second material having a second chemical composition different from the first chemical composition.

[0117] Since the second material has a chemical composition different from that of the first material, the physical properties of the first functional structure can change in response to a first external stimulus, while the physical properties of the second functional structure can change in response to a second stimulus different from the first stimulus. Therefore, the first MEMS device is a first type of MEMS device, and the second MEMS device is a second type of MEMS device different from the first type. Thus, the semiconductor device includes different types of MEMS devices, which can reduce manufacturing costs, reduce package size, reduce power consumption, etc.

[0118] Figure 1 A cross-sectional view showing some embodiments of a semiconductor device 100 that includes different types of microelectromechanical system (MEMS) devices.

[0119] As Figure 1As shown, semiconductor device 100 includes an integrated circuit (IC) structure 102. The IC structure 102 includes a semiconductor substrate 104. The semiconductor substrate 104 can include any type of semiconductor body (e.g., monocrystalline silicon / complementary metal-oxide-semiconductor (CMOS) substrate, silicon-germanium (SiGe), silicon on insulator (SOI), etc.).

[0120] In some embodiments, one or more IC devices 106 are disposed on / above the semiconductor substrate 104. The IC devices 106 can be, for example, or include active electronic devices (e.g., transistors), passive electronic devices (e.g., resistors, capacitors, inductors, fuses, etc.), some other electronic devices, or a combination of the foregoing. For example, one of the IC devices 106 can be a metal-oxide-semiconductor field-effect transistor (MOSFET), which includes a pair of source / drain regions 108 disposed in the semiconductor substrate 104, a gate dielectric 110 disposed above the semiconductor substrate 104 and between the source / drain regions 108, and a gate electrode 112 disposed above the semiconductor substrate 104 and covering the gate dielectric 110. For clarity, only some of the IC devices 106 are specifically labeled. In still other embodiments, the IC structure 102 is a complementary metal-oxide-semiconductor (CMOS) structure, and the IC devices 106 are part of a CMOS circuit.

[0121] The IC structure 102 includes an interconnect structure 114, a first dielectric structure 116, a second dielectric structure 119, a third dielectric structure 124, and a plurality of electrodes 128 disposed above the semiconductor substrate 104 and the IC devices 106. The interconnect structure 114 includes one or more first conductive contacts 118, one or more first vias 120, one or more first conductive lines 122, a plurality of second vias 121, a plurality of second conductive lines 123, and a plurality of third vias 126. The first conductive contacts 118, the first vias 120, and the first conductive lines 122 are embedded in the first dielectric structure 116. In some embodiments, the first conductive contacts 118, the first vias 120, and the first conductive lines 122 are referred to as a CMOS interconnect structure. The CMOS interconnect structure interconnects the IC devices 106 together in a predefined pattern.

[0122] The second dielectric structure 119 is disposed over the first dielectric structure 116, the first conductive contact 118, the first via 120, and the first conductive line 122. The second via 121 and the second conductive line 123 are embedded in the second dielectric structure 119. The third dielectric structure 124 is disposed over the second dielectric structure 119, the second via 121, and the second conductive line 123. The third via 126 and the electrode 128 are embedded in the third dielectric structure 124.

[0123] The interconnect structure 114 electrically couples the IC device 106 to the electrode 128. For example, the interconnect structure 114 electrically couples one or more of the IC devices 106 to the first electrode 128a of the electrodes 128, and / or the interconnect structure 114 electrically couples one or more of the IC devices 106 to the second electrode 128b of the electrodes 128. For clarity, only some of the first conductive contacts 118, some of the first vias 120, some of the first conductive lines 122, some of the second vias 121, some of the second conductive lines 123, some of the third vias 126, and some of the electrodes 128 are specifically labeled.

[0124] The first conductive contact 118, the first via 120, the first conductive line 122, and / or the third via 126 can be, for example, or include metal (such as copper (Cu), aluminum (Al), tungsten (W), etc.), metal nitride (such as titanium nitride (TiN)), polysilicon (such as doped polysilicon), other conductive materials, or a combination of the foregoing. The second via 121 and the second conductive line 123 can include, for example, metal (such as Al, Cu, aluminum-copper (AlCu), titanium (Ti), silver (Ag), gold (Au), etc.), metal nitride (such as TiN), other conductive materials, or a combination of the foregoing. The electrode 128 can be, for example, or include metal (such as Al, Cu, AlCu, Ti, etc.), metal nitride (such as TiN), other conductive materials, or a combination of the foregoing. The first dielectric structure 116, the second dielectric structure 119, and the third dielectric structure 124 include one or more stacked dielectric layers, and the one or more stacked dielectric layers can respectively include a low dielectric constant (low-k) dielectric (such as a dielectric material having a dielectric constant less than about 3.9), an oxide (such as silicon dioxide (SiO2)), etc.

[0125] A fourth dielectric structure 130 is disposed over the interconnect structure 114 and the third dielectric structure 124. The fourth dielectric structure 130 includes a first dielectric layer 132 and a second dielectric layer 134. The second dielectric layer 134 is disposed over the first dielectric layer 132. In some embodiments, the first dielectric layer 132 covers the electrode 128.

[0126] The first dielectric layer 132 can be, for example, or include a nitride (e.g., silicon nitride (SiN)), an oxide (e.g., SiO2), a oxynitride (e.g., silicon oxynitride (SiO X N Y )), other dielectric materials, or a combination of the foregoing. The second dielectric layer 134 can be, for example, or include an oxide (e.g., SiO2), a nitride (e.g., SiN), a oxynitride (e.g., SiO X N Y ), other dielectric materials, or a combination of the foregoing. In some embodiments, the first dielectric layer 132 can be a different dielectric material from the second dielectric layer 134. For example, the first dielectric layer 132 can be SiN, and the second dielectric layer 134 can be SiO2. Although the fourth dielectric structure 130 is shown as including the first dielectric layer 132 and the second dielectric layer 134, it should be understood that the fourth dielectric structure 130 can include any number of dielectric layers.

[0127] A microelectromechanical systems (MEMS) substrate 136 is disposed over the fourth dielectric structure 130 and the IC structure 102. In some embodiments, the MEMS substrate 136 is disposed on the fourth dielectric structure 130. In still other embodiments, there is a bonding interface at the interface between the MEMS substrate 136 and the fourth dielectric structure 130. For example, in some embodiments, the MEMS substrate 136 is bonded to the fourth dielectric structure 130 by a bonding process (e.g., fusion bonding), thereby forming a bonding interface at the interface between the MEMS substrate 136 and the fourth dielectric structure 130. The MEMS substrate 136 can be, for example, or include a semiconductor material (e.g., polysilicon, amorphous silicon, single-crystalline silicon, SiGe, Ge, etc.), a metal (e.g., Al, Cu, AlCu), an oxide (e.g., SiO2), a nitride (e.g., SiN), other suitable MEMS substrates, or a combination of the foregoing. In some embodiments in which the MEMS substrate 136 is or includes a semiconductor material, the semiconductor material can be doped or undoped. In yet other embodiments, the MEMS substrate 136 is a single semiconductor structure including a semiconductor material.

[0128] The third dielectric layer 138 is disposed over the MEMS substrate 136 and the fourth dielectric structure 130. A plurality of fourth vias 140 vertically extend through the third dielectric layer 138, the MEMS substrate 136, the fourth dielectric structure 130, and the third dielectric structure 124 to contact at least one of the second conductive lines 123 such that the fourth vias 140 are electrically coupled to the interconnect structure 114. For example, a fifth via 140a, which is one of the fourth vias 140, vertically extends through the third dielectric layer 138, the MEMS substrate 136, the fourth dielectric structure 130, and the third dielectric structure 124 to contact a third conductive line 123a, which is one of the second conductive lines 123, such that the fifth via 140a is electrically coupled to the interconnect structure 114. Additionally, a sixth via 140b, which is another one of the fourth vias 140, vertically extends through the third dielectric layer 138, the MEMS substrate 136, the fourth dielectric structure 130, and the third dielectric structure 124 to contact a fourth conductive line 123b, which is another one of the second conductive lines 123, such that the sixth via 140b is electrically coupled to the interconnect structure 114. The fourth vias 140 are laterally spaced apart from each other. In some embodiments, the fourth vias 140 are electrically isolated from each other. In still other embodiments, the fourth vias 140 laterally extend over the upper surface of the third dielectric layer 138.

[0129] The fourth vias 140 line a plurality of via openings 142, respectively. For example, the fifth via 140a lines a first via opening 142a, which is one of the via openings 142, and the sixth via 140b lines a second via opening 142b, which is another one of the via openings 142. The via openings 142 are disposed in the third dielectric layer 138, the MEMS substrate 136, the fourth dielectric structure 130, and the third dielectric structure 124. The via openings 142 vertically extend through the third dielectric layer 138, the MEMS substrate 136, the fourth dielectric structure 130, and the third dielectric structure 124 to expose one or more of the second conductive lines 123. For example, the first via opening 142a vertically extends through the third dielectric layer 138, the MEMS substrate 136, the fourth dielectric structure 130, and the third dielectric structure 124 to expose the third conductive line 123a. The via openings 142 are at least partially defined by the third dielectric layer 138, the MEMS substrate 136, the fourth dielectric structure 130, and the second conductive lines 123. For example, the sidewalls of the first via opening 142a are defined by the sidewalls of the third dielectric layer 138, the sidewalls of the MEMS substrate 136, the sidewalls of the fourth dielectric structure 130, and the sidewalls of the third dielectric structure 124, and the bottom surface of the first via opening 142a is at least partially defined by the upper surface of the third conductive line 123a.

[0130] A plurality of second conductive contacts 144 are disposed over the MEMS substrate 136 and the third dielectric layer 138. For example, a third conductive contact 144a, which is one of the second conductive contacts 144, and a fourth conductive contact 144b, which is another one of the second conductive contacts 144, are disposed over the MEMS substrate 136 and the third dielectric layer 138. In some embodiments, the second conductive contacts 144 extend through the third dielectric layer 138 and contact the MEMS substrate 136. In still other embodiments, the second conductive contacts 144 are electrically coupled to the MEMS substrate 136. For clarity, only some of the second conductive contacts 144 are specifically labeled. The second conductive contacts 144 can be electrically coupled to the interconnect structure 114 via the fourth vias 140. For example, the third conductive contact 144a is electrically coupled to a fifth via 140a, and the fourth conductive contact 144b is electrically coupled to a sixth via 140b.

[0131] The third dielectric layer 138 can be, for example, or include an oxide (e.g., SiO2), a nitride (e.g., SiN), a oxynitride (e.g., SiO X N Y )), other dielectric materials, or a combination of the foregoing. The fourth vias 140 can be, for example, or include a metal (e.g., Al, Cu, AlCu, Ti, Ag, Au, etc.), a metal nitride (e.g., TiN), other conductive materials, or a combination of the foregoing. The second conductive contacts 144 can be, for example, or include a metal (e.g., Al, Cu, AlCu, Ti, Ag, Au, etc.), a metal nitride (e.g., TiN), other conductive materials, or a combination of the foregoing. In some embodiments, the fourth vias 140 and the second conductive contacts 144 are of the same material. In still other embodiments, the fourth vias 140 can have a thickness between about 0.05 micrometer (μm) and about 1 micrometer. In yet other embodiments, the second conductive contacts 144 can have a thickness between about 0.05 micrometer and about 1 micrometer.

[0132] The semiconductor device 100 includes a plurality of MEMS devices 146 disposed over a semiconductor substrate 104 and a second dielectric structure 119. The plurality of MEMS devices 146 are laterally spaced apart from each other. The plurality of MEMS devices 146 respectively include a first plurality of cavities 148, respectively include a first plurality of movable diaphragms 150, and respectively include electrodes 128. The cavities 148 are laterally spaced apart from each other. The movable diaphragms 150 are laterally spaced apart from each other. The movable diaphragms 150 are portions of the MEMS substrate 136 configured to move (e.g., flex) in response to one or more stimuli (e.g., pressure, voltage, etc.). In some embodiments, the electrodes 128 are laterally spaced apart from each other. For clarity, only some of the MEMS devices 146, some of the cavities 148, and some of the movable diaphragms 150 are specifically labeled. [[ID=I]]

[0133] For example, the MEMS device 146 includes a first MEMS device 146a and a second MEMS device 146b. The first MEMS device 146a is laterally spaced apart from the second MEMS device 146b. The first MEMS device 146a includes a first cavity 148a among the cavities 148, a first movable diaphragm 150a among the movable diaphragms 150, and a first electrode 128a. The second MEMS device 146b includes a second cavity 148b among the cavities 148, a second movable diaphragm 150b among the movable diaphragms 150, and a second electrode 128b. The first cavity 148a is laterally spaced apart from the second cavity 148b. The first movable diaphragm 150a is laterally spaced apart from the second movable diaphragm 150b.

[0134] Each of the MEMS devices 146 is a different type of MEMS device. For example, the first MEMS device 146a is a first type of MEMS device, and the second MEMS device 146b is a second type of MEMS device different from the first type of MEMS device. The MEMS devices 146 can be, for example, capacitive micromachined ultrasonic transducers (CMUTs), piezoelectric micromachined ultrasonic transducers (PMUTs), contact-type ultrasonic MEMS sensors (e.g., fingerprint sensors), non-contact-type ultrasonic MEMS sensors (e.g., gesture sensors), resonant-type mechanical MEMS devices (e.g., radio frequency (RF) switches, RF filters, etc.), pressure sensors, humidity sensors, fluid sensors (e.g., gas composition sensors), biosensors (e.g., MEMS-based glucose sensors), IR sensors (e.g., IR detection sensors, IR image sensors, etc.), or other types of MEMS devices. For example, the first MEMS device 146a can be an IR detection sensor, and the second MEMS device 146b can be any other type of MEMS device other than an IR detection sensor (e.g., a CMUT, a different type of IR sensor). Since the semiconductor device 100 includes different types of MEMS devices, the semiconductor device 100 can reduce manufacturing costs, reduce package size, reduce power consumption, etc.

[0135] The MEMS devices 146 have different configurations (e.g., structural configurations) depending on the respective MEMS device types of the MEMS devices 146. For example, the first MEMS device 146a has a first configuration depending on the type of the first MEMS device 146a (e.g., an IR detection sensor), and the second MEMS device 146b has a second configuration different from the first configuration depending on the type of the second MEMS device 146b (e.g., a CMUT). Some embodiments of different types of MEMS devices with different configurations will be described in more detail herein.

[0136] In some embodiments, the MEMS devices 146 respectively include functional structures 152. The functional structures 152 respectively overlie the movable diaphragms 150 of the MEMS devices 146. In still other embodiments, the functional structures 152 can be laterally spaced apart. For example, the first MEMS device 146a includes a first functional structure 152a overlying the first movable diaphragm 150a, and the second MEMS device 146b includes a second functional structure 152b overlying the second movable diaphragm 150b. The first functional structure 152a and the second functional structure 152b are laterally spaced apart. In some embodiments, the bottommost surfaces of the functional structures 152 are substantially coplanar. For example, the bottommost surface of the first functional structure 152a and the bottommost surface of the second functional structure 152b are substantially coplanar.

[0137] The physical properties of the functional structure 152 change respectively in response to being exposed to a stimulus. For example, the physical properties of the first functional structure 152a change in response to being exposed to a first stimulus, and the physical properties of the second functional structure 152b change in response to being exposed to a second stimulus. In some embodiments, the type of MEMS device depends at least in part on the physical properties of the functional structure 152 that change in response to a stimulus and / or the stimulus that causes the physical properties of the functional structure 152 to change. For example, if the physical properties of the first functional structure 152a change in response to being exposed to IR, then the first MEMS device 146a is an IR sensor. Further, if the first MEMS device 146a is configured to detect IR, then the IR sensor is an IR detection sensor. On the other hand, if the first MEMS device 146a is configured to generate an image based on IR, then the first MEMS device 146a is an IR image sensor. It should be understood that the type of MEMS device can depend on other characteristics of the MEMS device 146 (e.g., the operating principle, such as a thermoelectric IR sensor, a pyroelectric IR sensor, a bolometer IR sensor, etc.).

[0138] In some embodiments, the physical properties of the functional structure 152 that change in response to a stimulus and / or the stimulus that causes the physical properties of the functional structure 152 to change depend at least in part on the chemical composition of the functional structure. For example, if the first MEMS device 146a is an IR sensor, then the first functional structure 152a can be or include an infrared sensitive material, and if the second MEMS device 146b is a PMUT, then the second functional structure 152b can be or include a piezoelectric material. Thus, the configurations of different types of MEMS devices can be different in terms of the chemical composition of their respective functional structures.

[0139] The MEMS device 146 can be a MEMS sensor, a MEMS actuator, a MEMS transceiver, or a combination of the foregoing. For example, if the first MEMS device 146a is a MEMS sensor, the first MEMS device 146a is configured to sense a change in the physical properties of the first functional structure 152a. In some embodiments, the shape of the first functional structure 152a can change in response to being exposed to a first stimulus (e.g., an electrical signal (e.g., voltage), a fluid (e.g., gas), a biological element (e.g., blood), radiation (e.g., IR), etc.). The change in the shape of the first functional structure 152a can deflect the first movable diaphragm 150a, causing the first MEMS device 146a to output an electrical signal corresponding to the distance by which the first movable diaphragm 150a is spaced apart from the first electrode 128a (e.g., due to a change in the capacitance between the first movable diaphragm 150a and the first electrode 128a). The electrical signal can be output via the first electrode 128a and analyzed by one or more of the IC devices 106. In other embodiments, the change in the physical properties can change the capacitance between the first functional structure 152a and the first electrode 128a (e.g., by changing the voltage of the first functional structure 152a due to the change in the physical properties).

[0140] In some embodiments, the shape of the second functional structure 152b can change in response to being exposed to a second stimulus (e.g., an electrical signal (e.g., voltage), a fluid (e.g., gas), a biological element (e.g., blood), radiation (e.g., IR), etc.). The change in the shape of the second functional structure 152b can deflect the second movable diaphragm 150b, causing the second MEMS device 146b to output an electrical signal corresponding to the distance by which the second movable diaphragm 150b is spaced apart from the second electrode 128b (e.g., due to a change in the capacitance between the second movable diaphragm 150b and the second electrode 128b). The electrical signal can be output via the second electrode 128b and analyzed by one or more of the IC devices 106. In other embodiments, the change in the physical properties can change the capacitance between the second functional structure 152b and the second electrode 128b (e.g., by changing the voltage of the second functional structure 152b due to the change in the physical properties). In still other embodiments, if the MEMS device 146 is a MEMS sensor, the functional structure 152 can be referred to as a sensing structure.

[0141] If the first MEMS device 146a is a MEMS actuator, a change in the physical properties of the first functional structure 152a causes the first MEMS device to output an action (e.g., mechanical movement, magnetic field, heat, etc.). If the first MEMS device 146a is a MEMS transducer (e.g., a CMUT), the first MEMS device 146a can operate as a receiver (e.g., a MEMS sensor) and a transmitter (e.g., a MEMS actuator) to output an action and sense a response to the action. It should be understood that MEMS sensors, MEMS actuators, and MEMS transceivers can be different types of MEMS devices.

[0142] The functional structure 152 can be, for example, or include a piezoelectric material (e.g., molybdenum (Mo), lead zirconate titanate (PZT), aluminum nitride (AlN), zinc oxide (ZnO), etc.), a bio-sensitive material (e.g., a biometric component disposed on a metal (e.g., Au, Ag, platinum (Pt), etc.) (or a part thereof)), an IR-sensitive material (e.g., vanadium oxide (VOx), mercury cadmium telluride (HgCdTe), silicon (Si), cadmium zinc telluride (CdZnTe), etc.), a polymer (e.g., polyimide, SU-8, negative / positive photoresist, etc.), etc. In some embodiments, if the first functional structure 152a is a piezoelectric material, the first MEMS device 146a can be a PMUT; if the first functional structure 152a is a bio-sensitive material, the first MEMS device 146a can be a biosensor; if the first functional structure 152a is an IR-sensitive material, the first MEMS device 146a can be an IR sensor; and if the first functional structure 152a is a polymer, the first MEMS device 146a can be other types of MEMS sensors (e.g., pressure sensors, gas sensors, humidity sensors, etc.).

[0143] Therefore, it should be understood that in some embodiments, the first functional structure 152a is or includes a first type of material, while the second functional structure 152b is not (or does not include) the first type of material. For example, the first functional structure 152a is (or includes) an IR-sensitive material, and the second functional structure 152b is not (or does not include) an IR-sensitive material, the first functional structure 152a is (or includes) a piezoelectric material, and the second functional structure 152b is not (or does not include) a piezoelectric material, the first functional structure 152a is (or includes) a bio-sensitive material, and the second functional structure 152b is not (or does not include) a bio-sensitive material, the first functional structure 152a is (or includes) a polymer, and the second functional structure 152b is not (or does not include) a polymer, and so on.

[0144] In some embodiments, the functional structures 152 may each have a thickness between about 0.0005 microns and about 50 microns. If the functional structures 152 have a thickness less than about 0.0005 microns, the MEMS device 146 may not be able to sense a change in the physical properties of the functional structures 152 (and / or may not be able to cause a change in the physical properties of the functional structures 152). If the functional structures 152 have a thickness greater than about 50 microns, the cost of manufacturing the semiconductor device 100 may increase without a significant benefit. More specifically, if the functional structures 152 comprise a polymer, the functional structures 152 may have a thickness between about 0.0005 microns and about 10 microns; if the functional structures 152 comprise an IR-sensitive material, the functional structures 152 may have a thickness between about 0.1 microns and about 0.2 microns; and if the functional structures 152 comprise a piezoelectric material, the functional structures 152 may have a thickness between about 0.05 microns and about 50 microns.

[0145] If the functional structures 152 comprise a polymer and have a thickness less than about 0.0005 microns, the MEMS device 146 may not be able to sense a change in the physical properties of the functional structures 152 (and / or may not be able to cause a change in the physical properties of the functional structures 152). If the functional structures 152 comprise a polymer and have a thickness greater than about 10 microns, the cost of manufacturing the semiconductor device 100 may increase without a significant benefit. If the functional structures 152 comprise an IR-sensitive material and have a thickness less than about 0.1 microns, the MEMS device 146 may not be able to sense a change in the physical properties of the functional structures 152 (and / or may not be able to cause a change in the physical properties of the functional structures 152). If the functional structures 152 comprise an IR-sensitive material and have a thickness greater than about 0.2 microns, the cost of manufacturing the semiconductor device 100 may increase without a significant benefit. If the functional structures 152 comprise a piezoelectric material and have a thickness less than about 0.05 microns, the MEMS device 146 may not be able to sense a change in the physical properties of the functional structures 152 (and / or may not be able to cause a change in the physical properties of the functional structures 152). If the functional structures 152 comprise a piezoelectric material and have a thickness greater than about 50 microns, the cost of manufacturing the semiconductor device 100 may increase without a significant benefit.

[0146] In some embodiments, the thicknesses of the functional structures 152 may be substantially the same. For example, the thickness of the first functional structure 152a may be substantially the same as that of the second functional structure 152b. In other embodiments, the thicknesses of the functional structures 152 may be different. For example, the thickness of the first functional structure 152a may be different from the thickness of the second functional structure 152b.

[0147] In some embodiments, the third conductive contact 144a, the fifth via 140a, and the third conductive line 123a are part of a first MEMS wiring structure that is electrically coupled to one or more of the IC devices 106. The fourth conductive contact 144b, the sixth via 140b, and the fourth conductive line 123b may be part of a second MEMS wiring structure that is electrically coupled to one or more of the IC devices 106. The first MEMS wiring structure electrically couples the first MEMS device 146a to one or more of the IC devices 106, and the second MEMS wiring structure electrically couples the second MEMS device 146b to the one or more IC devices 106. In some embodiments, the first MEMS wiring structure may be electrically coupled to one or more of the IC devices 106 and the first functional structure 152a. In still other embodiments, the second MEMS wiring structure may be electrically coupled to one or more of the IC devices 106 and the second functional structure 152b.

[0148] In some embodiments, the first MEMS wiring structure and the second MEMS wiring structure may be electrically isolated from each other. In still other embodiments, the first MEMS wiring structure and the second MEMS wiring structure may be electrically coupled to different (or different groups of) IC devices 106. In other embodiments, the first MEMS wiring structure and the second MEMS wiring structure may be electrically coupled to one or more of the same IC devices 106. It should be understood that in some embodiments, the semiconductor device 100 includes one MEMS wiring structure for each MEMS device 146.

[0149] Figure 2 Shown Figure 1 A cross-sectional view of some more detailed embodiments of the semiconductor device 100 shown.

[0150] As Figure 2 shown, the second dielectric structure 119 includes a fourth dielectric layer 202 and a fifth dielectric layer 204. The fourth dielectric layer 202 may be, for example, or include a low dielectric constant dielectric (e.g., a dielectric material having a dielectric constant less than about 3.9), an oxide (e.g., silicon dioxide (SiO2)), etc. The fifth dielectric layer 204 is disposed over the fourth dielectric layer 202. The fifth dielectric layer 204 may be, for example, or include a low dielectric constant dielectric (e.g., a dielectric material having a dielectric constant less than about 3.9), an oxide (e.g., silicon dioxide (SiO2)), etc. In some embodiments, the second conductive line 123 is disposed in the fifth dielectric layer 204. The second via 121 may be disposed in the fourth dielectric layer 202. In still other embodiments, the second via 121 and / or the fourth dielectric layer 202 are disposed vertically between the first dielectric structure 116 and the fifth dielectric layer 204.

[0151] The third dielectric structure 124 includes a sixth dielectric layer 206, a first anti - outgassing layer 208, a seventh dielectric layer 210, and an eighth dielectric layer 212. The first anti - outgassing layer 208 is disposed on the sixth dielectric layer 206, the seventh dielectric layer 210 is disposed on the first anti - outgassing layer 208, and the eighth dielectric layer 212 is disposed on the seventh dielectric layer 210. In some embodiments, the electrode 128 is disposed in the eighth dielectric layer 212. In still other embodiments, the third via 126 extends vertically through the sixth dielectric layer 206, the first anti - outgassing layer 208, and the seventh dielectric layer 210. In yet other embodiments, the electrode 128 can have a thickness between about 0.05 microns and about 1 micron.

[0152] The first anti - outgassing layer 208 prevents gases (e.g., oxygen, carbon dioxide, etc.) from outgassing from other features of the semiconductor device 100 into the cavity 148. In some embodiments, the first anti - outgassing layer 208 can be, for example, or include a nitride (e.g., SiN), a nitrogen oxide (e.g., SiO X N Y )), other anti - outgassing materials, or a combination of the foregoing. In still other embodiments, the sixth dielectric layer 206, the seventh dielectric layer 210, and / or the eighth dielectric layer 212 can be, for example, a low - dielectric - constant dielectric (e.g., a dielectric material having a dielectric constant less than about 3.9), an oxide (e.g., silicon dioxide (SiO2)), etc.

[0153] The fourth dielectric structure 130 includes a ninth dielectric layer 214, a first dielectric layer 132, a second anti - outgassing layer 216, and a second dielectric layer 134. The first dielectric layer 132 is disposed on the ninth dielectric layer 214, the second anti - outgassing layer 216 is disposed on the first dielectric layer 132, and the second dielectric layer 134 is disposed on the second anti - outgassing layer 216. The second anti - outgassing layer 216 prevents gases (e.g., oxygen, carbon dioxide, etc.) from outgassing from other features of the semiconductor device 100 into the cavity 148. In some embodiments, the second anti - outgassing layer 216 can be, for example, or include a nitride (e.g., SiN), a nitrogen oxide (e.g., SiO X N Y )), other anti - outgassing materials, or a combination of the foregoing. In still other embodiments, the ninth dielectric layer 214 can be, for example, or include a low - dielectric - constant dielectric (e.g., a dielectric material having a dielectric constant less than about 3.9), an oxide (e.g., silicon dioxide (SiO2)), etc.

[0154] In some embodiments, the MEMS substrate 136 includes a first MEMS structure 217 and a second MEMS structure 218. The first MEMS structure 217 is disposed above the second MEMS structure 218. In some embodiments, the first MEMS structure 217 is a semiconductor structure including a semiconductor material (e.g., polysilicon, amorphous silicon, single-crystalline silicon, SiGe, Ge, etc.). In still some other embodiments, the second MEMS structure 218 includes one or more dielectric layers, and the one or more dielectric layers respectively include oxides (e.g., SiO2), nitrides (e.g., SiN), etc. In yet some other embodiments, the second MEMS structure 218 may be a single-layer SiO2. A bonding interface may exist at the interface between the second MEMS structure 218 and the second dielectric layer 134. For example, in some embodiments, the second MEMS structure 218 is bonded to the second dielectric layer 134 through a bonding process (e.g., fusion bonding), thereby forming a bonding interface at the interface between the second MEMS structure 218 and the second dielectric layer 134. In some embodiments, the second dielectric layer 134 may have a thickness between about 0.1 micrometers and about 10 micrometers. In still some other embodiments, the second MEMS structure 218 may have a thickness between about 0.0005 micrometers and about 1 micrometer.

[0155] The isolation trench 220 is laterally disposed between the fifth via 140a and the sixth via 140b. In some embodiments, the isolation trench 220 vertically extends through the third dielectric layer 138 and the first MEMS structure 217. In still some other embodiments, the isolation trench vertically extends through the MEMS substrate 136. The isolation trench 220 may laterally extend around the MEMS device 146 in a closed path. The isolation trench 220 provides electrical isolation (or increases the resistivity) between the fifth via 140a and the sixth via 140b. It should be understood that, in some embodiments, the isolation trench 220 may be one of a plurality of isolation trenches that are respectively laterally disposed between the fourth vias 140.

[0156] The first passivation layer 222 is disposed above the MEMS substrate 136, the third dielectric layer 138, the fourth vias 140, and the second conductive contacts 144. In some embodiments, the first passivation layer 222 lines the fourth vias 140, the upper surface of the third dielectric layer 138, one or more sidewalls of the third dielectric layer 138, one or more sidewalls of the first MEMS structure 217, the upper surface of the second MEMS structure 218, one or more sidewalls of the second conductive contacts 144, and the upper surface of the second conductive contacts 144. In still some other embodiments, the first passivation layer 222 may contact the upper surface of the MEMS substrate 136 between the third dielectric layer 138 and the functional structure 152.

[0157] In some embodiments, the first passivation layer 222 may laterally separate the functional structure 152 from the third dielectric layer 138. In such embodiments, portions of the first passivation layer 222 may extend vertically from the MEMS substrate 136 between the sidewalls of the functional structure 152 and the sidewalls of the third dielectric layer 138. In still further such embodiments, the first passivation layer 222 may directly contact the MEMS substrate 136, the sidewalls of the functional structure 152, and / or the sidewalls of the third dielectric layer 138. The first passivation layer 222 may be a conformal layer. In some embodiments, the first passivation layer 222 may be, for example, or include an oxide (e.g., SiO2), a nitride (e.g., SiN), a oxynitride (e.g., SiO X N Y ), other dielectric materials, or a combination of the foregoing. In still further embodiments, the first passivation layer 222 has a different chemical composition from the functional structure 152.

[0158] The second passivation layer 224 may be disposed over the MEMS substrate 136, the third dielectric layer 138, the fourth via 140, the second conductive contact 144, the first passivation layer 222, and the functional structure 152. In some embodiments, the second passivation layer 224 lines the first passivation layer 222 and the functional structure 152. In still further embodiments, the second passivation layer 224 may line the upper surface of the functional structure 152. The second passivation layer 224 may be, for example, or include an oxide (e.g., SiO2), a nitride (e.g., SiN), a oxynitride (e.g., SiO X N Y ), other dielectric materials, or a combination of the foregoing. In some embodiments, the second passivation layer 224 may have a thickness between about 0.05 microns and about 2 microns. In still further embodiments, the second passivation layer 224 has a different chemical composition from the functional structure 152.

[0159] One or more gas getter structures 226 may be disposed in the third dielectric structure 124. In some embodiments, the gas getter structure 226 is disposed over the first degassing layer 208. In still further embodiments, the gas getter structure 226 is disposed in the eighth dielectric layer 212. The gas getter structure 226 is configured to absorb and / or consume gases within the cavity 148. The gas getter structure 226 may be, for example, or include Al, Cu, W, Ti, Au, other suitable getter materials, or a combination of the foregoing. In yet further embodiments, the gas getter structure 226 and the electrode 128 comprise the same material. For clarity, only some of the gas getter structures 226 are specifically labeled.

[0160] The cavity 148 is at least partially defined by the MEMS substrate 136 and the fourth dielectric structure 130. In some embodiments, the bottom surface of the first MEMS structure 217 defines the upper surface of the cavity 148. In other embodiments, the bottom surface of the second MEMS structure 218 defines the upper surface of the cavity 148. In some embodiments, the sidewalls of the cavity 148 are defined by the sidewalls of the second dielectric layer 134, the sidewalls of the second degassing prevention layer 216, the sidewalls of the first dielectric layer 132, and the sidewalls of the ninth dielectric layer 214. In still other embodiments, the first lower surface of the cavity 148 is defined by the upper surface of the first dielectric layer 132. In yet other embodiments, the second lower surface of the cavity 148 is defined by the upper surface of the getter structure 226. The second lower surface of the cavity 148 may be disposed between the first lower surface of the cavity 148 and the semiconductor substrate 104.

[0161] Figure 3 shown Figure 2 A cross-sectional view of some other embodiments of the semiconductor device 100 shown.

[0162] As Figure 3 shown, a plurality of fluid communication channels 302 are disposed in the fourth dielectric structure 130. For clarity, only some of the fluid communication channels 302 are specifically labeled. The fluid communication channels 302 extend laterally between the cavities 148 such that each of the cavities 148 is in fluid communication with each other. In some embodiments, each of the fluid communication channels 302 extends laterally between two adjacent cavities among the cavities 148 such that each of the cavities 148 is in fluid communication with each other. Since the cavities 148 are in fluid communication with each other, the cavity pressures (e.g., the pressures inside the cavities 148) of the cavities 148 are substantially the same. Since the cavity pressures are substantially the same, the device performance of the semiconductor device 100 can be improved (e.g., the transmit / receive sensitivity is increased).

[0163] For example, the first MEMS device 146a and the second MEMS device 146b can be configured to operate in combination with each other (e.g., a CMUT configured to operate as an ultrasonic receiver and a PMUT configured to operate as an ultrasonic transmitter). During the operation of the first MEMS device 146a and the second MEMS device 146b, the same operating voltage can be applied to the first MEMS device 146a and the second MEMS device 146b. Thus, due to the difference in the cavity pressure causing a change in the deflection of the movable diaphragm 150, the difference in the cavity pressure between the first MEMS device 146a and the second MEMS device 146b reduces the transmission sensitivity and / or the reception sensitivity. However, since the fluid communication channel 302 extends laterally between the cavities 148, such that each of the cavities 148 is in fluid communication with each other, the cavity pressures of the cavities 148 are substantially the same. Therefore, the fluid communication channel 302 can improve the transmission sensitivity and / or the reception sensitivity of the MEMS device 146.

[0164] The fluid communication channel 302 is at least partially defined by the MEMS substrate 136 and the fourth dielectric structure 130. In some embodiments, the bottom surface of the first MEMS structure 217 defines the upper surface of the fluid communication channel 302. In other embodiments, the bottom surface of the second MEMS structure 218 defines the upper surface of the fluid communication channel 302. In some embodiments, the sidewalls of the fluid communication channel 302 are defined by the sidewalls of the second dielectric layer 134 and the second degassing prevention layer 216. In still other embodiments, the lower surface of the fluid communication channel 302 is defined by the upper surface of the first dielectric layer 132.

[0165] Figure 4 Shown Figure 2 A cross-sectional view of some other embodiments of the semiconductor device 100 shown.

[0166] As Figure 4 As shown, one or more vent holes 402 are provided in the MEMS substrate 136. The vent holes 402 extend vertically through the MEMS substrate 136 such that the vent holes 402 are in fluid communication with the cavities 148. In some embodiments, the vent holes 402 are in fluid communication with the cavities 148 and the fluid communication channel 302. In still other embodiments, the vent holes 402 extend vertically through the MEMS substrate 136 and lead to the fluid communication channel 302, respectively. In other embodiments, the vent holes 402 extend vertically through the MEMS substrate 136 and lead to the cavities 14, respectively. The vent holes 402 are at least partially defined by the MEMS substrate 136. For example, the sidewalls of the vent holes 402 are at least partially defined by the sidewalls of the first MEMS structure 217 and the second MEMS structure 218. For clarity, only some of the vent holes 402 are specifically labeled.

[0167] One or more plugs 404 are disposed over the MEMS substrate 136 and cover the vent holes 402. For clarity, only some of the plugs 404 are specifically labeled. The plugs 404 completely cover the vent holes 402 respectively. The plugs 404 are configured to hermetically seal the cavity 148 and the vent holes 402 under a reference system pressure. In some embodiments, the plugs 404 are configured to hermetically seal the cavity 148, the fluid communication channel 302, and the vent holes 402 under a reference system pressure.

[0168] In some embodiments, the reference system pressure is less than or equal to 2 standard atmospheres (atm). In still other embodiments, the reference system pressure can be less than 0.1 atm (e.g., for high-vacuum MEMS devices). In yet other embodiments, the reference system pressure can be between 0.5 atm and 2 atm (e.g., for standard-pressure MEMS devices). Compared with semiconductor devices that do not include the vent holes 402, the vent holes 402 enable the cavity 148, the fluid communication channel 302, and the vent holes 402 to be hermetically sealed under a lower reference system pressure, because the plugs 404 can be formed under a pressure lower than the pressure for bonding the MEMS substrate 136 to the fourth dielectric structure 130. In some embodiments in which the semiconductor device 100 includes the vent holes 402 and the plugs 404, the reference system pressure can be less than 0.1 atm.

[0169] In some embodiments, the plugs 404 can be, for example, or include metals (e.g., Al, Cu, AlCu, Ti, Ag, Au, etc.), metal nitrides (e.g., TiN), oxides (e.g., SiO2), nitrides (e.g., SiN), oxynitrides (e.g., SiO X N Y ), semiconductor materials (e.g., amorphous silicon, Ge, etc.), other suitable materials for covering and sealing the vent holes 402, or combinations of the foregoing. In still other embodiments, the plugs 404 can be the same material as the second conductive contact 144. In yet other embodiments, the plugs 404 are part of the first MEMS wiring structure and / or the second MEMS wiring structure.

[0170] Figures 5A to 5B Shown Figure 4 Various views of some embodiments of the region 406 of the semiconductor device 100 shown (e.g., see Figure 4 ). Figure 5A Shown Figure 4Cross-sectional views of some embodiments of region 406 of the semiconductor device 100 shown. Figure 5B Shows along Figure 5A Cross-sectional views of some embodiments of region 406 taken along line A-A shown.

[0171] As Figures 5A to 5B shown, the MEMS substrate 136 has a thickness T (e.g., the distance between the uppermost surface and the lowermost surface of the MEMS substrate 136). The thickness T of the MEMS substrate can be between about 0.1 micrometers (um) and about 50 micrometers. Each of the vent holes 402 has a minimum dimension D. The minimum dimension D of a given vent hole is the distance between the closest opposing sidewalls of the given vent hole. In some embodiments, the minimum dimension D is between about 0.1 micrometer and about 2 micrometers. In some embodiments in which the MEMS substrate 136 comprises or is a semiconductor material (e.g., Si), the minimum dimension D is at most one-twentieth of the thickness T of the MEMS substrate 136. In still further embodiments, the sidewalls of the vent holes 402 extend downward from the uppermost surface of the MEMS substrate 136 at an angle Θ. The angle Θ can be between about 85 degrees and 95 degrees.

[0172] Figures 6A to 6B Shows Figure 4 Various views of some other embodiments of region 406 of the semiconductor device 100 shown (e.g., see Figure 4 ). Figure 6A Shows Figure 4 Cross-sectional views of some embodiments of region 406 of the semiconductor device 100 shown. Figure 6B Shows along Figure 6A Cross-sectional views of some embodiments of region 406 taken along line A-A shown.

[0173] As Figures 6A to 6B shown, a third passivation layer 602 can be disposed over the second passivation layer 224. In some embodiments, the third passivation layer 602 is disposed over the MEMS substrate 136, the third dielectric layer 138, the fourth via 140, the second conductive contact 144, the first passivation layer 222, the functional structure 152, and the second passivation layer 224. The third passivation layer 602 can be, for example, or comprise an oxide (e.g., SiO2), a nitride (e.g., silicon nitride), a oxynitride (e.g., SiO X N Y ), other dielectric materials, or a combination of the foregoing. In some embodiments, the third passivation layer 602 can be or comprise the same material as the first passivation layer 222. For example, the first passivation layer 222 can be an oxide (e.g., SiO2), the second passivation layer 224 can be a nitride (e.g., SiN), and the third passivation layer 602 can be an oxide (e.g., SiO2).

[0174] In some embodiments, one or more of the plugs 404 may have a first indentation. The first indentation is disposed along the bottom surface of the one or more plugs 404. The one or more plugs 404 may have a second indentation corresponding to the first indentation. The second indentation is disposed along the upper surface of the one or more plugs 404. In other embodiments, the upper surface of the plug 404 may be substantially flat.

[0175] The first passivation layer 222 may have a third indentation corresponding to the second indentation. The third indentation is disposed along the upper surface of the first passivation layer 222. The second passivation layer 224 may have a fourth indentation corresponding to the third indentation. The fourth indentation is disposed along the upper surface of the second passivation layer 224. The third passivation layer 602 may have a fifth indentation corresponding to the fourth indentation. The fifth indentation is disposed along the upper surface of the third passivation layer 6). In other embodiments, the upper surface of the first passivation layer 222, the upper surface of the second passivation layer 224, and / or the upper surface of the third passivation layer 602 may be substantially flat.

[0176] Figure 7 Shown Figure 2 A cross-sectional view of some other embodiments of the semiconductor device 100 shown.

[0177] As Figure 7As shown, some of the MEMS devices 146 may include functional structures 152, and some of the other MEMS devices 146 may not include functional structures 152. For example, the first MEMS device 146a includes the first functional structure 152a, but the second MEMS device 146b does not include the second functional structure 152b. Since the first MEMS device 146a includes the first functional structure 152a, the first MEMS device 146a can sense (or actuate) at least in part based on the physical properties of the first functional structure 152a changing in response to a stimulus (e.g., the shape of the first functional structure 152a changes in response to a stimulus, causing the first movable diaphragm 150a to deflect). Since the second MEMS device 146b does not include the second functional structure 152b, the second MEMS device 146b does not rely on the physical properties of the corresponding functional structure changing in response to a stimulus to sense (or actuate). Instead, the second MEMS device 146b can sense (or actuate) by directly deflecting the second movable diaphragm 150b based on the stimulus (e.g., rather than indirectly deflecting the second movable diaphragm 150b based on the physical properties of the corresponding functional structure). Therefore, the first MEMS device 146a is a first type of MEMS device, and the second MEMS device 146b is a second type of MEMS device different from the first type. Thus, the semiconductor device 100 includes different types of MEMS devices, which can reduce manufacturing costs, reduce package size, reduce power consumption, etc.

[0178] In some embodiments, the first passivation layer 222 may be vertically spaced apart from the first movable diaphragm 150a and contact the second movable diaphragm 150b. In still other embodiments, the first passivation layer 222 may have a first bottom surface disposed directly above the first movable diaphragm 150a and a second bottom surface disposed directly above the second movable diaphragm 150b. In yet other embodiments, the second bottom surface of the first passivation layer 222 may be disposed between the first bottom surface of the first passivation layer 222 and the upper surface of the first movable diaphragm 150a.

[0179] In some embodiments, the first functional structure 152a may vertically separate the first passivation layer 222 from the first movable diaphragm 150a. In such embodiments, the first passivation layer 222 may line the upper surface of the first functional structure 152a directly above the first movable diaphragm 150a and may line the upper surface of the second movable diaphragm 150b. In other embodiments, the third dielectric layer 138 may line the upper surface of the second movable diaphragm 150b. In such embodiments, the first passivation layer 222 may line the upper surface of the first functional structure 152a directly above the first movable diaphragm 150a and line the upper surface of the third dielectric layer 138 directly above the second movable diaphragm 150b.

[0180] Figure 8 Shown Figure 2 A cross-sectional view of some other embodiments of the semiconductor device 100 shown.

[0181] As Figure 8 Shown, a first doped region 802 and a second doped region 804 are disposed in the MEMS substrate 136. The first doped region 802 is at least partially disposed in the first movable diaphragm 150a, and the second doped region 804 is at least partially disposed in the second movable diaphragm 150b. In some embodiments, the first doped region 802 and the second doped region 804 are disposed in the first MEMS structure 217.

[0182] The first doped region 802 has a first doping type (e.g., n-type / p-type), and the second doped region 804 has a second doping type (e.g., n-type / p-type). In some embodiments, the first doping type and the second doping type are the same. In such embodiments, the first doped region 802 has a first doping type dopant with a first doping concentration (e.g., phosphorus (n-type), boron (p-type), etc.), and the second doped region 804 has a first doping type dopant with a second doping concentration different from the first doping concentration. In other embodiments, the first doping type and the second doping type are different.

[0183] Figure 8 Also shown is that the first MEMS device 146a does not include the first functional structure 152a, and the second MEMS device 146b does not include the second functional structure 152b. However, since the first doped region 802 is at least partially disposed in the first movable diaphragm 150a, and the second doped region 804 is at least partially disposed in the second movable diaphragm 150b, the first MEMS device 146a can be a different type of MEMS device from the second MEMS device 146b. For example, because the first doped region 802 has a first doping type (and / or first doping concentration) and the second doped region 804 has a second doping type (and / or second doping concentration), the first MEMS device 146a can be configured to emit (or sense) acoustic waves at a first frequency, while the second MEMS device 146b is configured to emit (or sense) acoustic waves at a second frequency different from the first frequency. Therefore, the first MEMS device 146a is a first type of MEMS device, and the second MEMS device 146b is a second type of MEMS device different from the first type. Therefore, the semiconductor device 100 includes different types of MEMS devices, which can reduce manufacturing costs, reduce package size, reduce power consumption, etc.

[0184] Figure 9 Shown Figure 2 A cross-sectional view of some other embodiments of the semiconductor device 100 shown.

[0185] As Figure 9 shown, the first MEMS device 146a includes a first functional structure 152a, and a first doped region 802 is disposed in the MEMS substrate 136. The second MEMS device 146b includes a second functional structure 152b, and a second doped region 804 is disposed in the MEMS substrate 136. In some embodiments in which the first doped region 802 and the second doped region 804 are disposed in the MEMS substrate 136, the second functional structure 152b may have the same chemical composition as the first functional structure 152a. Although the first functional structure 152a and the second functional structure 152b may have the same chemical composition, since the first doped region 802 has a first doping type (and / or a first doping concentration) and the second doped region 804 has a second doping type (and / or a second doping concentration), the first MEMS device 146a and the second MEMS device 146b may still be different types of MEMS devices. In other embodiments in which the first doped region 802 and the second doped region 804 are disposed in the MEMS substrate 136, the first functional structure 152a may have a chemical composition different from that of the second functional structure 152b. It should be understood that in some embodiments, since the first functional structure 152a and the second functional structure 152b have different chemical compositions, the first doped region 802 and the second doped region 804 have different doping types (and / or doping concentrations), the first MEMS device 146a includes the first functional structure 152a while the second MEMS device does not include the second functional structure 152b, or a combination of the foregoing reasons, the first MEMS device 146a and the second MEMS device 146b may be different types of MEMS devices.

[0186] Figure 10 shown Figure 2 A simplified layout diagram of some embodiments of the semiconductor device 100 shown. Figure 10 It is "simplified" because Figure 2 the various features shown are not shown in Figure 10 it.

[0187] As Figure 10 shown, in some embodiments, the first MEMS device 146a includes a first plurality of MEMS units 1002a. The first plurality of MEMS units 1002a each include a second plurality of cavities 148c. For example, the first MEMS unit 1002a1 in the first plurality of MEMS units 1002a includes the third cavity 148c1 in the second plurality of cavities 148c, and the second MEMS unit 1002a2 in the first plurality of MEMS units 1002a includes the fourth cavity 148c2 in the second plurality of cavities 148c. In some embodiments, the cavities in the second plurality of cavities 148c have substantially similar structures to each other.

[0188] The first plurality of MEMS units 1002a each include a second plurality of movable diaphragms 150c. For example, the first MEMS unit 1002a1 includes a third movable diaphragm 150c1 among the second plurality of movable diaphragms 150c, and the second MEMS unit 1002a2 includes a fourth movable diaphragm 150c2 among the second plurality of movable diaphragms 150c. In some embodiments, the movable diaphragms among the second plurality of movable diaphragms 150c have substantially similar structures (and / or doping types / concentrations) to each other.

[0189] In some embodiments, the first plurality of MEMS units 1002a each include a first plurality of functional structures 152c. For example, the first MEMS unit 1002a1 includes a third functional structure 152c1 among the first plurality of functional structures 152c, and the second MEMS unit 1002a2 includes a fourth functional structure 152c2 among the first plurality of functional structures 152c. In some embodiments, the functional structures among the first plurality of functional structures 152c have substantially similar structures to each other. In still further embodiments, each of the functional structures among the first plurality of functional structures 152c may have the same chemical composition. In yet other embodiments, each of the functional structures among the first plurality of functional structures 152c has the same chemical composition as the first functional structure 152a.

[0190] In some embodiments, the first plurality of MEMS units 1002a are configured to operate in conjunction with each other (e.g., in unison). For example, the first MEMS device 146a may be a CMUT, and the first plurality of MEMS units 1002a are separate multiple units of the CMUT. In still further embodiments, during operation of the first MEMS device 146a, the same operating voltage may be applied to each of the first plurality of MEMS units 1002a.

[0191] The second MEMS device 146b may include a second plurality of MEMS units 1002b. The second plurality of MEMS units 1002b each include a third plurality of cavities 148d. For example, the third MEMS unit 1002b1 among the second plurality of MEMS units 1002b includes a fifth cavity 148d1 among the third plurality of cavities 148d, and the fourth MEMS unit 1002b2 among the second plurality of MEMS units 1002b includes a sixth cavity 148d2 among the third plurality of cavities 148d. In some embodiments, the cavities among the third plurality of cavities 148d have substantially similar structures to each other.

[0192] The second plurality of MEMS units 1002b each include a third plurality of movable diaphragms 150d. For example, the third MEMS unit 1002b1 includes a fifth movable diaphragm 150d1 among the third plurality of movable diaphragms 150d, and the fourth MEMS unit 1002b2 includes a sixth movable diaphragm 150d2 among the third plurality of movable diaphragms 150d. In some embodiments, the movable diaphragms among the third plurality of movable diaphragms 150d have substantially similar structures (and / or doping types / concentrations) to each other.

[0193] In some embodiments, the second plurality of MEMS units 1002b each include a second plurality of functional structures 152d. For example, the third MEMS unit 1002b1 includes a fifth functional structure 152d1 among the second plurality of functional structures 152d, and the fourth MEMS unit 1002b2 includes a sixth functional structure 152d2 among the second plurality of functional structures 152d. In some embodiments, the functional structures among the second plurality of functional structures 152d have substantially similar structures to each other. In still further embodiments, each of the functional structures among the second plurality of functional structures 152d may have the same chemical composition. In yet further embodiments, each of the functional structures among the second plurality of functional structures 152d has the same chemical composition as the second functional structure 152b.

[0194] In some embodiments, the second plurality of MEMS units 1002b are configured to operate in conjunction with each other (e.g., coherently). For example, the second MEMS device 146b may be a PMUT, and the second plurality of MEMS units 1002b are separate pluralities of units of the PMUT. In still further embodiments, during the operation of the second MEMS device 146b, the same operating voltage may be applied to each of the second plurality of MEMS units 1002b.

[0195] Figures 11 to 22 Illustrates Figure 4 A series of cross-sectional views of some embodiments of a method for forming some embodiments of the semiconductor device 100 shown.

[0196] As Figure 11As shown, an IC structure 102 is provided. The IC structure 102 includes a semiconductor substrate 104. One or more IC devices 106 (not shown in the figure) are formed on / above the semiconductor substrate 104. In some embodiments, one or more of the IC devices 106 include a pair of source / drain regions 108, a gate dielectric 110, and a gate electrode 112. The IC structure 102 includes an interconnect structure 114, a first dielectric structure 116, a second dielectric structure 119, a third dielectric structure 124, a plurality of electrodes 128, and one or more getter structures 226 disposed above the semiconductor substrate 104 and the IC devices 106. The interconnect structure 114 includes one or more first conductive contacts 118 (not shown in the figure), one or more first vias 120, one or more first conductive lines 122, a plurality of second vias 121, a plurality of second conductive lines 123, and a plurality of third vias 126. The second dielectric structure 119 includes a fourth dielectric layer 202 and a fifth dielectric layer 204. The third dielectric structure 124 includes a sixth dielectric layer 206, a first outgassing prevention layer 208, a seventh dielectric layer 210, and an eighth dielectric layer 212. The IC structure 102 can be formed according to a CMOS manufacturing process.

[0197] Figure 11 Also shown is that a fourth dielectric structure 130 is formed above the IC structure 102. In some embodiments, the fourth dielectric structure 130 is formed above the third dielectric structure 124, the getter structure 226, and the electrodes 128. The fourth dielectric structure 130 can include a ninth dielectric layer 214, a first dielectric layer 132, a second outgassing prevention layer 216, and a second dielectric layer 134. The ninth dielectric layer 214 can be formed above the third dielectric structure 124, the getter structure 226, and the electrodes 128. The first dielectric layer 132 can be formed above the ninth dielectric layer 214. The second outgassing prevention layer 216 can be formed above the first dielectric layer 132. The second dielectric layer 134 can be formed above the second outgassing prevention layer 216.

[0198] In some embodiments, the process for forming the fourth dielectric structure 130 includes depositing a ninth dielectric layer 214 that covers the third dielectric structure 124, the getter structure 226, and the electrode 128 on the third dielectric structure 124, the getter structure 226, and the electrode 128. The ninth dielectric layer 214 can be deposited, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), other deposition processes, or a combination of the foregoing. Thereafter, a first dielectric layer 132 is deposited on the ninth dielectric layer 214. The first dielectric layer 132 can be deposited, for example, by CVD, PVD, ALD, other deposition processes, or a combination of the foregoing.

[0199] Then, a second degassing prevention layer 216 is deposited on the first dielectric layer 132. The second degassing prevention layer 216 can be deposited, for example, by CVD, PVD, ALD, other deposition processes, or a combination of the foregoing. Thereafter, a second dielectric layer 134 is deposited on the second degassing prevention layer 216. The second dielectric layer 134 can be deposited, for example, by CVD, PVD, ALD, other deposition processes, or a combination of the foregoing. In some embodiments, the second dielectric layer 134 can be deposited with a thickness between about 0.1 micrometers and about 10 micrometers. In still other embodiments, the ninth dielectric layer 214, the first dielectric layer 132, the second degassing prevention layer 216, and / or the second dielectric layer 134 can be formed as conformal layers.

[0200] As Figure 12 shown, a first plurality of openings 1202 are formed on the second dielectric structure 119. The first plurality of openings 1202 are formed to be laterally spaced apart from each other. In some embodiments, the first plurality of openings 1202 are at least partially formed in the third dielectric structure 124 and at least partially formed in the fourth dielectric structure 130. In still other embodiments, the first plurality of openings 1202 expose one or more of the second conductive lines 123. For example, in some embodiments, the first opening 1202a in the first plurality of openings 1202 exposes the third conductive line 123a, and the second opening 1202b in the first plurality of openings 1202 exposes the fourth conductive line 123b.

[0201] In some embodiments, the process for forming the first plurality of openings 1202 includes forming a first patterned masking layer (not shown in the figures) (e.g., positive / negative photoresist, hard mask, etc.) over the fourth dielectric structure 130. In still further embodiments, forming the first patterned masking layer may be accomplished by forming a masking layer (not shown in the figures) over the fourth dielectric structure 130, exposing the masking layer to a pattern (e.g., by a lithography process such as optical lithography, extreme ultraviolet lithography, etc.), and developing the masking layer to form the first patterned masking layer. Thereafter, a first etching process is performed to remove the unmasked portions of the fourth dielectric structure 130 and the unmasked portions of the third dielectric structure 124, thereby forming the first plurality of openings 1202 over the second dielectric structure 119. The first etching process may be a dry etching process, a wet etching process, a reactive ion etching (RIE) process, other etching processes, or a combination of the foregoing. Subsequently, in some embodiments, the first patterned masking layer is stripped off.

[0202] As Figure 13 shown, a plurality of cavity openings 1302 and a plurality of fluid communication channel openings 1304 are formed over the IC structure 102. The cavity openings 1302 and the fluid communication channel openings 1304 are formed in the fourth dielectric structure 130. In some embodiments, the cavity openings 1302 and the fluid communication channel openings 1304 are at least partially defined by the first dielectric layer 132, the second dielectric layer 134, and the second anti-outgassing layer 216.

[0203] The cavity openings 1302 are formed to be laterally spaced apart from each other. The cavity openings 1302 are respectively formed over the electrodes 128. For example, the first cavity opening 1302a among the cavity openings 1302 is formed over the first electrode 128a, and the second cavity opening 1302b among the cavity openings 1302 is formed over the second electrode 128b. The fluid communication channel openings 1304 are formed to extend laterally between the cavity openings 1302 such that opposite ends of the fluid communication channel openings 1304 lead to corresponding ones of the cavity openings 1302. In some embodiments, each of the fluid communication channel openings 1304 is formed to extend laterally between two adjacent ones of the cavity openings 1302 such that opposite ends of each of the fluid communication channel openings 1304 lead to two adjacent ones of the cavity openings 1302.

[0204] In some embodiments, the process for forming the cavity opening 1302 and the fluid communication channel opening 1304 includes forming a second patterned masking layer (not shown in the figure) (e.g., positive / negative photoresist, hard mask, etc.) on the fourth dielectric structure 130, on the second conductive line 123, and in the first plurality of openings 1202. Thereafter, a second etching process is performed to remove the unmasked portions of the second dielectric layer 134 and the second gettering layer 216, thereby forming the cavity opening 1302 and the fluid communication channel opening 1304 in the fourth dielectric structure 130. The second etching process can be a dry etching process, a RIE process, a wet etching process, other etching processes, or a combination of the foregoing. Subsequently, in some embodiments, the second patterned masking layer is stripped off.

[0205] As Figure 14 shown, a portion of the fourth dielectric structure 130 is removed to at least partially expose the getter structure 226. In some embodiments, a portion of the first dielectric layer 132 and a portion of the ninth dielectric layer 214 are removed to at least partially expose the getter structure 226. In some embodiments, the process for removing a portion of the fourth dielectric structure 130 to at least partially expose the getter structure 226 includes forming a third patterned masking layer (not shown in the figure) (e.g., positive / negative photoresist, hard mask, etc.) on the fourth dielectric structure 130, on the second conductive line 123, in the first plurality of openings 1202, in the cavity opening 1302, and in the fluid communication channel opening 1304. Thereafter, a third etching process is performed to remove the unmasked portion of the fourth dielectric structure 130, thereby at least partially exposing the getter structure 226. The third etching process can be a dry etching process, a RIE process, a wet etching process, other etching processes, or a combination of the foregoing. Subsequently, in some embodiments, the third patterned masking layer is stripped off.

[0206] As Figure 15 shown, the MEMS substrate 136 is bonded to the fourth dielectric structure 130. By bonding the MEMS substrate 136 to the fourth dielectric structure 130, a plurality of cavities 148 and a plurality of fluid communication channels 302 are formed on the IC structure 102. For example, once the MEMS substrate 136 is bonded to the fourth dielectric structure 130, the MEMS substrate 136 completely covers the cavity opening 1302 and the fluid communication channel opening 1304 (e.g., see Figure 14 ), thereby forming a plurality of cavities 148 and a plurality of fluid communication channels 302, respectively. In some embodiments, bonding the MEMS substrate 136 to the fourth dielectric structure 130 covers the first plurality of openings 1202.

[0207] In some embodiments, the MEMS substrate 136 is bonded to the fourth dielectric structure 130 by a fusion bonding process. It should be understood that other types of bonding processes (e.g., eutectic bonding) can be utilized to bond the MEMS substrate 136 to the fourth dielectric structure 130. In still other embodiments, the MEMS substrate 136 is bonded to the second dielectric layer 134.

[0208] The MEMS substrate 136 may include a first MEMS structure 217 and a second MEMS structure 218. In some embodiments, the first MEMS structure 217 may be bonded to the fourth dielectric structure 130. In other embodiments, the MEMS substrate 136 may not include the second MEMS structure 218. In such embodiments, the first MEMS structure 217 may be bonded to the fourth dielectric structure 130.

[0209] In some embodiments, a third dielectric layer 138 is disposed over one side of the MEMS substrate 136, the side opposite to the side of the MEMS substrate 136 that is bonded to the fourth dielectric structure 130. The third dielectric layer 138 may be disposed over the said side of the MEMS substrate 136 before bonding the MEMS substrate 136 to the fourth dielectric structure 130. In other embodiments, the third dielectric layer 138 may be formed over the MEMS substrate 136 and the IC structure 102 after bonding the MEMS substrate 136 to the third dielectric layer 138. In still other embodiments, the process for forming the third dielectric layer 138 over the MEMS substrate 136 and the IC structure 102 includes depositing or growing the third dielectric layer 138 on the MEMS substrate 136, for example, by CVD, PVD, ALD, thermal oxidation, other deposition or growth processes, or a combination of the foregoing.

[0210] As Figure 16 shown, a second plurality of openings 1602 are formed over the MEMS substrate 136. The second plurality of openings 1602 are formed in the third dielectric layer 138. In some embodiments, the second plurality of openings 1602 are part of one or more trenches disposed in the third dielectric layer 138 and extending over the MEMS substrate 136. For clarity, only some of the second plurality of openings 1602 are specifically labeled.

[0211] In some embodiments, the process for forming the second plurality of openings 1602 includes forming a fourth patterned masking layer (not shown in the figure) (e.g., positive / negative photoresist, hard mask, etc.) over the third dielectric layer 138. Thereafter, a fourth etching process is performed to remove the unmasked portion of the third dielectric layer 138, thereby forming the second plurality of openings 1602. The fourth etching process may be a dry etching process, an RIE process, a wet etching process, other etching processes, or a combination of the foregoing. Subsequently, in some embodiments, the fourth patterned masking layer is stripped.

[0212] As shown Figure 17 in the figure, a plurality of via openings 142 are formed extending vertically through the third dielectric layer 138, the MEMS substrate 136, the fourth dielectric structure 130, and the third dielectric structure 124. The via openings 142 expose one or more of the second conductive lines 123. For example, in some embodiments, a first via opening 142a among the plurality of via openings 142 exposes a third conductive line 123a, and a second via opening 142b among the plurality of via openings 142 exposes a fourth conductive line 123b.

[0213] In some embodiments, the process for forming the via openings 142 includes forming a fifth patterned mask layer (not shown in the figure) (e.g., positive / negative photoresist, hard mask, etc.) over the third dielectric layer 138 and in some of the second plurality of openings 1602. The fifth patterned mask layer at least partially exposes some of the others of the second plurality of openings 1602. The openings in the second plurality of openings 1602 that are at least partially exposed by the fifth patterned mask layer are the positions corresponding to where the via openings 142 are formed. Thereafter, a fifth etching process is performed to remove the unmasked portion of the MEMS substrate 136, thereby forming the via openings 142. The unmasked portions of the MEMS substrate 136 that are removed to form the via openings 142 respectively overlie the first plurality of openings 1202 (e.g., see Figure 16 ). In other words, the first plurality of openings 1202 are exposed by removing the unmasked portion of the MEMS substrate 136. The fifth etching process can be a dry etching process, an RIE process, a wet etching process, other etching processes, or a combination of the foregoing. Subsequently, in some embodiments, the fifth patterned mask layer can be stripped. It should be understood that in some embodiments, the fifth patterned mask layer may not expose some of the others of the second plurality of openings 1602, but rather exposes a portion of the third dielectric layer 138. In such embodiments, the fifth etching process removes the unmasked portion of the third dielectric layer 138 and the unmasked portion of the MEMS substrate 136, thereby forming the via openings 142.

[0214] Figure 17 Also shown in the figure is that one or more vent holes 402 are formed extending vertically through the MEMS substrate 136. In some embodiments, the vent holes 402 are formed to extend vertically through the MEMS substrate 136 respectively and lead to the fluid communication channels 302. In other embodiments, the vent holes 402 can be formed to extend vertically through the MEMS substrate 136 respectively and lead to the cavity 148.

[0215] In some embodiments, the process for forming the vent holes 402 includes forming a sixth patterned masking layer (not shown in the figures) (e.g., positive / negative photoresist, hard mask, etc.) over the third dielectric layer 138 and in some of the second plurality of openings 1602. The sixth patterned masking layer at least partially exposes some of the other second plurality of openings 1602. The openings in the second plurality of openings 1602 that are at least partially exposed by the sixth patterned masking layer are the positions corresponding to where the vent holes 402 are formed. Thereafter, a sixth etching process is performed to remove the unmasked portions of the MEMS substrate 136, thereby forming the vent holes 402. The sixth etching process can be a dry etching process, a RIE process, a wet etching process, other etching processes, or a combination of the foregoing. Subsequently, in some embodiments, the sixth patterned masking layer can be stripped. It should be understood that in some embodiments, the fifth etching process can form the vent holes 402. It should be understood that in some embodiments, the sixth patterned masking layer may not expose some of the other second plurality of openings 1602, but instead exposes a portion of the third dielectric layer 138. In such embodiments, the sixth etching process (or the fifth etching process) removes the unmasked portions of the third dielectric layer 138 and the unmasked portions of the MEMS substrate 136, thereby forming the vent holes 402.

[0216] As Figure 18 shown, a plurality of fourth vias 140, a plurality of second conductive contacts 144, and one or more plugs 404 are formed over the MEMS substrate 136. The fourth vias 140 are formed to vertically extend through the third dielectric layer 138, the MEMS substrate 136, the fourth dielectric structure 130, and the third dielectric structure 124 to contact a corresponding one of the second conductive lines 123. For example, a fifth via 140a, which is one of the fourth vias 140, is formed to vertically extend through the third dielectric layer 138, the MEMS substrate 136, the fourth dielectric structure 130, and the third dielectric structure 124 to contact the third conductive line 123a. A sixth via 140b, which is one of the fourth vias 140, is formed to vertically extend through the third dielectric layer 138, the MEMS substrate 136, the fourth dielectric structure 130, and the third dielectric structure 124 to contact the fourth conductive line 123b.

[0217] The second conductive contact 144 is formed to extend through the third dielectric layer 138 and contact the MEMS substrate 136. The plug 404 is formed to extend through the third dielectric layer 138 and contact the MEMS substrate 136. By forming the plug 404, the cavity 148 and the fluid communication channel 302 are hermetically sealed at a reference system pressure (e.g., less than or equal to 2 atm). In some embodiments in which the vent hole 402 is formed, the reference system pressure can be less than 0.1 atm (e.g., for high-vacuum MEMS devices). It should be understood that in some embodiments in which the vent hole 402 is not formed, the cavity 148 and the fluid communication channel 302 can be hermetically sealed by bonding the MEMS substrate 136 to the fourth dielectric structure 130.

[0218] In some embodiments, the process for forming the fourth vias 140, the second conductive contacts 144, and the plug 404 includes depositing a conductive layer (not shown in the figures) over the third dielectric layer 138, over the second conductive line 123, in the via openings 142, and in the second plurality of openings 1602. In still other embodiments, the conductive layer is at least partially deposited in the vent hole 402. The conductive layer can be, for example, a metal (e.g., Al, Cu, AlCu, Ti, Ag, Au, etc.), a metal nitride (e.g., TiN), other conductive materials, or a combination of the foregoing. The conductive layer can be deposited, for example, by CVD, PVD, ALD, electroless plating, electroplating, other deposition processes, or a combination of the foregoing. In some embodiments, the conductive layer can be deposited as a conformal layer. In still other embodiments, a conductive layer having a thickness between about 0.05 microns and about 1 micron can be formed.

[0219] Then a seventh patterned masking layer (not shown in the figures) (e.g., positive / negative photoresist, hard mask, etc.) is formed over the conductive layer. Then a seventh etching process is performed on the conductive layer to remove the unmasked portions of the conductive layer, thereby forming the fourth vias 140, the second conductive contacts 144, and the plug 404. The seventh etching process can be a dry etching process, an RIE process, a wet etching process, other etching processes, or a combination of the foregoing. Subsequently, in some embodiments, the seventh masking layer is stripped.

[0220] It should be understood that in some embodiments, if the seventh etching process is not performed, a planarization process (e.g., chemical-mechanical polishing (CMP)) can be performed on the conductive layer, thereby forming the fourth vias 140, the second conductive contacts 144, and the plug 404. It should also be understood that in some embodiments, the seventh patterned masking layer can be formed before depositing the conductive layer. In such embodiments, after depositing the conductive layer, a planarization process (e.g., CMP) can be performed on the conductive layer, thereby forming the fourth vias 140, the second conductive contacts 1, and the plug 404.

[0221] It should also be understood that in some embodiments, the fourth vias 140, the second conductive contacts 144, and / or the plugs 404 may be formed by different deposition / etching / planarization processes. For example, in some embodiments, the plugs 404 comprise a material different from that of the fourth vias 140 and the second conductive contacts 144. In such embodiments, the plugs 404 may be formed before (or after) the formation of the fourth vias 140 and the second conductive contacts 144. In still further such embodiments, the process for forming the plugs 404 may include depositing or growing a plug material layer (not shown in the figures) over the third dielectric layer 138, over the second conductive line 123, in the via opening 142, in the second plurality of openings 1602, and at least partially in the vent hole 402.

[0222] Thereafter, an eighth patterned masking layer (not shown in the figures) (e.g., positive / negative photoresist, hard mask, etc.) is formed over the plug material layer. Then an eighth etching process is performed to remove the unmasked portions of the plug material layer, thereby forming the plugs 404. The plug material layer may be, for example, a metal (e.g., Al, Cu, AlCu, Ti, Ag, Au, etc.), a metal nitride (e.g., TiN), an oxide (e.g., SiO2), a nitride (e.g., SiN), a oxynitride (e.g., SiO X N Y )), a semiconductor material (e.g., amorphous silicon, Ge, etc.), other suitable materials for covering and sealing the vent hole 402, or a combination of the foregoing. The plug material layer may be deposited or grown, for example, by CVD, PVD, ALD, epitaxy, electroless plating, electroplating, other deposition processes, or a combination of the foregoing. The eighth etching process may be a dry etching process, a RIE process, a wet etching process, other etching processes, or a combination of the foregoing. Subsequently, in some embodiments, the eighth patterned masking layer is stripped.

[0223] As Figure 19 shown, a third plurality of openings 1902 are formed over the MEMS substrate 136. The third plurality of openings 1902 are respectively formed directly above the cavities 148. For example, the third opening 1902a in the third plurality of openings 1902 is formed directly above the first cavity 148a, and the fourth opening 1902b in the third plurality of openings 1902 is formed directly above the second cavity 148b. In some embodiments, the plugs 404 (and / or the second conductive contacts 144) separate the third plurality of openings 1902 from each other.

[0224] In some embodiments, the process for forming the third plurality of openings 1902 includes forming a ninth patterned masking layer (not shown in the figures) (e.g., positive / negative photoresist, hard mask, etc.) over the third dielectric layer 138, the fourth vias 140, the second conductive contacts 144, and the plugs 404. Thereafter, a ninth etching process is performed to remove the unmasked portions of the third dielectric layer 138, thereby forming the third plurality of openings 1902. The ninth etching process can be a dry etching process, an RIE process, a wet etching process, other etching processes, or a combination of the foregoing. Subsequently, the ninth patterned masking layer can be stripped off.

[0225] Figure 19 Also shown is that an isolation trench 220 is formed laterally between the fifth via 140a and the sixth via 140b. The isolation trench 220 is formed to vertically extend through the third dielectric layer 138 and into the MEMS substrate 136. In some embodiments, the process for forming the isolation trench 220 includes forming a tenth patterned masking layer (not shown in the figures) (e.g., positive / negative photoresist, hard mask, etc.) over the third dielectric layer 138, the fourth vias 140, the second conductive contacts 144, the plugs 404, and within the third plurality of openings 1902. Thereafter, a tenth etching process is performed to remove the unmasked portions of the third dielectric layer 138 and the unmasked portions of the MEMS substrate 136, thereby forming the isolation trench 220. Subsequently, the tenth patterned masking layer can be stripped off. In some embodiments, the tenth etching process removes the unmasked portions of the first MEMS structure 217 and stops at the unmasked portions of the second MEMS structure 218. The tenth etching process can be a dry etching process, an RIE process, a wet etching process, other etching processes, or a combination of the foregoing. It should be understood that in some embodiments, the isolation trench 220 can be formed at least in part by the ninth etching process.

[0226] As Figure 20 shown, a first passivation layer 222 is formed over the third dielectric layer 138, the fourth vias 140, the second conductive contacts 144, the plugs 404, the first MEMS structure 217, and the second MEMS structure 218. In some embodiments, the first passivation layer 222 is formed to line the fourth vias 140, the second conductive contacts 144, the plugs 404, the isolation trench 220, and the third plurality of openings 1902. In still other embodiments, the process for forming the first passivation layer 222 includes depositing the first passivation layer 222 over the third dielectric layer 138, the fourth vias 140, the second conductive contacts 144, the plugs 404, and the MEMS substrate 136. The first passivation layer 222 can be deposited, for example, by CVD, PVD, ALD, other deposition processes, or a combination of the foregoing. In some embodiments, the first passivation layer 222 can be deposited as a conformal layer.

[0227] As Figure 21 As shown, a functional structure 152 is formed over a MEMS substrate 136. The functional structure 152 is respectively formed in a third plurality of openings 1902 (e.g., see Figure 20 ). For example, a first functional structure 152a in the functional structure 152 is formed in a third opening 1902a (e.g., see Figure 20 ), and a second functional structure 152b in the functional structure 152 is formed in a fourth opening 1902b (e.g., see Figure 20 ). In some embodiments, the functional structure 152 is formed on a first MEMS structure 217. In still other embodiments, each functional structure 152 is formed with a substantially coplanar bottom surface.

[0228] In some embodiments, the process for forming the functional structure 152 includes forming an eleventh patterned masking layer (not shown in the figures) (e.g., positive / negative photoresist, hard mask, etc.) over a first passivation layer 222. Thereafter, an eleventh etching process is performed to remove the unmasked portion of the first passivation layer 222. The unmasked portion of the first passivation layer 222 removed by the eleventh etching process is disposed in the third plurality of openings 1902 (e.g., see Figure 20 ). The eleventh etching process can be a dry etching process, a RIE process, a wet etching process, other etching processes, or a combination of the foregoing. In some embodiments, removing the unmasked portion of the first passivation layer 222 exposes a portion of the MEMS substrate 136. Subsequently, the eleventh patterned masking layer can be stripped.

[0229] Then a first functional material layer (not shown in the figures) is deposited over the first passivation layer 222 and over the MEMS substrate 136. The first functional material layer can be, for example, or include a piezoelectric material (e.g., molybdenum (Mo), lead zirconate titanate (PZT), aluminum nitride (AlN), zinc oxide (ZnO), etc.), a bio-sensitive material (e.g., a bio-identification component disposed on a metal (e.g., Au, Ag, platinum (Pt), etc.) (or a portion thereof)), an IR-sensitive material (e.g., vanadium oxide (VOx), mercury cadmium telluride (HgCdTe), silicon (Si), cadmium zinc telluride (CdZnTe), etc.), a polymer (e.g., polyimide, SU-8, negative / positive photoresist, etc.), etc. The first functional material layer can be deposited, for example, by CVD, PVD, ALD, electroless plating, electroplating, other deposition processes, or a combination of the foregoing.

[0230] Thereafter, a twelfth patterned masking layer (not shown in the figures) (e.g., positive / negative photoresist, hard mask, etc.) is formed over the first functional material layer. Then, a twelfth etching process is performed to remove the unmasked portion of the first functional material layer, thereby forming the first functional structure 152a. The first functional structure 152a is the portion of the first functional material layer that is not removed by the twelfth etching process. The twelfth etching process can be a dry etching process, a RIE process, a wet etching process, other etching processes, or a combination of the foregoing. Subsequently, the twelfth patterned masking layer can be stripped off.

[0231] In some embodiments, the first functional material layer can be formed as a conformal layer. In still other embodiments, the first functional material layer can be formed to have a thickness between about 0.0005 microns and about 50 microns. More specifically, if the first functional material layer is a polymer, the first functional material layer can be formed to have a thickness between about 0.0005 microns and about 10 microns; if the first functional material layer is an IR-sensitive material, the first functional material layer can be formed to have a thickness between about 0.1 microns and about 0.2 microns; and if the first functional material layer is a piezoelectric material, the first functional material layer can be formed to have a thickness between about 0.05 microns and about 50 microns.

[0232] After forming the first functional structure 152a, a second functional material layer (not shown in the figures) is deposited over the first passivation layer 222, over the MEMS substrate 136, and over the first functional structure 152a. The second functional material layer can be, for example, or include a piezoelectric material (e.g., molybdenum (Mo), lead zirconate titanate (PZT), aluminum nitride (AlN), zinc oxide (ZnO), etc.), a biosensitive material (e.g., a biometric recognition component disposed on a metal (e.g., Au, Ag, platinum (Pt), etc.) (or a portion thereof)), an IR-sensitive material (e.g., vanadium oxide (VOx), mercury cadmium telluride (HgCdTe), silicon (Si), cadmium zinc telluride (CdZnTe), etc.), a polymer (e.g., polyimide, SU-8, negative / positive photoresist, etc.), etc. The second functional material layer can be deposited, for example, by CVD, PVD, ALD, electroless plating, electroplating, other deposition processes, or a combination of the foregoing. In some embodiments, the second functional material layer is a material different from the first functional material layer.

[0233] Thereafter, a thirteenth patterned masking layer (not shown in the figures) (e.g., positive / negative photoresist, hard mask, etc.) is formed over the second functional material layer. Then, a thirteenth etching process is performed to remove the unmasked portion of the second functional material layer, thereby forming the second functional structure 152b. The second functional structure 152b is a part of the second functional material layer that is not removed by the thirteenth etching process. The thirteenth etching process can be a dry etching process, an RIE process, a wet etching process, other etching processes, or a combination of the foregoing. Subsequently, the thirteenth patterned masking layer can be stripped off.

[0234] In some embodiments, the second functional material layer can be formed as a conformal layer. In still other embodiments, the second functional material layer can be formed to have a thickness between about 0.0005 microns and about 50 microns. More specifically, if the second functional material layer is a polymer, the second functional material layer can be formed to have a thickness between about 0.0005 microns and about 10 microns; if the second functional material layer is an IR-sensitive material, the second functional material layer can be formed to have a thickness between about 0.1 microns and about 0.2 microns; and if the second functional material layer is a piezoelectric material, the second functional material layer can be formed to have a thickness between about 0.05 microns and about 50 microns. It should be understood that in some embodiments, the second functional structure 152b can be formed before the first functional structure 152a.

[0235] In some embodiments, after forming the functional structure 152, the formation of the plurality of MEMS devices 146 is completed. The MEMS devices 146 each include a cavity 148, a movable diaphragm 150, and a functional structure 152. For example, the first MEMS device 146a among the MEMS devices 146 includes a first cavity 148a, a first movable diaphragm 150a among the movable diaphragms 150, and a first functional structure 152a, and the second MEMS device 146b among the MEMS devices 146 includes a second cavity 148b, a second movable diaphragm 150b among the movable diaphragms 150, and a second functional structure 152b.

[0236] The first MEMS device 146a and the second MEMS device 146b are different types of MEMS devices. For example, in some embodiments, the second functional material layer is a material different from the first functional material layer. Thus, due to the difference in the chemical composition of the first functional structure 152a and the second functional structure 152b, the first MEMS device 146a and the second MEMS device 146b are formed with different configurations. Accordingly, the first MEMS device 146a and the second MEMS device 146b can be different types of MEMS devices (e.g., IR detection sensors and PMUTs). Since the first MEMS device 146a and the second MEMS device 146b are different types of MEMS devices, manufacturing costs can be reduced, package size can be reduced, power consumption can be reduced, etc. It should be understood that the difference in the configuration between different types of MEMS devices is not limited to the difference in the chemical composition of the functional structure, but other types of differences can exist between different types of MEMS devices, such as differences in the doping concentration of the movable diaphragm, the presence or absence of the functional structure, etc.

[0237] As Figure 22 shown, a second passivation layer 224 is formed over the first passivation layer 222 and the functional structure 152. In some embodiments, the process for forming the second passivation layer 224 includes depositing the second passivation layer 224 over the first passivation layer 222 and the functional structure 152. The second passivation layer 224 can be deposited, for example, by CVD, PVD, ALD, other deposition processes, or a combination of the foregoing. In some embodiments, the second passivation layer 224 can be formed as a conformal layer. In still other embodiments, the second passivation layer 224 can be formed to have a thickness between about 0.05 microns and about 2 microns.

[0238] Figure 22 It is also shown that, in some embodiments, a portion of the first passivation layer 222 disposed over the fifth vias 140a and a portion of the second passivation layer 224 disposed over the fifth vias 140a can be removed. In some embodiments, the process for removing the portion of the first passivation layer 222 disposed over the fifth vias 140a and the portion of the second passivation layer 224 disposed over the fifth vias 140a includes forming a fourteenth patterned masking layer over the second passivation layer 224.

[0239] Thereafter, a fourteenth etching process is performed to remove the unmasked portions of the second passivation layer 224 and the first passivation layer 222, thereby removing the portion of the first passivation layer 222 disposed over the fifth vias 140a and the portion of the second passivation layer 224 disposed over the fifth vias 140a. The fourteenth etching process may be a dry etching process, a RIE process, a wet etching process, other etching processes, or a combination of the foregoing. Subsequently, the fourteenth patterned mask layer may be stripped. In some embodiments, after the second passivation layer 224 is formed, the formation of the semiconductor device 100 is completed.

[0240] Figure 23 A flowchart showing some embodiments of a method for forming a semiconductor device including different types of microelectromechanical systems (MEMS) devices. Although Figure 23 the flowchart 2300 shown herein is shown and described as a series of acts or events, it should be understood that the order of the acts or events shown should not be construed as limiting. For example, some acts may occur in a different order and / or may occur concurrently with other acts or events other than those shown and / or described herein. In addition, not all of the acts shown may be required to implement one or more aspects or embodiments described herein, and one or more of the acts depicted herein may be implemented in one or more separate acts and / or phases.

[0241] At act 2302, a dielectric structure is formed over an integrated circuit (IC) structure, where the IC structure includes an interconnect structure disposed over a semiconductor substrate. Figure 11 A cross-sectional view showing some embodiments corresponding to act 2302 is shown.

[0242] At act 2304, a plurality of cavity openings are formed over the semiconductor substrate and in the dielectric structure. Figures 12 to 13 A series of cross-sectional views showing some embodiments corresponding to act 2304 are shown.

[0243] At act 2306, a microelectromechanical systems (MEMS) substrate is bonded to the dielectric structure, where bonding the MEMS substrate to the dielectric structure covers the cavity openings, thereby forming a plurality of cavities over the semiconductor substrate. Figures 14 and 15 A series of cross-sectional views showing some embodiments corresponding to act 2306 are shown.

[0244] At act 2308, a plurality of vias and a plurality of conductive contacts are formed over the MEMS substrate, where the vias extend vertically through the MEMS substrate and the dielectric structure such that the vias are electrically coupled to the interconnect structure. Figures 16 to 18 A series of cross-sectional views showing some embodiments corresponding to act 2308 are shown.

[0245] At operation 2310, a first MEMS device is formed over a semiconductor substrate, wherein forming the first MEMS device includes forming a first functional structure over the MEMS substrate and over a first cavity of the plurality of cavities. Figures 19 to 21 A series of cross-sectional views showing some embodiments corresponding to operation 2310.

[0246] At operation 2312, a second MEMS device is formed over the semiconductor substrate and laterally spaced from the first MEMS device, wherein forming the second MEMS device includes forming a second functional structure over the MEMS substrate and over a second cavity of the plurality of cavities, and wherein the second MEMS device is a different type of MEMS device than the first MEMS device. Figures 19 to 21 A series of cross-sectional views showing some embodiments corresponding to operation 2312.

[0247] At operation 2314, a passivation layer is formed over the MEMS substrate, the first functional structure, the second functional structure, the vias, and the conductive contacts. Figure 22 A cross-sectional view showing some embodiments corresponding to operation 2314.

[0248] In some embodiments, the present disclosure provides a semiconductor device. The semiconductor device includes an interconnect structure disposed over a semiconductor substrate. A first dielectric structure is disposed over the interconnect structure. A first cavity is disposed in the first dielectric structure. A second cavity is disposed in the first dielectric structure and laterally spaced from the first cavity. A microelectromechanical system (MEMS) substrate is disposed over the first dielectric structure, wherein the MEMS substrate includes a first movable diaphragm overlying the first cavity and a second movable diaphragm overlying the second cavity. A first functional structure overlies the first movable diaphragm and the first cavity, wherein the first functional structure comprises a first material having a first chemical composition. A second functional structure overlies the second movable diaphragm and the second cavity, wherein the second functional structure is laterally spaced from the first functional structure, and wherein the second functional structure comprises a second material having a second chemical composition different from the first chemical composition.

[0249] In some embodiments, in the semiconductor device, the first functional structure is configured to deflect the first movable diaphragm in response to a first stimulus; and the second functional structure is configured to deflect the second movable diaphragm in response to a second stimulus different from the first stimulus. In some embodiments, in the semiconductor device, the first functional structure deflects the first movable diaphragm a first distance in response to the first stimulus; and the second functional structure does not deflect the second movable diaphragm in response to the first stimulus or deflects the second movable diaphragm a second distance smaller than the first distance in response to the first stimulus. In some embodiments, in the semiconductor device, the bottommost surface of the first functional structure is substantially coplanar with the bottommost surface of the second functional structure. In some embodiments, in the semiconductor device, the first functional structure has a first thickness; and the second functional structure has a second thickness different from the first thickness. In some embodiments, in the semiconductor device, the first functional structure has a first thickness; and the second functional structure has a second thickness substantially the same as the first thickness. In some embodiments, the semiconductor device further includes a second dielectric structure disposed between the first dielectric structure and the semiconductor substrate; a first electrode disposed in the second dielectric structure and electrically coupled to the interconnect structure, wherein the first cavity overlies the first electrode, and wherein the first electrode outputs a first electrical signal corresponding to the distance between the first movable diaphragm and the first electrode; and a second electrode disposed in the second dielectric structure and electrically coupled to the interconnect structure, wherein the second cavity overlies the second electrode, and wherein the second electrode outputs a second electrical signal corresponding to the distance between the second movable diaphragm and the second electrode. In some embodiments, the semiconductor device further includes a fluid communication channel disposed in the first dielectric structure, wherein the fluid communication channel extends laterally between the first cavity and the second cavity such that the first cavity and the second cavity are in fluid communication. In some embodiments, in the semiconductor device, the first material is an infrared radiation sensitive material; and the second material is not an infrared radiation sensitive material. In some embodiments, in the semiconductor device, the first material is a piezoelectric material; and the second material is not a piezoelectric material. In some embodiments, in the semiconductor device, the first material is a biosensitive material; and the second material is not a biosensitive material. In some embodiments, in the semiconductor device, the first material is a polymer; and the second material is not a polymer.

[0250] In some embodiments, the present disclosure provides a semiconductor device. The semiconductor device includes an interconnect structure disposed over a semiconductor substrate. A dielectric structure is disposed over the interconnect structure. A first cavity is disposed in the dielectric structure. A second cavity is disposed in the dielectric structure and is laterally spaced from the first cavity. A microelectromechanical system (MEMS) substrate is disposed over the dielectric structure, wherein the MEMS substrate includes a first movable diaphragm overlying the first cavity and a second movable diaphragm overlying the second cavity. A sensing structure overlies the first movable diaphragm and the first cavity, wherein a physical property of the sensing structure changes in response to an external stimulus. A passivation layer is disposed over the MEMS substrate, wherein the sensing structure vertically separates a first bottom surface of the passivation layer from an upper surface of the first movable diaphragm, and wherein a second bottom surface of the passivation layer overlies the second movable diaphragm and is vertically disposed between the first bottom surface and the upper surface of the first movable diaphragm.

[0251] In some embodiments, in the semiconductor device, the passivation layer directly contacts an upper surface of the sensing structure and an upper surface of the second movable diaphragm. In some embodiments, in the semiconductor device, the sensing structure has a first chemical composition; and the passivation layer has a second chemical composition different from that of the sensing structure. In some embodiments, the semiconductor device further includes a fluid communication channel disposed in the dielectric structure, wherein the fluid communication channel extends laterally between the first cavity and the second cavity such that the first cavity and the second cavity are in fluid communication. In some embodiments, the semiconductor device further includes a vent hole disposed in the MEMS substrate, wherein the vent hole extends vertically through a topmost surface of the MEMS substrate from the fluid communication channel; and a plug disposed over the MEMS substrate and covering the vent hole, wherein the passivation layer is a continuous layer covering the sensing structure and the plug.

[0252] In some embodiments, the present disclosure provides a method for forming a semiconductor device. The method includes: receiving an integrated circuit (IC) structure, wherein the IC structure includes an interconnect structure disposed on a semiconductor substrate of the IC structure. Forming a dielectric structure over the interconnect structure. Forming a first opening in the dielectric structure. Forming a second opening in the dielectric structure that is laterally spaced apart from the first opening. Bonding a microelectromechanical system (MEMS) substrate to the dielectric structure, wherein bonding the MEMS substrate to the dielectric structure covers the first opening and the second opening, thereby forming a first cavity and a second cavity, respectively. Forming a first functional structure over the MEMS substrate that overlies the first cavity. Forming a second functional structure over the MEMS substrate that overlies the second cavity, wherein the second functional structure has a different chemical composition from the first functional structure.

[0253] In some embodiments, in the method of forming a semiconductor device, wherein the second functional structure is formed with a bottom surface that is substantially coplanar with the bottom surface of the first functional structure. In some embodiments, the method of forming a semiconductor device further includes forming a fluid communication channel opening in the dielectric structure that extends laterally from the first opening to the second opening before bonding the microelectromechanical system substrate to the dielectric structure.

[0254] The foregoing outlines features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis to design or modify other processes and structures for carrying out the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, comprising: An interconnect structure disposed over a semiconductor substrate; A first dielectric structure disposed over the interconnect structure; A first cavity disposed in the first dielectric structure; A second cavity disposed in the first dielectric structure and laterally spaced from the first cavity; A microelectromechanical system (MEMS) substrate disposed over the first dielectric structure, wherein the MEMS substrate includes a first movable diaphragm overlying the first cavity and a second movable diaphragm overlying the second cavity; A first functional structure overlying the first movable diaphragm and the first cavity, wherein the first functional structure includes a first material having a first chemical composition; And A second functional structure overlying the second movable diaphragm and the second cavity, wherein the second functional structure is laterally spaced from the first functional structure, the first functional structure and the second functional structure directly contact the MEMS substrate, and wherein the second functional structure includes a second material having a second chemical composition different from the first chemical composition.

2. The semiconductor device according to claim 1, wherein: The first functional structure is configured to deflect the first movable diaphragm in response to a first stimulus; and The second functional structure is configured to deflect the second movable diaphragm in response to a second stimulus different from the first stimulus.

3. The semiconductor device according to claim 2, wherein: The first functional structure deflects the first movable diaphragm a first distance in response to the first stimulus; and The second functional structure does not deflect the second movable diaphragm in response to the first stimulus or deflects the second movable diaphragm a second distance smaller than the first distance in response to the first stimulus.

4. The semiconductor device according to claim 1, wherein: The bottommost surface of the first functional structure and the bottommost surface of the second functional structure are substantially coplanar.

5. The semiconductor device according to claim 4, wherein: The first functional structure has a first thickness; and The second functional structure has a second thickness different from the first thickness.

6. The semiconductor device according to claim 4, wherein: The first functional structure has a first thickness; and The second functional structure has a second thickness substantially the same as the first thickness.

7. The semiconductor device according to claim 1, further comprising: A second dielectric structure disposed between the first dielectric structure and the semiconductor substrate; A first electrode disposed in the second dielectric structure and electrically coupled to the interconnect structure, wherein the first cavity overlies the first electrode, and wherein the first electrode outputs a first electrical signal corresponding to the distance between the first movable diaphragm and the first electrode; And A second electrode disposed in the second dielectric structure and electrically coupled to the interconnect structure, wherein the second cavity overlies the second electrode, and wherein the second electrode outputs a second electrical signal corresponding to the distance between the second movable diaphragm and the second electrode.

8. The semiconductor device according to claim 1, further comprising: A fluid communication channel disposed in the first dielectric structure, wherein the fluid communication channel extends laterally between the first cavity and the second cavity such that the first cavity and the second cavity are in fluid communication.

9. The semiconductor device according to claim 1, wherein: The first material is an infrared radiation sensitive material; and The second material is not an infrared radiation sensitive material.

10. The semiconductor device according to claim 1, wherein: The first material is a piezoelectric material; and The second material is not a piezoelectric material.

11. The semiconductor device according to claim 1, wherein: The first material is a biosensitive material; and The second material is not a biosensitive material.

12. The semiconductor device according to claim 1, wherein: The first material is a polymer; and The second material is not a polymer.

13. A semiconductor device, comprising: An interconnect structure disposed on a semiconductor substrate; A dielectric structure disposed on the interconnect structure; A first cavity disposed in the dielectric structure; A second cavity disposed in the dielectric structure and laterally spaced from the first cavity; A microelectromechanical system (MEMS) substrate disposed on the dielectric structure, wherein the MEMS substrate includes a first movable diaphragm overlying the first cavity and a second movable diaphragm overlying the second cavity; A sensing structure overlying the first movable diaphragm and the first cavity, wherein a physical property of the sensing structure changes in response to an external stimulus; And A passivation layer disposed on the MEMS substrate, wherein the sensing structure vertically separates a first bottom surface of the passivation layer from an upper surface of the first movable diaphragm, and wherein a second bottom surface of the passivation layer overlies the second movable diaphragm and is vertically disposed between the first bottom surface and the upper surface of the first movable diaphragm.

14. The semiconductor device according to claim 13, wherein the passivation layer directly contacts an upper surface of the sensing structure and an upper surface of the second movable diaphragm.

15. The semiconductor device according to claim 13, wherein: The sensing structure has a first chemical composition; and The passivation layer has a second chemical composition different from that of the sensing structure.

16. The semiconductor device according to claim 13, further comprising: A fluid communication channel disposed in the dielectric structure, wherein the fluid communication channel extends laterally between the first cavity and the second cavity such that the first cavity and the second cavity are in fluid communication.

17. The semiconductor device according to claim 16, further comprising: A vent hole disposed in the MEMS substrate, wherein the vent hole extends vertically from the fluid communication channel through a topmost surface of the MEMS substrate; And A plug disposed on the MEMS substrate and covering the vent hole, wherein the passivation layer is a continuous layer covering the sensing structure and the plug.

18. A method of forming a semiconductor device, the method comprising: An integrated circuit structure is collected, wherein the integrated circuit structure includes an interconnect structure disposed on a semiconductor substrate of the integrated circuit structure; A dielectric structure is formed on the interconnect structure; A first opening is formed in the dielectric structure; A second opening is formed in the dielectric structure and is laterally spaced apart from the first opening; A microelectromechanical system (MEMS) substrate is bonded to the dielectric structure, wherein bonding the MEMS substrate to the dielectric structure covers the first opening and the second opening, thereby forming a first cavity and a second cavity respectively; A first functional structure is formed on the MEMS substrate and overlies the first cavity; And A second functional structure is formed on the MEMS substrate and overlies the second cavity, wherein the first functional structure and the second functional structure directly contact the MEMS substrate, and the second functional structure has a chemical composition different from that of the first functional structure.

19. The method according to claim 18, wherein the second functional structure is formed with a bottom surface that is substantially coplanar with the bottom surface of the first functional structure.

20. The method according to claim 18, further comprising: Before bonding the MEMS substrate to the dielectric structure, forming a fluid communication channel opening in the dielectric structure that extends laterally from the first opening to the second opening.

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