Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and a method of manufacturing the same are provided, which includes a first semiconductor chip and a second semiconductor chip bonded together. The first semiconductor chip includes a first substrate, a first insulating layer disposed on the first substrate and having a top surface, a first metal pad embedded in the first insulating layer and having a top surface substantially flush with the top surface of the first insulating layer, and a first barrier disposed between the first insulating layer and the first metal pad. The second semiconductor chip includes a second substrate, a second insulating layer, a second metal pad, and a second barrier in a similar configuration as the first semiconductor chip. The top surface of the first insulating layer and a bottom surface of the second insulating layer are bonded to provide a bonding interface, the first metal pad and the second metal pad are connected, and a portion of the first insulating layer is in contact with a side region of the first metal pad.

Description

TECHNICAL FIELD

[0001] The disclosure relates to a semiconductor device and a manufacturing method thereof. BACKGROUND

[0002] Conventionally, the size of a semiconductor device can be reduced by bonding a plurality of substrates each of which has a semiconductor element or an integrated circuit formed thereon. A bonding surface of each substrate includes an insulating layer and a plurality of metal pads formed therein for interconnection. The bonding surface is subjected to a polishing process for planarization. However, even after the bonding surface of each substrate is polished, a step difference occurs at the metal pads and their adjacent bonding surface, and if the step difference is not controlled within a tolerance range, defects such as voids occur even after bonding, which results in a serious yield drop. SUMMARY

[0003] According to an aspect of an embodiment, there is provided a semiconductor device including: a first semiconductor chip; and a second semiconductor chip disposed on the first semiconductor chip. The first semiconductor chip includes: a first substrate; a first insulating layer disposed on the first substrate and having a top surface; a first metal pad embedded in the first insulating layer and having a top surface substantially flush with the top surface of the first insulating layer; and a first barrier disposed between the first insulating layer and the first metal pad. The second semiconductor chip includes: a second substrate; a second insulating layer disposed below the second substrate and having a bottom surface; a second metal pad embedded in the second insulating layer and having a bottom surface substantially flush with the bottom surface of the second insulating layer; and a second barrier disposed between the second insulating layer and the second metal pad. The top surface of the first insulating layer and the bottom surface of the second insulating layer are bonded to provide a bonding interface, the first metal pad and the second metal pad are connected to each other, and a portion of the first insulating layer is in contact with a side region of the first metal pad.

[0004] According to another aspect of an embodiment, there is provided a semiconductor device including: a first substrate; a first insulating layer disposed on the first substrate and having a top surface; a first metal pad embedded in the first insulating layer and having a top surface substantially flush with the top surface of the first insulating layer; a first barrier disposed between the first insulating layer and the first metal pad; and a second insulating layer disposed on the first insulating layer and having a bottom surface, wherein the first insulating layer and the second insulating layer are bonded to provide a bonding interface, and a portion of the first insulating layer adjacent to the bonding interface is in contact with a side region of the first metal pad.

[0005] According to another aspect of an embodiment, there is provided a semiconductor device including: a first semiconductor chip; and a second semiconductor chip disposed on the first semiconductor chip. The first semiconductor chip includes: a first substrate; a first insulating layer disposed on the first substrate and having a planar top surface; a first metal pad embedded in the first insulating layer and having a top surface substantially flush with the top surface of the first insulating layer; and a first barrier disposed between the first insulating layer and the first metal pad. The second semiconductor chip includes: a second substrate; a second insulating layer disposed below the second substrate and having a planar bottom surface; a second metal pad embedded in the second insulating layer and having a bottom surface substantially flush with the bottom surface of the second insulating layer; and a second barrier disposed between the second insulating layer and the second metal pad. The top surface of the first insulating layer and the bottom surface of the second insulating layer are bonded to provide a bonding interface, the first metal pad and the second metal pad are connected, an end portion of the first barrier is spaced apart from the bonding surface, and a portion of the first insulating layer in contact with a side region of the first metal pad includes a material different from a remaining portion of the first insulating layer.

[0006] According to another aspect of an embodiment, there is provided a semiconductor device including: a first semiconductor chip; and a second semiconductor chip disposed on the first semiconductor chip. The first semiconductor chip includes: a first substrate; a first insulating layer disposed on the first substrate and having a top surface; a first metal pad embedded in the first insulating layer and having a top surface substantially flush with the top surface of the first insulating layer; and a first barrier disposed between the first insulating layer and the first metal pad. The second semiconductor chip includes: a second substrate; a second insulating layer disposed below the second substrate and having a planar bottom surface; a second metal pad embedded in the second insulating layer and having a bottom surface substantially flush with the bottom surface of the second insulating layer; and a second barrier disposed between the second insulating layer and the second metal pad. The top surface of the first insulating layer and the bottom surface of the second insulating layer are bonded to provide a bonding interface, the first metal pad and the second metal pad are connected, an end portion of the first barrier extends to the bonding interface, and a portion of the first insulating layer in contact with a side region of the first metal pad is separated from another portion of the first insulating layer by the first barrier and includes a material different from the another portion of the first insulating layer.

[0007] According to another aspect of the embodiments, a method for manufacturing a semiconductor device is provided, the method comprising: forming an opening in an insulating layer disposed on a substrate; forming a barrier on a surface exposed through the opening; forming a metal pad on the barrier to fill the interior of the opening; chemically and mechanically polishing the metal pad such that a gap is created in the opening between the upper end of the metal pad and the barrier; selectively removing an exposed portion of the barrier such that the barrier is removed from the gap, the gap is enlarged, and a region of the insulating layer is exposed; forming an additional insulating layer on the metal pad to fill the opening and the enlarged gap; and after forming the additional insulating layer, polishing the additional insulating layer such that the metal pad has a top surface substantially flush with the surface of the additional insulating layer.

[0008] According to another embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, the method comprising: forming an opening in an insulating layer disposed on a substrate; forming a barrier on a surface exposed through the opening; forming a metal pad on the barrier to fill the interior of the opening; chemically and mechanically polishing the metal pad to expose a portion of the barrier; selectively removing the exposed portion of the barrier; forming an additional insulating layer on the metal pad to fill the opening; and polishing the additional insulating layer such that the metal pad has a top surface substantially flush with the surface of the additional insulating layer. Attached Figure Description

[0009] These and other aspects will be apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, wherein:

[0010] Figure 1 This is a schematic exploded perspective view showing a semiconductor device according to an embodiment;

[0011] Figure 2 It is shown Figure 1 The diagram shows a side cross-sectional view of the semiconductor device.

[0012] Figure 3 It is shown Figure 2 An enlarged cross-sectional view of region "A" of the semiconductor device shown;

[0013] Figures 4A-4F It is used to describe the manufacturing process according to the implementation method. Figure 3 A cross-sectional view of the method for the semiconductor device shown;

[0014] Figures 5A-5C This is a cross-sectional view showing a semiconductor device according to various embodiments;

[0015] Figure 6A and Figure 6B It is a cross-sectional view used to describe a method for manufacturing a semiconductor device according to an embodiment;

[0016] Figure 7 This is a cross-sectional view showing a semiconductor device according to an embodiment;

[0017] Figures 8A-8E It is used to describe the manufacturing process according to the implementation method. Figure 7 A cross-sectional view of the method for the semiconductor device shown;

[0018] Figure 9A and Figure 9B This is a cross-sectional view showing a semiconductor device according to various embodiments;

[0019] Figure 10 This is a cross-sectional view showing a semiconductor device according to an embodiment;

[0020] Figures 11A-11C It is used to describe the manufacturing process according to the implementation method. Figure 10 A cross-sectional view of the method for the semiconductor device shown; and

[0021] Figures 12A-12C This is a cross-sectional view showing a semiconductor device according to various embodiments. Detailed Implementation

[0022] In the following description, some embodiments will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used for the same constituent elements, and repeated descriptions thereof will be omitted.

[0023] Figure 1 This is a schematic exploded perspective view showing a semiconductor device according to an embodiment. Figure 2 It is shown Figure 1 The image shows a side cross-sectional view of the semiconductor device. Figure 3 It is shown Figure 2 An enlarged cross-sectional view of region "A" of the semiconductor device shown.

[0024] Reference Figure 1 The semiconductor device 500 according to the embodiment includes a first semiconductor chip 100 and a second semiconductor chip 200 stacked on the first semiconductor chip 100.

[0025] Semiconductor device 500 may be, for example, a stacked CMOS image sensor (CIS). In this case, the second semiconductor chip 200 may be a sensor chip such as a complementary metal-oxide-semiconductor (CMOS) image sensor for capturing images of objects, and the first semiconductor chip 100 may be a logic chip having logic circuitry for reading image signals from the captured images from the second semiconductor chip 200 and performing various signal processing on the read image signals.

[0026] like Figure 1As shown, the second semiconductor chip 200 may include a pixel region PA and a pixel peripheral region PEp. The pixel region PA may be located in the central region of the second semiconductor chip 200, and multiple pixels may be configured in a two-dimensional array in the pixel region PA, with each pixel including a CMOS device. The pixel peripheral region PEp may be located outside the pixel region PA to surround the pixel region PA.

[0027] The first semiconductor chip 100 may include a logic region LA and a logic peripheral region PEI. The logic region LA may be located in the central region of the second semiconductor chip 200, and multiple logic elements may be disposed in the logic region LA. The multiple logic elements may be configured to process various circuits for processing pixel signals from pixels of the second semiconductor chip 200. For example, these circuits may include analog signal processing circuits, analog-to-digital converter (ADC) circuits, image signal processing circuits, control circuits, etc.

[0028] In this disclosure, the logical peripheral region PEI and the pixel peripheral region Pep are respectively disposed on all outer portions of the four sides of the first semiconductor chip 100 and the second semiconductor chip 200, but the implementation is not limited thereto. At least one of the logical peripheral region PEI and the pixel peripheral region PEp may not be disposed on the outer portion of at least one of the four sides.

[0029] The first semiconductor chip 100 and the second semiconductor chip 200 can be coupled to each other to provide a semiconductor device 500, such as a stacked CMOS image sensor (CIS). Referring to a partial cross-section D1-D1', i.e., Figure 2 The cross-section of the first semiconductor chip 100 and the second semiconductor chip 200 in a stacked state along the Y direction is shown, which describes the structure of the semiconductor device 500 in more detail.

[0030] Reference Figure 2 The first semiconductor chip 100 may include a first substrate 120 and a first bonding structure BS1 disposed on the upper surface of the first substrate 120. The second semiconductor chip 200 may include a second substrate 220 and a second bonding structure BS2 disposed on the bottom surface of the second substrate 220.

[0031] The first substrate 120 may include a first device substrate 105 in which logic circuitry is implemented, and a first wiring portion 115 disposed on the upper surface of the first device substrate 105. The first wiring portion 115 may include a first interlayer insulating layer 111, a first wiring 112, and a first vertical contact 113. The first vertical contact 113 may electrically connect the first wiring 112 or electrically connect the first wiring 112 to the first device substrate 105 (e.g., logic circuitry).

[0032] Similarly, the second substrate 220 may include a second device substrate 205 in which a CMOS circuit is implemented, and a second wiring portion 215 disposed on the bottom surface of the second device substrate 205. The second wiring portion 215 may include a second interlayer insulating layer 211, a second wiring 212, and a second vertical contact 213. The second vertical contact 213 may electrically connect the second wiring 212 or electrically connect the second wiring 212 to the second device substrate 205 (e.g., a CMOS circuit).

[0033] Although not shown, color filters and microlenses can be formed on the upper surface of the second device substrate 205. A structure on which the second device substrate 205, on which pixels are formed, wherein the color filters and microlenses are formed in the opposite direction to the second wiring portion 215 is called a back-side illumination (BSI) structure. Conversely, a structure on the second device substrate 205 in which the color filters and microlenses are formed in the same direction as the second wiring portion 215 (i.e., the color filters and microlenses are formed on the second wiring portion 215) is called a front-side illumination (FSI) structure.

[0034] The first bonding structure BS1 of the first semiconductor chip 100 may include: a first insulating layer 131 disposed on the surface (e.g., the upper surface) of the first substrate 120; a plurality of first metal pads 155 embedded in the first insulating layer 131 and having end surfaces exposed by the first insulating layer 131; and a first blocking member 152 disposed between the first insulating layer 131 and the first metal pads 155. The first insulating layer 131 may have a flat surface, and the surface of the first insulating layer 131 may have a coplanar surface (hereinafter also referred to as "surface") substantially flush with the upper surface of the first metal pads 155. Each first metal pad 155 may be connected to a logic circuit via a first wiring portion 115 of the first substrate 120.

[0035] Similarly, the second bonding structure BS2 of the second semiconductor chip 200 may include a second insulating layer 231 formed on the surface (e.g., the lower surface) of the second substrate 220, a plurality of second metal pads 255 embedded at positions corresponding to the first metal pads 155 and having end surfaces exposed by the second insulating layer 231, and a second barrier 252 disposed between the second insulating layer 231 and the second metal pads 255. The second insulating layer 231 may have a flat surface, and the surface of the second insulating layer 231 may have a coplanar surface (hereinafter also referred to as "surface") substantially flush with the lower surface of the second metal pads 255. Each second metal pad 255 may be connected to a CMOS circuit via, for example, a second wiring portion 215 of the second substrate 220.

[0036] For example, at least one of the first metal pad 155 and the second metal pad 255 may include Cu, Co, Mo, Ru, W or alloys thereof. The first blocking member 152 and the second blocking member 252 may be conductive blocking members, and at least one of the first blocking member 152 and the second blocking member 252 may include Ta, TaN, Mn, MnN, WN, Ti, TiN or combinations thereof.

[0037] exist Figures 1-3 In some embodiments, etch stop layers 116 and 216 may be included between the first insulating layer 131 and the first wiring portion 115, and between the second insulating layer 231 and the second wiring portion 215, respectively. For example, etch stop layers 116 and 216 may include silicon nitride or aluminum nitride.

[0038] For example, the first insulating layer 131 and the second insulating layer 231 may include silicon oxide, silicon nitride, silicon oxide nitride, silicon carbon nitride, etc., and may have a multilayer structure with different materials. Figures 1-3 In the embodiments, the first insulating layer 131 and the second insulating layer 231 may include first insulating films 131a and 231a and second insulating films 131b and 231b, and the first insulating films 131a and 231a may include materials different from those of the second insulating films 131b and 231b. For example, the first insulating films 131a and 231a may be silicon oxide, and the second insulating films 131b and 231b may be silicon oxide nitride, silicon carbon nitride, or silicon nitride.

[0039] like Figure 2 As shown, the second semiconductor chip 200 can be disposed on the first semiconductor chip 100 to be bonded to the first semiconductor chip 100. The first semiconductor chip 100 and the second semiconductor chip 200 can be configured to be bonded to each other such that the first bonding structure BS1 and the second bonding structure BS2 face each other, that is, the first insulating layer 131 and the first metal pad 155 face each other, as do the second insulating layer 231 and the second metal pad 255.

[0040] exist Figures 1-3In this embodiment, after polishing and planarizing each surface of the first insulating layer 131 and the second insulating layer 231, the first semiconductor chip 100 and the second semiconductor chip 200 can be directly bonded without adhesive. In this bonding process, the first and second insulating layers 131, 231 can be initially bonded by hydrogen bonding due to intermolecular forces, and subsequently, by applying heat treatment to the first and second insulating layers 131, 231, the first and second semiconductor chips 100, 200 can be bonded by the bonding between the first metal pad 155 and the second metal pad 255 (e.g., Cu-Cu bonding) and the covalent bonding between the first insulating layer 131 and the second insulating layer 231. This heat treatment process can be performed under constant pressure conditions. The bonding between the first metal pad 155 and the second metal pad 255 can also be directly connected without the need for other bonding media (e.g., eutectic metal) to form an interconnected structure.

[0041] As described above, the first semiconductor chip 100 and the second semiconductor chip 200 are interconnected by a direct connection of the first metal pad 155 and the second metal pad 255, so that the image signal from the second semiconductor chip 200 can be transmitted to the logic circuit of the first semiconductor chip 100.

[0042] Because according to Figures 1-3 In this embodiment, the bonding of the first semiconductor chip 100 and the second semiconductor chip 200 is performed by bonding the first and second metal pads 155, 255 (i.e., metal bonding) and the first and second insulating layers 131, 231, so this is also referred to as hybrid bonding. In different embodiments, this bonding can be achieved through a stacking / bonding process of a wafer including a plurality of first semiconductor chips 100 and a wafer including a plurality of second semiconductor chips 200, rather than being achieved at a separate chip level.

[0043] For example, a wafer comprising multiple first semiconductor chips 100 and a wafer comprising multiple second semiconductor chips 200 can be bonded together and then separated into multiple individual stacked chip structures by a dicing process. Similar to... Figure 1 The semiconductor device 500 shown can have a two-layer structure, including a first semiconductor chip 100 and a second semiconductor chip 200, in each stacked chip structure.

[0044] exist Figures 1-3 In the bonding structure BS used in the embodiment, at least one of the first insulating layer 131 and the second insulating layer 231 may have a portion that contacts a side region of the adjacent bonding interface of the associated metal pad(s) (preferably see) Figure 3At least one insulating layer may be formed to be in close contact with the side region so that there are no gaps at the interface between the side regions and the adjacent bonding interfaces of the associated metal pad(s), thereby ensuring strong bonding strength.

[0045] Figure 3 yes Figure 2 An enlarged cross-sectional view of region "A" of the semiconductor device 500 shown.

[0046] Reference Figure 2 and Figure 3 The first insulating layer 131 has a portion 131S that contacts a side region SA adjacent to the bonding interface BL of the first metal pad 155, wherein the first insulating layer 131 and the second insulating layer 231 are bonded at the bonding interface BL. Similarly, the second insulating layer 231 has a portion 231S that contacts a side region SA adjacent to the bonding interface BL of the second metal pad 255. Figure 3 As shown, the ends 152T and 252T of the first and second blocking members 152 and 252 are spaced apart from the bonding interface BL. The spacing distance d1 can depend on the wet etching process conditions for the blocking members (see...). Figure 4D For example, the distance d1 can range from approximately 1 nm to approximately 100 nm, and in some embodiments, it can range from 2 nm to 20 nm. The side regions SA of the first metal pad 155 and the second metal pad 255 exposed by the gap can respectively make close contact with the first insulating layer 131 and the second insulating layer 231 up to a distance d1 apart. As a result, there are no gaps around the first metal pad 155 and the second metal pad 255 adjacent to the bonding interface BL, thus enhancing the bonding strength.

[0047] exist Figures 1-3 In the embodiments described above, the first insulating layer 131 and the second insulating layer 231 may respectively include first insulating films 131a and 231a and second insulating films 131b and 231b. In this case, as Figure 3 As shown, the ends 152T and 252T of the first and second blocking members 152 and 252 can be located in the second insulating films 131b and 231b, respectively. In addition, the portions 131S and 231S of the side regions SA of the first insulating layer 131 and the second insulating layer 231 that are adjacent to the bonding interface BL of the first metal pad 155 and the second metal pad 255 can be parts of the second insulating films 131b and 231b, respectively.

[0048] exist Figures 1-3In the embodiments described, both the first semiconductor chip 100 and the second semiconductor chip 200 have the same type of gapless structure, but the embodiments are not limited to this. One of the first semiconductor chip 100 and the second semiconductor chip 200 may adopt the above-described gapless structure, and the other semiconductor chip may have a different type of gapless structure or a prior art structure. Such various embodiments will be referred to later. Figures 5A-5C Describe it.

[0049] exist Figures 1-3 In some embodiments, the first semiconductor chip 100 is shown as including only logic regions. In some embodiments, in addition to logic regions, the first semiconductor chip 100 may also include memory regions. Memory elements may be disposed in the memory regions. For example, memory elements may include dynamic random access memory (DRAM) and / or magnetic random access memory (MRAM).

[0050] according to Figures 1-3 The semiconductor device 500 in one embodiment is shown as a two-layer structure of a first semiconductor chip 100 and a second semiconductor chip 200, but in another embodiment, the semiconductor device may have a structure in which three or more semiconductor chips are stacked.

[0051] For example, a stacked CIS according to some embodiments may include a first semiconductor chip in which logic elements are disposed, a second semiconductor chip disposed on top of the first semiconductor chip and having pixels and a CMOS sensor, and a third semiconductor chip disposed below the first semiconductor chip. The third semiconductor chip may include storage elements. Even in this case, at least one of the two bonding structures between the first and third semiconductor chips may have according to Figures 1-3 The joining structure of the implementation method.

[0052] Figures 4A-4F It is used to describe the manufacturing process according to the implementation method. Figure 3 A cross-sectional view of a method for manufacturing a semiconductor device. The manufacturing process can be used to form... Figure 1 and Figure 2 The process of the first bonding structure BS1 of the first semiconductor chip 100 of the semiconductor device 500 shown can be performed at the wafer level on the first substrate 120.

[0053] Reference Figure 4A An opening H is formed in the initial first insulating layer 131' disposed on the first substrate 120.

[0054] The initial first insulating layer 131' is formed to cover the first wiring 112 exposed from the surface of the first substrate 120. The initial first insulating layer 131' may include a first insulating film 131a disposed on the first substrate 120 and a second insulating film 131b disposed on the first insulating film 131a. For example, the first insulating film 131a may be silicon oxide, and the second insulating film 131b may be silicon oxide nitride, silicon carbon nitride, or silicon nitride.

[0055] An opening H may be formed to expose a portion of the first wiring 112. As described above, the first wiring 112 may be connected to logic elements of the first substrate 120. The opening H may be formed in the form of a hole or a trench. When an etch stop layer 116 is provided on the first wiring 112, the etch stop layer 116 may be removed to expose the first wiring 112.

[0056] Reference Figure 4B A first blocking element 152 and a first metal pad 155 are sequentially formed in the opening H.

[0057] A first barrier 152 is conformally formed on the inner surface of the opening H and the top surface of the initial first insulating layer 131'. For example, the first barrier 152 may include Ta, TaN, Mn, MnN, WN, Ti, TiN, or combinations thereof. A first metal pad 155 is formed on the first barrier to fill the interior of the opening H. For example, the first metal pad 155 may include Cu, Co, Mo, Ru, W, or alloys thereof. In some embodiments, the first barrier 152 may be TaN, and the first metal pad 155 may be Cu.

[0058] Next, refer to Figure 4C The first metal pad 155 was polished using a chemical mechanical polishing (CMP) process.

[0059] In this process, CMP is used to remove the portion of the first metal pad 155 located on the initial first insulating layer 131'. In this CMP process, the upper end of the first metal pad 155 can have a flat surface flush with the upper surface of the initial first insulating layer 131', but in practice, a step difference can occur between it and the initial first insulating layer 131'.

[0060] Simultaneously, electrochemical corrosion can occur between the material of the initial first insulating layer 131' and the metal of the first metal pad 155. As a result, such as Figure 4CAs shown, the corner portion of the first metal pad 155 can be removed. After the CMP process, the edge portion of the upper end 155T' of the first metal pad 155 can be removed. Therefore, a first gap G1 can be formed between the portion of the initial first insulating layer 131' adjacent to the upper end 155T' of the first metal pad 155 and the upper end 155T'. This first gap G1 remains around the metal pad and creates a void after the bonding process.

[0061] Reference Figure 4D The exposed portion of the first blocking member 152 can be selectively removed.

[0062] The process can be performed by wet etching, which can selectively etch the first barrier 152. For example, when the first barrier 152 is TaN, a wet etching process can be performed to selectively remove material from the first barrier 152, so that the initial first insulating layer 131' and the first metal pad 155 formed of other metals are not damaged.

[0063] The portion of the first barrier 152 disposed on the upper surface of the initial first insulating layer 131' and the portion of the first barrier 152 exposed inside the opening H can be removed. Since the first barrier 152 is removed by a wet etching process, it can be additionally removed to a depth equal to the distance d1 in the portion not exposed by the first gap G1, i.e., the portion between the initial first insulating layer 131' and the first metal pad 155. This depth (and therefore the distance) can be predetermined. Although the implementation is not limited to this, the additional removal depth (and therefore the distance d1) can, for example, be equal to or less than 100 nm.

[0064] As a result, the first gap G1 between the upper end 155T' of the first metal pad 155 and the initial first insulating layer 131' can be provided as an enlarged second gap G2. For example, with Figure 4C Compared to the first gap G1, the enlarged second gap G2 can increase the thickness of the removed first block 152 in terms of width, and in terms of height, the enlarged second gap G2 can increase the depth of the additional removed portion of the first block 152.

[0065] Next, refer to Figure 4E An additional insulating layer 131b' can be formed on the first metal pad 155 to fill the opening H.

[0066] When the opening H is filled by the additional insulating layer 131b', the enlarged second gap G2 can also be filled. Specifically, since the second gap G2 extends to a sufficient size (e.g., tens of nanometers or larger) in the aforementioned process, the enlarged second gap G2 can be filled by conventional insulating layer formation processes (e.g., CVD deposition, etc.). The additional insulating layer 131b' can contact the upper end 155T' of the first metal pad 155 and its adjacent side region (i.e., the portion without the first barrier 152).

[0067] For example, the additional insulating layer 131b' may include silicon oxide, silicon nitride, silicon oxide nitride, silicon carbon nitride, etc. Figures 4A-4F In some embodiments, the additional insulating layer 131b' may be made of the same material as the second insulating film 131b. The additional insulating layer 131b' is not limited to this and may be formed of a different material from the surrounding insulating layers (e.g., the second insulating film 131b), (see...) Figure 6A and Figure 6B ).

[0068] Next, refer to Figure 4F The result obtained in the aforementioned process is polished to form a bonding surface BP, on which the top surface 155T of the first metal pad 155 is exposed, thereby completing the first insulating layer 131.

[0069] pass Figures 4A-4F In the process, at the bonding surface BP, the first metal pad 155 may have a top surface 155T that is substantially flush with the surface of the first insulating layer 131. The end 152T of the first stop 152 may be spaced apart from the bonding surface BP. After the polishing process, the additional insulating layer 131b' may be retained as a portion 131S, which has a surface substantially flush with the surface of the other portions of the first insulating layer 131. The retained portion 131S can be understood as a part of the first insulating layer 131 and may be provided directly to the side region of the first metal pad 155 adjacent to the bonding surface BP without the first stop 152.

[0070] In some implementations, similar manufacturing processes can be performed to form Figure 1 and Figure 2 The second bonding structure BS2 of the second semiconductor chip 200 of the semiconductor device 500 shown.

[0071] Figures 5A-5C This is a cross-sectional view showing a semiconductor device according to various embodiments.

[0072] refer to Figure 5A You can refer to this. Figures 1-3The illustrated embodiment is used to understand the semiconductor device, except that there is a gap V in the bonding structure of the semiconductor chip (e.g., the second semiconductor chip 200). Additionally, reference can be made to... Figures 1-3 The description of the same or similar elements in the illustrated embodiments is used for understanding. Figure 5A The elements of the embodiments are as follows, unless otherwise specifically stated.

[0073] exist Figure 5A In the implementation method, the first semiconductor chip 100 may have, as in Figures 1-3 The voidless structure described in the embodiment. Specifically, the end 152T of the first blocking member 152 is spaced apart from the bonding interface, and in the spaced-apart region, the first insulating layer 131 has a portion 131S that contacts the side region of the first metal pad 155 and is adjacent to the bonding interface.

[0074] On the other hand, Figure 5A In the embodiment, the second semiconductor chip 200 has a gap V around the second metal pad 255', which is similar to the prior art. Specifically, the end 252T' of the second barrier 252 extends to the bonding interface, and a gap V is generated between the side regions of the second barrier 252 and the second metal pad 255' in the region adjacent to the bonding interface.

[0075] In addition, Figure 5A In this embodiment, even if a gap V exists at the bonding surface of the second semiconductor chip 200, the gap V is removed from the bonding surface of the first semiconductor chip 100 on the other side, thereby improving the overall bonding strength.

[0076] Reference Figure 5B You can refer to this. Figures 1-3 The illustrated embodiment is used to understand the semiconductor device, except that the first and second metal pads are slightly misaligned. Additionally, reference can be made to... Figures 1-3 The description of the same or similar elements in the illustrated embodiments is used for understanding. Figure 5B The elements of the embodiments are as follows, unless otherwise specifically stated.

[0077] In some cases, the first metal pad 155 and the second metal pad 255' can be precisely aligned before forming the bonding structure. However, during bonding, the first metal pad 155 and the second metal pad 255' can be bonded to a slight offset within tolerance. Even in this slightly offset state, the first semiconductor chip 100 and the second semiconductor chip 200 have a gapless structure, thereby ensuring a strong bond and effectively preventing defects caused by the expansion of gaps during the thermo-pressing of the metal bonding of the first and second metal pads (155, 255').

[0078] ReferenceFigure 5C You can refer to this. Figures 1-3 The semiconductor device is understood through the embodiments shown, except that the first and second metal pads to be bonded can be different. Additionally, reference can be made to... Figures 1-3 The description of the same or similar elements in the illustrated embodiments is used for understanding. Figure 5C The elements of the embodiments are as follows, unless otherwise specifically stated.

[0079] In some embodiments, the first metal pad 155 and the second metal pad 255'' to be joined do not necessarily have to have the same size. For example, in Figure 5C In one embodiment, the second metal pad 255'' may have a width W2 greater than the width W1 of the first metal pad 155. Similar to... Figure 5A The first semiconductor chip 100 can have, for example, the following characteristics: Figures 1-3 In the embodiment of the gapless structure, the end 252T'' of the second barrier 252'' in the second semiconductor chip 200 can extend to the bonding interface, and a gap V can be generated in the region adjacent to the bonding interface BL between the side region of the second barrier 252'' and the second metal pad 255''.

[0080] In addition, Figure 5C In this embodiment, even if there is a gap V on the bonding surface of the second semiconductor chip 200, the gap V can be removed from the bonding surface of the first semiconductor chip 100 on the other side, thereby improving the overall bonding strength.

[0081] According to Figures 4A-4F In the manufacturing process of this embodiment, the additional insulating layer that fills the enlarged gap can be a material different from the first insulating layer. This will refer to... Figure 6A and Figure 6B It is described using the process.

[0082] Figure 6A and Figure 6B This is a cross-sectional view used to describe a method of manufacturing a semiconductor device according to an embodiment, and can be understood as... Figure 4D The process introduced after the previous process. That is, in Figure 6A and Figure 6B The process shown can be performed beforehand. Figures 4A-4D The process.

[0083] Reference Figure 6A An additional insulating layer 131c can be formed on the first metal pad 155 to fill the opening H with an enlarged second gap G2.

[0084] The additional insulating layer 131c can be formed of an insulating material different from that of the second insulating film 131b. For example, when the first insulating film 131a is silicon oxide and the second insulating film 131b is silicon carbonitride, the additional insulating layer 131c can be silicon oxide. Of course, this is just an example; in some embodiments, the additional insulating layer 131c can be formed of a material different from that of the first insulating film 131a and the second insulating film 131b. For example, the additional insulating layer 131c can be formed of silicon oxide nitride, silicon nitride, etc. The additional insulating layer 131c can contact the upper end 155T' of the first metal pad 155 and the adjacent side region without the first blocking member 152, and can also be distinguished from the second insulating film 131b.

[0085] Next, refer to Figure 6B Polishing can be performed using the aforementioned process (i.e., Figure 6A The result obtained is used to form a bonding surface BP on the top surface 155T of the first metal pad 155 exposed thereon.

[0086] After polishing, at the bonding surface BP, the first metal pad 155 may have a top surface 155T that is substantially flush with the surface of the first insulating layer 131. The end 152T of the first stop 152 may be spaced apart from the bonding surface BP. In the spaced-apart region, the side region of the first metal pad 155 adjacent to the bonding surface BP may contact the reserved portion 131S of the additional insulating layer 131c. The portion 131S may include a material different from the material of the first insulating film 131a and the second insulating film 131b of the first insulating layer 131.

[0087] Furthermore, the shape of the upper end of the first metal pad 155 can be consistent with... Figures 1-4F The shapes vary depending on the polishing thickness in this process. Figures 1-4F In this implementation, the surface is polished sufficiently so that the upper end of the final first metal pad 155 has a substantially vertical side surface (see...). Figure 4F Conversely, in Figure 6B In the process, the region C where the upper edge of the first metal pad 155 was removed can be retained in the final structure.

[0088] Figure 7 This is a cross-sectional view showing a semiconductor device according to an embodiment.

[0089] Reference Figure 7 You can refer to this. Figures 1-3 The semiconductor device is understood through the illustrated embodiments, except that the first insulating layer 131 can be formed of a single insulating material. Additionally, reference can be made to... Figures 1-3 The description of the same or similar elements in the illustrated embodiments is used for understanding. Figure 7The elements of the embodiments are as follows, unless otherwise specifically stated.

[0090] Similar to Figures 1-3 In one embodiment, the first bonding structure of the first semiconductor chip 100 may include: a first insulating layer 131 disposed on the surface of the first substrate 120; a plurality of first metal pads 155 embedded in and exposed from the first insulating layer 131; and a first blocking member 152 disposed between the first insulating layer 131 and the first metal pads 155. The first insulating layer 131 may have a flat surface, and the surface of the first insulating layer 131 may have a surface substantially coplanar with the top surface 155T of the first metal pads 155. Each of the first metal pads 155 may be connected to a logic circuit via a first wiring portion 115 of the first substrate 120.

[0091] Similarly, the second bonding structure of the second semiconductor chip 200 may include: a second insulating layer 231 formed on the surface (e.g., the bottom surface) of the second substrate 220; a plurality of second metal pads 255 embedded at positions corresponding to the first metal pads 155 and having portions exposed from the second insulating layer 231; and a second barrier 252 disposed between the second insulating layer 231 and the second metal pads 255. The second insulating layer 231 may have a coplanar surface substantially flush with the lower surface of the second metal pads 255. Each second metal pad 255 may be connected to a CMOS circuit via, for example, a second wiring portion 215 of the second substrate 220.

[0092] and Figures 1-3 Depending on the implementation method, the first insulating layer 131 and the second insulating layer 231 can be formed from a single material. For example, the first insulating layer 131 and the second insulating layer 231 may include silicon oxide, silicon nitride, silicon oxide nitride, silicon carbon nitride, etc.

[0093] The first insulating layer 131 may have a portion 131S that contacts the side region of the first metal pad 155 adjacent to the bonding interface BL. Similarly, the second insulating layer 231 may have a portion 231S that contacts the side region of the second metal pad 255 adjacent to the bonding interface BL. As a result, there are no gaps around the first metal pad 155 and the second metal pad 255 adjacent to the bonding interface BL, thus enhancing the bonding strength.

[0094] Figures 8A-8E It is used to describe the manufacturing process according to the implementation method. Figure 7 A cross-sectional view of the method for the semiconductor device shown.

[0095] Reference Figure 8A A first barrier 152 and a first metal pad 155 are sequentially formed in the opening H in the initial first insulating layer 131'.

[0096] The initial first insulating layer 131' may include, for example, silicon oxide as a single material. An opening H may be formed to expose a portion of the first wiring 112. As described above, the first wiring 112 may be connected to logic elements of the first substrate 120. A first barrier 152 is conformally formed on the inner surface of the opening H and the upper surface of the initial first insulating layer 131'. A first metal pad 155 is formed on the first barrier 152. In some embodiments, the first barrier 152 may be TaN, and the first metal pad 155 may be Cu.

[0097] Next, refer to Figure 8B The first metal pad 155 can be polished using the CMP process.

[0098] In this process, a portion of the first metal pad 155 located on the initial first insulating layer 131' is removed using a CMP process. In such a CMP process, a step difference with the initial first insulating layer 131' can be created, and the corner portion of the upper end 155T' of the first metal pad 155 can be removed due to electrochemical etching. As a result, a first gap G1 can be formed around the upper end 155T' of the first metal pad 155 between the upper end 155T' and the initial first insulating layer 131'. After the bonding process, the first gap G1 can remain around the first metal pad 155 to create a void.

[0099] Subsequently, referring to Figure 8C The exposed portion of the first blocking member 152 can be selectively removed.

[0100] This process can be performed by wet etching, which selectively etches the first barrier 152. The portion of the first barrier 152 disposed on the upper surface of the initial first insulating layer 131' and the portion exposed inside the opening H can be removed. Since the first barrier 152 is removed by the wet etching process, in the portion not exposed in the first gap G1, i.e., the portion between the initial first insulating layer 131' and the first metal pad 155, the first barrier 152 can be additionally removed to a depth equal to the distance d1. This depth (and therefore the distance) can be predetermined. As a result, the first gap G1 between the upper end 155T' of the first metal pad 155 and the initial first insulating layer 131' can be provided as an enlarged second gap G2.

[0101] Next, refer to Figure 8D An additional insulating layer 131b' can be formed on the first metal pad 155 to fill the opening H.

[0102] As the opening H is filled with the additional insulating layer 131b', the enlarged second gap G2 can also be filled simultaneously. Specifically, since the second gap G2 extends to a sufficient size (e.g., tens of nanometers or larger) in the aforementioned process, it can be filled using conventional insulating layer formation processes (e.g., CVD deposition, etc.). The additional insulating layer 131b' can contact the upper end 155T' of the first metal pad 155 and the adjacent side region without the first barrier 152.

[0103] Next, refer to Figure 8E The result obtained in the aforementioned process is polished to form a bonding surface BP, where the top surface 155T of the first metal pad 155 is exposed, thereby completing the first insulating layer 131.

[0104] pass Figures 8A-8E In the process, at the bonding surface BP, the first metal pad 155 may have a top surface 155T that is substantially flush with the surface of the first insulating layer 131. The end 152T of the first stop 152 may be spaced apart from the bonding surface BP. After the polishing process, the additional insulating layer 131b' may be retained as a portion 131S having a surface substantially flush with the surface of the other portions of the first insulating layer 131. The side surface of the first metal pad 155 adjacent to the bonding surface BP may directly contact said portion 131S without the first stop 152.

[0105] Figure 9A and 9B This is a cross-sectional view showing a semiconductor device according to various embodiments.

[0106] Reference Figure 9A Semiconductor devices can be similar to Figure 7 The illustrated embodiment, except that the misalignment between the second semiconductor chip 200 and the first semiconductor chip 100, and the presence of a gap V in the bonding structure of the second semiconductor chip 200, are also present. Additionally, reference can be made to... Figure 7 The description of the same or similar elements in the illustrated embodiments is used for understanding. Figure 9A The elements of the embodiments are as follows, unless otherwise specifically stated.

[0107] exist Figure 9A The first semiconductor chip 100 used in the embodiment has, as shown in the example Figure 7 The voidless structure described in the embodiment. Specifically, the end 152T of the first blocking member 152 is spaced apart from the bonding interface BL, and in the spaced-apart region, the first insulating layer 131 has a portion 131S that contacts the side region of the first metal pad 155 adjacent to the bonding interface BL.

[0108] On the other hand, the second semiconductor chip 200 has a gap V around the second metal pad 255. Specifically, the end 252T' of the second barrier 252 extends to the bonding interface BL, and a gap V is formed between the second barrier 252 and the side region of the second metal pad 255 in a region adjacent to the bonding interface BL. Additionally, in Figure 9A In one embodiment, the first metal pad 155 and the second metal pad 255 can be joined to be slightly offset within tolerance.

[0109] In addition, Figure 9A In this embodiment, even if a gap V exists on the bonding surface of the second semiconductor chip 200 and is slightly misaligned, the gap V is removed from the bonding surface of the first semiconductor chip 100 on the other side, thereby improving the overall bonding strength.

[0110] Reference Figure 9B Semiconductor devices can be similar to Figure 7 In the illustrated embodiment, except that portions 131S' and 231S' of the insulating layer that contact the side regions of the first metal pad 155 and the second metal pad 255 are formed of a material different from the other portions of the first insulating layer 131 and the second insulating layer 231. Additionally, reference can be made to... Figure 7 The description of the same or similar elements in the illustrated embodiments is used for understanding. Figure 9B The elements of the embodiments are as follows, unless otherwise specifically stated.

[0111] Both the first semiconductor chip 100 and the second semiconductor chip 200 can have a gapless structure. Specifically, the ends 152T of the first blocking member 152 and the second blocking member 252 are spaced apart from the bonding interface BL, and in the spaced-apart regions, the first insulating layer 131 and the second insulating layer 231 have portions 131S' and 231S' that respectively contact the side surfaces of the first metal pad 155 and the second metal pad 255 adjacent to the bonding interface. Portions 131S' and 231S' may each comprise a material different from the material of the other portions of the first insulating layer 131 and the second insulating layer 231. According to this structure, Figure 9B The semiconductor device shown can be used Figure 8D The additional insulating layer 131b' shown is made of a different material than the other parts of the first insulating layer 131.

[0112] Unlike the aforementioned embodiments, the barrier can be formed by filling the gaps created in the CMP process with an insulating material, without the need for wet etching. This embodiment... Figure 10 As shown in the image.

[0113] Figure 10 This is a cross-sectional view showing a semiconductor device according to an embodiment.

[0114] Reference Figure 10 The diagram illustrates a first semiconductor chip 100 and a second semiconductor chip 200 bonded together. The first semiconductor chip 100 includes a first substrate 120, a first insulating layer 131 disposed on the first substrate 120 and having a flat surface, a first metal pad 155 embedded in the first insulating layer 131 and having a surface substantially flush with the surface of the first insulating layer 131, and a first barrier 152 disposed between the first insulating layer 131 and the first metal pad 155.

[0115] Similarly, the second semiconductor chip 200 may include a second substrate 220, a second insulating layer 231 disposed on the second substrate 220 and having a flat surface, a second metal pad 255 embedded in the second insulating layer 231 and having a surface substantially flush with the surface of the second insulating layer 231, and a second barrier 252 disposed between the first and second insulating films 231a and 231b of the second insulating layer 231 and the second metal pad 255.

[0116] exist Figure 10 In the embodiments, the first insulating layer 131 and the second insulating layer 231 may include first insulating films 131a and 231a and second insulating films 131b and 231b, and the first insulating films 131a and 231a may include materials different from those of the second insulating films 131b and 231b. For example, the first insulating films 131a and 231a may be silicon oxide, and the second insulating films 131b and 231b may be silicon oxide nitride, silicon carbon nitride, or silicon nitride.

[0117] The surfaces of the first insulating layer 131 and the second insulating layer 231 can be joined together to provide a bonding interface BL. The first metal pad 155 and the second metal pad 255 can be connected to each other.

[0118] The end of the first blocking member 152 extends to the bonding interface BL, and the portion 131F of the first insulating layer 131 that contacts the side region of the first metal pad 155 can be separated from the first insulating film 131a and the second insulating film 131b of the first insulating layer 131 by the first blocking member 152. Similarly, the end of the second blocking member 252 extends to the bonding interface BL, and the portion 231F of the second insulating layer 231 that contacts the side region of the second metal pad 255 can be separated from the first insulating film 231a and the second insulating film 231b of the second insulating layer 231 by the second blocking member 252.

[0119] In other words, such as Figure 10As shown, the side regions of the adjacent bonding interface BL of the first metal pad 155 and the second metal pad 255 have a recessed portion C, and the recessed portion C can be filled by portions 131F and 231F.

[0120] As a result, there may be no gaps around the first metal pad 155 and the second metal pad 255 near the joint interface BL, thereby enhancing the joint strength.

[0121] exist Figure 10 In some embodiments, both the first semiconductor chip 100 and the second semiconductor chip 200 have the same gapless structure. However, the embodiments are not limited to this, and in some embodiments, only one of the first and second semiconductor chips may have a gapless structure, while the other semiconductor chip may have a different type of gapless structure or a structure identical to that in the prior art. Such various embodiments will be referred to later. Figures 12A-12C Describe it.

[0122] Figures 11A-11C It is used to describe the manufacturing process according to the implementation method. Figure 10 A cross-sectional view of the method for the semiconductor device shown.

[0123] Reference Figure 11A CMP process is used as the manufacturing method according to the above embodiments. Figure 4C The corresponding process is used to polish the first metal pad 155. That is, it can be done... Figure 11A Before the process is performed Figure 4A and 4B The process.

[0124] exist Figure 11A In the process, CMP (Chemical Mechanical Polishing) can be used to remove the portion of the first metal pad 155 located on the initial first insulating layer 131'. In this CMP process, a step difference may exist between the upper end of the first metal pad 155 and the initial first insulating layer 131', and after the CMP process, the corner of the upper end 155T' of the first metal pad 155 can be removed due to electrochemical etching. As a result, a first gap G1 can be generated around the upper end 155T' of the first metal pad 155 between the upper end 155T' and the initial first insulating layer 131'.

[0125] Next, refer to Figure 11B An additional insulating layer 131c can be formed on the first metal pad 155 to fill the opening H.

[0126] While the opening H is filled with the additional insulating layer 131c, the first gap G1 can also be filled. This is consistent with the previous embodiment ( Figure 4EUnlike other methods, the first gap G1 can have a very narrow spacing d2 because the first barrier 152 is retained without additional etching. For example, the spacing d2 of the first gap G1 can be 2 nm or less (1 nm or less in some embodiments). Therefore, the formation process of the additional insulating layer 131c to fill the first gap G1 can include atomic layer deposition (ALD). In some embodiments, the first insulating film 131a and the second insulating film 131b are formed by a deposition process such as CVD, while the additional insulating layer 131c is formed by an ALD process, such that the additional insulating layer 131c can have a different film quality than the first and second insulating films 131a and 131b.

[0127] Reference Figure 11C ,exist Figure 11B The result obtained after the aforementioned process can be polished to form a bonding surface BP, on which the top surface 155T of the first metal pad 155 is exposed, thereby completing the first insulating layer 131.

[0128] At the bonding surface BP, the first metal pad 155 may have a top surface 155T that is substantially flush with the surface of the first insulating layer 131. The end 152T of the first stop 152 may extend to the bonding surface BP. After the polishing process, an additional insulating layer may be retained as a portion 131F, which has a surface substantially flush with the surface of the rest of the first insulating layer 131. The retained portion 131F can be understood as part of the first insulating layer 131, and the retained portion 131F that is in direct contact with the side region of the first metal pad 155 and adjacent to the bonding surface BP can be separated from the rest of the first insulating layer 131 by the first stop 152.

[0129] Figures 12A-12C This is a cross-sectional view showing a semiconductor device according to various embodiments.

[0130] Reference Figure 12A Semiconductor devices can be similar to Figure 10 The illustrated embodiment, except that the second semiconductor chip 200 may be misaligned with the first semiconductor chip 100 and a gap V may exist in the bonding structure of the second semiconductor chip 200. Additionally, reference can be made to... Figure 10 The description of the same or similar elements in the illustrated embodiments is used for understanding. Figure 12A The elements of the embodiments are as follows, unless otherwise specifically stated.

[0131] The first semiconductor chip 100 used in this embodiment has, as follows: Figure 10The voidless structure described in the embodiment. Specifically, the end of the first barrier 152 extends to the bonding interface BL, and the portion 131F that contacts (or fills) the side region of the first metal pad 155 adjacent to the bonding interface BL can be separated from the other portions of the first insulating layer 131 by the first barrier 152.

[0132] Similarly, the second semiconductor chip 200 has a gap V around the second metal pad 255. Specifically, the end 252T' of the second barrier 252 extends to the bonding interface BL, and a gap V is formed between the second barrier 252 and the side region of the second metal pad 255 in a region adjacent to the bonding interface BL.

[0133] In addition, Figure 12A In one embodiment, the first metal pad 155 and the second metal pad 255 can be joined to be slightly offset within tolerance.

[0134] In addition, Figure 12A In this embodiment, even if a gap V exists on the bonding surface of the second semiconductor chip 200 and is slightly misaligned, the gap can be removed from the bonding surface of the first semiconductor chip 100 on the other side, thereby improving the overall bonding strength.

[0135] Reference Figure 12B Semiconductor devices can be similar to Figure 10 The illustrated embodiment differs from the fact that the first insulating layer 131 and the second insulating layer 231 are formed of a single insulating material, and the filling portions 131'F and 231'F that contact the side regions are formed of a material different from that of the first insulating layer 131 and the second insulating layer 231. Additionally, reference can be made to... Figure 10 The description of the same or similar elements in the illustrated embodiments is used for understanding. Figure 12B The elements of the embodiments are as follows, unless otherwise specifically stated.

[0136] and Figure 10 Depending on the implementation method, the first insulating layer 131 and the second insulating layer 231 can be formed from a single material. For example, the first insulating layer 131 and the second insulating layer 231 may include silicon oxide, silicon nitride, silicon oxide nitride, silicon carbon nitride, etc.

[0137] The ends of the first blocking member 152 and the second blocking member 252 extend to the bonding interface BL, respectively, and the filling portions 131'F and 231'F that contact the side regions of the bonding interface BL adjacent to the first metal pad 155 and the second metal pad 255 can be separated from the first insulating layer 131 and the second insulating layer 231 by the first blocking member 152 and the second blocking member 252, respectively. The filling portions 131'F and 231'F can be made of materials different from the materials of the first insulating layer 131 and the second insulating layer 231, respectively.

[0138] Specifically, in the process of forming the additional insulating layer in the above manufacturing process (see...) Figure 11B ), can be achieved by using a different material than the first insulating layer 131 according to Figure 12B The additional insulating layer 131c is obtained in the form of the embodiment.

[0139] Reference Figure 12C Semiconductor devices can be similar to Figure 10 The exemplary embodiments shown include alternative structures where the first semiconductor chip 100 can employ another type of gapless structure. Additionally, reference can be made to... Figure 10 The description of the same or similar elements in the embodiments shown is used to understand the process. Figure 12C The elements of the embodiments are as follows, unless otherwise specifically stated.

[0140] The first semiconductor chip 100 has a reference form that differs from that of the second semiconductor chip 200. Figure 3 The described gapless structure. In detail, the end 152T of the first blocking member 152 may be spaced apart from the bonding interface BL, and in the spaced area, the first insulating layer 131 may be a portion 131S that contacts the side region of the first metal pad 155 and is adjacent to the bonding interface BL.

[0141] On the other hand, the second semiconductor chip 200 has, for example, Figure 10 The voidless structure described in the embodiment. Specifically, the end of the second barrier 252 extends to the bonding interface BL and contacts the side region of the second metal pad 255 and the portion 231'F adjacent to the bonding interface BL can be separated from the second insulating layer 231 by the second barrier 252.

[0142] As a result, there are no gaps around the first metal pad 155 and the second metal pad 255 near the joint interface BL, thus enhancing the joint strength.

[0143] By removing the voids generated during the chemical mechanical polishing process via subsequent processes, the reliability of the bonding strength between the first semiconductor chip and the second semiconductor chip can be improved.

[0144] The various advantages and effects of this disclosure are not limited to those described above. Additional advantages and effects will become more readily apparent in the process of describing specific embodiments of this disclosure. Exemplary embodiments have been disclosed herein, and although specific terminology has been used, it is used and interpreted in a general and descriptive sense only, and not for limiting purposes. In some instances, it will be apparent to those skilled in the art at the time of filing this application that features, characteristics, and / or elements described in connection with specific embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise specifically indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of this disclosure as set forth in the appended claims.

[0145] This application claims priority to Korean Patent Application No. 10-2019-0104505, filed with the Korean Intellectual Property Office (KIPO) on August 26, 2019, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device comprising: a first semiconductor chip; and a second semiconductor chip disposed on the first semiconductor chip, wherein the first semiconductor chip comprises: a first substrate; a first insulating layer disposed on the first substrate and having a top surface; a first metal pad embedded in the first insulating layer and having a top surface substantially flush with the top surface of the first insulating layer; and a first barrier disposed between the first insulating layer and the first metal pad, wherein the second semiconductor chip comprises: a second substrate; a second insulating layer disposed below the second substrate and having a bottom surface; a second metal pad embedded in the second insulating layer and having a bottom surface substantially flush with the bottom surface of the second insulating layer; and a second barrier disposed between the second insulating layer and the second metal pad; and wherein the top surface of the first insulating layer and the bottom surface of the second insulating layer are bonded to provide a bonding interface, the first metal pad and the second metal pad are connected to each other, and a portion of the first insulating layer is in contact with a side region of the first metal pad, wherein the first insulating layer comprises a first insulating film disposed on the first substrate and a second insulating film disposed on the first insulating film, an end portion of the first barrier being located in the second insulating film.

2. The semiconductor device of claim 1, wherein, The end portion of the first barrier is spaced apart from the bonding interface.

3. The semiconductor device of claim 2, wherein, The end portion of the first barrier is spaced apart from the bonding interface by a distance of 1 nm to 100 nm.

4. The semiconductor device of claim 1, wherein, The portion of the first insulating layer that is in contact with the side region of the first metal pad and is adjacent to the bonding interface is part of the second insulating film.

5. The semiconductor device of claim 4, wherein, A void is disposed between a side region of the second metal pad adjacent to the bonding interface and an end portion of the second barrier.

6. The semiconductor device of claim 4, wherein, A portion of the second insulating film that is in contact with the side region of the first metal pad covers a portion of the bottom surface of the second metal pad at the bonding interface.

7. The semiconductor device of claim 1, wherein, The first insulating film comprises silicon oxide, the second insulating film comprises an insulating material, the insulating material comprising silicon oxynitride, silicon carbonitride, or silicon nitride.

8. The semiconductor device of claim 1, wherein, The end portion of the first barrier extends to the bonding interface, and the portion of the first insulating layer that is in contact with the side region of the first metal pad is separated from another portion of the first insulating layer by the first barrier.

9. The semiconductor device of claim 8, wherein, The portion of the first insulating layer that is in contact with the side region of the first metal pad is part of the second insulating film.

10. The semiconductor device of claim 1, wherein, The second insulating layer has a portion in contact with a side region of the second metal pad.

11. The semiconductor device of claim 10, wherein, A width of the second metal pad is greater than a width of the first metal pad, and The portion of the first insulating layer that is in contact with the side region of the first metal pad covers a portion of the bottom surface of the second metal pad.

12. The semiconductor device of claim 1, wherein, The first substrate comprises a wiring portion electrically connected to a first device substrate, and an etching stopper layer is disposed between the wiring portion and the first insulating layer.

13. The semiconductor device of claim 12, wherein, The etch stop layer is in contact with a side region of the first barrier.

14. A semiconductor device, comprising: a first substrate; a first insulating layer disposed on the first substrate and having a top surface; a first metal pad embedded in the first insulating layer and having a top surface that is substantially flush with the top surface of the first insulating layer; a first barrier disposed between the first insulating layer and the first metal pad; and a second insulating layer disposed on the first insulating layer and having a bottom surface, wherein the first insulating layer and the second insulating layer are bonded to provide a bond interface, and a portion of the first insulating layer adjacent to the bond interface is in contact with a side region of the first metal pad, wherein the first insulating layer includes a first insulating film disposed on the first substrate and a second insulating film disposed on the first insulating film, an end of the first barrier being located in the second insulating film.

15. A semiconductor device, comprising: a first semiconductor chip; and a second semiconductor chip disposed on the first semiconductor chip, wherein the first semiconductor chip includes a first substrate, a first insulating layer disposed on the first substrate and having a planar top surface, a first metal pad embedded in the first insulating layer and having a top surface that is substantially flush with the top surface of the first insulating layer, a first barrier disposed between the first insulating layer and the first metal pad, wherein the second semiconductor chip includes a second substrate, a second insulating layer disposed below the second substrate and having a planar bottom surface, a second metal pad embedded in the second insulating layer and having a bottom surface that is substantially flush with the bottom surface of the second insulating layer, and a second barrier disposed between the second insulating layer and the second metal pad, and wherein the top surface of the first insulating layer and the bottom surface of the second insulating layer are bonded to provide a bond interface, the first metal pad and the second metal pad are connected, an end of the first barrier is spaced apart from the bond interface, and a portion of the first insulating layer that is in contact with a side region of the first metal pad includes a material that is different from a remainder of the first insulating layer, wherein the first insulating layer includes a first insulating film disposed on the first substrate and a second insulating film disposed on the first insulating film, the end of the first barrier being located in the second insulating film. a top surface of the second insulating film is bonded to the bottom surface of the second insulating layer to provide the bond interface, and 16. The semiconductor device of claim 15, wherein, a portion of the second insulating film is in contact with the side region of the first metal pad and includes a material that is different from the first insulating film.

17. A semiconductor device, comprising: a first semiconductor chip; and a second semiconductor chip disposed on the first semiconductor chip, wherein the first semiconductor chip includes: a first substrate; a first insulating layer disposed on the first substrate and having a top surface; a first metal pad embedded in the first insulating layer and having a top surface that is substantially flush with the top surface of the first insulating layer; and a first barrier disposed between the first insulating layer and the first metal pad. a first metal pad embedded in the first insulating layer and having a top surface that is substantially flush with the top surface of the first insulating layer; and a first barrier disposed between the first insulating layer and the first metal pad, wherein the second semiconductor chip comprises: a second substrate; a second insulating layer disposed below the second substrate and having a flat bottom surface; a second metal pad embedded in the second insulating layer and having a bottom surface that is substantially flush with the bottom surface of the second insulating layer; and a second barrier disposed between the second insulating layer and the second metal pad; and wherein the top surface of the first insulating layer and the bottom surface of the second insulating layer are bonded to provide a bonding interface, the first metal pad and the second metal pad are connected, an end portion of the first barrier contacts the bonding interface, and a portion of the first insulating layer that is in contact with a side region of the first metal pad is separated from another portion of the first insulating layer by the first barrier and comprises a different material than the other portion of the first insulating layer.

18. The semiconductor device of claim 17, wherein, the portion of the first insulating layer that is in contact with the side region of the first metal pad has a width of 2 nm or less. a first metal pad embedded in the first insulating layer and having a top surface that is substantially flush with the top surface of the first insulating layer; and a first barrier disposed between the first insulating layer and the first metal pad, wherein the second semiconductor chip comprises: a second substrate; a second insulating layer disposed below the second substrate and having a flat bottom surface; a second metal pad embedded in the second insulating layer and having a bottom surface that is substantially flush with the bottom surface of the second insulating layer; and a second barrier disposed between the second insulating layer and the second metal pad; and wherein the top surface of the first insulating layer and the bottom surface of the second insulating layer are bonded to provide a bonding interface, the first metal pad and the second metal pad are connected, an end portion of the first barrier contacts the bonding interface, and a portion of the first insulating layer that is in contact with a side region of the first metal pad is separated from another portion of the first insulating layer by the first barrier and comprises a different material than the other portion of the first insulating layer. the portion of the first insulating layer that is in contact with the side region of the first metal pad has a width of 2 nm or less.

Images