Memory cell, memory device, and method for forming a memory device

Abstract

Various embodiments of the present disclosure relate to a memory cell including a data storage structure. A top electrode overlies a bottom electrode. The data storage structure is disposed between the top electrode and the bottom electrode. The data storage structure includes a first data storage layer, a second data storage layer, and a third data storage layer. The second data storage layer is disposed between the first data storage layer and the third data storage layer. The second data storage layer has a lower band gap than the third data storage layer. The first data storage layer has a lower band gap than the second data storage layer.

Description

Technical Field

[0001] Embodiments of the present invention relate to a memory cell, a memory device, and a method for forming the memory device. Background Art

[0002] Many modern electronic devices contain electronic memory configured to store data. Electronic memory can be either volatile memory or non-volatile memory. Volatile memory stores data while it is powered, while non-volatile memory is able to retain the stored data when power is removed. Resistive random access memory (RRAM) is a promising candidate for the next generation of non-volatile memory technology due to its simple structure and compatibility with complementary metal-oxide semiconductor (CMOS) logic processes. An RRAM cell contains a dielectric data storage structure with a variable resistance. Such a dielectric data storage structure is typically placed between two electrodes disposed within an interconnect metallization layer. Summary of the Invention

[0003] According to some embodiments of the present invention, a memory cell is provided. The memory cell includes a bottom electrode, a top electrode, and a data storage structure. The top electrode overlies the bottom electrode. The data storage structure is disposed between the top electrode and the bottom electrode, wherein the data storage structure includes a first data storage layer, a second data storage layer, and a third data storage layer, the second data storage layer being disposed between the first data storage layer and the third data storage layer, the second data storage layer having a lower band gap than the third data storage layer, and the first data storage layer having a lower band gap than the second data storage layer.

[0004] According to some embodiments of the present invention, a memory device is provided. The memory device includes a bottom electrode, a top electrode, and a data storage structure. The top electrode overlies the bottom electrode. The data storage structure is disposed between the bottom electrode and the top electrode, wherein the data storage structure includes a first data storage layer, a second data storage layer, and a third data storage layer. The first data storage layer contacts the bottom electrode and includes a first material. The second data storage layer contacts the first data storage layer and includes a second material different from the first material. The third data storage layer is disposed between the second data storage layer and the top electrode, wherein the third data storage layer includes a third material different from the first material and the second material. The respective band gaps of the first data storage layer, the second data storage layer, and the third data storage layer gradually decrease or increase from the top electrode to the bottom electrode, wherein the top electrode is configured to receive a programming voltage and the bottom electrode is configured to receive a reference voltage.

[0005] According to some embodiments of the present invention, a method for forming a memory device is provided. The method includes: forming a lower interconnect wire over a substrate; forming a memory cell film stack over the lower interconnect wire, wherein the memory cell film stack includes a bottom electrode film, a first data storage film, a second data storage film, a third data storage film, and a top electrode film; patterning the memory cell film stack to define a top electrode, a bottom electrode, and a data storage structure disposed between the top electrode and the bottom electrode, wherein the data storage structure includes a first data storage layer, a second data storage layer, and a third data storage layer; and forming a via and a conductive line over the top electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 Cross-sectional views of some embodiments of memory devices including a data storage structure having three data storage layers are shown.

[0008] Figures 2 to 4 Cross-sectional views illustrating some embodiments of operating a memory device including a data storage structure having three data storage layers.

[0009] Figure 5 and Figure 6 Show Figure 1 Cross-sectional views of some alternative embodiments of memory devices.

[0010] Figure 7 Cross-sectional views of some embodiments of an integrated chip including memory cells disposed within an embedded memory region laterally adjacent to a logic region are shown.

[0011] Figure 8 Show the basis Figure 7 The line Figure 7 Top views of some alternative embodiments of integrated chips.

[0012] Figure 9 Cross-sectional views of some embodiments of an integrated chip are shown that include a memory cell including a data storage structure having three data storage layers disposed within an interconnect structure.

[0013] Figures 10 to 15 Cross-sectional views illustrating some embodiments of methods of forming a memory device including a data storage structure having three data storage layers.

[0014] Figure 16A flow chart illustrating some embodiments of a method for forming a memory device including a data storage structure having three data storage layers is shown.

[0015] Explanation of Figure Numbers

[0016] 100, 500, 600: memory devices;

[0017] 102: substrate;

[0018] 104: access transistor;

[0019] 106, 908: source / drain regions;

[0020] 108, 910: gate dielectric layer;

[0021] 110, 912: gate electrode;

[0022] 112: transistor sidewall spacer structure;

[0023] 114: conductive contact;

[0024] 116: lower internal connecting wire;

[0025] 118: Interconnect dielectric structure;

[0026] 120: bottom electrode through hole;

[0027] 122: storage unit;

[0028] 122a: first storage unit;

[0029] 122b: second storage unit;

[0030] 123: interface;

[0031] 124: bottom electrode;

[0032] 125: Region;

[0033] 126: data storage structure;

[0034] 128: first data storage layer;

[0035] 130: second data storage layer;

[0036] 132: the third data storage layer;

[0037] 134: top electrode;

[0038] 134a: metal layer;

[0039] 134b: metal oxide layer;

[0040] 136, 916: vias;

[0041] 138, 918: conductive thread;

[0042] 200: first state;

[0043] 202: oxygen atom;

[0044] 300: second state;

[0045] 302: vacant;

[0046] 400: third state;

[0047] 501: lower ILD layer;

[0048] 502: lower dielectric layer;

[0049] 504: first ILD layer;

[0050] 506: second ILD layer;

[0051] 508: cover layer;

[0052] 510: sidewall spacer structure;

[0053] 512: top electrode through hole;

[0054] 602: membrane stack;

[0055] 602m: middle area;

[0056] 602p: peripheral area;

[0057] 700, 900: integrated chip;

[0058] 702: embedded memory area;

[0059] 704: logical area;

[0060] 800: top view;

[0061] 902: transistor body node;

[0062] 904: well region;

[0063] 906: semiconductor devices;

[0064] 914: Internal connection structure;

[0065] 1000, 1100, 1200, 1300, 1400, 1500: cross-sectional views;

[0066] 1002: bottom electrode through-hole film;

[0067] 1004: memory cell film stack;

[0068] 1006: bottom electrode film;

[0069] 1008: a first data storage film;

[0070] 1010: a second data storage film;

[0071] 1012: a third data storage film;

[0072] 1014: top electrode film;

[0073] 1016: cover film;

[0074] 1102: first mask layer;

[0075] 1202: passivation layer;

[0076] 1204: second mask layer;

[0077] 1600: Method;

[0078] 1602, 1604, 1606, 1608, 1610, 1612, 1614: action;

[0079] d1: distance. DETAILED DESCRIPTION

[0080] The present disclosure provides many different embodiments or examples for implementing the different features of the provided themes. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these components and arrangements are merely examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are directly contacted, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself specify the relationship between the various embodiments and / or configurations discussed.

[0081] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and similar terms may be used herein to describe the relationship of one element or feature to another (other) element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted similarly accordingly.

[0082] A resistive random access memory (RRAM) cell includes a data storage structure (e.g., one or more oxide layers) disposed between a top electrode and a bottom electrode. The variable resistance of the data storage structure represents a data cell, such as a data bit. Depending on the voltage applied between the top and bottom electrodes, the variable resistance undergoes a reversible change between a high resistance state and a low resistance state, corresponding to the data state of the data cell. The high resistance state refers to a high resistance state when the variable resistance exceeds a threshold, and the low resistance state refers to a low resistance state when the variable resistance is below the threshold.

[0083] Before an RRAM cell can be used to store data, an initial conductive path (i.e., a conductive filament) is typically formed across the data storage structure. The formation of the initial conductive path makes subsequent write operations (which form the conductive path) easier to perform. To form the initial conductive path, a forming voltage is applied across the top and bottom electrodes at the end of the RRAM fabrication process. In some types of RRAM cells, the conductive path may include vacancies (e.g., oxygen vacancies). In such devices, the forming voltage can knock out oxygen atoms in the crystal lattice of the data storage structure, thereby forming localized oxygen vacancies. These localized oxygen vacancies tend to align to form a conductive path extending through the data storage structure. Subsequently, a set voltage or a reset voltage can be applied across the top and bottom electrodes to change the resistivity of the data storage structure. For example, when the reset voltage is applied, oxygen atoms move back into the data storage structure, thereby filling the oxygen vacancies and blocking the conductive path, increasing the resistivity. In yet another example, when the set voltage is applied, oxygen atoms in the data storage structure move to the top electrode, leaving behind oxygen vacancies and reforming the conductive path, reducing the resistivity.

[0084] In an RRAM cell, the data storage structure may generally include a first data storage layer and a second data storage layer. The first data storage layer is disposed along a bottom electrode, and the second data storage layer is disposed along a top electrode. The first data storage layer includes a first dielectric material having a first bandgap, and the second data storage layer includes a second dielectric material having a second bandgap greater than the first bandgap, wherein the first and second dielectric materials each comprise an oxide. Due to the difference between the first and second bandgaps, during formation of the conductive path, a higher number of oxygen vacancies may form in the second data storage layer compared to the first data storage layer. This, in turn, helps control the size of the conductive path so that the width of the conductive path increases from the first data storage layer to the second data storage layer. However, it is understood that after performing several set and / or reset operations, a higher number of oxygen vacancies may form in the first data storage layer, for example, along the interface between the first data storage layer and the bottom electrode. This may occur during the several set and / or reset operations due to heat accumulation at the interface, where the accumulated heat contributes to the formation of additional oxygen vacancies in the first data storage layer (i.e., the accumulated heat may break the bonds between oxygen atoms and metal atoms in the first dielectric material). This can reduce the ability of the RRAM cell to switch between discrete data states and / or cause the device to fail after a few switching cycles (e.g., within about 2×10 5 switching cycles) fault.

[0085] In some embodiments, the present disclosure relates to an RRAM cell having a data storage structure comprising a first data storage layer, a second data storage layer, and a third data storage layer. The first data storage layer is disposed along a bottom electrode, the third data storage layer is disposed along a top electrode, and the second data storage layer is disposed between the first data storage layer and the third data storage layer. The first data storage layer comprises a first dielectric material having a first band gap and the second data storage layer comprises a second dielectric material having a second band gap greater than the first band gap. In addition, the third data storage layer comprises a third dielectric material having a third band gap greater than the second band gap. Thus, the width of the conductive path formed within the data storage structure shrinks through the first data storage layer and increases from the bottom electrode to the top electrode. In addition, the first data storage layer has strong bonds between the metal atoms and the oxygen atoms within the first dielectric material (e.g., greater than about 600 kilojoules per mole (kJ / mol)). The strong bonds help increase the number of set operations and / or reset operations that can be performed on the RRAM cell because the strong bonds can survive (i.e., not break) at the high temperatures accumulated at the interface between the first data storage layer and the bottom electrode. This in turn increases the number of switching cycles (e.g., greater than 5×10 5 switching cycles), enhancing data retention and the reliability of the RRAM cell.

[0086] Figure 1 A cross-sectional view of some embodiments of a memory device 100 including a memory cell 122 having a data storage structure 126 including a first storage layer 128 , a second data storage layer 130 , and a third data storage layer 132 is shown.

[0087] Memory device 100 includes a memory cell 122 disposed above substrate 102. An interconnect dielectric structure 118 includes one or more inter-level dielectric (ILD) materials overlying substrate 102. An access transistor 104 is within substrate 102 and interconnect dielectric structure 118. Access transistor 104 includes a gate electrode 110, transistor sidewall spacer structures 112, a gate dielectric layer 108, and source / drain regions 106. Overlying access transistor 104 are one or more lower interconnect layers. According to various embodiments, access transistor 104 can be configured as another semiconductor device. The one or more lower interconnect layers include a conductive contact 114 and a lower interconnect line 116 disposed within interconnect dielectric structure 118. The bottom electrode via 120 is disposed between the lower interconnect line 116 and the memory cell 122 , wherein the bottom electrode via 120 is configured to electrically couple the memory cell 122 to one or more lower interconnect layers.

[0088] Memory cell 122 includes a bottom electrode 124, a top electrode 134, and a data storage structure 126 disposed between bottom electrode 124 and top electrode 134. Data storage structure 126 includes a first data storage layer 128, a third data storage layer 132, and a second data storage layer 130 disposed between first data storage layer 128 and third data storage layer 132. First data storage layer 128 includes a first material having a first band gap, second data storage layer 130 includes a second material having a second band gap, and third data storage layer 132 includes a third material having a third band gap. In some embodiments, the first material, the second material, and the third material are different from one another. In some embodiments, the first band gap is smaller than the second band gap, and the second band gap is smaller than the third band gap. Furthermore, first data storage layer 128 has strong bond strengths (e.g., greater than 600 kilojoules per mole (kJ / mol)) between metal atoms and oxygen atoms within the first material. However, other bond strengths can be verified. Vias 136 overlie top electrode 134 and electrically couple memory cell 122 to conductive line 138. In some embodiments, the memory cell 122 may be configured as a resistive random access memory (RRAM) cell, such that the data storage structure 126 includes a material having a variable resistance configured to undergo a reversible phase change between a high resistance state and a low resistance state. It should be understood that a memory cell 122 configured as another memory device (e.g., phase change RAM (PCRAM) or the like) is within the scope of the present disclosure. In other embodiments, the memory cell 122 and the access transistor 104 may be configured in a one-transistor one-resistive memory cell configuration (e.g., 1T1R).

[0089] During operation, the memory cell 122 relies on redox reactions to form and dissolve a conductive path in the region 125 of the data storage structure 126 between the top electrode 134 and the bottom electrode 124. The presence of a conductive path in the region 125 between the top electrode 134 and the bottom electrode 124 results in a low resistance state, while the absence of a conductive path in the region 125 results in a high resistance state. Thus, the memory cell 122 can be switched between a high resistance state and a low resistance state by applying an appropriate bias voltage to the memory cell 122 to create or eliminate the conductive path in the region 125. In some embodiments, the top electrode 134 is configured to receive a programming voltage (e.g., a forming voltage, a set voltage, a reset voltage, etc.) and the bottom electrode 124 is configured to receive a reference voltage (e.g., a ground voltage, 0 volts, etc.). In various embodiments, the memory cell 122 can be switched between a high resistance state and a low resistance state by applying a programming voltage to the top electrode 134 and a reference voltage to the bottom electrode 124.

[0090] To increase the number of switching cycles that can be performed on memory cell 122, the first band gap is smaller than the second band gap, and the second band gap is smaller than the third band gap. During the removal of the conductive path in region 125 (i.e., a "reset" operation), the number of oxygen atoms removed from first data storage layer 128 is smaller than the number of oxygen atoms removed from third data storage layer 132 due to the reduced band gap from third data storage layer 132 to first data storage layer 128. As a result, the width of the conductive path increases as it progresses from bottom electrode 124 to top electrode 134, shrinking the conductive path through first data storage layer 128. Consequently, the majority of oxygen vacancies within data storage structure 126 are located near top electrode 134, thereby making it easier for oxygen atoms to flow from or to top electrode 134 during switching cycles. This, in turn, increases the discrete data states, reliability, and endurance of memory cell 122.

[0091] In other embodiments, when switching operations are performed on memory cell 122, heat may accumulate along interface 123 between first data storage layer 128 and bottom electrode 124. In some embodiments, if the bond strength between metal atoms and oxygen atoms within the first material is less than approximately 600 kilojoules / mole, the heat accumulated along interface 123 may help break bonds within the first material, thereby reducing the ability to switch between high and low resistances. This may occur because, as more switching operations are performed, more oxygen atoms may break from metal atoms within first data storage layer 128 and travel to top electrode 134, thereby reducing data retention and / or the durability of memory cell 122. In other embodiments, if the bond strength between metal atoms and oxygen atoms within the first material exceeds approximately 600 kilojoules / mole, the bonds between metal atoms and oxygen atoms may not be affected by the heat accumulation along interface 123. This may increase the number of switching operations that can be performed on memory cell 122, thereby enhancing data retention, durability, and / or discrete data states of memory cell 122.

[0092] In some embodiments, the second data storage layer 130 and / or the third data storage layer 132 may each be or include, for example, hafnium oxide, aluminum oxide, silicon oxide, zirconium oxide, hafnium titanium oxide, hafnium tantalum oxide, tantalum aluminum oxide, hafnium zirconium oxide, tantalum zirconium oxide, hafnium cerium oxide, zirconium cerium oxide, combinations thereof, or the like. However, other materials are readily apparent. In some embodiments, the first data storage layer 128 may be, for example, or include, titanium oxide (e.g., TiO2), tantalum oxide, cerium oxide, tantalum oxynitride, hafnium tantalum oxide, hafnium tantalum oxynitride, hafnium cerium oxide, hafnium cerium oxynitride, titanium oxynitride, cerium oxynitride, tantalum oxycarbide, titanium oxynitride carbide (TiON(C)), tantalum oxynitride carbide, hafnium tantalum oxycarbide, titanium tantalum oxynitride, titanium tantalum oxycarbide, combinations thereof, or the like, and / or have a thickness in the range of approximately 5 angstroms to 20 angstroms. It should be understood that other values ​​for the thickness of the first data storage layer 128 are also within the scope of the present disclosure. Furthermore, however, other materials can be examined. In some embodiments, the second data storage layer 130 may have a thickness in the range of approximately 5 angstroms to 20 angstroms. It should be understood that other values ​​for the thickness of the second data storage layer 130 are also within the scope of the present disclosure. In other embodiments, the third data storage layer 132 may have a thickness in a range of approximately 10 angstroms to 40 angstroms. It should be understood that other values ​​for the thickness of the third data storage layer 132 are also within the scope of the present disclosure.

[0093] In other embodiments, the first data storage layer 128 may include titanium oxide (e.g., TiO2), thereby having a band gap of approximately 3.3 electron volts (eV) and a bond strength (between metal atoms and oxygen atoms) of approximately 662 kilojoules / mole, the second data storage layer 130 may include hafnium oxide (e.g., HfO2), thereby having a band gap of approximately 5.5 eV, and the third data storage layer 132 may include aluminum oxide (e.g., Al2O3), thereby having a band gap of approximately 8.5 eV. Thus, in such embodiments, the band gap of the first data storage layer 128 is smaller than the band gaps of the second data storage layer 130 and the third data storage layer 132, and the first data storage layer 128 has a strong bond strength (e.g., greater than 600 kilojoules / mole). Therefore, in some embodiments, the respective band gaps of the first data storage layer 128, the second data storage layer 130, and the third data storage layer 132 gradually decrease from the top electrode 134 to the bottom electrode 124. In other embodiments, the first data storage layer 128 may include a material having a band gap of less than approximately 4.5 eV, the second data storage layer 130 may include a material having a band gap in the range of approximately 3.5 eV to 5.5 eV, and the third data storage layer 132 may include a material having a band gap exceeding approximately 4 eV. In some embodiments, if the band gap of the first data storage layer 128 exceeds approximately 4.5 eV, a higher number of bonds between metal atoms and oxygen atoms may be broken in the first data storage layer 128 compared to the second data storage layer 130 and / or the third data storage layer 132, such that the conductive path in the data storage structure 126 may not be constricted through the first data storage layer 128. This, in turn, may reduce the number of switching operations that can be performed on the memory cell 122. Additionally, it should be understood that other values ​​for the respective band gaps of the first data storage layer 128, the second data storage layer 130, and the third data storage layer 132 are also within the scope of the present disclosure.

[0094] In yet other embodiments, the vertical layout of the first data storage layer 128, the second data storage layer 130, and the third data storage layer 132 may be reversed (not shown). For example, in some embodiments, the first data storage layer 128 may be disposed along the bottom surface of the top electrode 134, the third data storage layer 132 may be disposed along the top surface of the bottom electrode 124 (i.e., below the first data storage layer 128), and the second data storage layer 130 may be disposed between the first data storage layer 128 and the third data storage layer 132. In such embodiments, the respective band gaps of the first data storage layer 128, the second data storage layer 130, and the third data storage layer 132 may gradually increase from the top electrode 134 to the bottom electrode 124. Therefore, in various embodiments, the respective band gaps of the first data storage layer 128, the second data storage layer 130, and the third data storage layer 132 may gradually decrease or increase from the top electrode 134 to the bottom electrode 124, wherein the top electrode 134 is configured to receive a programming voltage (e.g., a forming voltage, a set voltage, a reset voltage, etc.) and the bottom electrode is configured to receive a reference voltage (e.g., a ground voltage, 0 volts, etc.).

[0095] Figures 2 to 4 Show Figure 1 1 and 2. In some embodiments, the memory cell 122 is a cross-sectional view of some embodiments of different states. Figure 2 A first state 200 is shown in which a forming operation has not yet been performed on the memory cell 122 and / or the memory cell 122 is in a high resistance state (eg, storing logic "0"). In other embodiments, Figure 3 A second state 300 is shown in which a forming operation has been performed on the memory cell 122 and / or the memory cell 122 is in a low resistance state (eg, storing logic "1"). In yet other embodiments, Figure 4 A third state 400 is shown in which the memory cell 122 is in a high resistance state (eg, storing a logic "0"). In various embodiments, Figures 2 to 4 During different states of the memory cell 122, the top electrode 134 is configured to receive a programming voltage (e.g., a forming voltage, a set voltage, a reset voltage, etc.) and the bottom electrode 124 is configured to receive a reference voltage (e.g., a ground voltage, 0 volts, etc.), or vice versa.

[0096] although Figures 2 to 4 While the memory cells are described as having conductive paths formed by oxygen vacancies, it should be understood that the disclosed data storage structures are not limited to memory devices having such paths. For example, in some embodiments, the data storage structures can be used in memory devices having conductive paths formed by conductive ions other than oxygen vacancies, or having conductive paths formed by both oxygen vacancies and conductive ions.

[0097] Figure 2An embodiment of a first state 200 of a memory cell 122 is shown. In some embodiments, the first state 200 shows the memory cell 122 before a forming operation is performed on the memory cell 122. The data storage structure 126 includes a first data storage layer 128, a second data storage layer 130, and a third data storage layer 132. In some embodiments, the first data storage layer 128, the second data storage layer 130, and / or the third data storage layer 132 may each include, for example, an oxide (such as a metal oxide), a high-k dielectric material, another suitable dielectric material, or the like. As used herein, a high-k dielectric material is a dielectric material having a dielectric constant greater than 3.9. Thus, the first data storage layer 128, the second data storage layer 130, and the third data storage layer 132 include a plurality of oxygen atoms 202 distributed across each layer. It should be understood that there may be any number of oxygen atoms distributed across the data storage structure 126 in many different locations, thereby Figure 2 This is merely an example, and for ease of illustration, some oxygen atoms present may not be shown. Furthermore, because a formation operation has not yet been performed on the memory cell 122, the first state 200 illustrates the memory cell 122 in a high resistance state. In some embodiments, the top electrode 134 may include a metal layer 134a (e.g., comprising titanium, tantalum, tungsten, or any of the aforementioned metal nitrides) overlying a metal oxide layer 134b (e.g., titanium oxide, tantalum oxide, tungsten oxide, etc.).

[0098] Figure 3 One embodiment of a second state 300 of memory cell 122 is shown, wherein a forming operation or a set operation is performed on memory cell 122. In some embodiments, during the forming operation, metal oxide layer 134b is configured to receive oxygen atoms 202 from data storage structure 126, thereby forming a vacancy 302 (e.g., an oxygen vacancy) in data storage structure 126. In other embodiments, vacancy 302 may span from top electrode 134 to bottom electrode 124, thereby defining a conductive path within region 125 such that memory cell 122 is in a low-resistance state.

[0099] In some embodiments, the first data storage layer 128 includes a first material having a first band gap, the second data storage layer 130 includes a second material having a second band gap, and the third data storage layer 132 includes a third material having a third band gap. In some embodiments, the first material, the second material, and the third material are all different from one another. Furthermore, in some embodiments, the first band gap is smaller than the second band gap, and the second band gap is smaller than the third band gap. Due to the decreasing band gap levels (from the top electrode 134 to the bottom electrode 124) and / or the proximity of the first, second, and third data storage layers 128, 130, and 132 to the top electrode 134, the number of oxygen atoms 202 removed from the first data storage layer 128 is smaller than the number of oxygen atoms 202 removed from the third data storage layer 132. Furthermore, the number of oxygen atoms 202 removed from the second data storage layer 130 is greater than the number of oxygen atoms 202 removed from the first data storage layer 128 and less than the number of oxygen atoms 202 removed from the third data storage layer 132. As a result, the width of the conductive path disposed within region 125 decreases as it travels from top electrode 134 to bottom electrode 124, causing the width of the conductive path to shrink through first data storage layer 128. Consequently, the majority of vacancies 302 within data storage structure 126 are located proximate to top electrode 134, thereby making it easier for oxygen atoms 202 to flow from or to top electrode 134 during subsequent switching cycles. This, in turn, enhances data retention, reliability, and endurance of memory cell 122.

[0100] Figure 4 One embodiment of a third state 400 of the memory cell 122 is shown, wherein a reset operation is performed on the memory cell 122. In some embodiments, the third state 400 is the state of the memory cell 122 after applying appropriate reset bias conditions between the top electrode 134 and the bottom electrode 124 such that the memory cell 122 is in a high resistance state. This, in turn, eliminates and / or removes at least a portion of the conductive path within the region 125 such that the conductive path may not extend continuously from the top electrode 134 to the bottom electrode 124. Figure 4 As shown in Figure 3 Most of the vacancies 302 are filled with corresponding oxygen atoms 202. In some embodiments, oxygen atoms 202 may travel from the top electrode 134 to fill the vacancies 302 disposed within the data storage structure 126. In other embodiments, Figure 4 All vacancies 302 are filled with corresponding oxygen atoms 202 (not shown).

[0101] In some embodiments, after performing several switching cycles, heat may accumulate at the interface 123 between the first data storage layer 128 and the bottom electrode 124. To reduce and / or eliminate degradation of the conductive path within region 125, the first material of the first data storage layer 128 has a high bond strength between the metal atoms and the oxygen atoms within the first material (e.g., greater than about 600 kilojoules / mole). This, in turn, prevents and / or mitigates the accumulated heat from breaking the bonds between the oxygen atoms and the metal atoms within the first material, thereby preventing additional vacancies from forming within the first data storage layer 128 as the number of switching cycles increases. Thus, the first data storage layer 128, including a low band gap (e.g., less than about 4.5 eV) and a high bond strength between the metal atoms and the oxygen atoms within the first material, increases the number of switching operations that can be performed on the memory cell 122 and enhances data retention of the memory cell 122.

[0102] In some embodiments, the vacancy 302 extends continuously from the bottom electrode 124 to a point below the upper surface of the second data storage layer 130. Thus, the vacancy 302 may extend continuously from the first data storage layer 128 to the second data storage layer 130 after a reset operation is performed on the memory cell 122. In some embodiments, the vacancy 302 is vertically offset from the oxygen atom 202 by a distance d1. In such embodiments, the distance d1 is non-zero. In yet other embodiments, the vacancy 302 directly contacts the oxygen atom 202 (not shown), in which case the distance d1 is zero. In various embodiments, the oxygen atom 202 between the top electrode 134 and the vacancy 302 ensures that the bottom electrode 124 is not directly electrically coupled to the top electrode 134 after a reset operation is performed. In yet other embodiments, the vacancy 302 is not present within the third data storage layer 132 after a reset operation is performed on the memory cell 122.

[0103] Figure 5 Shown corresponding to Figure 1 FIG. 5 is a cross-sectional view of a memory device 500 according to some alternative embodiments of the memory device 100 .

[0104] Memory device 500 includes a lower dielectric layer 502 and a lower ILD layer 501 below the lower dielectric layer 502. In some embodiments, the lower ILD layer 501 may be, for example, or include an oxide such as silicon dioxide, a low-k dielectric material, another suitable dielectric material, or any combination thereof. A lower interconnect 116 is disposed within the lower ILD layer 501. In some embodiments, the lower interconnect 116 may be, for example, or include tungsten, copper, aluminum, a combination thereof, or the like. However, other materials are contemplated. A bottom electrode via 120 overlies the lower dielectric layer 502 and extends through the lower dielectric layer 502 to contact the lower interconnect 116. In some embodiments, the bottom electrode via 120 may be, for example, or include titanium, aluminum, tungsten, copper, a combination thereof, or the like. However, other materials are contemplated.

[0105] A first ILD layer 504 overlies and surrounds the bottom electrode via 120, and a second ILD layer 506 overlies the first ILD layer 504. In some embodiments, the first ILD layer 504 and / or the second ILD layer 506 may each be or include an oxide (e.g., silicon dioxide), a low-k dielectric material, a combination thereof, or another suitable dielectric material. A memory cell 122 is disposed within the first ILD layer 504 and overlies the bottom electrode via 120. The memory cell 122 includes a cap layer 508, a top electrode 134, a bottom electrode 124, and a data storage structure 126 disposed between the top and bottom electrodes 134, 124. The data storage structure 126 may include a first data storage layer 128, a second data storage layer 130, and a third data storage layer 132. In some embodiments, the thickness of the first data storage layer 128 is less than the thickness of the second data storage layer 130, and the thickness of the second data storage layer 130 is less than the thickness of the third data storage layer 132. In some embodiments, the first data storage layer 128, the second data storage layer 130, and the third data storage layer 132 may each be, for example, or include, a high-k dielectric material. However, other materials are readily apparent. Furthermore, a sidewall spacer structure 510 is disposed within the first ILD layer 504 and laterally surrounds the sidewalls of the memory cell 122.

[0106] In some embodiments, the top electrode 134 and / or the bottom electrode 124 may each be or include, for example, titanium, titanium nitride, tantalum nitride, tantalum, tungsten, tungsten nitride, combinations of the foregoing, or the like. However, other materials are readily apparent. In some embodiments, the cap layer 508 may be or include, for example, hafnium, titanium, tantalum, aluminum, zirconium, combinations of the foregoing, or the like. In some embodiments, the second data storage layer 130 and / or the third data storage layer 132 may each be or include, for example, hafnium oxide, aluminum oxide, silicon oxide, zirconium oxide, hafnium titanium oxide, hafnium tantalum oxide, tantalum aluminum oxide, hafnium zirconium oxide, tantalum zirconium oxide, hafnium cerium oxide, zirconium cerium oxide, combinations of the foregoing, or the like. In some embodiments, the first data storage layer 128 may be, for example, or include titanium oxide (e.g., TiO2), tantalum oxide, cerium oxide, tantalum oxynitride, hafnium tantalum oxide, hafnium tantalum oxynitride, hafnium cerium oxide, hafnium cerium oxynitride, titanium oxynitride, cerium oxynitride, tantalum oxycarbide, titanium oxycarbide, combinations thereof, or the like, and / or have a thickness in the range of approximately 5 angstroms to 20 angstroms. It should be understood that other values ​​for the thickness of the first data storage layer 128 are also within the scope of the present disclosure. In addition, however, other materials can be tested. In some embodiments, the sidewall spacer structure 510 may be, for example, or include silicon nitride, silicon carbide, or the like. However, other materials can be tested.

[0107] Additionally, a top electrode via 512 is disposed along the upper surface of the first ILD layer 504 and overlies the cap layer 508. In some embodiments, the top electrode via 512 may be, for example, or include tungsten, titanium, tantalum, combinations thereof, or the like. However, other materials are readily contemplated. In some embodiments, the top electrode via 512 directly contacts the cap layer 508. Additionally, a via 136 and a conductive line 138 are disposed within the second ILD layer 506. In some embodiments, the via 136 and the conductive line 138 may each be, for example, or include aluminum, copper, tungsten, titanium, combinations thereof, or the like. However, other materials are readily contemplated.

[0108] Figure 6 Shown corresponding to Figure 1 1 is a cross-sectional view of a memory device 600 of some alternative embodiments of the memory device 100 .

[0109] The memory cell 122 includes a film stack 602 comprising the following: the bottom electrode via 120, the bottom electrode 124, the first data storage layer 128, the second data storage layer 130, the third data storage layer 132, the top electrode 134, and the cap layer 508. The film stack 602 includes a middle region 602m above the lower interconnect 116 and a peripheral region 602p laterally offset from the top electrode via 512. The bottom surface of the middle region 602m of the film stack 602 is lower than the bottom surface of the peripheral region 602p of the film stack 602.

[0110] In some embodiments, the layers within the film stack 602 are each non-planar. This is because the layers are disposed within / above trenches defined by the sidewalls of the lower dielectric layer 502. For example, the bottom electrode via 120 extends continuously from the top surface of the lower dielectric layer 502 and along the sidewalls of the lower dielectric layer 502 to the top surface of the lower interconnect 116. Furthermore, the layers within the film stack 602 overlying the bottom electrode via 120 conform to the shape of the bottom electrode via 120. Consequently, the bottom electrode 124, the first data storage layer 128, the second data storage layer 130, the third data storage layer 132, the top electrode 134, and the cap layer 508 are each non-planar.

[0111] Figure 7 A cross-sectional view of some embodiments of an integrated chip 700 is shown including a first memory cell 122 a and a second memory cell 122 b disposed laterally within an embedded memory region 702 , where the embedded memory region 702 is laterally adjacent to a logic region 704 .

[0112] In some embodiments, the first storage unit 122a and / or the second storage unit 122b are respectively configured as Figure 5 Memory cells 122 are formed in the upper portion of the logic region 704. The first memory cell 122a and the second memory cell 122b are laterally offset from the logic region 704. In some embodiments, the logic region 704 includes a lower interconnect line 116 disposed within the lower ILD layer 501. Additionally, a via 136 is disposed within the logic region 704 and extends vertically from the conductive line 138 to the lower interconnect line 116.

[0113] Figure 8 Shown along Figure 7 The line intercepted Figure 7 A top view 800 of some embodiments of the integrated chip 700 is shown.

[0114] In some embodiments, as Figure 7 , when viewed from above, the first memory cell 122a and / or the second memory cell 122b each have a square shape. In some embodiments, when viewed from above, the first memory cell 122a and / or the second memory cell 122b may each have a rectangular shape, a circular shape, an elliptical shape, or another suitable shape. In addition, the sidewall spacer structure 510 laterally encloses the cap layer 508. In other embodiments, when viewed from above, the via 136 within the logic region 704 may have, for example, an elliptical or circular shape.

[0115] Figure 9 A cross-sectional view of some embodiments of an integrated chip 900 including a memory cell 122 disposed within an interconnect structure 914 is shown.

[0116] The integrated chip 900 includes an interconnect structure 914 overlying a substrate 102. The substrate 102 may be, for example, or include, a bulk substrate (e.g., a bulk silicon substrate) or a silicon-on-insulator (SOI) substrate. A semiconductor device 906 is disposed within and / or on the substrate 102. In some embodiments, the semiconductor device 906 may be configured as a metal-oxide-semiconductor field-effect transistor (MOSFET). In such embodiments, the semiconductor devices 906 each include a source / drain region 908 disposed within the substrate 102 and laterally spaced apart from each other. A gate dielectric layer 910 overlies the substrate 102 between the source / drain regions 908, and a gate electrode 912 overlies the gate dielectric layer 910. In some embodiments, the gate electrode 912 may be, for example, or include, polysilicon, a metal material (e.g., aluminum, titanium), a combination thereof, or another suitable conductive material. In some embodiments, substrate 102 includes a first doping type (e.g., p-type) and source / drain regions 908 include a second doping type (e.g., n-type) opposite the first doping type. In some embodiments, source / drain regions 908 include a doping concentration greater than the doping concentration of substrate 102. It should be understood that in some embodiments, semiconductor device 906 may be configured as other field-effect transistor devices. Well region 904 is disposed between source / drain regions 908 and includes a first doping type having a higher doping concentration than substrate 102.

[0117] The interconnect structure 914 includes an interconnect dielectric structure 118 overlying the substrate 102 and the semiconductor device 906. In some embodiments, the interconnect dielectric structure 118 includes one or more ILD layers composed of one or more ILD materials. In some embodiments, the one or more ILD materials may be, for example, or include silicon dioxide, a low-k dielectric material, a combination of the foregoing, or another suitable dielectric material. As used herein, a low-k dielectric material is a dielectric material having a dielectric constant of less than 3.9. A plurality of conductive lines 918 and vias 916 are stacked within the interconnect dielectric structure 118 and configured to provide electrical connections between various devices (e.g., the semiconductor device 906 and / or the memory cell 122) disposed throughout the integrated chip 900. In some embodiments, the conductive lines 918 and / or vias 916 may each be, for example, or include, copper, aluminum, tungsten, titanium, a combination of the foregoing, or some other suitable conductive material.

[0118] The memory cell 122 is disposed within the interconnect dielectric structure 118 of the interconnect structure 914. In some embodiments, the memory cell 122 includes a top electrode 134, a cap layer 508, a bottom electrode 124, a first data storage layer 128, a second data storage layer 130, and a third data storage layer 132. A bottom electrode via 120 extends from the underlying conductive line 918 to the bottom electrode 124, and a top electrode via 512 extends from the overlying conductive line 916 to the cap layer 508. In addition, the conductive line 918 overlies the memory cell 122 and is electrically coupled to the top electrode 134 via the top electrode via 512. In addition, a sidewall spacer structure 510 laterally surrounds the sidewalls of the memory cell 122. In some embodiments, the memory cell 122 is configured as Figure 1 、 Figure 5 or Figure 6 storage unit 122.

[0119] In some embodiments, the gate electrodes 912 of the semiconductor devices 906 are each electrically coupled to a word line (WL), such that an appropriate WL voltage can be applied to the gate electrodes 912 to electrically couple the memory cells 122 to a source line (SL) and / or a bit line (BL). The SL is electrically coupled to a source / drain region 908 of one of the semiconductor devices 906 via a via 916 and a conductive line 918. Furthermore, the BL is electrically coupled to a common source / drain region 908 (e.g., a source / drain region shared by all semiconductor devices 906) via the conductive line 918, the via 916, and the memory cells 122. In some embodiments, the common source / drain region 908 is a source / drain region laterally disposed between and shared by the semiconductor devices 906. Thus, in some embodiments, upon application of an appropriate WL voltage, the output of the BL and / or the memory cells 122 can be accessed at the SL. In other embodiments, a voltage may be applied at a transistor body node 902 that is electrically coupled to a well region 904 (i.e., the body of the semiconductor device 906) disposed beneath the gate electrode 912. The voltage applied at the transistor body node 902 may be configured to help control a conductive channel formed in the well region 904. In other embodiments, the memory cell 122 and the semiconductor device 906 may be configured in a two-transistor, one-resistive memory cell (e.g., 2T1R) configuration.

[0120] Figures 10 to 15 Cross-sectional views 1000 through 1500 illustrate some embodiments of a method of forming a memory device including a memory cell having a data storage structure having a first data storage layer, a second data storage layer, and a third data storage layer according to the present disclosure. Figures 10 to 151000 to 1500, but it should be understood that Figures 10 to 15 The structures depicted in the drawings are not limited to the methods described and can in fact stand alone independently of the methods described. Figures 10 to 15 Described as a series of actions, it should be understood that these actions are non-limiting, because the order of the actions can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some actions illustrated and / or described can be omitted in whole or in part.

[0121] like Figure 10 As shown in cross-sectional view 1000 of FIG1 , a lower interconnect 116 is formed within the lower ILD layer 501. A lower dielectric layer 502 is formed above the lower ILD layer 501. A bottom electrode via film 1002 is formed above the lower interconnect 116 and the lower dielectric layer 502. A memory cell film stack 1004 is formed above the bottom electrode via film 1002. The memory cell film stack 1004 includes a bottom electrode film 1006, a first data storage film 1008, a second data storage film 1010, a third data storage film 1012, a top electrode film 1014, and a cap film 1016. In some embodiments, the layers of the memory cell film stack 1004 and / or the bottom electrode via film 1002 may be formed by, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, electroless plating, electroplating, or another suitable growth or deposition process.

[0122] like Figure 11 As shown in the cross-sectional view 1100 of , a first mask layer 1102 is formed over the memory cell film stack 1004. In some embodiments, the first mask layer 1102 covers a middle region of the memory cell film stack 1004 and exposes a peripheral region of the memory cell film stack 1004.

[0123] like Figure 12 As shown in the cross-sectional view 1200, according to the first mask layer ( Figure 11 1102) patterned memory cell film stack ( Figure 11 1004), thereby defining the first data storage layer 128, the second data storage layer 130, the third data storage layer 132, the top electrode 134 and the cap layer 508. In some embodiments, the patterning process may include: forming a first mask layer ( Figure 11 1102) is exposed to one or more etchants; and a removal process (not shown) is performed to remove the first mask layer ( Figure 11 In some embodiments, the patterning process may etch a portion of the first data storage layer 128 so that the first data storage layer 128 continuously extends along the upper surface of the bottom electrode film 1006 after the patterning process is performed.

[0124] Figure 12 Also shown in FIG. 1 , a passivation layer 1202 is formed over the cap layer 508 and the first data storage layer 128. In some embodiments, the passivation layer 1202 may be or include, for example, silicon carbide, silicon nitride, silicon oxynitride, or the like. However, other materials are contemplated. In other embodiments, the passivation layer 1202 may be deposited by, for example, CVD, PVD, ALD, or another suitable deposition process. Furthermore, after forming the passivation layer 1202, a second mask layer 1204 is formed over the passivation layer 1202, where the second mask layer 1204 overlies the cap layer 508.

[0125] like Figure 13 As shown in the cross-sectional view 1300, according to the second mask layer ( Figure 12 1204) Figure 12 The structure of the substrate is patterned to define the data storage structure 126, the bottom electrode 124, the bottom electrode through hole 120, the sidewall spacer structure 510 and the memory cell 122. In some embodiments, the patterning process may include: Figure 12 exposing the unmasked area of ​​the structure to one or more etchants; and performing a removal process to remove the second mask layer ( Figure 12 1204). In some embodiments, the patterning process etches completely through the first data storage layer 128. In other embodiments, after the patterning process, the first data storage layer 128, the bottom electrode 124, and / or the bottom electrode through-hole 120 each have inclined, opposing outer sidewalls. In some embodiments, the data storage structure 126 includes the first data storage layer 128, the second data storage layer 130, and the third data storage layer 132. In other embodiments, the memory cell 122 includes the cap layer 508, the top electrode 134, the bottom electrode 124, and the data storage structure 126 disposed between the top electrode 134 and the bottom electrode 124.

[0126] like Figure 14As shown in cross-sectional view 1400 of FIG1 , a first ILD layer 504 is formed above and around the memory cell 122. In some embodiments, the first ILD layer 504 can be deposited, for example, by PVD, CVD, ALD, or another suitable deposition process. Additionally, a top electrode via 512 is formed above the memory cell 122, wherein the top electrode via 512 extends through the first ILD layer 504 and the sidewall spacer structure 510 to contact the cap layer 508. In some embodiments, the top electrode via 512 can be formed, for example, by CVD, PVD, electroless plating, electroplating, or another suitable deposition or growth process.

[0127] like Figure 15 As shown in cross-sectional view 1500 of FIG5 , a second ILD layer 506 is formed over the first ILD layer 504. In some embodiments, the second ILD layer 506 can be deposited by, for example, CVD, PVD, ALD, or another suitable deposition process. Additionally, the vias 136 and the conductive lines 138 are formed over the top electrode vias 512. In some embodiments, the vias 136 and / or the conductive lines 138 can be formed by a single damascene process or by a dual damascene process.

[0128] Figure 16 A method 1600 for forming a memory device including a memory cell having a data storage structure according to some embodiments of the present disclosure is shown, wherein the data storage structure has a first data storage layer, a second data storage layer, and a third data storage layer. Although method 1600 is illustrated and / or described as a series of actions or events, it should be understood that the method is not limited to the illustrated order or actions. Therefore, in some embodiments, the actions may be performed in a different order than described, and / or may be performed simultaneously. In addition, in some embodiments, the described actions or events may be subdivided into multiple actions or events, which may be performed at different times or simultaneously with other actions or sub-actions. In some embodiments, some of the described actions or events may be omitted, and other undescribed actions or events may be included.

[0129] At act 1602, lower interconnects are formed over a substrate. Figure 10 A cross-sectional view 1000 is shown corresponding to some embodiments of act 1602 .

[0130] At act 1604, a memory cell film stack is formed above the lower interconnect wire. The memory cell film stack includes a first data storage film, a second data storage film, a third data storage film, a top electrode film, and a bottom electrode film. Figure 10 A cross-sectional view 1000 is shown corresponding to some embodiments of act 1604 .

[0131] At act 1606 , a first patterning process is performed on the memory cell film stack, thereby defining a first data storage layer, a second data storage layer, a third data storage layer, and a top electrode. Figure 12 A cross-sectional view 1200 is shown corresponding to some embodiments of act 1606 .

[0132] At act 1608, a passivation layer is formed over the top electrode and along an upper surface of the first data storage layer. Figure 12 A cross-sectional view 1200 is shown corresponding to some embodiments of act 1608 .

[0133] At act 1610 , a second patterning process is performed on the passivation layer, the first data storage layer, and the bottom electrode film, thereby defining a sidewall spacer structure, a bottom electrode, and a memory cell. Figure 13 A cross-sectional view 1300 corresponding to some embodiments of act 1610 is shown.

[0134] At act 1612, a top electrode via is formed over the memory cell. Figure 14 A cross-sectional view 1400 is shown corresponding to some embodiments of act 1612 .

[0135] At act 1614 , a via and a conductive line are formed over the top electrode via. Figure 15 Cross-sectional view 1500 is shown corresponding to some embodiments of act 1614 .

[0136] Thus, in some embodiments, the present disclosure relates to a memory cell comprising a top electrode, a bottom electrode, and a data storage structure disposed between the top electrode and the bottom electrode. The data storage structure comprises a first data storage layer, a second data storage layer, and a third data storage layer, wherein the first data storage layer has a lower band gap than the second data storage layer, and the second data storage layer has a lower band gap than the third data storage layer.

[0137] In some embodiments, the present application provides a memory cell comprising: a bottom electrode; a top electrode overlying the bottom electrode; and a data storage structure disposed between the top and bottom electrodes, wherein the data storage structure comprises a first data storage layer, a second data storage layer, and a third data storage layer, wherein the second data storage layer is disposed between the first and third data storage layers, wherein the second data storage layer has a lower band gap than the third data storage layer, and wherein the first data storage layer has a lower band gap than the second data storage layer. In the above memory cell, the first data storage layer comprises a different material than the second and third data storage layers. In the above memory cell, the third data storage layer contacts the top electrode, and the first data storage layer contacts the bottom electrode. In the above memory cell, the thickness of the first data storage layer is less than the thickness of the second data storage layer, and the thickness of the second data storage layer is less than the thickness of the third data storage layer. In the above memory cell, the width of the first data storage layer increases discretely in a direction toward the bottom electrode. In the above memory cell, the first data storage layer comprises metal atoms and oxygen atoms, wherein the bond between the metal atoms and the oxygen atoms is greater than 600 kilojoules per mole. In the above memory cell, the memory cell further includes a sidewall spacer structure laterally surrounding the top electrode and sidewalls of the data storage structure, wherein a bottom surface of the sidewall spacer structure directly contacts an upper surface of the first data storage layer. In the above memory cell, a minimum width of the bottom electrode is greater than a maximum width of the top electrode. In the above memory cell, the first data storage layer includes a first pair of opposing sidewalls and a second pair of opposing sidewalls, wherein the first pair of opposing sidewalls is laterally spaced between the second pair of opposing sidewalls.

[0138] In some embodiments, the present application provides a memory device comprising: a bottom electrode; a top electrode overlying the bottom electrode; and a data storage structure disposed between the bottom electrode and the top electrode, wherein the data storage structure comprises: a first data storage layer contacting the bottom electrode and comprising a first material; a second data storage layer contacting the first data storage layer and comprising a second material different from the first material; and a third data storage layer disposed between the second data storage layer and the top electrode, wherein the third data storage layer comprises a third material different from the first and second materials; and wherein the respective band gaps of the first, second, and third data storage layers gradually decrease or increase from the top electrode to the bottom electrode, wherein the top electrode is configured to receive a programming voltage and the bottom electrode is configured to receive a reference voltage. In the above memory device, the first, second, and third materials each comprise a high-k dielectric material. In the above memory device, sidewalls of the third data storage layer are aligned with sidewalls of the bottom electrode. In the above memory device, the first band gap of the first data storage layer is less than 4.5 eV. In the above-mentioned memory device, the memory device further includes a cap layer overlying the top electrode; a top electrode through-hole overlying the cap layer; and a sidewall spacer structure extending continuously from the sidewalls of the data storage structure to the sidewalls of the top electrode through-hole, wherein the sidewall spacer structure contacts the upper surface of the cap layer. In the above-mentioned memory device, the first data storage layer includes a pair of vertically opposing sidewalls and a pair of obliquely opposing sidewalls, wherein the pair of vertically opposing sidewalls overly the pair of obliquely opposing sidewalls. In the above-mentioned memory device, the maximum width of the first data storage layer is greater than the maximum width of the third data storage layer.

[0139] In some embodiments, the present application provides a method for forming a memory device, the method comprising: forming a lower interconnect wire over a substrate; forming a memory cell film stack over the lower interconnect wire, wherein the memory cell film stack comprises a bottom electrode film, a first data storage film, a second data storage film, a third data storage film, and a top electrode film; patterning the memory cell film stack to define a top electrode, a bottom electrode, and a data storage structure disposed between the top and bottom electrodes, wherein the data storage structure comprises a first data storage layer, a second data storage layer, and a third data storage layer; and forming a via and a conductive line over the top electrode. In the above method for forming a memory device, the first data storage layer has a first band gap, the second data storage layer has a second band gap greater than the first band gap, and the third data storage layer has a third band gap greater than the second band gap. In the above-mentioned method for forming a memory device, patterning the memory cell film stack includes: forming a first mask layer over the memory cell film stack; performing a first etching process based on the first mask layer to remove at least a portion of the top electrode film, the first data storage film, the second data storage film, and the third data storage film, thereby defining the top electrode, the first data storage layer, the second data storage layer, and the third data storage layer, respectively; forming a second mask layer over the top electrode, wherein the second mask layer has a width greater than that of the first mask layer; and performing a second etching process based on the second mask layer to remove at least a portion of the bottom electrode film, thereby defining the bottom electrode. In the above-mentioned method for forming a memory device, the method further includes forming sidewall spacer structures along respective sidewalls of the top electrode, the first data storage layer, the second data storage layer, and the third data storage layer, wherein the sidewall spacer structures are formed after the first etching process and before the second mask layer is formed.

[0140] The foregoing summarizes the features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use this disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications may be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. A storage unit, characterized in that: include: bottom electrode; a top electrode, overlying the bottom electrode; as well as A data storage structure is disposed between the top electrode and the bottom electrode, wherein the data storage structure includes a first data storage layer, a second data storage layer and a third data storage layer, wherein the second data storage layer is disposed between the first data storage layer and the third data storage layer, wherein the second data storage layer has a lower band gap than the third data storage layer, and wherein the first data storage layer has a lower band gap than the second data storage layer. 2 . The memory cell of claim 1 , wherein the first data storage layer comprises a different material than the second data storage layer and the third data storage layer. 3 . The memory cell of claim 1 , wherein the third data storage layer contacts the top electrode and the first data storage layer contacts the bottom electrode. 4 . The memory cell of claim 1 , wherein a thickness of the first data storage layer is less than a thickness of the second data storage layer, and wherein the thickness of the second data storage layer is less than a thickness of the third data storage layer. 5 . The memory cell of claim 1 , wherein a width of the first data storage layer discretely increases in a direction toward the bottom electrode.

6. The memory cell of claim 1, wherein the first data storage layer comprises metal atoms and oxygen atoms, wherein the bond between the metal atoms and the oxygen atoms is greater than 600 kilojoules per mole.

7. The storage unit according to claim 1, further comprising: A sidewall spacer structure laterally surrounds the top electrode and sidewalls of the data storage structure, wherein a bottom surface of the sidewall spacer structure directly contacts an upper surface of the first data storage layer.

8. The memory cell of claim 1, wherein a minimum width of the bottom electrode is greater than a maximum width of the top electrode.

9. The memory cell of claim 1, wherein the first data storage layer comprises a first pair of opposing sidewalls and a second pair of opposing sidewalls, wherein the first pair of opposing sidewalls are laterally spaced between the second pair of opposing sidewalls.

10. A memory device, characterized in that: include: bottom electrode; a top electrode, overlying the bottom electrode; as well as A data storage structure is disposed between the bottom electrode and the top electrode, wherein the data storage structure comprises: a first data storage layer contacting the bottom electrode and comprising a first material; a second data storage layer contacting the first data storage layer and comprising a second material different from the first material; a third data storage layer disposed between the second data storage layer and the top electrode, wherein the third data storage layer comprises a third material different from the first material and the second material; and The respective band gaps of the first data storage layer, the second data storage layer, and the third data storage layer gradually decrease or increase from the top electrode to the bottom electrode, wherein the top electrode is configured to receive a programming voltage and the bottom electrode is configured to receive a reference voltage. 11 . The memory device of claim 10 , wherein the first material, the second material, and the third material each comprise a high-k dielectric material. 12 . The memory device of claim 10 , wherein a sidewall of the third data storage layer is aligned with a sidewall of the bottom electrode. 13 . The memory device of claim 10 , wherein a first band gap of the first data storage layer is less than 4.5 eV.

14. The memory device according to claim 10, further comprising: a cap layer covering the top electrode; A top electrode through hole, covering the cover layer; as well as A sidewall spacer structure continuously extends from a sidewall of the data storage structure to a sidewall of the top electrode through hole, wherein the sidewall spacer structure contacts an upper surface of the cap layer. 15 . The memory device of claim 10 , wherein the first data storage layer comprises a pair of vertically opposing sidewalls and a pair of obliquely opposing sidewalls, wherein the pair of vertically opposing sidewalls overlie the pair of obliquely opposing sidewalls. 16 . The memory device of claim 10 , wherein a maximum width of the first data storage layer is greater than a maximum width of the third data storage layer.

17. A method for forming a memory device, characterized in that: The method comprises: forming a lower interconnect wire above the substrate; forming a memory cell film stack above the lower interconnect wire, wherein the memory cell film stack comprises a bottom electrode film, a first data storage film, a second data storage film, a third data storage film, and a top electrode film; patterning the memory cell film stack to define a top electrode, a bottom electrode, and a data storage structure disposed between the top electrode and the bottom electrode, wherein the data storage structure includes a first data storage layer, a second data storage layer, and a third data storage layer, wherein the first data storage layer has a first band gap, the second data storage layer has a second band gap greater than the first band gap, and the third data storage layer has a third band gap greater than the second band gap; and A via and a conductive line are formed over the top electrode.

18. The method for forming a memory device of claim 17, wherein the first band gap of the first data storage layer is less than 4.5 eV.

19. The method for forming a memory device according to claim 17, wherein patterning the memory cell film stack comprises: forming a first mask layer over the memory cell film stack; Performing a first etching process according to the first mask layer to remove at least a portion of the top electrode film, the first data storage film, the second data storage film, and the third data storage film, thereby defining the top electrode, the first data storage layer, the second data storage layer, and the third data storage layer, respectively; forming a second mask layer over the top electrode, wherein the second mask layer has a width greater than a width of the first mask layer; as well as A second etching process is performed based on the second mask layer so that at least a portion of the bottom electrode film is removed, thereby defining the bottom electrode.

20. The method for forming a memory device according to claim 19, further comprising: A sidewall spacer structure is formed along respective sidewalls of the top electrode, the first data storage layer, the second data storage layer, and the third data storage layer, wherein the sidewall spacer structure is formed after the first etching process and before forming the second mask layer.

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